Dummy gate cutting process and resulting gate structure

Abstract

The present disclosure relates to dummy gate cutting processes and resulting gate structures. A method includes: forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer, and the second dielectric layer extends into the opening. Then a planarization process is performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. Then the dummy gate stack is removed to form trenches on opposite sides of the gate isolation region. The method further includes: performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming a replacement gate in the trenches.

Description

Technical Field

[0001] The present disclosure relates to dummy gate cutting processes and resulting gate structures. Background Art

[0002] Metal-oxide-semiconductor (MOS) devices are fundamental building blocks in integrated circuits. Existing MOS devices typically have a gate electrode that is polysilicon doped with p-type or n-type impurities using doping operations such as ion implantation or thermal diffusion. The work function of the gate electrode is adjusted to the band-edge of silicon. For n-type metal-oxide-semiconductor (NMOS) devices, the work function can be adjusted to be close to the conduction band of silicon. For p-type metal-oxide-semiconductor (PMOS) devices, the work function can be adjusted to be close to the valence band of silicon. By selecting an appropriate impurity, adjustment of the work function of the polysilicon gate electrode can be achieved.

[0003] MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, which is also known as the polycrystalline depletion effect. The polycrystalline depletion effect occurs when the applied electric field sweeps carriers from the gate region near the gate dielectric, forming a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized immobile donor sites, where in a p-doped polysilicon layer, the depletion layer includes ionized immobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult to create an inversion layer at the surface of the semiconductor.

[0004] The polysilicon depletion problem can be solved by forming a metal gate electrode or a metal silicide gate electrode, where the metal gates used in NMOS devices and PMOS devices can also have a band-edge work function. Since NMOS devices and PMOS devices have different requirements for the work function, dual-gate CMOS devices are used.

[0005] When forming a metal gate electrode, a long dummy gate is first formed and then etched such that portions of the long dummy gate are separated from each other. Then, a dielectric material can be filled into the openings left by the etched portions of the long dummy gate. Then, the dielectric material is polished, leaving portions of the dielectric material between the remaining portions of the dummy gate. Then, the separated portions of the dummy gate are replaced with metal gates. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, including: forming a dummy gate stack; etching the dummy gate stack to form an opening; depositing a first dielectric layer extending into the opening; depositing a second dielectric layer on the first dielectric layer, and the second dielectric layer extending into the opening; performing a planarization process to form a gate isolation region including the first dielectric layer and the second dielectric layer; removing portions of the dummy gate stack on opposite sides of the gate isolation region to form trenches; performing a first etching process to remove sidewall portions of the first dielectric layer; performing a second etching process to thin the second dielectric layer; and forming replacement gates in the trenches.

[0007] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a first semiconductor region and a second semiconductor region; a first gate stack and a second gate stack, the first gate stack and the second gate stack being respectively located on the first semiconductor region and the second semiconductor region; a dielectric region located between the first semiconductor region and the second semiconductor region; and a gate isolation region located between the first gate stack and the second gate stack, wherein a bottom surface of the gate isolation region contacts the dielectric region, and wherein, in a plan view of the gate isolation region, the gate isolation region has recessed sidewalls contacting the first gate stack and the second gate stack.

[0008] According to yet another embodiment of the present disclosure, a semiconductor structure is provided, including: a first gate stack including: a first gate dielectric; and a first gate electrode overlapping a first bottom portion of the first gate dielectric; a second gate stack including: a second gate dielectric; and a second gate electrode overlapping a second bottom portion of the second gate dielectric; a first gate spacer; and a gate isolation region located between the first gate stack and the second gate stack, wherein the gate isolation region includes: a first dielectric layer including a bottom portion and two sidewall portions located above and connected to opposite ends of the bottom portion, wherein the first dielectric layer forms a first interface with the first gate stack and a second interface with the first gate spacer, and the first interface and the second interface form an acute angle; and a second dielectric layer located between the two sidewall portions. Description of the Drawings

[0009] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that various features are not drawn to scale in accordance with standard industry practice. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0010] Figures 1-4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B-1 , Figure 8B-2 , Figure 8C , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12A , Figure 12B and Figure 12C illustrate cross-sectional, top, and perspective views of intermediate stages in forming a fin field-effect transistor (FinFET) and a gate isolation region on a dummy fin, according to some embodiments.

[0011] Figure 13 , Figure 14A , Figure 14B and Figures 15-19 illustrate cross-sectional and perspective views of intermediate stages in forming a fin field-effect transistor (FinFET) and a gate isolation region on a shallow trench isolation region, according to some embodiments.

[0012] Figures 20 to 23 illustrates a cross-sectional view of forming a gate-all-around (GAA) transistor and a gate isolation region, according to some embodiments.

[0013] Figure 24 and Figure 25 illustrate the formation of a gate isolation region having multiple layers, according to some embodiments.

[0014] Figure 26 illustrates a process flow for forming a FinFET and a gate isolation region, according to some embodiments. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatially relative terms (such as "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (some) element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0017] A gate isolation region, a fin field-effect transistor (FinFET), and a method of forming the same are provided in accordance with various embodiments. Intermediate stages in forming the gate isolation region are shown in accordance with some embodiments. Some variations of some embodiments are discussed. The embodiments discussed herein provide examples that enable the making or using of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope contemplated by the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0018] According to some embodiments of the present disclosure, forming the gate isolation region includes etching a dummy gate to form an opening, filling the opening with a first dielectric layer and a second layer, and performing a planarization process. The dummy gate is then removed. A first etching process is performed to remove the exposed sidewall portions of the first dielectric layer. Then a second etching process is performed to thin the second dielectric layer such that the resulting gate isolation region has a recessed top view shape. Then replacement gates are formed on opposite sides of the gate isolation region.

[0019] Figures 1-4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、Figure 7C , Figure 8A , Figure 8B-1 , Figure 8B-2 , Figure 8C , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12A , Figure 12B and Figure 12C show a cross-sectional view of an intermediate stage in forming a FinFET and a gate isolation region on a dummy fin. The corresponding process is also schematically reflected in Figure 26 the process flow shown.

[0020] Figure 1 shows a perspective view of an initial structure. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 can be a semiconductor substrate, which can be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 can be doped with p-type or n-type impurities. Isolation regions 22 (e.g., shallow trench isolation (STI) regions) are formed to extend from the top surface of the substrate 20 into the substrate 20. The corresponding process is as shown by process 202 in the process flow 200 Figure 26 shown. The portion of the substrate 20 located between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some embodiments of the present disclosure, the semiconductor strip 24 is a portion of the original substrate 20, and thus the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor strip 24 is an alternative strip formed by etching the portion of the substrate 20 located between the STI regions 22 to form a groove and performing an epitaxial process to regrow another semiconductor material in the groove. Thus, the semiconductor strip 24 is formed of a semiconductor material different from that of the substrate 20. According to some embodiments, the semiconductor strip 24 is formed of Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.).

[0021] The STI regions 22 can include a liner oxide (not shown), which can be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner oxide can also be a deposited silicon oxide formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. The STI regions 22 can further include a dielectric material above the liner oxide, and the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0022] Figure 2shows the formation of the dielectric dummy strip 25, which can be formed by etching one of the semiconductor strips 24 to form a groove and then filling the groove with a dielectric material. The corresponding process is as shown in process 204 of the process flow 200 as shown in Figure 26 . The dielectric material can include or can be a high-k dielectric material, such as silicon nitride. In addition, the material of the dielectric dummy strip 25 is selected such that it has a high etch selectivity with respect to the material of the metal gate (e.g., tungsten and titanium nitride) and the material of the STI region 22 (e.g., silicon oxide). According to some embodiments of the present disclosure, the material of the dielectric dummy strip 25 includes a silicon-based material, such as SiN, SiON, SiOCN, SiC, SiOC, SiO 2 , etc. According to an alternative embodiment of the present invention, the material of the dummy strip 25 includes a metal-based material (oxide or nitride), such as TaN, TaO, HfO, etc. The bottom surface of the dielectric dummy strip 25 can be higher than, flush with, or lower than the bottom surface of the STI region 22.

[0023] Referring to Figure 3 , the STI region 22 is recessed. The corresponding process is as shown in process 206 of the process flow 200 as shown in Figure 26 . The tops of the semiconductor strip 24 and the dielectric dummy strip 25 protrude higher than the top surface 22A of the remaining portion of the STI region 22 to form a protruding semiconductor fin 24' and a dielectric dummy fin 25', respectively. The etching can be performed using a dry etching process, where HF and NH 3 are used as etching gases. According to an alternative embodiment of the present disclosure, the recessing of the STI region 22 is performed by a wet etching process. For example, the etching chemical can include an HF solution. The height H1 of the dielectric dummy fin 25' can be equal to, greater than, or less than the height H2 of the protruding fin 24'. According to some embodiments of the present disclosure, the height H1 of the dielectric dummy fin 25' is in the range of about to about . The width W1 of the dielectric dummy fin 25' can be in the range of about to about .

[0024] In the above embodiments, the fins may be patterned by any suitable method. For example, one or more lithography processes including double patterning or multi-patterning processes may be used to pattern the fins. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the generation of patterns having a pitch, for example, smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0025] Also refer to Figure 3 , dummy gate stacks 30 are formed on the top surfaces and sidewalls of the (projecting) fins 24' and 25'. The corresponding process is as shown in process 208 in process flow 200 as shown in Figure 26 . The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate electrode 34 may be formed of, for example, polysilicon and may also be formed of other materials. Each of the dummy gate stacks 30 may further include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers of the foregoing. The dummy gate stack 30 may span over a single or multiple projecting fins 24' and 25' and the STI region 22. The length direction of the dummy gate stack 30 is also perpendicular to the length direction of the projecting fin 24'.

[0026] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. The corresponding process is also as shown in process 208 in process flow 200 as shown in Figure 26 . According to some embodiments of the present disclosure, the gate spacers 38 are formed of a dielectric material (e.g., silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, etc.) and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0027] According to some embodiments of the present disclosure, an etching step is performed to etch the portions of the projecting fin 24' that are not covered by the dummy gate stack 30 and the gate spacers 38, thereby obtaining the structure shown in Figure 4 . The corresponding process is as shown in Figure 26as shown by process 210 in the process flow 200 shown. The recess can be anisotropic, and thus the portion of fin 24' directly under the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI region 22. The space left by the etched portion of the protruding fin 24' is referred to as a groove 40. In the etching process, the dielectric dummy fin 25' is not etched. For example, SiCONi(NF 3 and NH 3 ), Certas (HF and NH 3 ) etc. can be used to etch the protruding fin 24'.

[0028] Next, an epitaxial region (source / drain region) 42 is formed by selectively growing semiconductor material from the groove 40, resulting in the structure in Figure 5A . The corresponding process is as shown by process 212 in the process flow 200 shown in Figure 26 . According to some embodiments, the epitaxial region 42 includes silicon germanium, silicon, silicon carbide, etc. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, in-situ doping of p-type or n-type impurities can be carried out using epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 42 is formed of a group III-V compound semiconductor (e.g., GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations of the foregoing, or multiple layers of the foregoing). After the epitaxial region 42 completely fills the groove 40, the epitaxial region 42 begins to expand horizontally and can form facets.

[0029] Figure 5B shows the formation of the source / drain region 42 covering according to an alternative embodiment of the present disclosure. According to these embodiments, the protruding fin 24' shown in Figure 4 is not recessed, and the epitaxial region 41 is grown on the protruding fin 24'. The material of the epitaxial region 41 can be similar to the material of the epitaxial semiconductor material 42 shown in Figure 5A , depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET. Thus, the source / drain 42 includes the protruding fin 24' and the epitaxial region 41. Implantation to implant n-type impurities or p-type impurities can (or may not) be performed.

[0030] Figure 6A perspective view of the structure after the formation of a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48 is shown. The corresponding process is as shown in process 214 of process flow 200 as Figure 26 shown. For example, the CESL 46 can be formed of silicon nitride, silicon carbonitride, etc. The CESL 46 can be formed using a conformal deposition method such as ALD or CVD. The ILD 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The ILD 48 can also be formed of or include a dielectric material containing oxygen, and the dielectric material containing oxygen can be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to make the top surfaces of the ILD 48, the dummy gate stack 30, and the gate spacers 38 flush with each other. According to some embodiments of the present disclosure, the planarization process stops on top of the hard mask layer 36. According to alternative embodiments, the hard mask layer 36 is also removed during the planarization process, and the planarization process stops on the top surface of the dummy gate electrode 34. Therefore, in some subsequent figures, the hard mask layer 36 is represented by a dashed line to indicate that it may or may not be present.

[0031] Referring Figure 7A , the dummy gate cutting process is performed by: etching the dummy gate stack 30 to form an opening 50. The corresponding process is as shown in process 216 of process flow 200 as Figure 26 shown. Thus, the dummy gate stack 30 is separated into discrete portions. To perform the dummy gate cutting process, an etch mask can be formed and patterned, and the etch mask can include a photoresist (not shown). Figure 7B A cross-sectional view obtained from the reference cross-section 7B-7B as shown in Figure 7A is shown. In the dummy gate cutting process, the dummy gate stack 30 is etched in an anisotropic process until the dielectric dummy fin 25' is exposed. As a result, a portion of the dummy gate stack 30 is removed. The long dummy gate stack 30 is thus cut into two discrete portions 30A and 30B that are disconnected from each other. Each discrete portion of the dummy gate stack 30 can span one, two, or more protruding fins 24' so as to form a single-fin FinFET or a multi-fin FinFET. After etching the dummy gate stack 30, the etch mask is removed, for example, by an ashing process.

[0032] Figure 7C A view shows Figure 7ATop view of a portion of the structure shown. Each opening 50 is formed between corresponding gate spacer portions 38A and 38B, which are parallel opposing portions of the gate spacer 38. The gate spacer portions 38A and 38B have sidewalls exposed to the opening 50. The dielectric dummy fin 25’ is exposed through the opening 50.

[0033] Next, as Figure 8A shown, the opening 50 is filled with layers / regions 52-1 and 52-2 that form the gate isolation region 52. The corresponding process is as shown in process 218 of the process flow 200 as Figure 26 shown. The layers / regions 52-1 and 52-2 may be formed of a dielectric material and are thus referred to hereinafter as dielectric layers / regions, while they may also be formed of a non-dielectric material. The dielectric layers 52-1 and 52-2 are formed of different dielectric materials or the same material with different properties (e.g., different density values). The dielectric layers 52-1 and 52-2 may be selected from the same group of dielectric materials, including but not limited to oxide-based dielectric materials, nitride-based dielectric materials, oxynitride-based dielectric materials, oxycarbide-based dielectric materials, carbide-based dielectric materials, etc. For example, the dielectric layers 52-1 and 52-2 may be formed of materials selected from SiN, SiON, SiOCN, SiC, SiOC, SiO 2 etc. The layers 52-1 and 52-2 may also be formed of a non-dielectric material such as SiGe. According to some embodiments, the dielectric layer 52-1 is formed of an oxide (e.g., silicon oxide), while the dielectric layer 52-2 is formed of a nitride (e.g., silicon nitride). According to alternative embodiments, the dielectric layers 52-1 and 52-2 are formed of the same material (e.g., silicon oxide) but have different porosity values and thus different density values. According to some embodiments, the dielectric layer 52-1 is denser (has a lower porosity) than the dielectric layer 52-2. In addition, the dielectric layers 52-1 and 52-2 may be formed of the same material but using different process conditions. For example, a higher temperature and a lower temperature may be used to form the dielectric layer 52-1 and the dielectric layer 52-2, respectively. For example, when the dielectric layers 52-1 and 52-2 are formed of silicon oxide, the higher temperature may be in the range between about 400 °C and about 600 °C, and the lower temperature may be in the range between about 200 °C and about 400 °C. In addition, the higher temperature may be greater than about 50 °C higher than the lower temperature, and the difference may be in the range between about 50 °C and about 300 °C. When using other materials than silicon oxide, the higher and lower temperature ranges may be different from the temperature range of silicon oxide. According to alternative embodiments, as Figure 24As shown, the gate isolation region 52 may include more than two layers, such as three, four, five, etc., up to ten layers. Whether formed of different materials or the same material, the dielectric layers 52-1 and 52-2 can be distinguished from each other, for example, using X-ray diffraction, transmission electron microscopy (TEM), etc.

[0034] Figure 8B-1 and Figure 8B-2 illustrates a process for forming the gate isolation region 52. According to some embodiments, as Figure 8B-1 shown, a conformal deposition method is used to form the dielectric layer 52-1, and thus the thickness T2 of its vertical portion ( Figure 8B-2 ) is close to the thickness T1 of its horizontal portion (e.g., where the thickness difference is less than about 20%). According to some embodiments, atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), low-pressure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or other suitable deposition methods are used to form the dielectric layer 52-1. According to some embodiments, each lower layer (e.g., 52-1, or 52-2 if more layers are formed) may have a thickness T1 / T2 in the range of about to about . The dielectric layer / region 52-2 fills the remaining space in the opening 50 ( Figure 7A ) that is not filled by the dielectric layer 52-1. The dielectric layers 52-1 and 52-2 have some portions that are higher than the top surfaces of the dummy gate stacks 30A and 30B.

[0035] Referring to Figure 8B-2 , a planarization process is performed to remove the excess portions of the dielectric layers 52-1 and 52-2, leaving the gate isolation region 52. The portions of the dielectric layers 52-1 and 52-2 that are higher than the top surfaces of the dummy gate stacks 30A and 30B are removed. As a result, as Figure 8C shown, the dummy gate stacks 30A and 30B are exposed. At the same time, according to some embodiments, the ILD 48 ( Figure 8A ) may also be exposed. Hereinafter, the remaining portions of the dielectric layers 52-1 and 52-2 are collectively referred to as the gate isolation region 52, which includes the remaining portions of the dielectric layers 52-1 and 52-2.

[0036] As Figure 8C shown, the gate isolation region 52 separates the respective dummy gate stacks 30A and 30B from each other. In a top view, the gate isolation region 52 and the dummy gate stacks 30A and 30B are combined to form an elongated strip, and each elongated strip is located between the opposing portions 38A and 38B of the gate spacer 38.

[0037] Then, the dummy gate stacks 30A and 30B are removed by etching, and the resulting structure is shown in Figure 9A and Figure 9B . The corresponding process is as shown in process 220 of process flow 200 as shown in Figure 26 . According to some embodiments, the dummy gate dielectric 32 is removed. According to alternative embodiments, the dummy gate dielectric 32 is not removed during this process, and the dummy gate dielectric 32 is exposed after the dummy gate electrode 34 is removed. Thus, in Figure 9B and Figure 10 , the dummy gate dielectric 32 is shown in dashed lines to indicate that it may or may not be present in the corresponding structure. In these embodiments, when etching the dielectric layer 52-2 in the process shown in Figure 11A and Figure 11B , the dummy gate dielectric 32 may be removed, or it may be removed after the process shown in Figure 11A and Figure 11B and before forming the replacement gate. Openings 54A and 54B are formed in the spaces left by the removed dummy gate electrodes 34 (and possibly the dummy gate dielectric 32). As shown in Figure 9A , each of the openings 54A and 54B is defined by the gate isolation region 52 and the gate spacer 38, and the openings 54A and 54B are also separated from each other by the gate isolation region 52. Figure 9B shows a cross-sectional view obtained from the reference cross-section 9B-9B in Figure 9A . According to some embodiments of the present disclosure, as shown in Figure 9B , the gate isolation region 52 is wider than the underlying dielectric dummy fin 25'. According to alternative embodiments, the gate isolation region 52 may have the same width as the dielectric dummy fin 25', or may be narrower than the dielectric dummy fin 25'.

[0038] Referring to Figure 10 , a first etching process 56 is performed to remove the outer sidewall portions of the dielectric layer 52-1, thereby exposing the sidewalls of the dielectric layer 52-2. The corresponding process is as shown in process 222 of process flow 200 as shown in Figure 26 . The etching process is isotropic and can be performed by dry etching or wet etching. The etchant is selected according to the materials of the dielectric layers 52-1 and 52-2, so as to have a high etching selectivity ER 52-1 / ER 52-2 , for example, higher than about 4, where the etching selectivity ER 52-1 / ER 52-2 is the etching rate of the dielectric layer 52-1 relative to the etching rate of the dielectric layer 52-2. Thus, in the first etching process 56, the dielectric layer 52-2 is not etched.

[0039] Referring to Figure 11AAnd Figure 11B , a second etching process 58 is performed to thin the dielectric layer 52-2, thereby changing the profile of the dielectric layer 52-2. The corresponding process is as shown in process 224 in process flow 200 as shown in Figure 26 . The etching process is isotropic and can be performed by dry etching or wet etching. The etchant is selected according to the materials of the dielectric layers 52-1 and 52-2, so as to have a relatively high etching selectivity ER 52-2 / ER 52-1 (etching rate of the dielectric layer 52-2 relative to the etching rate of the dielectric layer 52-1). Therefore, the dielectric layer 52-2 is etched at a higher rate than in the first etching process 56. On the other hand, the etching selectivity ER 52-2 / ER 52-1 can be kept not too high so that the corners of the dielectric layer 52-1 can still be rounded in the second etching process 58. According to some embodiments, the etching selectivity ER 52-2 / ER 52-1 is in the range of about 2 to about 20. According to some embodiments of the present disclosure, if the dummy gate dielectric 32 ( Figure 9A and Figure 9B ) is not removed in the processes shown in Figure 10 , it can be removed in the second etching process 58.

[0040] According to some embodiments, when performing one of the etching processes 56 and 58, depending on the materials of the dielectric layers 52-1 and 52-2, the etching gas can be selected from the group consisting of: Cl 2 , HBr, CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, C 4 F 6 , BCl 3 , SF 6 , H 2 , HF, NH 3 , NF 3 and combinations of the foregoing. In addition, gases such as N 2 , O 2 , CO 2 , SO 2 , CO, SiCl 4 or combinations of the foregoing can be added to improve the etching selectivity. Inert gases such as Ar, He, Ne, etc. can be added as dilution gases (carrier gases). For example, when the dielectric layer 52-1 is formed of SiN and the dielectric layer 52-2 is formed of SiO 2In the formed embodiments, fluorine-containing gases (e.g., a mixture of CF 4 , O 2 , and N 2 , a mixture of NF 3 and O 2 , SF 6 , or a mixture of SF 6 and O 2 , etc.) can be used to etch the dielectric layer 52-1, while a mixture of NF 3 and NH 3 , a mixture of HF and NH 3 , etc. can be used to thin the dielectric layer 52-2. In the first etching process 56 and the second etching process 58, the plasma source power can be in the range between about 10 watts and about 3,000 watts, and the plasma bias power can be less than about 3,000 watts. The pressure of the etching gas can be in the range between about 1 millitorr and about 800 millitorr. The flow rate of the etching gas can be in the range between about 1 sccm and about 5,000 sccm.

[0041] When wet etching is performed in the first etching process 56 and the second etching process 58, still depending on the materials of the dielectric layers 52-1 and 52-2, the corresponding etching solutions for etching the respective dielectric layers 52-1 and 52-2 can include HF solution (in which fluorine (F 2 ) is dissolved), H 2 SO 4 , HCl, HBr, NH 3 , etc. or combinations of the foregoing. The solvent can include deionized water, ethanol, acetone, etc.

[0042] According to an alternative embodiment, the same etching process can be performed to etch both the dielectric layer 52-1 and the dielectric layer 52-2, rather than using different etching chemicals to perform two etching processes. The etchant is selected such that the dielectric layer 52-1 has a lower etching rate than the dielectric layer 52-2. In the initial stage, the sidewall portion of the dielectric layer 52-1 is etched, while the dielectric layer 52-2 is protected by the sidewall portion of the dielectric layer 52-1. After removing the sidewall portion of the dielectric layer 52-1, the sidewall of the dielectric layer 52-2 is exposed, and both the dielectric layer 52-1 and the dielectric layer 52-2 are etched. Since the dielectric layer 52-2 has a higher etching rate than the dielectric layer 52-1, the dielectric layer 52-2 is laterally recessed faster than the dielectric layer 52-1, thus forming a profile as shown in Figure 11B . It should be understood that according to these embodiments, the etching selectivity ER 52-1 / ER 52-2(The etching rate of the dielectric layer 52-1 relative to the etching rate of the dielectric layer 52-2) is less than 1.0 and is selected to be within a specific range that is not too high and not too low. If the etching selectivity ER 52-1 / ER 52-2 is too high, the sidewalls of the gate isolation region 52 will be convex (opposite to that shown in Figure 11B ), rather than concave. If the etching selectivity ER 52-1 / ER 52-2 is too low, there is a risk that the dielectric layer 52-2 will be etched through or even completely removed. According to some embodiments, the etching selectivity ER 52-1 / ER 52-2 is in the range between about 0.05 and 1.

[0043] The dielectric layers 52-1 and 52-2 can also be formed of the same material with different properties. For example, both the dielectric layers 52-1 and 52-2 can be formed of silicon oxide, and the dielectric layer 52-2 is more porous than the dielectric layer 52-1. Thus, the same etching process can be performed to etch both the dielectric layer 52-1 and 52-2, rather than performing two etching processes using different etching chemicals. At the start of the etching process, the sidewall portions of the dielectric layer 52-1 are etched, while the dielectric layer 52-2 is protected by the sidewall portions of the dielectric layer 52-1. After removing the sidewall portions of the dielectric layer 52-1, the sidewalls of the dielectric layer 52-2 are exposed, and both the dielectric layer 52-1 and 52-2 are etched. Since the dielectric layer 52-2 has a lower density than the dielectric layer 52-1, the dielectric layer 52-2 has a higher etching rate than the dielectric layer 52-1. As a result, the resulting gate isolation region 52 also has a profile as shown in Figure 11A and Figure 11B .

[0044] By etching the dielectric layers 52-1 and 52-2 as described above, a profile as shown in Figure 11A and Figure 11B can be formed. As shown in Figure 11AAs shown, the bottom width of the dielectric layer 52-2, the bottom width of the dielectric layer 52-1, and the top width of the dielectric dummy fin 25' are respectively labeled as LD1, LD2, and LD3. According to some embodiments, the bottom width LD1 is less than the bottom width LD2. The bottom width LD2 may be equal to or less than the top width LD3. The bottom portion of the sidewall of the gate isolation region 52 may have a recessed shape. In addition, the bottom portion of the sidewall of the gate isolation region 52 is curved and smooth. Since there is no undercut that is difficult to fill, this smooth and recessed profile makes it easy to form a replacement gate subsequently. For example, a dashed line 60 is drawn to show the curved bottom of the gate isolation region formed using a conventional method, where the gate isolation region will be formed of a homogeneous material. The dashed line 60 shows that sharp undercuts will be formed directly below the edge portion of the gate isolation region, and these undercuts are very difficult to be filled by the replacement gate.

[0045] Figure 11B is shown Figure 11A A top view of the structure shown. Due to the etching process as described above, the gate isolation region 52 has a recessed sidewall. For example, the middle portion of the gate isolation region 52 may be the narrowest, while the edge portion of the gate isolation region 52 that contacts the gate spacer 38 may be the widest. In Figure 11B it, the width (lateral dimension) LD4 is greater than the width LD5, and the width LD5 is greater than the width LD6. According to some embodiments, the width difference (LD4 - LD5) may be greater than about and the ratio (LD4 - LD5) / LD4 may be greater than about 0.05, and may be in the range of about 0.05 to about 1. In addition, the width difference (LD5 - LD6) may be greater than about and the ratio (LD5 - LD6) / LD5 may be greater than about 0.05, and may be in the range of about 0.05 to about 1.

[0046] In addition, the angle θ formed between the sidewall of the gate isolation region 52 and the corresponding portion of the sidewall of the gate spacer 38 is equal to or greater than 90 degrees, and may be in the range of 90 degrees to about 160 degrees. This right angle or obtuse angle also makes it easy to fill the replacement gate in subsequent processes.

[0047] Figure 12A , Figure 12B and Figure 12C respectively show a perspective view, a cross-sectional view, and a top view when forming the replacement gate stacks 66A and 66B. The corresponding processes are as Figure 26as shown by process 226 in the process flow 200 shown. Thus, FinFETs 68A and 68B are formed, where gate stacks 66A and 66B are alternative gate stacks of FinFETs 68A and 68B, respectively. The alternative gates 66A and 66B share common gate spacers 38A and 38B. In addition, both of the alternative gates 66A and 66B are adjacent to the gate isolation region 52.

[0048] The alternative gate stacks 66A and 66B include a gate dielectric 62 and a gate electrode 64. The gate dielectric 62 may include a high-k dielectric material such as hafnium oxide, zirconium oxide, lanthanum oxide, etc., and may also include a silicon oxide layer as an interface layer between the high-k dielectric material and the protruding fin 24'. According to some embodiments of the present disclosure, the gate electrode 64 is formed of a metal, a metal alloy, a metal silicide, a metal nitride, etc., and may have a composite structure including multiple layers formed of TiN, TiAl, Co, Al, etc. The corresponding metal and structure are selected such that the resulting alternative gate electrode 64 has an appropriate work function. For example, when the resulting FinFET is an n-type FinFET, the work function of the gate electrode 64 is lower than 4.5 eV, while when the resulting FinFET is a p-type FinFET, the work function of the gate electrode 64 is higher than 4.5 eV.

[0049] Figure 12B A cross-sectional view is shown taken from Figure 12A reference cross-section 12B-12B therein. As Figure 12B shown, the gate dielectric 62 contacts both the dielectric layers 52-1 and 52-2 of the gate isolation region 52. Figure 12C A top view of the Figure 12A shown structure is shown. Figure 12C An angle θ and its complementary angle α are shown. The angle α may be equal to or greater than 90 degrees and may be in the range between 90 degrees and about 160 degrees. Since the portion of the alternative gate stack 66 that contacts the gate isolation region 52 has a convex shape, it is easy to fill the alternative gate stack 66 therein without leaving voids.

[0050] Figure 13 , Figure 14A , Figure 14B and Figures 15-19 A cross-sectional view and a perspective view are shown of an intermediate stage in forming a FinFET and a gate isolation region according to some embodiments. These embodiments are similar to the embodiments disclosed in the foregoing embodiments, except that the gate isolation region 52 is not located on the dielectric dummy fin 25', but on the STI region 22. Unless otherwise specified, these embodiments (and Figures 20-25The materials and formation processes of the components in the (illustrated embodiment) are substantially the same as those of the same components labeled with the same reference numerals in the foregoing embodiments shown in the foregoing figures. Therefore, regarding Figure 13 , Figure 14A , Figure 14B and Figures 15-19 Details of the formation processes and materials of the components shown in can be found in the discussion of the foregoing embodiments.

[0051] Figure 13 The first semiconductor strip 24 and the second semiconductor strip 24 are shown, wherein the continuous STI region 22 extends from the first semiconductor strip 24 to the second semiconductor strip 24. Next, the processes shown in Figures 3-6 and Figure 7A are performed. The process shown in Figure 2 is skipped, and thus the dielectric dummy fin is not formed.

[0052] Figure 14A The structure after forming the CESL 46 and the ILD 48 is shown. In addition, an opening 50 is formed to cut the dummy gate stack 30 into shorter portions 30A and 30B. Figure 14B shows a cross-sectional view obtained from the reference cross-section 14B-14B in Figure 14A . The opening 50 extends all the way to the STI region 22, such that the dummy gate stack 30A is physically and electrically isolated from the dummy gate stack 30B. Figure 14A and Figure 14B The top-view shape of the structure shown is substantially the same as the top-view shape of the structure shown in Figure 7C , except that the dielectric dummy fin 25' is not formed, and the STI region 22 will be exposed to the opening 50.

[0053] Next, as shown in Figure 15 , a gate isolation region 52 is formed in the opening 50. Details of the formation and materials can be found by referring to the discussion in Figure 8B-1 and Figure 8B-2 . Next, the dummy gate stacks 30A and 30B are removed to expose the dummy gate dielectric 32 or the protruding fin 24', depending on whether the dummy gate dielectric 32 has been removed at this time. Figure 16 The resulting structure is shown in.

[0054] Figure 17 The first etching process 56 is shown, wherein the sidewall portions of the dielectric layer 52-1 are removed, and the sidewalls of the dielectric layer 52-2 are exposed to the openings 54A and 54B. Figure 18 The second etching process 58 is shown, thereby forming as shown in Figure 18The profiles shown. The values of the widths LD1, LD2, and LD3 and the relationships (e.g., ratios) between the widths LD1, LD2, and LD3 can be similar to those of the reference Figure 11A discussed and will not be repeated here. The top view shape of the gate isolation region 52 can be substantially the same as that Figure 11B shown in. Figure 19 Illustrated is the formation of alternative gate stacks 66A and 66B. Thus, FinFETs 68A and 68B are formed.

[0055] The processes for forming the gate isolation region can also be applied to form other types of transistors besides FinFETs. For example, these processes can be applied to dummy gate cuts for planar transistors, gate-all-around (GAA) transistors, etc. Figures 20 to 23 Illustrated is an exemplary embodiment in which a gate isolation region is formed for a GAA transistor.

[0056] Reference Figure 20 , two stacked layers 114 and 114' are formed. Each of the stacked layers 114 and 114' includes a channel layer 110 and a sacrificial film 112. The total number of channel layers 110 and the total number of sacrificial films 112 can be in the range of 1 to about 10 and include 1 to about 10. The materials of the channel layer 110 and the sacrificial film 112 are different from each other. According to some embodiments, the channel layer 110 is formed of or includes: Si, SiGe, etc. The sacrificial film 112 can be formed of or include: SiGe, SiP, SiOCN, SiC, etc. The stacked layers 114 and 114' overlap with the corresponding semiconductor strips 24. A dummy gate stack 30 is formed on the stacked layers 114 and 114', and the dummy gate stack 30 includes a dummy gate dielectric 32, a dummy gate electrode 34, and a hard mask 36. An opening 50 is formed by etching the dummy gate stack 30.

[0057] According to some embodiments, except that the dielectric dummy fin 25' is not formed and the protruding fin 24' is replaced by the stacked layers 114 and 114', Figure 20 the perspective view shape and the top view shape of the structure shown are substantially the same as those of the structure Figure 14A and Figure 7C shown. The formation process can be anticipated with reference to the foregoing embodiments.

[0058] Reference Figure 21 , a gate isolation region 52 is formed. Then, the dummy gate stacks 30A and 30B are removed, resulting in trenches 54A and 54B as shown in Figure 22 . In subsequent processes, a first etching process 56 ( Figure 17 ) and a second etching process 58 ( Figure 18)to modify the profile of the gate isolation region 52. Except that Figure 11B the protruding fin 24’ in Figure 22 is replaced by the stacked layer 114 in Figure 22 the top view shape of the structure shown in Figure 11B is similar to the top view shape shown in

[0059] In a subsequent process, the sacrificial film 112 is removed, and then replacement gates 66A and 66B are formed, which include a gate dielectric 62 surrounding the channel layer 110 and a gate electrode 64 filling the remaining space between the channel layers 110. Thus, GAA transistors 68A’ and 68B’ are formed.

[0060] According to some embodiments of the present disclosure, the gate isolation region 52 includes two layers, such as layer 52-1 and layer 52-2. According to alternative embodiments, the gate isolation region 52 may include more layers, such as three layers, four layers, five layers, and up to ten layers. For example, Figure 24 shows a top view of the gate isolation region 52, which includes layer 52-1, layer 52-n, and layers 52-2 to 52-(n-1) (not shown), where the integer n is, for example, equal to or greater than 2 and equal to or less than 10. The forming process includes using a conformal deposition method to deposit layers 52-1 to 52-(n-1), where the materials of layers 52-1 to 52-n are different from each other, depositing the dielectric layer 52-n, and performing a planarization process. Figure 25 shows a top view of the transistors 68A and 68B after the gate isolation region 52 is formed. The profile is similar to the profile discussed with reference to Figure 11B where the outer layer of the gate isolation region 52 is wider and wider than the corresponding inner layer.

[0061] Embodiments of the present disclosure have some advantageous features. By forming a multi-layer gate isolation region and etching the multi-layer, the profile of the corner region of the gate isolation region is shaped without forming an undercut and a sharp corner. Therefore, the formation of the replacement gate is easier and voids are less likely to be formed.

[0062] According to some embodiments of the present disclosure, a method includes: forming a dummy gate stack; etching the dummy gate stack to form an opening; depositing a first dielectric layer extending into the opening; depositing a second dielectric layer on the first dielectric layer and the second dielectric layer extending into the opening; performing a planarization process to form a gate isolation region including the first dielectric layer and the second dielectric layer; removing portions of the dummy gate stack on opposite sides of the gate isolation region to form trenches; performing a first etching process to remove sidewall portions of the first dielectric layer; performing a second etching process to thin the second dielectric layer; and forming replacement gates in the trenches. In an embodiment, in the first etching process, the first dielectric layer has a higher etching rate than the second dielectric layer, while in the second etching process, the first dielectric layer has a lower etching rate than the second dielectric layer. In an embodiment, the first etching process and the second etching process result in the gate isolation region having a recessed sidewall facing the trenches. In an embodiment, the method further includes: forming a dielectric dummy fin that protrudes from isolation regions located on opposite sides of the dielectric dummy fin, and the gate isolation region has a bottom surface in contact with the dielectric dummy fin. In an embodiment, the method further includes: forming a shallow trench isolation region extending into the semiconductor substrate, wherein the gate isolation region has a bottom surface in contact with the shallow trench isolation region. In an embodiment, the dummy gate stack extends over two adjacent semiconductor fins. In an embodiment, the dummy gate stack extends over two adjacent stacks of a stack layer, and each stack of the stack layer includes alternating channel layers and sacrificial films, and the method further includes removing the sacrificial films.

[0063] According to some embodiments of the present disclosure, a structure includes: a first semiconductor region and a second semiconductor region; a first gate stack and a second gate stack, the first gate stack and the second gate stack being located on the first semiconductor region and the second semiconductor region respectively; a dielectric region located between the first semiconductor region and the second semiconductor region; and a gate isolation region located between the first gate stack and the second gate stack, wherein a bottom surface of the gate isolation region contacts the dielectric region, and wherein in a plan view of the gate isolation region, the gate isolation region has recessed sidewalls that contact the first gate stack and the second gate stack. In an embodiment, the structure further includes: a first gate spacer and a second gate spacer, the first gate spacer and the second gate spacer being located on opposite sides of the gate isolation region and contacting the gate isolation region. In an embodiment, each of the first gate spacer and the second gate spacer further contacts the first gate stack and the second gate stack. In an embodiment, the gate isolation region has a bottom portion that contacts the dielectric region, and wherein an upper portion of the bottom portion is narrower than a corresponding lower portion of the bottom portion. In an embodiment, the gate isolation region includes: a first dielectric layer and a second dielectric layer. The first dielectric layer includes the bottom portion and two sidewall portions located above opposite ends of the bottom portion and connected to the opposite ends of the bottom portion. The second dielectric layer is located between the two sidewall portions. In an embodiment, the first dielectric layer and the second dielectric layer are formed of different materials. In an embodiment, the first dielectric layer and the second dielectric layer are formed of the same material, and the first dielectric layer and the second dielectric layer have different porosity values.

[0064] According to some embodiments of the present disclosure, a structure includes: a first gate stack and a second gate stack. The first gate stack includes a first gate dielectric; and a first gate electrode that overlaps a first bottom portion of the first gate dielectric. The second gate stack includes a second gate dielectric; and a second gate electrode that overlaps a second bottom portion of the second gate dielectric. The structure further includes: a first gate spacer; and a gate isolation region located between the first gate stack and the second gate stack, wherein the gate isolation region includes a first dielectric layer that includes a bottom portion and two sidewall portions located above and connected to opposite end portions of the bottom portion, wherein the first dielectric layer forms a first interface with the first gate stack and a second interface with the first gate spacer, and the first interface and the second interface form an acute angle; and a second dielectric layer located between the two sidewall portions. In an embodiment, the structure further includes a second gate spacer, wherein both the first gate spacer and the second gate spacer are in contact with the gate isolation region. In an embodiment, the first dielectric layer and the second dielectric layer are formed of different materials. In an embodiment, the first dielectric layer and the second dielectric layer are formed of the same material and have different density values. In an embodiment, both the first dielectric layer and the second dielectric layer are in contact with both the first gate stack and the second gate stack. In an embodiment, the structure further includes: a dielectric region located below and in contact with the gate isolation region, wherein the dielectric region forms a first interface with the gate isolation region, and the bottom portion of the first dielectric layer forms a second interface with the second dielectric layer, and the second interface is shorter than the first interface.

[0065] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0066] Example 1 is a method for forming a semiconductor structure, including: forming a dummy gate stack; etching the dummy gate stack to form an opening; depositing a first dielectric layer extending into the opening; depositing a second dielectric layer on the first dielectric layer, and the second dielectric layer extending into the opening; performing a planarization process to form a gate isolation region including the first dielectric layer and the second dielectric layer; removing portions of the dummy gate stack on opposite sides of the gate isolation region to form a trench; performing a first etching process to remove sidewall portions of the first dielectric layer; performing a second etching process to thin the second dielectric layer; and forming a replacement gate in the trench.

[0067] Example 2 is the method according to Example 1, wherein, in the first etching process, the first dielectric layer has a higher etching rate than the second dielectric layer, and in the second etching process, the first dielectric layer has a lower etching rate than the second dielectric layer.

[0068] Example 3 is the method according to Example 1, wherein the first etching process and the second etching process result in the gate isolation region having a recessed sidewall facing the trench.

[0069] Example 4 is the method according to Example 1, further including: forming a dielectric dummy fin protruding from isolation regions located on opposite sides of the dielectric dummy fin, and the gate isolation region having a bottom surface contacting the dielectric dummy fin.

[0070] Example 5 is the method according to Example 1, further including: forming a shallow trench isolation region extending into the semiconductor substrate, wherein the gate isolation region has a bottom surface contacting the shallow trench isolation region.

[0071] Example 6 is the method according to Example 1, wherein the dummy gate stack extends over two adjacent semiconductor fins.

[0072] Example 7 is the method according to Example 1, wherein the dummy gate stack extends over two adjacent stacks of a stack layer, and each stack of the stack layer includes alternating channel layers and sacrificial films, and the method further includes removing the sacrificial films.

[0073] Example 8 is a semiconductor structure, comprising: a first semiconductor region and a second semiconductor region; a first gate stack and a second gate stack, the first gate stack and the second gate stack being located on the first semiconductor region and the second semiconductor region respectively; a dielectric region located between the first semiconductor region and the second semiconductor region; and a gate isolation region located between the first gate stack and the second gate stack, wherein a bottom surface of the gate isolation region contacts the dielectric region, and wherein, in a plan view of the gate isolation region, the gate isolation region has a recessed sidewall contacting the first gate stack and the second gate stack.

[0074] Example 9 is the structure of Example 8, further comprising: a first gate spacer and a second gate spacer, the first gate spacer and the second gate spacer being located on opposite sides of the gate isolation region and contacting the gate isolation region.

[0075] Example 10 is the structure of Example 9, wherein each of the first gate spacer and the second gate spacer further contacts the first gate stack and the second gate stack.

[0076] Example 11 is the structure of Example 8, wherein the gate isolation region has a bottom portion contacting the dielectric region, and wherein an upper portion of the bottom portion is narrower than a corresponding lower portion of the bottom portion.

[0077] Example 12 is the structure of Example 11, wherein the gate isolation region comprises: a first dielectric layer, the first dielectric layer comprising: a bottom portion; and two sidewall portions located above opposite ends of the bottom portion and connected to the opposite ends of the bottom portion; and a second dielectric layer located between the two sidewall portions.

[0078] Example 13 is the structure of Example 12, wherein the first dielectric layer and the second dielectric layer are formed of different materials.

[0079] Example 14 is the structure of Example 12, wherein the first dielectric layer and the second dielectric layer are formed of the same material, and the second dielectric layer is more porous than the first dielectric layer.

[0080] Example 15 is a semiconductor structure, comprising: a first gate stack including a first gate dielectric and a first gate electrode overlapping a first bottom portion of the first gate dielectric; a second gate stack including a second gate dielectric and a second gate electrode overlapping a second bottom portion of the second gate dielectric; a first gate spacer; and a gate isolation region located between the first gate stack and the second gate stack, wherein the gate isolation region includes a first dielectric layer having a bottom portion and two sidewall portions located above and connected to opposite ends of the bottom portion, wherein the first dielectric layer forms a first interface with the first gate stack and a second interface with the first gate spacer, and the first interface and the second interface form an acute angle; and a second dielectric layer located between the two sidewall portions.

[0081] Example 16 is the structure of Example 15, further comprising: a second gate spacer, wherein both the first gate spacer and the second gate spacer are in contact with the gate isolation region.

[0082] Example 17 is the structure of Example 15, wherein the first dielectric layer and the second dielectric layer are formed of different materials.

[0083] Example 18 is the structure of Example 15, wherein the first dielectric layer and the second dielectric layer are formed of the same material and have different density values.

[0084] Example 19 is the structure of Example 15, wherein both the first dielectric layer and the second dielectric layer are in contact with both the first gate stack and the second gate stack.

[0085] Example 20 is the structure of Example 15, further comprising: a third dielectric layer located between the first dielectric layer and the second dielectric layer.

Claims

1. A method for forming a semiconductor structure, comprising: forming a dielectric dummy fin protruding from an isolation region, wherein the isolation region is located on opposite sides of the dielectric dummy fin; forming a dummy gate stack on the dielectric dummy fin; etching the dummy gate stack to form an opening; depositing a first dielectric layer extending into the opening; depositing a second dielectric layer on the first dielectric layer, and the second dielectric layer extends into the opening; performing a planarization process to form a gate isolation region including the first dielectric layer and the second dielectric layer, wherein the gate isolation region has a bottom surface contacting the dielectric dummy fin; removing a portion of the dummy gate stack on opposite sides of the gate isolation region to form a trench; performing a first etching process to remove sidewall portions of the first dielectric layer; performing a second etching process to thin the second dielectric layer; and forming a replacement gate in the trench.

2. The method according to claim 1, wherein, in the first etching process, the first dielectric layer has a higher etching rate than the second dielectric layer, and in the second etching process, the first dielectric layer has a lower etching rate than the second dielectric layer.

3. The method according to claim 1, wherein, the first etching process and the second etching process cause the gate isolation region to have a recessed sidewall facing the trench.

4. The method according to claim 1, wherein, the replacement gate contacts opposite sidewalls of the dielectric dummy fin.

5. The method according to claim 1, wherein, the dummy gate stack extends over two adjacent semiconductor fins.

6. The method according to claim 1, wherein, the dummy gate stack extends over two adjacent stacks of a stack layer, and each stack of the stack layer includes alternating channel layers and sacrificial films, and the method further includes removing the sacrificial films.

7. A semiconductor structure, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a dielectric dummy fin located between the isolation regions and protruding above a top surface of the isolation region; a first semiconductor region and a second semiconductor region located on opposite sides of the dielectric dummy fin; a first gate stack and a second gate stack located on the first semiconductor region and the second semiconductor region, respectively; a dielectric region located between the first semiconductor region and the second semiconductor region; and a gate isolation region located between the first gate stack and the second gate stack, wherein a bottom surface of the gate isolation region contacts a top surface of the dielectric dummy fin.

8. The structure according to claim 7, further comprising: A first gate spacer and a second gate spacer, the first gate spacer and the second gate spacer being located on opposite sides of the gate isolation region and in contact with the gate isolation region.

9. The structure according to claim 8, wherein, each of the first gate spacer and the second gate spacer further contacts the first gate stack and the second gate stack.

10. The structure according to claim 7, wherein, the gate isolation region has a bottom portion in contact with the dielectric region, and wherein an upper portion of the bottom portion is narrower than a corresponding lower portion of the bottom portion.

11. The structure according to claim 10, wherein, the gate isolation region includes: a first dielectric layer, the first dielectric layer including: a bottom portion; and two sidewall portions located above opposite ends of the bottom portion and connected to the opposite ends of the bottom portion; and a second dielectric layer located between the two sidewall portions.

12. The structure according to claim 11, wherein, the first dielectric layer and the second dielectric layer are formed of different materials.

13. The structure according to claim 11, wherein, the first dielectric layer and the second dielectric layer are formed of the same material, and the second dielectric layer is more porous than the first dielectric layer.

14. A semiconductor structure, comprising: a semiconductor substrate; an isolation region extending into the semiconductor substrate; a dielectric dummy fin located between the isolation regions and protruding above a top surface of the isolation region; a first gate stack located on opposite sides of the dielectric dummy fin, the first gate stack including: a first gate dielectric; and a first gate electrode overlapping a first bottom portion of the first gate dielectric; a second gate stack located on opposite sides of the dielectric dummy fin, the second gate stack including: a second gate dielectric; and a second gate electrode overlapping a second bottom portion of the second gate dielectric; a first gate spacer; and a gate isolation region located between the first gate stack and the second gate stack, wherein a bottom surface of the gate isolation region contacts a top surface of the dielectric dummy fin, and the gate isolation region includes: a first dielectric layer including a bottom portion and two sidewall portions located above opposite ends of the bottom portion and connected to the opposite ends of the bottom portion, wherein the first dielectric layer forms a first interface with the first gate stack and a second interface with the first gate spacer, and the first interface and the second interface form an acute angle; and a second dielectric layer located between the two sidewall portions.

15. The structure according to claim 14, further comprising: A second gate spacer, wherein both the first gate spacer and the second gate spacer are in contact with the gate isolation region.

16. The structure according to claim 14, wherein, the first dielectric layer and the second dielectric layer are formed of different materials.

17. The structure according to claim 14, wherein, the first dielectric layer and the second dielectric layer are formed of the same material and have different density values.

18. The structure according to claim 14, wherein, both the first dielectric layer and the second dielectric layer are in contact with both the first gate stack and the second gate stack.

19. The structure according to claim 14, further comprising: a third dielectric layer, the third dielectric layer being located between the first dielectric layer and the second dielectric layer.

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