Method for forming a semiconductor device

Abstract

Semiconductor devices employing dielectric structures and methods of forming semiconductor devices are described herein. The semiconductor devices are for wrap-around gate devices that are formed on a substrate and separated from each other by a dielectric structure. The dielectric structure is formed on a fin between two wrap-around gate devices and cuts a gate formed on the fin into two separate gates. The two wrap-around gate devices also have a bottom spacer under a source / drain region of the wrap-around gate device. The bottom spacer separates the source / drain region from the substrate. The dielectric structure has a shallow bottom that is higher than a bottom of the bottom spacer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to continuous polysilicon cross-diffusion edge structures. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to shrink the minimum structural size to improve the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, allowing more components to be integrated into a given area. However, as the minimum structural size shrinks, additional problems arise that need to be addressed. Summary of the Invention

[0004] In one embodiment, a method of forming a semiconductor device includes: forming a fin in a multilayer stack, the fin including a substrate and at least one first layer on the substrate; forming a gate on the fin; etching an opening in the fin adjacent to the gate; forming a recess along the sidewall of the opening, the recess being formed in at least one first layer; depositing spacer material in the recess; forming a bottom spacer at the bottom of the opening, the bottom spacer and the spacer material having a first interface; forming a source / drain region on the bottom spacer; and forming a dielectric structure extending through the gate into the substrate of the fin, the bottom of the dielectric structure being higher than the bottom of the bottom spacer.

[0005] In another embodiment, the method of forming a semiconductor device includes: etching a first opening through a gate, exposing a gate dielectric layer in the first opening; removing the gate dielectric layer in the first opening, wherein removing the gate dielectric layer exposes a portion of a substrate, a stack of nanowires, and an isolation region; performing an etching process to remove the stack of nanowires in the first opening and to recess a portion of the substrate to a first level between an upper surface of the isolation region and a lower surface of the isolation region; and depositing a dielectric material in the first opening, wherein the dielectric material isolates a first portion of the gate from a second portion of the gate.

[0006] In one embodiment, the semiconductor device includes: a stack of nanostructures on a first semiconductor fin, the first semiconductor fin being located on a substrate; an isolation region extending on the substrate between the first semiconductor fin and a second semiconductor fin, the isolation region having a first surface remote from the substrate and the first surface being spaced from the substrate by a first distance; a gate surrounding each nanostructure in the stack of nanostructures; and a dielectric material adjacent to the gate, the dielectric material having a first portion adjacent to the second semiconductor fin, the first portion being spaced from the substrate by a second distance, the second distance being smaller than the first distance. Attached Figure Description

[0007] Figure 1 This is a top view of a fully wound gate semiconductor device in some embodiments.

[0008] Figure 2A and 2B These are cross-sectional views of some embodiments in which a multilayer structure is formed and fins are formed in the multilayer structure.

[0009] Figure 3A and 3B In some embodiments, a cross-sectional view is formed of a dummy gate stacked on a fin.

[0010] Figures 4A to 4C This is a cross-sectional view of the openings and inner spacers in some embodiments of a multilayer structure.

[0011] Figures 5A to 5C These are cross-sectional views of the bottom spacer and source / drain regions in some embodiments.

[0012] Figure 6A and 6B These are cross-sectional views of the interlayer dielectric layer and planarization process in some embodiments.

[0013] Figures 7A to 7C These are cross-sectional views of removing the dummy gate stack, performing a wire release process, and forming the gate dielectric layer in some embodiments.

[0014] Figure 8A and 8B This is a cross-sectional view of the gate and gate cap formed in some embodiments.

[0015] Figure 9A and 9B These are cross-sectional views of openings formed during the dicing process of a metal gate in some embodiments.

[0016] Figure 10A and 10B This is a cross-sectional view of forming a cut metal gate dielectric plug in some embodiments.

[0017] Figure 11A and11B This is a cross-sectional view of an opening formed in an intermediate step of forming a continuous polysilicon cross-diffusion edge structure in some embodiments.

[0018] Figure 12A and 12B This is a cross-sectional view of the openings extended in other intermediate steps of forming a continuous polysilicon cross-diffusion edge structure in some embodiments.

[0019] Figure 13A and 13B This is a cross-sectional view of forming a continuous polysilicon cross-diffusion edge structure in a fully wound gate semiconductor device in some embodiments.

[0020] Figure 14A and 14B This is a cross-sectional view of the source / drain contact plug in some embodiments.

[0021] Explanation of reference numerals in the attached figures:

[0022] CL1: Channel Length

[0023] CW1: Channel Width

[0024] D1: First Depth

[0025] D2: Second Depth

[0026] H1: First Height

[0027] H2: Second Altitude

[0028] H3: Third Height

[0029] H4: Fourth Height

[0030] H5: The Fifth Height

[0031] H6: Sixth Height

[0032] H7: Seventh Height

[0033] H8: Eighth Height

[0034] H9: Ninth Height

[0035] L1: First Length

[0036] L5: Fifth Length

[0037] S1: First Space

[0038] Th1: First thickness

[0039] Th2: Second thickness

[0040] Th3: Third thickness

[0041] W1: First width

[0042] W2: Second width

[0043] W3: Third Width

[0044] W4: Fourth Width

[0045] W5: Fifth Width

[0046] 100: Fully wound gate semiconductor device

[0047] 101,201: Substrate

[0048] 103: Multi-layer structure

[0049] 105: Fins

[0050] 107: Gate

[0051] 109: Cutting metal gate structure

[0052] 111: Continuous polycrystalline silicon transdiffusion edge structure

[0053] 203: Multi-layer stacking

[0054] 205: First Floor

[0055] 207: Second Floor

[0056] 209: Quarantine Zone

[0057] 211: Dummy gate dielectric layer

[0058] 301: Dummy Gate Stack

[0059] 303: Dummy Gate

[0060] 305: First Hard Mask

[0061] 307: Second Hard Mask

[0062] 309: Top spacer

[0063] 401: First Opening

[0064] 403: Inner spacer

[0065] 405: Partial

[0066] 501: Bottom spacer

[0067] 503: Source / Drain Region

[0068] 507: Spacer Interface

[0069] 601: Contact Etching Stop Layer

[0070] 603: Interlayer dielectric layer

[0071] 701: Nanostructure

[0072] 703: Gate dielectric layer

[0073] 801: Gate cap

[0074] 901: Second opening

[0075] 903: Masking layer

[0076] 1003: The Third Opening

[0077] 1104: Dielectric capping layer

[0078] 1401: Source / Drain Contact

[0079] 1403: Silicide junction

[0080] 1405: Second interlayer dielectric layer

[0081] 1407: Source / Drain Via

[0082] 1409: Gate via Detailed Implementation

[0083] The different embodiments or examples provided below can implement different structures of this disclosure. Embodiments of specific components and configurations are used to simplify the content of this disclosure and not to limit it. For example, a description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of this disclosure may repeat the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or configurations do not necessarily have the same correspondence.

[0084] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90° or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0085] Figure 1 This is a top view of an intermediate structure forming a fully wound gate semiconductor device 100 in some embodiments. Specifically, Figure 1 The multilayer structure 103 shown includes multiple nanosheets formed on a semiconductor substrate 101 (illustrated in subsequent figures), fins 105 formed in the multilayer structure 103, and multiple gates 107 located on the fins 105. Figure 1It further shows multiple diced metal gate structures 109 separating the two gates 107, and a continuous polysilicon transdiffusion edge structure 111 that divides the fin 105 into two parts and intersects with the diced metal gate structures 109.

[0086] Although Figure 1 The accompanying figures show two fins 105, but it should be understood that any suitable number of fins 105 can be formed in the multilayer structure 103 to form the desired fully wound gate semiconductor device 100, depending on the number of fully wound gate semiconductor devices 100 and the desired design. Furthermore, any suitable number of gates 107, continuous polysilicon cross-diffusion edge structures 111, and diced metal gate structures 109 can be formed to form the desired fully wound gate semiconductor device 100.

[0087] Figure 1 The first tangent (X-tangent) and the second tangent (Y-tangent) of the intermediate structure are also shown. The first tangent (X-tangent) passes through the length direction that divides the fin 105 into two parts, and passes through the continuous polysilicon trans-diffusion edge structure 111. The second tangent (Y-tangent) passes through the length direction of a gate 107 separated by two diced metal gate structures 109, passes through the two diced metal gate structures 109, and passes through the continuous polysilicon trans-diffusion edge structure 111 that intersects with the two diced metal gate structures 109.

[0088] Figure 2A and 2B This is a cross-sectional view of the formation of a multilayer structure 103 and the formation of fins 105 within the multilayer structure 103 during an intermediate step in forming a fully wound gate semiconductor device 100 in some embodiments. Specifically, dopants can be implanted to Figure 1 Well regions are formed in the substrate 201 shown. In one embodiment, the substrate 201 is a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, a III-V group material substrate (e.g., gallium arsenide, gallium phosphide, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium arsenide, gallium indium phosphide, indium antimonide, gallium arsenide phosphide, or combinations thereof), or a substrate formed of other semiconductor materials (e.g., high-bandgap to band tunneling materials). The substrate 201 may or may not be doped. In some embodiments, the substrate 201 may be a base semiconductor substrate such as a base silicon substrate (e.g., a wafer), a semiconductor-on-insulator substrate, a multilayer or gradient substrate, or the like.

[0089] like Figure 2A and 2B In some embodiments shown, a multilayer structure 103 is deposited during an intermediate stage of fabricating the fully wound gate semiconductor device 100. Specifically, Figure 2A It also shows the first layer 205 and the second layer 207 formed by a series of deposition steps, and the multilayer stack 203 formed by their interleaving is located on the substrate 201.

[0090] In some embodiments, the first layer 205 may be a first semiconductor material with a first lattice constant, such as silicon-germanium, germanium, silicon, gallium arsenide, indium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or the like. In some embodiments, the method of epitaxially growing the first semiconductor material (such as silicon-germanium) layer 205 on the substrate 201 may employ deposition techniques such as epitaxial growth, vapor phase epitaxy, or molecular beam epitaxy, but may also employ other deposition processes such as chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma chemical vapor deposition, combinations thereof, or similar processes. In some embodiments, the first thickness Th1 of the first layer 205 is between about 3 nm and about 10 nm. However, any suitable thickness is within the scope of the embodiments.

[0091] Once the first layer 205 is formed on the substrate 201, the second layer 207 can be formed on the first layer 205. In some embodiments, the second layer 207 may be a second semiconductor material with a second lattice constant, such as silicon, silicon germanium, germanium, gallium arsenide, indium antimonide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or the like, and the second lattice constant is different from the first lattice constant of the first layer 205. In a specific embodiment, the first layer 205 is silicon germanium, and the second layer 207 is silicon. However, any suitable material composition can be used for the first layer 205 and the second layer 207.

[0092] In some embodiments, the deposition technique used to epitaxially grow the second layer 207 on the first layer 205 may be similar to the deposition technique used to form the first layer 205. However, the second layer 207 may employ any of the aforementioned deposition techniques or other suitable techniques suitable for forming the first layer 205. In some embodiments, the thickness of the second layer 207 may be similar to the thickness of the first layer 205. However, the thickness of the second layer 207 may also differ from the thickness of the first layer 205. In some embodiments, the second thickness Th2 of the second layer 207 is between about 5 nm and about 15 nm. However, any suitable thickness may be used.

[0093] Once the second layer 207 is formed on the first layer 205, the deposition process can be repeated to form the remaining material layers in an alternating series of the first layer 205 and the second layer 207 until the top layer required to form the multilayer stack 203 is formed. In this embodiment, the first layer 205 may have the same or similar first thickness, and the second layer 207 may have the same or similar second thickness. However, the first layer 205 may have different thicknesses from each other, and / or the second layer 207 may have different thicknesses from each other, and the first layer 205 and the second layer 207 may have any combination of thicknesses. In this embodiment, the top layer of the multilayer stack 203 is the second layer 207. However, in other embodiments, the top layer of the multilayer stack 203 may be the first layer 205. Furthermore, although the embodiments described herein include three first layers 205 and three second layers 207, the multilayer stack 203 may have any suitable number of layers (such as nanosheets). For example, the multilayer stack 203 may contain multiple nanosheets, such as between 2 and 10 nanosheets. In some embodiments, the multilayer stack 203 may include the same number of first layers 205 and second layers 207; however, in other embodiments, the number of first layers 205 and second layers 207 may be different. In some embodiments, the first height H1 of the multilayer stack 203 may be between about 12 nm and about 100 nm. However, any suitable height may be used.

[0094] exist Figure 2A and 2B In some embodiments shown, a patterning process for a multilayer structure 103 and the formation of an isolation region 209 may be performed during an intermediate stage of fabricating the fully wound gate semiconductor device 100. A patterning process is employed to form fins 105 in the multilayer structure 103 and trenches are formed between the fins 105 to prepare for the formation of the isolation region 209. In some embodiments, the patterning process for forming the fins 105 includes applying photoresist to the multilayer stack 203 and patterning and developing the photoresist to form a mask on the multilayer stack 203. Once the mask is formed, the mask pattern is then transferred to a lower layer during an etching process, such as an isotropic etching process, and trenches are formed through the multilayer stack 203 to the substrate 201 to define the fins 105, wherein the trenches separate the fins 105.

[0095] Furthermore, although a single masking process is described, this is illustrative and not a limitation of the embodiment. Any suitable method can be used to pattern the full-wrap gate device structure. For example, one or more photolithography processes can be used to pattern the structure, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are used to pattern the full-wrap gate structure.

[0096] In one embodiment, a dielectric material is deposited in a trench to form an isolation region 209, such as a shallow trench isolation region. In some embodiments, the dielectric material used to form the isolation region 209 may be an oxide material (such as a flowable oxide), a high-density plasma oxide, or the like. After cleaning and lining the trench as appropriate, a dielectric material may be formed using chemical vapor deposition (such as a high aspect ratio process), high-density plasma chemical vapor deposition, or other suitable methods to fill or overfill the area surrounding the fin 105. In some embodiments, a post-placement annealing process (such as oxide densification) may be performed to densify the material of the isolation region 209 and reduce its wet etch rate. Chemical mechanical planarization, etching, or a combination thereof may be performed to remove any excess material from the isolation region 209.

[0097] Once the dielectric material is deposited to fill or overfill the area surrounding the fin 105, the dielectric material can then be recessed from the surface of the fin 105 to form an isolation region 209. The recessing process can be performed to expose at least a portion of the sidewalls of the fin 105 adjacent to the upper surface of the fin 105. The method for recessing the dielectric material can be wet etching, such as immersing the upper surface of the fin 105 in an etchant selective for the dielectric material. Other methods such as reactive ion etching, dry etching, chemical oxide etching, or dry chemical cleaning can also be used.

[0098] like Figure 2A and 2BAs shown, a dummy gate dielectric layer 211 is formed on the exposed portion of the fin 105. Once the isolation region 209 is formed, the dummy gate dielectric layer can be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art for forming a gate dielectric layer. The thickness of the dummy gate dielectric layer 211 on the top may differ from the thickness of the dummy gate dielectric layer 211 on the sidewalls, depending on the gate dielectric layer formation technique. In some embodiments, the dummy gate dielectric layer 211 may be formed by depositing a material such as silicon, followed by oxidizing or nitriding a silicon layer to form a dielectric layer such as silicon oxide or silicon oxynitride. In these embodiments, the thickness of the dummy gate dielectric layer 211 may be between approximately to approximately Between, for example, about In other embodiments, the dummy gate dielectric layer 211 may be composed of a high dielectric constant material such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or a combination thereof, with an equivalent oxide thickness between approximately to approximately Between, for example, less than or equal to approximately In addition, any combination of silicon oxide, silicon oxynitride, and / or high dielectric constant materials can be used for the dummy gate dielectric layer 211.

[0099] like Figure 3A and 3B In some embodiments shown, a dummy gate stack 301 is formed on the fin 105. In some embodiments, the dummy gate stack 301 includes a dummy gate dielectric layer 211, a dummy gate 303 on the dummy gate dielectric layer 211, a first hard mask 305 on the dummy gate 303, and a second hard mask 307 on the first hard mask 305.

[0100] In some embodiments, the conductive material included in the dummy gate 303 may be polysilicon, tungsten, aluminum, aluminum copper, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or similar materials. The deposition method of the dummy gate 303 may be chemical vapor deposition, sputtering deposition, or other known techniques in this art for depositing conductive materials. The thickness of the dummy gate 303 may be approximately [missing information - likely a number]. to approximately The dummy gate 303 may have a non-flat upper surface, and the upper surface of the dummy gate 303 may be planarized before patterning or etching the gate. In this case, ions may or may not be introduced into the dummy gate 303. For example, ions may be introduced using ion implantation techniques.

[0101] Once the dummy gate 303 is formed, the dummy gate dielectric layer 211 and the dummy gate 303 can be patterned. In one embodiment, the patterning method may first form a first hard mask 305 on the dummy gate 303, and then form a second hard mask 307 on the first hard mask 305.

[0102] In some embodiments, the first hard mask 305 may comprise a dielectric material such as silicon nitride, oxide, silicon oxide, titanium nitride, silicon oxynitride, combinations thereof, or the like. The formation process of the first hard mask 305 may be chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar processes. However, any other suitable materials and formation methods may be used. The thickness of the first hard mask 305 may be between approximately... to approximately Between, for example, about

[0103] The second hard mask 307 comprises a different dielectric material than the first hard mask 305. The second hard mask 307 may contain any material and process suitable for forming the first hard mask 305, and the thickness of the second hard mask 307 may be the same as or similar to that of the first hard mask 305. In embodiments where the first hard mask 305 comprises silicon nitride, the second hard mask 307 may be an oxide. However, any suitable dielectric material, process, and thickness may be used to form the second hard mask.

[0104] Once the first hard mask 305 and the second hard mask 307 are formed, they can be patterned. In one embodiment, the patterning method for the first hard mask 305 and the second hard mask 307 may involve first placing a photoresist (not shown) on the first hard mask 305 and the second hard mask 307, and then exposing the photoresist with a patterning energy source (such as light) to initiate a chemical reaction to adjust the physical properties of the exposed portion of the photoresist. Next, a first developer (not shown) may be applied to develop the photoresist, and the difference in physical properties between the exposed and unexposed areas may be used to selectively remove the exposed or unexposed areas.

[0105] Once the photoresist is patterned, it can be used as a mask to pattern the underlying first hard mask 305 and second hard mask 307. In one embodiment, the patterning method for the first hard mask 305 and second hard mask 307 can be one or more reactive ion etching processes using photoresist as a mask, and the patterning process can continue until the dummy gate 303 under the first hard mask 305 is exposed.

[0106] Once the first hard mask 305 and the second hard mask 307 are patterned, the photoresist can be removed using methods such as ashing, for example, by raising the photoresist temperature until the photoresist is thermally decomposed. The decomposed photoresist can then be easily removed using one or more cleaning processes. However, any other suitable removal process can be used.

[0107] Once the first hard mask 305 and the second hard mask 307 are patterned, the dummy gate 303 and the dummy gate dielectric layer 211 can be patterned to form a series of dummy gate stacks 301. In one embodiment, the dummy gate 303 and the dummy gate dielectric layer 211 are patterned using an isotropic etching process (such as reactive ion etching), but any suitable process can be used.

[0108] like Figure 3A and 3B As shown, a top spacer 309 is formed. In one embodiment, a spacer material is formed by blanket deposition on the dummy gate stack 301 and the multilayer structure 103. In this way, the spacer material can be deposited on the upper surface and sidewalls of the dummy gate stack 301, the upper surface and sidewalls of the fins 105, and the upper surface of the isolation region 209. In some embodiments, the spacer material comprises a dielectric material, and its formation method may employ chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, thermal oxidation, or any other suitable method. In some embodiments, the spacer material may be silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, any suitable material such as a low dielectric constant material with a dielectric constant below about 4.0, combinations thereof, or the like.

[0109] Once the spacer material is formed, it can be etched to shape the top spacer 309 on the dummy gate stack 301 and fin 105, exposing the top of the dummy gate stack 301 and fin 105. In some embodiments, anisotropic etching processes (such as dry etching processes, like reactive ion etching processes), isotropic etching processes (such as wet etching processes), combinations thereof, or similar processes can be used to etch the spacer material. In some embodiments, during the etching process and / or subsequent etching processes, the spacer material formed on the fin 105 in the source / drain region can be recessed to expose portions along the sidewalls of the fin 105 in the source / drain region.

[0110] Although the embodiments use a single spacer material, this is illustrative and not limiting. Rather, any number of spacer materials and any combination of deposition and removal processes can be used, and all of these processes are entirely within the scope of the embodiments.

[0111] Figures 4A to 4CThis is a cross-sectional view of the formation of the first opening 401 and the inner spacer 403 in the fin 105 in some embodiments. When forming the top spacer 309, the spacer material used for the top spacer 309 can be removed to expose the multilayer stack 203 again. Once the multilayer stack 203 is exposed, an etching process can be performed to remove material from the multilayer stack 203 and the substrate to form the first opening 401 (such as a trench, recess, channel, or similar structure) extending through the multilayer stack 203 into the semiconductor substrate 101 to prepare for the formation of source / drain regions therein. In one embodiment, one or more anisotropic etching passes, such as reactive ion etching, can be used, but any suitable process can be employed.

[0112] In one embodiment, the first width W1 of the first opening 401 may be between about 10 nm and about 40 nm, such as about 20 nm. Furthermore, the first depth D1 of the first opening 401 extending into the substrate 101 may be between about 3 nm and about 40 nm, such as about 10 nm. However, any suitable size may be used.

[0113] like Figures 4A to 4C As shown, an inner spacer 403 is formed in the first layer 205. Specifically, Figure 4C show Figure 4A The enlarged view of portion 405, highlighted by dashed lines, is shown below in conjunction with the description of the formation of the inner spacer 403. In some embodiments, the inner spacer 403 may be formed by wet etching to pattern recesses, where the etchant used has higher selectivity for the material of the first layer 205 (e.g., silicon-germanium) than for the material of the second layer 207 or the substrate 201 (e.g., silicon). For example, in an embodiment where the first layer 205 is silicon-germanium and the second layer 207 is silicon, the etchant used for wet etching may be hydrogen chloride.

[0114] In one embodiment, wet etching processes such as immersion, spraying, spin etching, or similar processes can be performed, using any suitable process temperature (between about 400°C and about 600°C) and any suitable process time (between about 100 seconds and about 1000 seconds, such as about 300 seconds). However, any suitable process conditions and parameters can be used. A continuous etching process allows recesses with crystal-plane-constrained surfaces to be formed in each of the first layer 205, and the recesses can be reached from the sidewalls of the first opening 401 at any desired distance.

[0115] Furthermore, the selectivity of the etchant can be chosen. In some embodiments, an etching process can also be performed to remove portions of the second layer 207 and the substrate 201, such that the recess extends vertically to any suitable height in the sidewall direction of the first opening 401, as described below.

[0116] However, wet etching is not the only process for recessing the first layer 205. For example, in another embodiment, the step of recessing the first layer 205 may be an isotropic dry etching process, or a combination of dry etching and wet etching. Any suitable process can be used to recess the first layer 205, and these processes are entirely within the scope of the embodiments.

[0117] Once a recess is formed in each of the first layers 205, spacer material is formed on the multilayer structure 103. In some embodiments, the spacer material may differ from the material of the top spacer 309 and may be a silicon-containing dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, any suitable material such as a low dielectric constant material with a dielectric constant less than 4.0, or even an air gap, or a combination thereof. The spacer material may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to a thickness between about 2 nm and about 10 nm (e.g., about 5 nm). However, any suitable thickness or deposition process may be used.

[0118] By depositing spacer material onto the multilayer structure 103, the spacer material can line the sidewalls of the first opening 401 and fill the recesses in the first layer 205. Once the spacer material has filled the recesses, a removal process can then be performed to remove any excess spacer material from the first opening 401 and retain the inner spacer 403. In one embodiment, the method for removing excess spacer material can employ an etching process such as an isotropic dry etching process (e.g., reactive ion etching). However, any suitable etching conditions can be used to remove excess spacer material from the first opening 401 and retain the inner spacer 403.

[0119] By filling the recess with spacer material and removing excess spacer material from the first opening 401, the inner spacer 403 can have a recessed shape. Furthermore, although the inner spacer 403 formed in the embodiment has a crystal plane shape, this is illustrative and not limiting. Conversely, any suitable shape can be used, such as a recessed shape or a raised shape, even making the inner spacer 403 recessed. All of these shapes are entirely within the scope of the embodiments. In some embodiments, the second width W2 of the inner spacer 403 can be between about 2 nm and about 10 nm (e.g., about 5 nm), and its second height H2 can be between about 5 nm and about 20 nm (e.g., about 10 nm). Furthermore, the spacing of the inner spacers 403 has a first space S1, which is between about 3 nm and about 10 nm, e.g., about 5 nm. However, any suitable width, height, and spacing can be used.

[0120] Figure 4CThe relative dimensions of the first layer 205, the second layer 207, and the inner spacer 403 are also shown. In some embodiments, the second height H2 of the inner spacer 403 is greater than the height of the first layer 205 (e.g., the first thickness Th1). In some embodiments, the first space S1 between the inner spacers 403 is less than the second thickness Th2 of the second layer 207. However, any suitable dimensions may be used.

[0121] Figures 5A to 5C These are cross-sectional views of the bottom spacer 501 and the source / drain region 503 in some embodiments. Specifically, Figure 5C show Figure 5A Enlarged view of the part 505 emphasized by the dashed line.

[0122] Once the inner spacer 403 is formed, a bottom spacer 501 can be formed at the bottom of the first opening 401 using a semiconductor material (such as silicon-germanium), but other materials suitable for forming the first layer 205 can also be used. In some embodiments, the bottom spacer 501 is composed of silicon-germanium, and its epitaxial growth at the bottom of the first opening 401 can be achieved using deposition techniques such as epitaxial growth, vapor phase epitaxy, or molecular beam epitaxy. However, any other deposition process suitable for forming the first layer 205 can also be used.

[0123] Once the spacer 501 is deposited, an oxidation process can be performed to increase the density and / or dielectric constant of the spacer 501. In this way, the spacer 501 can be composed of silicon-germanium oxides such as silicon-germanium oxide, silicon-germanium oxynitride, silicon-germanium carbonitride, or the like. Following the oxidation process, an etching process (such as wet etching) can be performed to remove any oxides formed along the sidewalls of the first opening 401 and / or to recess the spacer 501 to the desired height. In some embodiments, the third height H3 of the spacer 501 is between about 3 nm and about 30 nm, for example, about 20 nm. However, any suitable height can be used.

[0124] Once the bottom spacer 501 reaches the desired height, a post-placement annealing process can be performed to remove germanium from the material of the bottom spacer 501. In some embodiments, the annealing process includes one or more annealing processes, such as steam annealing, high-temperature annealing, a combination of the above, or similar processes, which may be performed in a furnace or in a rapid thermal process chamber. In some embodiments, the post-placement annealing process may include dry annealing, for example, at a process temperature of about 500°C to about 700°C (e.g., about 600°C) under nitrogen and for about 30 minutes to about 180 minutes (e.g., about 60 minutes). However, any suitable oxygen source, process temperature, and process time can be used. Once the post-placement annealing process is completed, the germanium can be removed and the bottom spacer 501 can be converted into a dielectric material such as silicon nitride, oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, or the like.

[0125] Figure 5C The spacer interface 507 between the bottommost spacer of the inner spacer 403 and the bottom spacer 501 is also shown. In some embodiments, the first length L1 of the spacer interface 507 is between about 3 nm and about 15 nm, such as about 5 nm. However, the spacer interface 507 can take any suitable length.

[0126] In some embodiments, the bottom spacer 501 may be formed by depositing a second spacer material such as silicon oxynitride, and the deposition process may employ chemical vapor deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar processes. However, any suitable spacer material and deposition process may be used, such as materials and processes suitable for forming the top spacer 309. In some embodiments, the second spacer material is different from the materials of the top spacer 309 and the inner spacer 403, and the second spacer material may be deposited to fill and / or overfill the first opening 401.

[0127] Once the second spacer material is deposited, it can be etched to recess the bottom spacer 501 to the desired third height H3, exposing the sidewalls above the first opening 401 of the bottom spacer 501. In some embodiments, the etching method for the second spacer material may employ anisotropic etching processes (such as dry etching processes, e.g., reactive ion etching processes), isotropic etching processes (such as wet etching processes), combinations thereof, or similar processes. The etchant that recesses the bottom spacer 501 is selective for the second spacer material without significantly removing the material from the top spacer 309, the second layer 207, and the inner spacer 403.

[0128] Once the bottom spacer 501 is formed, the source / drain regions 503 can be formed on the bottom spacer 501. The source / drain regions 503 can be formed using growth processes such as selective epitaxial growth to form a suitable semiconductor material required for the device. For example, in embodiments where the source / drain regions 503 are used to form an n-type metal-oxide-semiconductor device, the source / drain regions 503 can be semiconductor materials such as silicon, silicon phosphide, silicon carbide, combinations thereof, or the like.

[0129] The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, or the like, and may last from about 5 minutes to about 120 minutes (e.g., about 30 minutes). In some embodiments, the fourth height H4 of the source / drain region 503 is between about 30 nm and about 90 nm, such as about 50 nm. However, any suitable height and / or suitable depth may be used.

[0130] Once the source / drain region 503 is formed, suitable dopants can be implanted into the source / drain region 503 to supplement the dopants in the remaining portion of the first device region. For example, n-type dopants such as phosphorus, carbon, arsenic, silicon, antimony, the like, or combinations thereof (such as silicon phosphide, silicon carbide, silicon carbide phosphide, silicon arsenide, silicon, antimony, or the like) can be implanted to form an n-type metal-oxide-semiconductor field-effect transistor device. A dummy gate stack 301 and a top spacer 309 can be used as a mask to implant these dopants.

[0131] In another embodiment, dopants in the source / drain region 503 can be introduced during the growth of the source / drain region 503. For example, phosphorus can be introduced in situ during the formation of the source / drain region 503. Any suitable process can be used to introduce dopants into the source / drain region 503, and all such processes are within the scope of the embodiments. Furthermore, an annealing process can be performed to activate the dopants in the source / drain region 503. During the annealing process, the dopants in the source / drain region 503 can laterally diffuse into the second layer 207 at the interface between the second layer 207 and the source / drain region 503. In this way, a lightly doped drain region can be formed in the second layer 207.

[0132] Figure 6A and 6B This is a cross-sectional view of the junction etch stop layer 601 and the interlayer dielectric layer 603 in some embodiments. For example... Figure 6A and 6B As shown, the first hard mask 305 and the second hard mask 307 are removed, and the contact etching stop layer 601, interlayer dielectric layer 603, dummy gate 303, and top spacer 309 are planarized.

[0133] The contact etch stop layer 601 is formed in Figures 5A to 5C In the structure shown, the interlayer dielectric layer 603 is formed on the contact etch stop layer 601. The contact etch stop layer 601 can serve as an etch stop layer in subsequent etch processes and may contain suitable materials such as silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or similar materials, and its formation method may be a suitable formation method such as chemical vapor deposition, physical vapor deposition, combinations thereof, or similar methods.

[0134] The interlayer dielectric layer 603 may comprise silicon oxide, a low dielectric constant dielectric material (such as a material with a dielectric constant lower than that of silicon oxide), such as silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicon glass, silicon oxycarbonate, spin-coated glass, spin-coated polymer, silicon carbide, the above-mentioned compounds, the above-mentioned composites, analogs, or combinations thereof, but any suitable dielectric layer may also be used. The interlayer dielectric layer 603 may be formed using plasma-assisted chemical vapor deposition, but other processes such as low-pressure chemical vapor deposition may also be used.

[0135] Once the interlayer dielectric layer 603 and the contact etch stop layer 601 are formed, a planarization process such as chemical mechanical planarization can be used to planarize both of them with the dummy gate 303 and the top spacer 309. However, any suitable planarization process can be used. Furthermore, the first hard mask 305 and the second hard mask 307 can be removed during the planarization process. In some embodiments, one or more etching processes and / or chemical mechanical planarization can be used to remove the first hard mask 305 and the second hard mask 307. In this way, the dummy gate 303 can be exposed after the first hard mask 305 is removed.

[0136] Figure 7A and 7B This is a cross-sectional view of some embodiments with the dummy gate 303 and dummy gate dielectric layer 211 removed. Figure 7A and 7B In some embodiments, a circuit release process is used to form a nanostructure 701 from the second layer 207. Figure 7A and 7B In some embodiments, a gate dielectric layer 703 is formed on the nanostructure 701.

[0137] Once the dummy gate 303 is exposed, it can be removed to expose the underlying dummy gate dielectric layer 211. In one embodiment, the dummy gate 303 can be removed using one or more wet etching or dry etching processes, employing an etchant selective for the dummy gate 303. However, any suitable removal process can be used.

[0138] Once the dummy gate dielectric layer 211 is exposed, it can be removed. In one embodiment, the dummy gate dielectric layer 211 can be removed using a wet etching process, but any suitable etching process can be used.

[0139] like Figure 7A and 7BAs shown, once the dummy gate dielectric layer 211 is removed and the side portion of the first layer 205 is exposed, the first layer 205 can be removed from between the substrate 201 and the second layer 207 in the linear release process step. The linear release process step can also be considered as a sheet release process step, a sheet formation process step, a nanosheet formation process step, or a line formation process step. In one embodiment, the removal method of the first layer 205 can employ an etching process, which can selectively remove the material of the first layer 205 (such as silicon-germanium) without significantly removing the material of the substrate 201 and the second layer 207 (such as silicon). However, any suitable removal process can be used.

[0140] For example, one embodiment may use an etchant such as high-temperature hydrogen chloride to selectively remove the material of the first layer 205 (e.g., silicon-germanium) without substantially removing the material of the substrate 201 and / or the second layer 207 (e.g., silicon). Furthermore, the temperature of the wet etching process may be between about 400°C and about 600°C (e.g., about 560°C), and the time may be between about 100 seconds and about 600 seconds (e.g., about 300 seconds). However, any suitable etchant, process parameters, and time may be used.

[0141] By removing the material of the first layer 205, the second layer 207 can be exposed (e.g., ...). Figure 7A and 7B The nanostructure 701 (as indicated in the diagram) has sidewalls. The nanostructures 701 are spaced apart by inner spacers 403. In some embodiments, the space between the nanostructures 701 is between about 5 nm and about 15 nm, for example, about 10 nm. The nanostructure 701 includes a channel region between the source / drain regions 503 on both sides, with a channel length CL1 between about 5 nm and about 180 nm (for example, about 10 nm) and a channel width CW1 between about 8 nm and about 100 nm (for example, about 30 nm). In one embodiment, the thickness of the nanostructure 701 is the same as the original thickness of the second layer 207 (for example, between about 3 nm and about 15 nm, such as about 8 nm), but the thickness of the nanostructure 701 can also be reduced by an etching process.

[0142] In some embodiments, the linear release process may, when removing the first layer 205, partially remove material from the second layer 207 (e.g., through etching). This reduces the thickness of the nanosheet structure 701 compared to the original thickness of the second layer 207. Consequently, the third thickness Th3 of the nanostructure 701 can be less than the original thickness of the second layer 207 (e.g., the second thickness Th2). Furthermore, in this partial removal process, the top spacer 309 and the inner spacer 403 protect adjacent material of the second layer 207 from removal. This prevents further reduction in the thickness of the distal portion of the nanostructure 701 during the linear release process.

[0143] In addition, although Figures 7A to 7C Three nanostructures 701 are shown, but the number of nanostructures 701 formed from the nanosheets provided by the multilayer stack 203 can be any suitable number. For example, the multilayer stack 203 can contain any suitable number of first layers 205 and any suitable number of second layers 207. In this way, after removing the first layer 205, the multilayer stack 203 containing fewer first layers 205 and fewer second layers 207 will form one or two nanostructures 701. After removing the first layer 205, the multilayer stack 203 containing many first layers 205 and many second layers 207 will form four or more nanostructures 701.

[0144] Figure 7A and 7B Also shown in some embodiments, a gate dielectric layer 703 is formed on the nanostructure 701. In one embodiment, the gate dielectric layer 703 comprises a material with a high dielectric constant (greater than or equal to 9), such as tantalum oxide, aluminum oxide, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, lanthanum oxide (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, lanthanum oxide, zirconium oxide, or titanium oxide), combinations thereof, or the like, and its deposition process may be atomic layer deposition, chemical vapor deposition, or a similar process. In some embodiments, the gate dielectric layer 703 comprises a nitrogen-doped oxide dielectric layer, which may be formed prior to the formation step of a dielectric material with a high dielectric constant (greater than 13) of metallic composition. The deposition thickness of the gate dielectric layer 703 may be between about 1 nm and about 3 nm, but any suitable material and thickness may be used. As shown in the figure, the gate dielectric layer 703 covers the nanostructure 701, thus forming a channel region between the source / drain regions 503.

[0145] Figure 8A and 8B This is a cross-sectional view of the formation of gate 107 and gate cap 801 in some embodiments. Once the gate dielectric layer 703 is formed, gate 107 can be formed to surround nanostructure 701. In some embodiments, gate 107 may be multilayered, and the method of depositing each layer sequentially may employ a compliant deposition process such as atomic layer deposition, but any suitable deposition process may be used. In some embodiments, gate 107 may include a capping layer, a barrier layer, an n-type metal work function layer, a p-type metal work function layer, and a filler material.

[0146] A capping layer may be formed adjacent to the gate dielectric layer 703, and the capping layer may be composed of metallization materials such as tantalum nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar. The deposition process of the metallization material may be atomic layer deposition, chemical vapor deposition, or similar processes, but any suitable deposition process may be used.

[0147] A barrier layer may be formed adjacent to the capping layer, and the materials of the barrier layer and the capping layer may be different. For example, the barrier layer may be one or more metallized materials such as titanium nitride, tantalum nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar materials. The barrier layer may be deposited using atomic layer deposition, chemical vapor deposition, or similar processes, but any suitable deposition process may be used.

[0148] An n-type metal work function layer can be formed adjacent to the barrier layer. In one embodiment, the material of the n-type metal work function layer can be tungsten, copper, aluminum copper, aluminum carbide, titanium aluminum nitride, titanium aluminum, platinum, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, silver, aluminum, tantalum aluminum, tantalum aluminum carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type work function materials, or combinations thereof. For example, the deposition method of the first n-type metal work function layer can employ atomic layer deposition, chemical vapor deposition, or similar processes. However, any suitable materials and processes can be used to form the n-type metal work function layer.

[0149] A p-type metal work function layer can be formed adjacent to an n-type metal work function layer. In one embodiment, the first p-type metal work function layer may be composed of metallization materials such as tungsten, aluminum, copper, titanium nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum, tantalum nitride, cobalt, nickel, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, tantalum silicide, nickel silicide, manganese, zirconium, zirconium silicide, ruthenium, aluminum copper, molybdenum, molybdenum silicide, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar materials. Furthermore, the deposition process of the p-type metal work function layer may employ atomic layer deposition, chemical vapor deposition, or similar processes, but any suitable deposition process may be used.

[0150] Once the p-type metal work function layer is formed, a filler material is deposited to fill the remaining portion of the opening. In one embodiment, the filler material may be tungsten, aluminum, copper, aluminum-copper, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or similar materials, and its formation method may employ deposition processes such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or similar processes. However, any suitable material may be used.

[0151] Once the opening left by removing the dummy gate 303 is filled, the materials of gate 107 and gate dielectric layer 703 can be planarized, removing any material outside the opening left by removing the dummy gate 303. In a specific embodiment, a planarization process such as chemical mechanical planarization can be used for the removal step, but any suitable planarization and removal process can be used. In some embodiments, the fifth length L5 of the gate can be between about 8 nm and about 30 nm. However, any suitable length can be used.

[0152] Once the gate 107 is formed, it can be recessed below the planarized surface of the in-layer dielectric layer 603. In some embodiments, an etching process such as wet etching, dry etching, a combination of the above, or a similar process can be used to recess the gate 107. Once recessed, the distance between the gate 107 and the topmost nanostructure 701 is a fifth height H5. In some embodiments, the fifth height H5 is between about 8 nm and about 30 nm. However, any suitable height can be used.

[0153] The gate cap 801 can be formed by first depositing a dielectric material on the gate 107 to fill and / or overfill the recess. In some embodiments, the gate cap 801 may be composed of a dielectric material such as silicon nitride, oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, or the like. In some embodiments, the gate cap 801 may be composed of an oxide of a metal such as zirconium, hafnium, aluminum, or the like. Furthermore, the gate cap 801 can be formed using a suitable deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the above, or a similar process. However, any suitable material and deposition process can be used. Once the gate cap 801 is deposited, a planarization process such as chemical mechanical planarization can be used to planarize the gate cap 801 and the interlayer dielectric layer 603. Once the gate cap 801 is planarized, the sixth height H6 of the gate cap 801 can be between about 10 nm and about 30 nm. However, any suitable height can be used.

[0154] Figure 9A and 9BThis is a cross-sectional view of forming the second opening 901 during the dicing metal gate process in some embodiments. Once the gate cap 801 and interlayer dielectric layer 603 are planarized, a masking layer 903 is deposited on the planarized surfaces of the gate cap 801, interlayer dielectric layer 603, contact etch stop layer 601, top spacer 309, and gate dielectric layer 703. Once the masking layer 903 is deposited, it is patterned to expose the underlying material (including the gate cap 801 and interlayer dielectric layer 603) at the desired locations where the diced metal gate structure 109 will be formed.

[0155] Once the mask layer 903 is patterned, it can be used as an etching mask to etch the underlying material, forming a second opening (such as a trench, recess, channel, or similar structure). In the etching process, an anisotropic etching process can be used to etch the material of the gate cap 801 and the gate 107, stopping at the upper surface of the gate dielectric layer 703 or the upper surface of the isolation region 209. The second opening can be formed between adjacent fins 105 and can cut through one or more gates 107. In some embodiments, two second openings 901 are formed to cut through two adjacent gates 107 and are located on both sides of a fin 105, such as... Figure 1 As shown. In some embodiments, the second opening 901 is located between the top spacers 309 of two adjacent devices. Once the second opening 901 is formed, the masking layer 903 can be removed.

[0156] Figure 10A and 10B This is a cross-sectional view of forming a diced metal gate structure 109 in some embodiments. The diced metal gate structure 109 can be formed once the second opening 901 is formed, for example, by first depositing a dielectric material to fill or overfill the second opening 901. In some embodiments, the diced metal gate structure 109 can employ any dielectric material and deposition process suitable for forming the gate cap 801. In some embodiments, the dielectric material of the diced metal gate structure 109 can be the same as the dielectric material of the gate cap 801, but the dielectric material can also be different. For example, in an embodiment where the gate cap 801 is made of silicon nitride, the diced metal gate structure 109 can be made of silicon nitride formed by atomic layer deposition. However, any suitable dielectric material and deposition process can be used. In some embodiments, the third width W3 of the diced metal gate structure 109 can be between about 5 nm and about 50 nm, for example, about 10 nm. However, any suitable width can be used.

[0157] The diced metal gate structure 109 divides the longer plurality of gates 107 into a plurality of shorter gates 107, and isolates the plurality of gates 107 from each other. Furthermore, excess dielectric material of the diced metal gate structure 109 outside the second opening 901 can be retained as a masking layer in the continuous polysilicon cross-diffusion edge process. In this way, in Figure 10BThe dashed line in the middle emphasizes the cut metal gate structure 109, which has excess dielectric material retained outside the second opening 901.

[0158] Figure 11A and 11B This is a cross-sectional view showing the formation of a third opening 1003 in the initial step of forming the continuous polysilicon trans-diffusion edge structure 111. The continuous polysilicon trans-diffusion edge structure 111 can be considered here as an isolation structure, a cleaved polysilicon structure, or a cleaved polysilicon trans-diffusion edge structure, which will be described in detail below with reference to the accompanying drawings.

[0159] Once the diced metal gate structure 109 is formed, photoresist is formed on the excess dielectric material, and openings are formed in the photoresist at the desired locations for the subsequent formation of the continuous polysilicon trans-diffusion edge structure 111. The openings in the photoresist expose a portion of the gate cap 801 between the two diced metal gate structures 109. Furthermore, the edge portions of the diced metal gate structures 109 may be exposed by the openings in the photoresist to provide some process tolerances for the continuous polysilicon trans-diffusion edge structure 111. In some embodiments, the width of the exposed edge portion may be a fourth width W4, which is between about 3 nm and about 25 nm, such as about 5 nm. However, any suitable width may be used.

[0160] Next, photoresist is used as an etching mask to etch excess dielectric material, cut the edge portions of the metal gate structure 109, the gate cap 801, and the gate 107 to form a third opening 1003 (such as a trench, recess, channel, or similar structure) at the desired location in the continuous polysilicon trans-diffusion edge structure 111. In some embodiments, the etching process may stop at the gate dielectric layer 703. In this way, the gate dielectric layer 703 and the nanostructure 701 remain at the bottom of the third opening 1003. In some embodiments, the etching process used to form the third opening 1003 may be an isotropic etching process (such as a wet etching process), in which the etchant used stops at the gate dielectric layer 703. However, other suitable etching processes may be used, including anisotropic etching processes (such as dry etching processes or reactive ion etching processes), combinations of isotropic and anisotropic etching, or similar processes. In some embodiments, the fifth width W5 of the third opening 1003 may be between about 20 nm and about 200 nm, such as about 70 nm. However, any suitable width may be used.

[0161] Figure 12A and 12BThis is a cross-sectional view of some embodiments, showing additional etching processes performed in an intermediate step of a continuous polysilicon cross-diffusion edge process. Once the gate dielectric layer 703 is exposed, another etching process can be performed to remove the material of the gate dielectric layer 703 in the third opening 1003, exposing the nanostructure 701, fins 105, and isolation region 209 in the third opening 1003. In some embodiments, wet etching, dry etching, a combination of the above, or similar processes can be used to remove the material of the gate dielectric layer 703 without substantially removing the material of the top spacer 309 and the inner spacer 403 along the vertical sidewalls of the third opening 1003. However, any suitable etching process can be used.

[0162] Once the portion of the nanostructure 701 and the fin 105 protruding above the isolation region 209 is exposed, other etching processes can be used to remove the material of the nanostructure 701 and form a recess in the fin 105. In some embodiments, etching processes such as wet etching, dry etching, a combination of the above, or similar processes can be used to remove this material without substantially removing the material of the top spacer 309, the inner spacer 403, and the isolation region 209 exposed by the third opening 1003. In one embodiment, the portion of the fin 105 protruding above the isolation region 209 can be recessed to a second depth D2, which is between about 2 nm and about 20 nm (e.g., about 10 nm). However, any suitable depth can be used. In some embodiments, the first ratio R1 between the second depth D2 and the third height H3 of the bottom spacer 501 can be between about 0.05:1 and about 1:1. Once the nanostructure 701 is removed and the portion of the fin 105 protruding above the isolation region 209 is recessed, the photoresist can be removed by methods such as ashing processes.

[0163] Figure 13A and 13BThis is a cross-sectional view of a continuous polysilicon trans-diffusion edge structure 111 formed in some embodiments. The continuous polysilicon trans-diffusion edge structure 111 may be formed by depositing a dielectric material to fill and / or overfill the third opening 1003. The composition of the continuous polysilicon trans-diffusion edge structure 111 may employ dielectric materials such as silicon nitride, oxides, silicon oxynitride, silicon carbonitride, silicon carbonitride, or the like. In some embodiments, the composition of the continuous polysilicon trans-diffusion edge structure 111 may employ oxides of metals such as zirconium, hafnium, aluminum, or the like. Furthermore, the formation method of the continuous polysilicon trans-diffusion edge structure 111 may employ suitable deposition processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or similar processes. The continuous polysilicon trans-diffusion edge structure 111 may employ any dielectric material and process suitable for forming the diced metal gate structure 109. In some embodiments, the dielectric material forming the continuous polysilicon trans-diffusion edge structure 111 may be the same as the dielectric material forming the diced metal gate structure 109, but different dielectric materials may also be used. For example, in some embodiments, the diced metal gate structure 109 is made of silicon nitride, while the continuous polysilicon trans-diffusion edge structure 111 may be made of silicon nitride (its deposition process may be chemical vapor deposition, atomic layer deposition, sputtering, or similar processes).

[0164] Once the continuous polysilicon transdiffusion edge structure 111 is formed, excess material of the continuous polysilicon transdiffusion edge structure 111, excluding the third opening 1003, can be removed by a chemical mechanical planarization process. In some embodiments, a continuous chemical mechanical planarization process is performed to planarize the continuous polysilicon transdiffusion edge structure 111, the gate 107, and the upper surface of the interlayer dielectric layer 603. Once planarized, the seventh height H7 of the continuous polysilicon transdiffusion edge structure 111 on the fin 105 can be between about 55 nm and about 140 nm, for example, about 70 nm. However, any suitable height can be used. The eighth height H8 of the gate cap 801 can be between about 10 nm and about 30 nm, for example, about 15 nm. However, any suitable height can be used. Furthermore, the ninth height H9 of the diced metal gate structure 109 can be between about 50 nm and about 120 nm, for example, about 60 nm. However, any suitable height can be used.

[0165] Figure 14A and 14B This is a cross-sectional view of the source / drain contact 1401 to the source / drain region 503 in some embodiments. Figure 14A and 14B In some of the embodiments shown, source / drain vias 1407 and gate vias 1409 are formed.

[0166] Once a continuous polysilicon cross-diffusion edge structure is formed, silicide contacts 1403 and source / drain contacts 1401 can be formed through the interlayer dielectric layer 603 to electrically connect to the source / drain region 503. In one embodiment, the silicide contacts 1403 and source / drain contacts 1401 can be formed by first forming an opening through the interlayer dielectric layer 603 to expose the source / drain region 503. The opening can be formed using a suitable photolithography masking and etching process.

[0167] The silicide contact 1403 may contain titanium, nickel, cobalt, or erbium to reduce the Schottky barrier of the source / drain contact 1401. However, other metals such as platinum, palladium, or similar materials may also be used. A suitable metal layer may be deposited as a blanket, followed by annealing to allow the metal to react with the exposed silicon in the underlying source / drain region 503 for silicide processing. The unreacted metal is then removed, possibly by a selective etching process. The thickness of the silicide contact 1403 may be between approximately 5 nm and approximately 50 nm. However, any suitable thickness may be used.

[0168] In one embodiment, the source / drain contact 1401 may be a conductive material such as aluminum, copper, tungsten, cobalt, titanium, tantalum, ruthenium, titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum carbide, nickel tungsten silicide, cobalt tungsten silicide, combinations thereof, or the like, but any suitable material may also be deposited into the opening to fill and / or overfill it. The deposition process of the conductive material may be sputtering, chemical vapor deposition, electroplating, electroless plating, or similar processes. Once the opening is filled and / or overfilled, a planarization process such as chemical mechanical planarization can be used to remove any deposited material outside the opening. However, any suitable material and formation process may be used.

[0169] Once the source / drain contacts 1401 are formed, dielectric material can be deposited on the interlayer dielectric layer 603, the contact etch stop layer 601, the top spacer 309, the gate dielectric layer 703, the gate cap 801, the diced metal gate structure 109, and the flat upper surface of the continuous polysilicon trans-diffusion edge structure 111 to form a second interlayer dielectric layer 1405. The second interlayer dielectric layer 1405 can be formed using any process and materials suitable for forming and planarizing the aforementioned interlayer dielectric layer 603.

[0170] Once the second interlayer dielectric layer 1405 is formed, a source / drain via 1407 can be formed through the second interlayer dielectric layer 1405 to electrically connect to the source / drain region 503. Additionally, a gate via 1409 can pass through the second interlayer dielectric layer 1405 and the gate cap 801 to electrically connect to the gate 107. Any suitable masking and etching process can be used to form openings through the second interlayer dielectric layer 1405 and the dielectric cap layer 1104. In some embodiments, the same etching process can be used to pattern the openings for the source / drain via 1407 and the gate via 1409 together. In other embodiments, the openings for the source / drain via 1407 and the gate via 1409 can be patterned by separate etching processes.

[0171] Once the openings for the source / drain vias 1407 and the gate via 1409 are formed, conductive material such as copper can be deposited to fill and / or overfill the openings. The deposition method can be plating, chemical vapor deposition, sputtering, a combination of the above, or similar methods. Excess material can then be removed, and the removal method can be a planarization process such as chemical mechanical planarization or similar processes.

[0172] In the embodiment described herein, the bottom spacer 501 and the bottommost spacer of the inner spacer 403 have a spacer interface 507. The length of the spacer interface 507 can be between about 3 nm and about 15 nm. This ensures that the epitaxial growth of the source / drain region 503 is separated from the substrate 201. If the first length L1 of the spacer interface 507 is too short (e.g., less than 3 nm), the epitaxial growth of the source / drain region 503 may not be separated from the substrate 201 when considering variations in etching depth. Furthermore, if the length of the spacer interface 507 is too long (e.g., greater than 15 nm) and greater than the second height H2 of the inner spacer 403, the bottom spacer 501 may block current injection from the source / drain region 503 into the nanostructure 701 during operation. This may degrade throughput and / or device performance.

[0173] By isolating the source / drain regions 503 from the substrate 201, the continuous polysilicon transdiffusion edge structure 111 can have a shallow recess into the fins 105 without cutting through the isolation region 209. In some embodiments, the second depth D2 of the shallow recess can be between about 2 nm and about 20 nm. A first ratio R1 can define the ratio between the second depth D2 of the shallow recess used to form the continuous polysilicon transdiffusion edge structure 111 and the third height H3 of the bottom spacer 501. In this way, the first ratio R1 can be used to confirm that the second depth D2 of the shallow recess can be used to form continuous polysilicon transdiffusion edge structures 111 at different technology nodes. In some embodiments, the first ratio R1 can be between about 0.05:1 and about 1:1. By forming a continuous polysilicon transdiffusion edge structure 111 with a shallow recess having a first ratio R1 that is approximately less than 1:1, a larger source / drain damage tolerance range and accurate control of the gate height can be obtained. Because of the large tolerance range for source / drain damage, the source / drain regions 503 can be formed without damage when forming the continuous polysilicon transdrain edge structure 111, even when applied to N5 technology and later technologies. Furthermore, due to precise control of the gate height, gate height loss is minimal or nonexistent when forming the continuous polysilicon transdrain edge structure 111. Thus, the continuous polysilicon transdrain edge structure 111 with a second depth D2 used for the shallow recess depth can achieve N3 technology and later technologies. Moreover, forming the continuous polysilicon transdrain edge structure 111 with a ratio R1 of at least 0.05:1 ensures effective truncation of the nanostructure 701 to isolate the source / drain regions 503 from the substrate 201 during device operation. This increases yield and / or improves device performance.

[0174] In one embodiment, a method of forming a semiconductor device includes: forming a fin in a multilayer stack, the fin including a substrate and at least one first layer on the substrate; forming a gate on the fin; etching an opening in the fin adjacent to the gate; forming a recess along the sidewall of the opening, the recess being formed in at least one first layer; depositing spacer material in the recess; forming a bottom spacer at the bottom of the opening, the bottom spacer and the spacer material having a first interface; forming a source / drain region on the bottom spacer; and forming a dielectric structure through the gate into the substrate of the fin, the bottom of the dielectric structure being higher than the bottom of the bottom spacer. In one embodiment, the thickness of the spacer material in the recess is greater than that of at least one first layer. In one embodiment, the step of forming the bottom spacer further includes forming the bottom spacer to a height between about 3 nm and about 30 nm. In one embodiment, the length of the first interface is between about 3 nm and about 15 nm. In one embodiment, the method further includes forming a diced gate dielectric layer before forming the dielectric structure. In one embodiment, the method further includes forming isolation regions on both sides of the fin, wherein the step of forming a gate includes forming a gate on the isolation region, and the bottom of the dielectric structure is horizontally located between the upper and lower surfaces of the isolation region. In one embodiment, the bottom of the dielectric structure extends horizontally into the substrate by a distance between about 2 nm and about 20 nm.

[0175] In another embodiment, a method of forming a semiconductor device includes: etching a first opening through a gate, exposing a gate dielectric layer in the first opening; removing the gate dielectric layer in the first opening, wherein removing the gate dielectric layer exposes a portion of a substrate, a stack of nanowires, and an isolation region; performing an etching process to remove the stack of nanowires in the first opening and recess a portion of the substrate to a first level between an upper surface and a lower surface of the isolation region; and depositing a dielectric material in the first opening, wherein the dielectric material isolates a first portion of the gate from a second portion of the gate. In one embodiment, the first level is at most 20 nm below the upper surface of the isolation region. In another embodiment, the first level is at least 2 nm below the upper surface of the isolation region. In one embodiment, the method further includes: forming a bottom spacer adjacent to the substrate before etching the first opening through the gate; and forming source / drain regions on the bottom spacer. In one embodiment, the bottom of the bottom spacer is below the first level. In one embodiment, the method further includes forming an inner spacer in a second stack of nanostructures, wherein the inner spacer and the bottom spacer have a first interface. In one embodiment, the length of the first interface is between about 3 nm and about 15 nm.

[0176] In one embodiment, the semiconductor device includes: a stack of nanostructures on a first semiconductor fin, the first semiconductor fin being located on a substrate; an isolation region extending on the substrate between the first semiconductor fin and a second semiconductor fin, the isolation region having a first surface remote from the substrate and the first surface being spaced from the substrate by a first distance; a gate surrounding each nanostructure in the stack of nanostructures; and a dielectric material adjacent to the gate, the dielectric material having a first portion adjacent to the second semiconductor fin, the first portion being spaced from the substrate by a second distance, the second distance being smaller than the first distance. In one embodiment, the difference between the second distance and the first distance is at most 20 nm. In one embodiment, the semiconductor device further includes: a first source / drain region adjacent to the stack of nanostructures; a first bottom spacer isolating the first source / drain region from the substrate; and an inner spacer adjacent to the first bottom spacer and separating the first bottom spacer from the dielectric material. In one embodiment, the inner spacer and the first bottom spacer have a first interface, and the distance between the first interface is between about 3 nm and about 15 nm. In some embodiments, the first height of the inner spacer is between about 5 nm and about 20 nm. In one embodiment, the first height is greater than the second height of a nanostructure in the stack of nanostructures.

[0177] The features of the above embodiments are beneficial to those skilled in the art in understanding this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the concept and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A fin is formed in a multilayer stack, and the fin includes a substrate and at least one first layer on the substrate; A dummy gate is formed on the fin; An opening is etched in the fin adjacent to the dummy gate; A recess is formed along one side wall of the opening, and the recess is formed in the at least one first layer; A spacer material is deposited in the depression; A bottom spacer is formed at the bottom of the opening, and the bottom spacer and the spacer material have a first interface; A source / drain region is formed on the bottom spacer; Replace at least a portion of the dummy gate with a gate; and A dielectric structure is formed through the gate into the substrate of the fin, and the bottom of the dielectric structure is higher than the bottom of the bottom spacer.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the thickness of the spacer material in the recess is greater than the thickness of the at least one first layer.

3. The method for forming a semiconductor device as claimed in claim 1, wherein the step of forming the bottom spacer further comprises forming the bottom spacer to a height between 3 nm and 30 nm.

4. The method of forming a semiconductor device as claimed in claim 1, wherein the length of the first interface is between 3 nm and 15 nm.

5. The method for forming a semiconductor device as claimed in claim 1, further comprising forming a diced gate dielectric layer before forming the dielectric structure.

6. The method of forming a semiconductor device as claimed in claim 1, further comprising forming a plurality of isolation regions on both sides of the fin, wherein the step of forming the gate includes forming the gate on the isolation regions, and wherein the bottom of the dielectric structure is horizontal between the upper and lower surfaces of the isolation regions.

7. The method of forming a semiconductor device as claimed in claim 6, wherein the bottom of the dielectric structure extends horizontally into the substrate at a distance between 2 nm and 20 nm.

8. A method for forming a semiconductor device, comprising: A bottom spacer is formed adjacent to a substrate; A source / drain region is formed on the bottom spacer; A first opening is etched through a gate, and a gate dielectric layer is exposed in the first opening; Remove the gate dielectric layer from the first opening, wherein after removing the gate dielectric layer, a portion of the substrate, a stack of multiple nanostructures, and multiple isolation regions are exposed, wherein the stack of nanostructures includes a first nanostructure located on the substrate and a second nanostructure located on the first nanostructure. An etching process is performed to remove the stack of nanostructures in the first opening, and to partially recess the substrate to a first level between the upper and lower surfaces of the isolation regions, wherein the bottom of the bottom spacer is below the first level; and A dielectric material is deposited in the first opening, and the dielectric material isolates the first portion of the gate from the second portion of the gate.

9. The method of forming a semiconductor device as claimed in claim 8, wherein the distance between the first level and the upper surface of the isolation regions is at most 20 nm.

10. The method of forming a semiconductor device as claimed in claim 8, wherein the distance between the first level and the upper surface of the isolation regions is at least 2 nm.

11. The method of forming a semiconductor device as claimed in claim 8, further comprising: An inner spacer is formed in a second stack of multiple nanostructures, and the inner spacer has a first interface with the bottom spacer.

12. The method of forming a semiconductor device as claimed in claim 11, wherein the length of the first interface is between 3 nm and 15 nm.

13. A method for forming a semiconductor device, comprising: Multiple nanostructures are stacked on a first semiconductor fin, and the first semiconductor fin is located on a substrate; An isolation region is formed between the first semiconductor fin and a second semiconductor fin on the substrate, a first surface of the isolation region is away from the substrate, and the first surface is separated from the substrate by a first distance. A first bottom spacer is formed extending downward toward the substrate into the second semiconductor fin, and the first bottom spacer extends to a first horizontal level on the substrate; A dielectric material is formed adjacent to each of the nanostructures in the stack, and a first portion of the dielectric material is adjacent to the second semiconductor fin, while the first portion is separated from the substrate by a second distance and is higher than the first level, and the second distance is smaller than the first distance; and Before the dielectric material is formed, a gate is formed to surround each of the nanostructures in the stack, wherein the gate is adjacent to the dielectric material after the dielectric material is formed.

14. The method of forming a semiconductor device as claimed in claim 13, wherein the second distance is at most 20 nm smaller than the first distance.

15. The method of forming a semiconductor device as claimed in claim 13, further comprising: A first source / drain region is formed, wherein after the first source / drain region is formed, the first bottom spacer isolates the first source / drain region from the substrate; as well as An inner spacer is formed, wherein after the dielectric material is formed, the inner spacer is adjacent to the first bottom spacer and separates the first bottom spacer from the dielectric material.

16. The method of forming a semiconductor device as claimed in claim 15, wherein the inner spacer and the first bottom spacer have a first interface, and the distance between the first interface is between 3 nm and 15 nm.

17. The method of forming a semiconductor device as claimed in claim 16, wherein the first height of the inner spacer is between 5 nm and 20 nm.

18. The method of forming a semiconductor device as claimed in claim 17, wherein the first height is greater than the second height of one of the nanostructures in the stack of the nanostructures.

19. A semiconductor device, comprising: A first nanostructure and a second nanostructure are located on a fin on a semiconductor substrate; A first inner spacer is located between the first nanostructure and the semiconductor substrate; A first spacer material, in physical contact with the first inner spacer; A first source / drain region is located on the first spacer material and the first inner spacer and is in physical contact with the first spacer material and the first inner spacer; A gate surrounding the first nanostructure and the second nanostructure; and A dielectric structure extends through the gate into the fin, with the bottom of the dielectric structure being higher than the bottom of the first spacer material.

20. The semiconductor device of claim 19, wherein the height of the first spacer material is between 3 nm and 30 nm.

21. The semiconductor device of claim 19, wherein the interface length between the first spacer material and the first inner spacer is between 3 nm and 15 nm.

22. The semiconductor device of claim 19, wherein the dielectric structure extends into the fin by a distance between 2 nm and 20 nm.

23. The semiconductor device of claim 19, wherein the first spacer material comprises silicon oxide.

24. The semiconductor device of claim 19, wherein the first spacer material comprises silicon oxynitride.

25. The semiconductor device of claim 19, wherein the height of the first inner spacer is between 5 nm and 20 nm.

26. A semiconductor device, comprising: A first bottom spacer separates a first source / drain region from a semiconductor substrate; A first inner spacer, which physically contacts the first bottom spacer and the first source / drain region; A first nanostructure physically contacts the first inner spacer and the first source / drain region; A second nanostructure is located on the first nanostructure; A gate surrounding the first nanostructure and the second nanostructure; and A dielectric material is adjacent to the gate, and the lower surface of the dielectric material is further away from the semiconductor substrate than the first bottom spacer.

27. The semiconductor device of claim 26, wherein the width of the first inner spacer is between 2 nm and 10 nm.

28. The semiconductor device of claim 27, wherein the height of the first inner spacer is between 5 nm and 20 nm.

29. The semiconductor device of claim 28, further comprising a second inner spacer, wherein the second inner spacer is separated from the first inner spacer by a first space, and the first space is between 3 nm and 10 nm.

30. The semiconductor device of claim 26, wherein the length of a first channel of the first nanostructure is between 5 nm and 180 nm.

31. The semiconductor device of claim 26, wherein the first channel width of the first nanostructure is between 8 nm and 100 nm.

32. The semiconductor device of claim 26, wherein the first inner spacer physically contacts a first side and a second side of the first nanostructure, and the first side and the second side form an angle.

33. A semiconductor device, comprising: A stack of multiple nanostructures is located on a first semiconductor fin, and the first semiconductor fin is located on a substrate; An isolation region extends between the first semiconductor fin and the second semiconductor fin on the substrate, a first surface of the isolation region being away from the substrate and the first surface being separated from the substrate by a first distance; A gate surrounding each of the nanostructures in the stack; and A dielectric material adjacent to the gate, the dielectric material having a first lower surface, and a first portion of the dielectric material adjacent to the second semiconductor fin, the first portion being spaced from the substrate by a second distance, the second distance being smaller than the first distance; and A first bottom spacer is adjacent to the dielectric material, the first bottom spacer having a second lower surface, and the second lower surface being lower than the first lower surface.

34. The semiconductor device of claim 33, wherein the second distance is at most 20 nm smaller than the first distance.

35. The semiconductor device of claim 33, further comprising: A first source / drain region is adjacent to the stack of the nanostructures, wherein the first bottom spacer isolates the first source / drain region from the substrate; as well as An inner spacer is adjacent to the first bottom spacer and separates the first bottom spacer from the gate.

36. The semiconductor device of claim 35, wherein the inner spacer and the first bottom spacer have a first interface, and the distance between the first interface is between 3 nm and 15 nm.

37. The semiconductor device of claim 36, wherein a first height of the inner spacer is between 5 nm and 20 nm.

38. The semiconductor device of claim 37, wherein the first height is greater than a second height of the gate.

Images