Semiconductor structure, integrated chip and manufacturing method thereof

Abstract

Various embodiments of the present disclosure relate to an integrated chip including a resistor structure. A resistor layer overlies a substrate. The resistor structure overlies the substrate. The resistor structure includes a resistor segment of the resistor layer and a via structure overlying the resistor segment. A ring structure encloses the resistor structure. The ring structure extends continuously from a first point above the conductive structure to a second point below the bottom surface of the resistor layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure, an integrated chip and a method for manufacturing the same. Background Art

[0002] Modern integrated chips use a variety of devices to achieve a variety of functionalities. Generally speaking, integrated chips include active devices and passive devices. Active devices include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET)), while passive devices include inductors, capacitors, and resistors. Resistors are widely used in many applications such as resistor-capacitor (RC) circuits, power drivers, power amplifiers, radio frequency (RF) applications, etc. Summary of the invention

[0003] An embodiment of the present disclosure proposes an integrated chip, comprising: a substrate; a resistor layer overlying the substrate; a resistor structure overlying the substrate, wherein the resistor structure comprises: a resistor segment of the resistor layer; a conductive structure overlying the resistor segment; and a ring structure enclosing the resistor structure, wherein the ring structure extends continuously from a first point above the conductive structure to a second point below the bottom surface of the resistor layer.

[0004] The disclosed embodiment proposes a semiconductor structure, comprising: a substrate; a resistor layer overlying the substrate; a resistor structure overlying the substrate, wherein the resistor structure comprises a resistor segment of the resistor layer, a contact structure overlying the resistor segment, and a dielectric structure overlying the contact structure; and an isolation structure continuously surrounding the outer periphery of the resistor segment, wherein the isolation structure comprises a conductor and a first pad extending along relative side walls of the conductor.

[0005] The presently disclosed embodiment proposes a method for forming an integrated chip, comprising: depositing a resistor layer on a substrate, wherein the resistor layer comprises a first material; forming a conductive structure on the resistor layer, wherein the conductive structure comprises a second material different from the first material; forming an interlayer dielectric structure on the conductive structure; patterning the interlayer dielectric structure and the resistor layer to define a plurality of through-hole openings and a ring structure opening, so that the ring structure opening laterally encloses the resistor segment of the resistor layer, wherein the ring structure opening extends from the upper surface of the interlayer dielectric structure to a point below the resistor layer; forming a plurality of conductive holes in the plurality of through-hole openings; and forming a ring structure within the ring structure opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated chips having a ring structure laterally enclosing a resistor structure are shown.

[0008] Figure 2 Shown along line A-A' Figure 1 Top views of some alternative embodiments of integrated chips.

[0009] Figure 3 Cross-sectional views of some embodiments of integrated chips having resistor structures disposed within interconnect structures are shown.

[0010] Figure 4 Shown according to line BB' Figure 3 Top views of some alternative embodiments of integrated chips.

[0011] FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B A series of various views illustrating some embodiments of methods of forming an integrated chip having a resistor structure overlying a substrate.

[0012] Fig.14 A flow chart illustrating some embodiments of a method of forming an integrated chip having a resistor structure overlying a substrate. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] The integrated chip may have a passive device disposed on / in the substrate. The passive device may, for example, include an inductor, a resistor, a capacitor, a diode, etc. A common type of resistor used in an integrated chip is a polysilicon resistor. However, polysilicon resistors may face many problems, such as breakdown problems. For example, due to the material of the polysilicon resistor, the temperature coefficient of resistance (TCR) of the polysilicon resistor is relatively high (e.g., about 990ppm / C). This may in turn cause the resistance of the polysilicon resistor to change over time, especially in high voltage applications, where high heat may accumulate at the polysilicon resistor due to the high voltage. In addition, a relatively high TCR may result in a low breakdown voltage, thereby causing device failure of the integrated chip.

[0016] In some embodiments, the resistor structure may be made to include silicon chromium (SiCr). Due to the SiCr material, the resistor structure may have a reduced TCR (e.g., less than about 50ppm / C), so that the resistance change caused by heat can be mitigated. However, the method of forming the resistor structure is complicated. For example, the method may include forming a resistor layer on a substrate, wherein the resistor layer includes SiCr. A conductive contact layer is formed on the resistor layer, and a dielectric structure is formed on the conductive contact layer. Subsequently, a first patterning process is performed on the resistor layer to form one or more resistor segments so that the one or more resistor segments are laterally offset from each other. A second patterning process is performed to remove a portion of the conductive contact layer and the dielectric structure. A third patterning process is performed on the conductive contact layer to define one or more conductive contacts on each resistor segment, thereby defining a plurality of resistor structures. In addition, a via is formed on the conductive contact. Since the method utilizes at least three patterning processes, the time and cost associated with production are unfavorably increased.

[0017] The present disclosure relates to a method for simplifying the manufacture of a resistor structure by reducing the number of patterning processes utilized during manufacture. For example, the method may include: forming a resistor layer (e.g., comprising SiCr) on a substrate, forming a conductive contact layer on the resistor layer, and forming a dielectric structure on the conductive contact layer. Subsequently, a first patterning process is performed to remove at least a portion of the dielectric structure and the conductive contact layer. In addition, a second patterning process is performed on the conductive contact layer to form a plurality of conductive contacts on the resistor layer. A via is formed on the conductive contact, and one or more ring structures are formed on the substrate. The ring structure extends through the resistor layer, thereby defining a plurality of resistor sections that are laterally offset and electrically isolated from each other. In addition, the ring structures respectively surround a corresponding set of conductive contacts, thereby defining one or more resistor structures. The via and the ring structure may be formed simultaneously with each other. This in turn reduces the number of patterning processes used to form the resistor structure, thereby reducing the cost and time of forming the resistor structure.

[0018] Figure 1 A cross-sectional view of some embodiments of an integrated chip 100 including a resistor structure 115 is shown.

[0019] A resistor structure 115 overlies the substrate 102. A first inter-level dielectric (ILD) structure 104 overlies the substrate 102. A first insulator layer 112 overlies the first ILD structure 104, and a second insulator layer 116 overlies the first insulator layer 112. In addition, the resistor layer 114 is disposed between the first insulator layer 112 and the second insulator layer 116. A second ILD structure 124 overlies the second insulator layer 116. A plurality of conductive lines 106 and a plurality of vias 108 are disposed in the first ILD structure 104 and / or the second ILD structure 124 and overlie the substrate 102. The conductive lines 106 and / or the vias 108 are configured to electrically couple devices disposed in the integrated chip 100 to each other. In some embodiments, the resistor structure 115 may be used, for example, in an RC circuit, a power driver, a power amplifier, a radio frequency application, an analog to digital converter (ADC) and / or a digital to analog converter (DAC).

[0020] The contact structure 120 is disposed on the resistive layer 114. The dielectric structure 122 directly overlies each contact structure 120. In some embodiments, the resistor structure 115 includes the contact structure 120 and a resistor segment 114rs of the resistive layer 114 disposed between the sidewalls of the ring structure 117. In some embodiments, the resistive layer 114 may be or include silicon chromium (SiCr), for example, so that the TCR of the resistor structure 115 is relatively low. However, other materials for the resistive layer 114 are also acceptable. In some embodiments, one or more vias 108 overlying the resistive layer 114 may be surrounded by a first liner 118. In further embodiments, the first liner 118 may be configured as an isolation liner so that the vias 108 extending through the entire thickness of the resistive layer 114 are electrically isolated from the resistive layer 114. In some embodiments, the first liner 118 may be, for example, or include, tetra-ethyl-ortho-silicate (TEOS) (e.g., plasma enhanced TEOS, low particle TEOS, etc.), an oxide (e.g., silicon oxide, silicon dioxide, etc.), a nitride, another suitable dielectric material, or any combination of the foregoing materials. In further embodiments, the second liner 110 laterally surrounds the via 108 underlying the resistor structure 115. In some embodiments, the second liner 110 may be configured as a conductive adhesive structure and / or a buffer layer.

[0021] The ring structure 117 (in some embodiments, referred to as an isolation structure) laterally encloses the resistor structure 115. In some embodiments, the ring structure 117 may include an electrical conductor 109 and a first liner 118. The electrical conductor 109 laterally encloses the resistor structure 115, and the first liner 118 is disposed around the sidewalls of the electrical conductor 109. In some embodiments, this ensures that the electrical conductor 109 is laterally offset from the resistive layer 114 by a non-zero distance. Thus, the first liner 118 is configured to electrically isolate the electrical conductor 109 from the resistor structure 115. In further embodiments, the ring structure 117 defines the outer perimeter of the resistor segment 114rs of the resistive layer 114. In some embodiments, the electrical conductor 109 and the first liner 118 of the ring structure 117 extend completely through the thickness of the resistive layer 114. In yet other embodiments, the electrical conductor 109 comprises the same material as the via 108.

[0022] In some embodiments, during the formation of the integrated chip 100, the via 108 directly overlying the contact structure 120 and / or extending through the resistive layer 114 can be formed simultaneously with the ring structure 117. By forming the ring structure 117 simultaneously with the via 108, the cost and complexity of manufacturing the integrated chip 100 can be reduced. In addition, since the ring structure 117 extends through the entire thickness of the resistive layer 114, it defines the outer periphery of the resistor segment 114rs. In addition, since the ring structure 117 includes the first liner 118 and laterally encloses the resistor segment 114rs, the resistor segment 114rs can be isolated from other segments and / or peripheral areas of the resistive layer 114.

[0023] Figure 2 Shown is a view taken along line A-A' Figure 1 FIG. 2 is a top view 200 of some alternative embodiments of the integrated chip 100. For clarity, Figure 2 The second insulator layer 116 and the second ILD structure 124 overlying the resistive layer 114 are omitted in the top view 200 of FIG.

[0024] The ring structure 117 laterally encloses the resistor segment 114rs of the resistor layer 114. Therefore, the resistor segment 114rs is defined between the inner side walls of the ring structure 117. In addition, the outer periphery of the resistor segment 114rs is defined by the inner periphery of the ring structure 117. In addition, the first liner 118 is disposed along the opposite side wall of the conductor 109, so that the first liner 118 can isolate the resistor segment 114rs from the conductor 109 and / or the peripheral region 114p of the resistor layer 114. In addition, the contact structure ( Figure 1 The plurality of vias 108 may extend through the entire thickness of the dielectric structure 122 and directly contact the corresponding contact structure ( Figure 1120). In some embodiments, the ring structure 117 may have a ring shape, such as a rectangular shape, a square shape, a circular shape, an elliptical shape, or another corresponding shape, so that the ring structure 117 laterally encloses the resistor structure 115. In some embodiments, the ring structure 117 includes a first outer region 117o1, a second outer region 117o2, and a central region 117c disposed between the first outer region 117o1 and the second outer region 117o2. The first outer region 117o1 and the second outer region 117o2 have a first width W1, and the central region 117c has a second width W2 that is smaller than the first width W1.

[0025] Figure 3 A cross-sectional view of some embodiments of an integrated chip 300 is shown, which includes a first resistor structure 302 a disposed within an interconnect structure 305 .

[0026] The interconnect structure 305 overlies the substrate 102. In some embodiments, the substrate 102 may be, for example, or include a semiconductor substrate material (e.g., silicon), a bulk silicon substrate (e.g., bulk silicon), a silicon-on-insulator (SOI) substrate, or another suitable substrate material. The interconnect structure 305 includes a plurality of dielectric layers, a plurality of wires 106, and a plurality of vias 108. The plurality of wires 106 and / or vias 108 are disposed within the plurality of dielectric layers. In some embodiments, the plurality of wires 106 and / or vias 108 may be configured to electrically couple devices disposed within and / or on the substrate 102 to each other. In some embodiments, the wires 106 and / or vias 108 may be, for example, or include aluminum, copper, tungsten, another suitable conductive material, or any combination of the foregoing materials.

[0027] A plurality of semiconductor devices 304 may be disposed in and / or on the substrate 102. In some embodiments, the semiconductor devices 304 may be configured as transistors. In such embodiments, the semiconductor devices 304 each include a source / drain region 306, a gate dielectric layer 308, a gate electrode 312, and a sidewall spacer structure 310. The gate electrode 312 overlies the gate dielectric layer 308, and the source / drain region 306 is disposed in the substrate 102 on the opposite side of the gate electrode 312. A first interlayer dielectric (ILD) structure 104 overlies the substrate 102. In some embodiments, the first ILD structure 104 may be or include, for example, silicon dioxide, a low dielectric constant (k) dielectric material, another suitable dielectric material, or any combination of the foregoing materials. A first insulator layer 112 overlies the first ILD structure 104. A resistive layer 114 overlies the first insulator layer 112, and a second insulator layer 116 overlies the resistive layer 114. In some embodiments, the first insulator layer 112 and / or the second insulator layer 116 may be, for example, respectively or include an oxide (e.g., silicon dioxide) or another suitable dielectric material. The first insulator layer 112 and / or the second insulator layer 116 may be configured to dissipate heat generated by the first resistor structure 302a during operation of the integrated chip 300. The second ILD structure 124 overlies the second insulator layer 116. In some embodiments, the second ILD structure 124 may be, for example, or include an oxide (e.g., silicon dioxide), a low-k dielectric material, another suitable dielectric material, or any combination of the foregoing materials.

[0028] The contact structure 120 is disposed on the resistor segment 114rs of the resistor layer 114. In some embodiments, the contact structure 120 may be, for example, or include titanium nitride, tantalum nitride, another suitable material, or any combination of the foregoing materials, and / or may include a material different from the resistor layer 114. A dielectric structure 122 directly overlies each contact structure 120. In some embodiments, the dielectric structure 122 may be, for example, or include silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing materials. In some embodiments, the first resistor structure 302a includes the contact structure 120 and the resistor segment 114rs of the resistor layer 114 disposed between the sidewalls of the ring structure 117. In some embodiments, the resistor layer 114 may be, for example, or include silicon chromium (SiCr), so that the TCR of the first resistor structure 302a is relatively low (e.g., less than about 50 ppm / C). In some further embodiments, the resistor layer 114 may be, for example, or include titanium nitride, silicon chromium, nickel chromium aluminum, tantalum nitride, another suitable material, or any combination of the foregoing materials. In some embodiments, one or more vias 108 overlying the resistive layer 114 and / or extending through the resistive layer 114 may be surrounded by a first liner 118. In further embodiments, the first liner 118 may be configured as an isolation liner so that the vias 108 extending through the entire thickness of the resistive layer 114 may be electrically isolated from the resistive layer 114. In some embodiments, the first liner 118 may be, for example, or include tetraethyl orthosilicate (TEOS) (e.g., plasma enhanced TEOS, low particle TEOS, etc.), an oxide (e.g., silicon oxide, silicon dioxide, etc.), a nitride, another suitable dielectric material, or any combination of the foregoing materials. In further embodiments, the second liner 110 laterally surrounds the vias 108 underlying the first resistor structure 302a. In some embodiments, the second liner 110 may be configured as a conductive adhesive structure and / or a buffer layer. In some embodiments, the second liner 110 may be, for example, or include titanium nitride, tantalum nitride, another suitable material, or any combination of the foregoing materials.

[0029] The ring structure 117 laterally encloses the resistor segment 114rs of the resistive layer 114. The ring structure 117 includes a conductor 109 and a first liner 118. The conductor 109 laterally encloses the first resistor structure 302a, and the first liner 118 is disposed around the sidewall of the conductor 109. This ensures that the conductor 109 is laterally offset from the resistive layer 114 by a non-zero distance. Therefore, the first liner 118 is configured to electrically isolate the conductor 109 from the first resistor structure 302a. In further embodiments, the ring structure 117 defines the outer periphery of the resistor segment 114rs of the resistive layer 114. In some embodiments, the conductor 109 and the first liner 118 of the ring structure 117 extend completely through the thickness of the resistive layer 114. In some embodiments, the conductor 109 may be, for example, or include aluminum, copper, tungsten, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing materials. In addition, the upper ILD layer 314 overlies the second ILD structure 124. The conductive lines 106 are disposed in the upper ILD layer 314 and overlie the corresponding vias 108 .

[0030] Figure 4 Shows the area taken along line B-B' Figure 3 400 of some alternative embodiments of the integrated chip 300. For clarity, Figure 4 The second insulator layer 116 and the second ILD structure 124 overlying the resistive layer 114 are omitted in the top view 400 of FIG.

[0031] like Figure 4 As shown, the first resistor structure 302a is laterally offset from the second resistor structure 302b. In some embodiments, the second resistor structure 302b is configured as the first resistor structure 302a, so that the second resistor structure 302b includes a contact structure 120 and a resistor segment 114rs of the resistive layer 114 disposed between the sidewalls of the ring structure 117. The contact structure 120 is disposed between the dielectric structure and the resistive layer 114.

[0032] FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B A series of various views showing some embodiments of a method of forming an integrated chip having a resistor structure overlying a substrate. The figures with suffix "A" show cross-sectional views of the integrated chip during various formation processes. The figures with suffix "B" show corresponding top views taken along line CC' of the figures with suffix "A". Although FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B The various views shown in the drawings are described with reference to methods of forming an integrated chip, but it will be understood that FIG. 5A to FIG. 5B arrive FIG. 13A to FIG. 13B The structure shown in is not limited to the formation method described, but may be independent of the method described.

[0033] like FIG. 5A to FIG. 5B As shown in the cross-sectional view 500a and the top view 500b of , a substrate 102 is provided, and a first interlayer dielectric (ILD) structure 104 is formed on the substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. The first interlayer dielectric (ILD) structure 104 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, or another suitable deposition or growth process. Subsequently, a conductive line 106 may be formed in the first ILD structure 104. In some embodiments, the conductive line 106 may be formed, for example, by a dual damascene process or a single damascene process. In further embodiments, the conductive line 106 may be, for example, or include aluminum, copper, titanium nitride, tantalum nitride, tungsten, another suitable conductive material, or any combination of the foregoing materials.

[0034] Also like FIG. 5A to FIG. 5BAs shown, a first insulator layer 112 is formed over the first ILD structure 104. In some embodiments, the first insulator layer 112 may be or include, for example, an oxide (e.g., silicon dioxide), another suitable dielectric material, or any combination of the foregoing materials, and / or may be formed to a thickness of about 1000 angstroms. It will be understood that other values ​​of the thickness of the first insulator layer 112 are also within the scope of the present disclosure. A resistive layer 114 is formed over the first insulator layer 112. In some embodiments, the resistive layer 114 may be or include, for example, silicon chromium and / or may be formed to a thickness of about 48 angstroms, about 50 angstroms, or a thickness in the range of about 30 angstroms to 60 angstroms. It will be understood that other values ​​of the thickness of the resistive layer 114 are also within the scope of the present disclosure. In addition, it will be understood that other suitable materials for the resistive layer 114 are also within the scope of the present disclosure. A contact layer 502 is formed over the resistive layer 114. In further embodiments, the contact layer 502 may be or include, for example, titanium nitride, tantalum nitride, another suitable material, or any combination of the foregoing materials, and / or may be formed to a thickness of about 750 angstroms. It will be appreciated that other values ​​of the thickness of the contact layer 502 are also within the scope of the present disclosure. In some embodiments, the contact layer 502 comprises a material different from the resistive layer 114. In addition, a dielectric layer 504 is formed over the contact layer 502. In yet other embodiments, the dielectric layer 504 may be, for example, or comprise silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing materials, and / or may be formed to a thickness of about 320 angstroms or in a range of about 300 to 350 angstroms. It will be appreciated that other values ​​of the thickness of the dielectric layer 504 are also within the scope of the present disclosure. In some embodiments, the first insulator layer 112, the resistive layer 114, the contact layer 502, and / or the dielectric layer 504 may be, for example, formed by CVD, PVD, ALD, thermal oxidation, or another suitable deposition or growth process, respectively.

[0035] like FIG. 6A to FIG. 6B As shown in the cross-sectional view 600a and the top view 600b, in the dielectric layer ( Fig. 6A The first patterning process is performed on the contact layer 504 and the contact layer 502 to define the dielectric structure 122 above the resistive layer 114. In some embodiments, the first patterning process may include performing a dry etching process according to a mask layer (not shown). The first patterning process removes at least a portion of the contact layer 502 so that the upper surface 502us of the contact layer 502 is disposed below the top surface of the contact layer 502 by a distance d1. In some embodiments, the distance d1 is about 250 angstroms. In addition, the first patterning process defines the dielectric structure 122 so that it has a width W3 respectively. In a further embodiment, the width W3 is about 1.36 microns or in a range of about 1.3 microns to 1.4 microns.

[0036] like FIG. 7A to FIG. 7B As shown in the cross-sectional view 700a and the top view 700b, FIG. 6A to FIG. 6B The second patterning process is performed on the structure of the contact layer 120 to define the contact structure 120. In some embodiments, the second patterning process may include forming the contact layer ( Fig. 6A 502) is exposed to one or more etchants. In further embodiments, the second patterning process may include performing a wet etching process, a dry etching process, or another suitable etching process, and / or the one or more etchants may include hydrogen peroxide (e.g., H2O2). During the second patterning process, the contact layer ( Fig. 6A 502), the dielectric structure 122 and the resistive layer 114 are exposed to the one or more etchants (e.g., hydrogen peroxide). In some embodiments, the one or more etchants (e.g., hydrogen peroxide) are effective for the contact layer ( Fig. 6A 502) has a higher etching selectivity than the dielectric structure 122 and the resistor layer 114. For example, during the second patterning process, the contact layer ( Fig. 6A The contact structure 120 may be etched at a first etching rate, the dielectric structure 122 may be etched at a second etching rate, and the resistive layer 114 may be etched at a third etching rate, such that the first etching rate is greater than the second etching rate and the third etching rate. In some embodiments, due to a wet etching process (not shown), the outer sidewall of the contact structure 120 may be concave.

[0037] like FIG. 8A to FIG. 8B As shown in the cross-sectional view 800a and the top view 800b of , a second insulator layer 116 is formed on the resistive layer 114. In some embodiments, the second insulator layer 116 may be or include an oxide (e.g., silicon dioxide), another suitable dielectric material, or any combination of the foregoing materials, for example, and / or may be formed to a thickness of about 500 angstroms or in a range of about 450 angstroms to 550 angstroms. It will be understood that other values ​​of the thickness of the second insulator layer 116 are also within the scope of the present disclosure. In further embodiments, the second insulator layer 116 may be formed, for example, by CVD, PVD, ALD, thermal oxidation, or another suitable growth or deposition process.

[0038] like FIG. 9A to FIG. 9BAs shown in the cross-sectional view 900a and the top view 900b of , a second ILD structure 124 is formed on the second insulator layer 116. In some embodiments, the second ILD structure 124 may be or include, for example, fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), some other low-k dielectric material, silicon oxide, some other suitable dielectric material, or any combination of the foregoing materials, and / or may be formed to a thickness of about 5,500 angstroms or in a range of about 5,000 angstroms to 6,000 angstroms. It will be understood that other values ​​of the thickness of the second ILD structure 124 are also within the scope of the present disclosure. In further embodiments, the second ILD structure 124 may be formed, for example, by CVD, PVD, ALD, plasma enhanced CVD (PECVD), thermal oxidation, or another suitable growth or deposition process.

[0039] like FIG. 10A to FIG. 10B As shown in the cross-sectional view 1000a and the top view 1000b , a planarization process (eg, a chemical mechanical planarization (CMP) process) is performed on the second ILD structure 124 so that the top surface of the second ILD structure 124 is substantially flat.

[0040] like FIG. 11A to FIG. 11B As shown in the cross-sectional view 1100a and the top view 1100b, FIG. 10A to FIG. 10B A third patterning process is performed on the structure of the resistor layer 114 to define a plurality of ring structure openings 1102 and a plurality of through-hole openings 1104. In some embodiments, the third patterning process includes performing one or more dry etching processes according to a mask layer (not shown). In addition, the third patterning process defines a first resistor structure 302a that is laterally adjacent to the second resistor structure 302b. In some embodiments, the first resistor structure 302a and the second resistor structure 302b respectively include a resistor segment 114rs of the resistor layer 114 and one or more conductive structures 120 overlying the corresponding resistor segment 114rs. The ring structure opening 1102 laterally closes the corresponding resistor segment 114rs of the resistor layer 114. In some embodiments, the conductive structure 120 can be used as an etch stop layer during the third patterning process so that the resistor segment 114rs of the resistor layer 114 is not damaged during the third patterning process.

[0041] like FIG. 12A to FIG. 12BAs shown in the cross-sectional view 1200a and the top view 1200b of FIG. 1200 , a first liner 118 is formed in each of the plurality of ring structure openings 1102 and the plurality of via openings 1104. In some embodiments, the process of forming the first liner 118 may include: depositing (e.g., by CVD, PVD, etc.) a dielectric material (e.g., tetraethyl orthosilicate (TEOS) (e.g., plasma enhanced TEOS, low particle TEOS, etc.), an oxide (e.g., silicon oxide, silicon dioxide, etc.), a nitride, another suitable dielectric material, etc.) on the substrate 102 to line at least a portion of each ring structure opening 1102 and each via opening 1104; and performing an etch-back process to remove the dielectric material from the horizontal surface to expose the upper surface of the contact structure 120 and / or the conductive line 106. In some other embodiments, a planarization process (e.g., a CMP process) may be performed in the dielectric material until the top surface of the second ILD structure 124 is reached.

[0042] like FIG. 13A to FIG. 13B As shown in the cross-sectional view 1300a and the top view 1300b of FIG. 1300, the vias 108 and the conductors 109 are formed in the plurality of through-hole openings 1104 and the plurality of ring structure openings 1102, respectively, so as to define the ring structure 117. Therefore, in some embodiments, the vias 108 may be formed simultaneously with the ring structure 117. In some embodiments, the process of forming the vias 108 and / or the conductors 109 may include: Fig. 12A 1102) and through hole opening ( Fig. 12A A conductive material (e.g., aluminum, copper, tungsten, another conductive material, or any combination thereof) is deposited (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, or another suitable growth or deposition process) in the first ILD structure 1104; and a planarization process (e.g., a CMP process) is performed in the conductive material until a top surface of the second ILD structure 124 is reached. The first liner 118 is configured to electrically isolate the conductor 109 from the corresponding resistor segment 114rs of the resistive layer 114. In some embodiments, the via 108 is formed simultaneously with at least the conductor 109 of the ring structure 117. Due to the formation of the ring structure 117 having the via 108, at least one patterning process can be omitted from the manufacturing process of the first resistor structure 302a and the second resistor structure 302b. This partially reduces the cost and time associated with forming the first resistor structure 302a and the second resistor structure 302b. In addition, since the ring structures 117 respectively include the first pads 118 and laterally close the resistor segments 114 rs, the resistor segments 114 rs may be isolated from other segments of the resistance layer 114 .

[0043] Fig.14A method 1400 for forming an integrated chip is shown, the integrated chip having a resistor structure overlying a substrate. Although method 1400 is shown and / or described as a series of event actions, it will be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, these actions can be implemented in a different order than the illustrated order, and / or can be implemented simultaneously. In addition, in some embodiments, the illustrated actions or events can be subdivided into multiple actions or events, which can be implemented at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the illustrated actions or events can be omitted, and other actions or events not shown can be included.

[0044] In act 1402, a stack of layers is formed over a substrate. The stack of layers includes a resistive layer, a dielectric layer, and a contact layer disposed between the resistive layer and the dielectric layer. FIG. 5A to FIG. 5B Various views corresponding to some embodiments of act 1402 are shown.

[0045] In act 1404 , a first patterning process is performed on the dielectric layer and the contact layer to define a plurality of dielectric structures and remove a portion of the contact layer. FIG. 6A to FIG. 6B Various views corresponding to some embodiments of act 1404 are shown.

[0046] In act 1406 , a second patterning process is performed on the contact layer to define a plurality of contact structures disposed between the resistive layer and corresponding dielectric structures. FIG. 7A to FIG. 7B Various views corresponding to some embodiments of act 1406 are shown.

[0047] In act 1408, an interlayer dielectric (ILD) structure is formed over the resistive layer. FIG. 8A to FIG. 8B arrive FIG. 10A to FIG. 10B Various views corresponding to some embodiments of act 1408 are shown.

[0048] In act 1410, a third patterning process is performed on the ILD structure and the layers underlying the ILD structure to define a plurality of via openings, ring structure openings, and resistor structures. The ring structure openings extend through the entire thickness of the resistor layer, wherein the ring structure openings laterally enclose the resistor structure. FIG. 11A to FIG. 11B Various views corresponding to some embodiments of act 1410 are shown.

[0049] In act 1412, a first liner is formed in the via opening and the ring structure opening, wherein the first liner comprises a dielectric material. FIG. 12A to FIG. 12B Various views corresponding to some embodiments of act 1412 are shown.

[0050] In act 1414, a conductive material is formed in the via opening and the ring structure opening, thereby defining a via and a ring structure. The ring structure includes a conductive body and a first liner that laterally enclose the resistor structure, respectively. FIG. 13A to FIG. 13B Various views corresponding to some embodiments of act 1414 are shown.

[0051] Thus, in some embodiments, the present disclosure is directed to a resistor structure comprising a resistor segment of a resistor layer and a conductive structure overlying the resistor segment, wherein a ring structure laterally encloses the resistor structure.

[0052] In some embodiments, the present application provides an integrated chip, which includes: a substrate; a resistor layer overlying the substrate; a resistor structure overlying the substrate, wherein the resistor structure includes: a resistor segment of the resistor layer; a conductive structure overlying the resistor segment; and a ring structure that closes the resistor structure, wherein the ring structure extends continuously from a first point above the conductive structure to a second point below the bottom surface of the resistor layer.

[0053] In some embodiments, the ring structure includes: a conductor surrounding the resistor segment of the resistor layer; and a dielectric liner disposed along a sidewall of the conductor to separate the conductor from the resistor layer, wherein the conductor and the dielectric liner extend through the resistor layer.

[0054] In some embodiments, the electrical conductor comprises tungsten and the dielectric liner comprises tetraethyl orthosilicate.

[0055] In some embodiments, the integrated chip further includes: a via directly overlying the conductive line, wherein the via extends continuously from the first point to the second point, wherein the via is laterally offset from the ring structure by a non-zero distance; and wherein the resistor layer extends continuously from the dielectric pad to the via, so that the resistor layer laterally closes the via.

[0056] In some embodiments, the integrated chip further includes: a plurality of vias directly overlying the corresponding conductive structure, wherein the vias extend continuously from the first point to a third point disposed between the first point and the second point, respectively; and wherein the dielectric pad extends continuously along the relative side walls of each of the plurality of vias.

[0057] In some embodiments, the plurality of vias are vertically separated from the resistor segments of the resistive layer by the conductive structure.

[0058] In some embodiments, the conductive structure includes a first material and the resistive layer includes a second material different from the first material.

[0059] In some embodiments, the first material is titanium nitride and the second material is silicon chromium.

[0060] In some embodiments, the integrated chip further includes: a plurality of dielectric structures overlying corresponding conductive structures, wherein the width of the dielectric structures in the plurality of dielectric structures is greater than the width of the corresponding conductive structures. In some embodiments, the present application provides a semiconductor structure, comprising: a substrate; a resistor layer overlying the substrate; a resistor structure overlying the substrate, wherein the resistor structure includes a resistor segment of the resistor layer, a contact structure overlying the resistor segment, and a dielectric structure overlying the contact structure; and an isolation structure continuously surrounding the outer periphery of the resistor segment, wherein the isolation structure includes a conductor and a first liner extending along opposite sidewalls of the conductor.

[0061] In some embodiments, the isolation structure extends continuously through the thickness of the resistive layer.

[0062] In some embodiments, the first liner includes a first dielectric material, and the dielectric structure includes a second dielectric material different from the first dielectric material.

[0063] In some embodiments, the resistor segment of the resistive layer is laterally separated from a peripheral region of the resistive layer by the isolation structure.

[0064] In some embodiments, the thickness of the resistive layer is less than the thickness of the contact structure.

[0065] In some embodiments, the contact structure includes a first contact structure and a second contact structure, wherein the first contact structure is laterally offset from the second contact structure by a non-zero distance, wherein the resistor segment extends continuously along the non-zero distance.

[0066] In some embodiments, the isolation structure includes a first outer region, a second outer region, and a central region disposed between the first outer region and the second outer region, wherein the first outer region and the second outer region have a first width, and the central region has a second width less than the first width. In some embodiments, the present application provides a method for forming an integrated chip, the method comprising: depositing a resistive layer on a substrate, wherein the resistive layer comprises a first material; forming a conductive structure on the resistive layer, wherein the conductive structure comprises a second material different from the first material; forming an interlayer dielectric (ILD) structure on the conductive structure; patterning the ILD structure and the resistive layer to define a plurality of through-hole openings and a ring structure opening, so that the ring structure opening laterally encloses a resistor segment of the resistive layer, wherein the ring structure opening extends from an upper surface of the ILD structure to a point below the resistive layer; forming a plurality of vias in the plurality of through-hole openings; and forming a ring structure within the ring structure opening.

[0067] In some embodiments, forming the multiple vias and the ring structure includes: forming a dielectric liner, which at least partially lines the multiple through-hole openings and the ring structure openings; depositing a conductive material in the multiple through-hole openings and the ring structure openings; and performing a planarization process in the conductive material to define a conductor in the ring structure openings and define the multiple vias in the multiple through-hole openings, wherein the ring structure includes the dielectric liner and the conductor, so that the dielectric liner separates the conductor from the resistor segment of the resistive layer.

[0068] In some embodiments, the via and the ring structure are formed simultaneously.

[0069] In some embodiments, the process of forming the conductive structure includes: depositing a conductive layer on the resistive layer; depositing a dielectric layer on the conductive layer; performing a dry etching process on the dielectric layer and the conductive layer to define a dielectric structure on the conductive layer; and performing a wet etching process on the conductive layer to define the conductive structure, so that the width of the dielectric structure is greater than the width of the conductive structure.

[0070] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

[0071] [Explanation of Symbols]

[0072] 100, 300: Integrated chip

[0073] 102: Substrate

[0074] 104: First ILD structure

[0075] 106: Wire

[0076] 108: Via hole

[0077] 109: Conductor

[0078] 110: Second liner

[0079] 112: First insulator layer

[0080] 114: Resistance layer

[0081] 114p: Outlying area

[0082] 114rs: Resistor section

[0083] 115: Resistor structure

[0084] 116: Second insulator layer

[0085] 117: Ring structure

[0086] 117c: Central area

[0087] 117o1: First External Area

[0088] 117o2: Second external area

[0089] 118: First liner

[0090] 120: Contact structure

[0091] 122: Dielectric Structure

[0092] 124: Second ILD structure

[0093] 200, 400, 500b, 600b, 700b, 800b, 900b, 1000b, 1100b, 1200b, 1300b: Top view

[0094] 302a: First resistor structure

[0095] 302b: Second resistor structure

[0096] 304: Semiconductor devices

[0097] 305: Internal connection structure

[0098] 306: Source / drain region

[0099] 308: Gate dielectric layer

[0100] 310: Sidewall spacer structure

[0101] 312: Gate electrode

[0102] 314: Upper ILD layer

[0103] 500a, 600a, 700a, 800a, 900a, 1000a, 1100a, 1200a, 1300a: Cross-sectional view

[0104] 502: Contact layer

[0105] 502us: upper surface

[0106] 504: Dielectric layer

[0107] 1102: Ring structure opening

[0108] 1104: Through hole opening

[0109] 1400: Methods

[0110] 1402, 1404, 1406, 1408, 1410, 1412, 1414: Action

[0111] A-A', B-B', C-C': Line

[0112] d1: distance

[0113] W1: First width

[0114] W2: Second width

[0115] W3: Width

Claims

1. An integrated chip, characterized in that include: substrate; a resistance layer overlying the substrate; A resistor structure overlying the substrate, wherein the resistor structure comprises: a resistor segment of the resistive layer; a conductive structure overlying the resistor segment; and A ring structure laterally encloses the resistor structure, wherein the ring structure extends continuously from a first point above the conductive structure to a second point below the bottom surface of the resistive layer.

2. The integrated chip according to claim 1, wherein the ring structure comprises: an electrical conductor surrounding the resistor segment of the resistor layer; and A dielectric liner is disposed along the sidewall of the conductor to separate the conductor from the resistor layer, wherein the conductor and the dielectric liner extend through the resistor layer.

3. The integrated chip of claim 2, wherein the electrical conductor comprises tungsten and the dielectric liner comprises tetraethyl orthosilicate.

4. The integrated chip according to claim 2, further comprising: a via directly overlying the conductive line, wherein the via extends continuously from the first point to the second point, wherein the via is laterally offset from the ring structure by a non-zero distance; and The resistor layer continuously extends from the dielectric liner to the via hole, so that the resistor layer laterally closes the via hole.

5. The integrated chip according to claim 2, further comprising: A plurality of vias are directly overlying corresponding conductive structures, wherein the vias extend continuously from the first point to a third point disposed between the first point and the second point, respectively; and wherein the dielectric liner extends continuously along the opposite sidewalls of each of the plurality of vias. 6 . The integrated chip of claim 5 , wherein the plurality of vias are vertically separated from the resistor segments of the resistor layer by the conductive structure. 7 . The integrated chip of claim 1 , wherein the conductive structure comprises a first material, and the resistive layer comprises a second material different from the first material.

8. The integrated chip of claim 7, wherein the first material is titanium nitride and the second material is silicon chromium.

9. The integrated chip according to claim 1, further comprising: A plurality of dielectric structures overlying the corresponding conductive structures, wherein a width of a dielectric structure in the plurality of dielectric structures is greater than a width of the corresponding conductive structure.

10. A semiconductor structure, characterized in that include: substrate; a resistance layer overlying the substrate; a resistor structure overlying the substrate, wherein the resistor structure comprises a resistor segment of the resistor layer, a contact structure overlying the resistor segment, and a dielectric structure overlying the contact structure; and The isolation structure continuously surrounds the outer periphery of the resistor segment, wherein the isolation structure includes a conductor and a first liner extending along opposite side walls of the conductor. The semiconductor structure of claim 10 , wherein the isolation structure extends continuously through the thickness of the resistive layer. 12 . The semiconductor structure of claim 10 , wherein the first liner comprises a first dielectric material and the dielectric structure comprises a second dielectric material different from the first dielectric material.

13. The semiconductor structure of claim 10, wherein the resistor segment of the resistive layer is laterally separated from a peripheral region of the resistive layer by the isolation structure. The semiconductor structure according to claim 10 , wherein a thickness of the resistive layer is smaller than a thickness of the contact structure.

15. The semiconductor structure of claim 10, wherein the contact structure comprises a first contact structure and a second contact structure, wherein the first contact structure is laterally offset from the second contact structure by a non-zero distance, wherein the resistor segment extends continuously along the non-zero distance.

16. The semiconductor structure of claim 10, wherein the isolation structure comprises a first outer region, a second outer region, and a central region disposed between the first outer region and the second outer region, wherein the first outer region and the second outer region have a first width, and the central region has a second width smaller than the first width.

17. A method for forming an integrated chip, characterized in that include: depositing a resistive layer over a substrate, wherein the resistive layer comprises a first material; forming a conductive structure over the resistive layer, wherein the conductive structure comprises a second material different from the first material; forming an interlayer dielectric structure on the conductive structure; patterning the interlayer dielectric structure and the resistor layer to define a plurality of via openings and ring structure openings such that the ring structure openings laterally enclose the resistor segment of the resistor layer, wherein the ring structure openings extend from an upper surface of the interlayer dielectric structure to a point below the resistor layer; forming a plurality of vias in the plurality of via openings; and A ring structure is formed within the ring structure opening.

18. The method according to claim 17, wherein forming the plurality of vias and the ring structure comprises: forming a dielectric liner that at least partially lines the plurality of via openings and the ring structure opening; depositing a conductive material in the plurality of through-hole openings and the ring structure opening; and A planarization process is performed in the conductive material to define a conductor in the ring structure opening and to define the plurality of vias in the plurality of through-hole openings, wherein the ring structure includes the dielectric liner and the conductor, such that the dielectric liner separates the conductor from the resistor segment of the resistive layer. The method according to claim 18 , wherein the via and the ring structure are formed simultaneously.

20. The method according to claim 17, wherein the process of forming the conductive structure comprises: depositing a conductive layer on top of the resistive layer; depositing a dielectric layer over the conductive layer; performing a dry etching process on the dielectric layer and the conductive layer to define a dielectric structure above the conductive layer; and A wet etching process is performed on the conductive layer to define the conductive structure such that a width of the dielectric structure is greater than a width of the conductive structure.

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