Three-dimensional semiconductor device and method of forming a three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device and a method of forming a three-dimensional semiconductor device are provided. The three-dimensional semiconductor device can include a substrate having a cell region and an extension region, a word line stack disposed above the substrate, the word line stack including alternately stacked mold layers and word lines, a vertical channel structure vertically penetrating the word line stack in the cell region, and a first extension through via structure vertically penetrating the word line stack in the extension region. The first extension through via structure can include a first via plug and a first via liner layer surrounding a sidewall of the first via plug. The first via liner layer can include first recesses respectively disposed horizontally at a same level as the word lines of the word line stack.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0135208, filed on October 29, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a three-dimensional semiconductor device including a through-via structure with a protruding via pad layer and a method for forming the three-dimensional semiconductor device. Background Technology

[0003] As the integration and stacking height of three-dimensional semiconductor devices increase, the process of forming through-via structures for powering the string select lines becomes increasingly difficult. Specifically, finer patterns and through-via structures must be formed, and the through-via structures must be fully electrically insulated from the word lines. Summary of the Invention

[0004] Some exemplary embodiments of this disclosure provide a three-dimensional semiconductor device. The three-dimensional semiconductor device may include: a substrate having cell regions and extended regions; a word line stack disposed above the substrate, the word line stack including alternately stacked molded layers and word lines; a vertical channel structure vertically penetrating the word line stack in the cell regions; and a first extended through-via structure vertically penetrating the word line stack in the extended regions. The first extended through-via structure may include a first via plug and a first via pad layer surrounding the sidewalls of the first via plug. The first via pad layer may include first recesses disposed at the same level as the word lines of the word line stack.

[0005] Some exemplary embodiments of this disclosure provide a three-dimensional semiconductor device. The three-dimensional semiconductor device may include: a word line stack disposed over a substrate having cell regions and extension regions, the word line stack including alternately stacked molded layers and word lines, the word line stack extending horizontally in the cell regions and having a stepped structure in the extension regions; and a vertical channel structure, a word line dicing structure, and a first through-via structure vertically penetrating the word line stack. The first through-via structure may include a first via plug and a first via pad layer surrounding the sidewall of the first via plug. A first recess may be provided on the inner sidewall of the first via pad layer.

[0006] Some exemplary embodiments of this disclosure provide a three-dimensional semiconductor device. The three-dimensional semiconductor device may include: a substrate having a cell region, a dummy region, and an extension region; a logic device layer disposed on the substrate and including transistors and via pads; a lower interlayer insulating layer located on the logic device layer; a common source layer embedded in the lower interlayer insulating layer; a lower word line stack and a lower step insulating layer located on the lower insulating layer; an upper word line stack located on the lower word line stack; an upper step insulating layer located on the lower step insulating layer; a vertical channel structure and a word line dicing structure vertically penetrating the lower word line stack and the upper word line stack to connect to the common source layer in the cell region; a dummy vertical channel structure vertically penetrating the lower word line stack and the upper word line stack to connect to the common source layer in the dummy region; and a first through-via structure vertically penetrating a portion of the lower word line stack to electrically connect to the via pads in the extension region. The first through-hole structure may include a first through-hole plug and a first through-hole liner surrounding the sidewall of the first through-hole plug. The inner sidewall of the first through-hole liner may include a seam positioned at the same level as the letter lines of the letter line stack. The seam may have an annular or disc-shaped shape in a plan view.

[0007] Some exemplary embodiments of this disclosure provide a method for forming a three-dimensional semiconductor device. The method may include: forming a lower interlayer insulating layer over a substrate; forming a molded stack on the lower interlayer insulating layer, the molded stack including alternately stacked molded layers and sacrificial layers; forming an upper interlayer insulating layer on the molded stack; forming a vertical channel structure that vertically penetrates the upper interlayer insulating layer and the molded stack; forming a through-hole that vertically penetrates the upper interlayer insulating layer and the molded stack; partially removing the sacrificial layer of the molded stack through the through-hole to form a first recess; forming a through-via structure in the through-via including a via pad layer and a via plug filling the interior of the first recess; forming word line dicing trenches vertically penetrating the upper interlayer insulating layer and the molded stack between the vertical channel structures; removing the sacrificial layer of the molded stack through the word line dicing trench to form a second recess; forming word lines in the second recess to form a word line stack; and forming trench pads and trench plugs in the word line dicing trench to form a word line dicing structure.

[0008] Some exemplary embodiments of this disclosure provide a method for forming a three-dimensional semiconductor device. The method may include: forming a lower interlayer insulating layer having a common source layer on a substrate, the substrate having cell regions and extension regions; forming a molded stack comprising alternating molded layers and sacrificial layers on the lower interlayer insulating layer; forming an upper interlayer insulating layer on the molded stack; forming a vertical channel structure in the cell regions that vertically penetrates the upper interlayer insulating layer and the molded stack to connect with the common source layer; forming through-holes in the extension regions that vertically penetrate the upper interlayer insulating layer and the molded stack; and partially removing the sacrificial layer of the molded stack through the through-holes. To form a first recess; to form a through-hole pad and a through-hole plug surrounded by the through-hole pad to form a through-hole structure, the outer surface of the through-hole pad including a protrusion protruding toward the sacrificial layer; to form a letter line cutting groove vertically penetrating the upper interlayer insulation layer and the molded stack between vertical channel structures; to remove the sacrificial layer of the molded stack through the letter line cutting groove to form a second recess; to form letter lines in the second recess to form a letter line stack; and to form a groove pad and a groove plug in the letter line cutting groove to form a letter line cutting structure.

[0009] Some exemplary embodiments of this disclosure provide a method for forming a three-dimensional semiconductor device. The method may include: forming a logic device layer with via pads on a substrate having cell regions and extended regions; forming a lower interlayer insulating layer having a common source layer on the logic device layer; forming a molded stack having alternating molded layers and sacrificial layers on the lower interlayer insulating layer; forming an upper interlayer insulating layer on the molded stack; forming a vertical channel structure that vertically penetrates the upper interlayer insulating layer and the molded stack to be electrically connected to the common source layer; forming a through-hole that vertically penetrates the upper interlayer insulating layer, the molded stack, and the lower interlayer insulating layer to expose the upper surface of the via pads; and passing through the through-hole portion... The sacrificial layer of the molded stack is removed to form a first recess; a via pad and a via plug are formed to fill the interior of the first recess to form a through-via structure electrically connected to the via pad; a word line cutting trench is formed between the vertical channel structures to penetrate the upper interlayer insulation layer and the molded stack to expose the upper surface of the common source layer; the sacrificial layer of the molded stack is removed through the word line cutting trench to form a second recess; word lines are formed in the second recess to form a word line stack; and a trench pad and a trench plug are formed in the word line cutting trench to form a word line cutting structure electrically connected to the common source layer. Attached Figure Description

[0010] Figures 1A to 1D This is a schematic layout of a three-dimensional semiconductor device according to various embodiments of the present disclosure.

[0011] Figures 2A to 2G This is a schematic longitudinal sectional view of a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 3 to 18 This is a diagram illustrating a method for forming a three-dimensional memory device according to some example embodiments of the present disclosure.

[0013] Figures 19A to 19C This is a view illustrating a method of forming a three-dimensional semiconductor device according to some example embodiments of the present disclosure. Detailed Implementation

[0014] Figures 1A to 1D This is a schematic layout of a three-dimensional semiconductor device according to various exemplary embodiments of the present disclosure. (Refer to...) Figure 1A A three-dimensional semiconductor device according to some example embodiments of the present disclosure may include a cell region CA, a dummy region DA, and an extension region EA. The dummy region DA may be disposed between the cell region CA and the extension region EA.

[0015] Multiple vertical channel structures (VCs) can be set in the unit region CA. Multiple dummy vertical channel structures (DVCs) can be set in the dummy region DA. The extension region EA may include a first word line contact region MCA1, a second word line contact region MCA2, a first extension through-hole region ETA1, and a second extension through-hole region ETA2.

[0016] A first dummy contact MC1 and a first dummy contact DMC1 can be disposed within a first dummy contact area MCA1. Four first dummy contacts DMC1 can surround a first dummy contact MC1. A second dummy contact MC2 and a second dummy contact DMC2 can be disposed within a second dummy contact area MCA2. Four second dummy contacts DMC2 can surround a second dummy contact MC2. The first dummy contact DMC1 and the second dummy contact DMC2 can have an elliptical shape.

[0017] The first extended through-hole region ETA1 can be located between the first word line contact region MCA1 and the second word line contact region MCA2. The first extended through-hole structure TVE1 can be located in the first extended through-hole region ETA1. For example, the first extended through-hole structure TVE1 can be arranged in a Z-shape in both the row and column directions, but other arrangements can be used.

[0018] The second extended through-via region ETA2 can be located on one side of the second word line contact region MCA2. For example, the second word line contact region MCA2 can be located between the first extended through-via region ETA1 and the second extended through-via region ETA2. The second extended through-via structure TVE2 and the common source via TCS can be located in the second extended through-via region ETA2.

[0019] Word line cutters LC1, LC2, and LC3 can be arranged to extend parallel to each other in the row direction. Word line cutters LC1, LC2, and LC3 can include a first word line cutter LC1, a second word line cutter LC2, and a third word line cutter LC3. A pair of first word line cutters LC1 can define a main string select line SSL.

[0020] The second word line cutter structure LC2 can be respectively disposed at the center between the two first word line cutter structures LC1. The second word line cutter structure LC2 can separate a main string select line SSL into a first string select line pair SSLa and a second string select line pair SSLb. The second word line cutter structure LC2 can have multiple long segments extending parallel to each other along the column direction on the same line. The main string select lines SSL can be electrically activated independently. For example, the main string select lines SSL can be electrically insulated from each other.

[0021] The third word line cutting structure LC3 can be respectively positioned at the center between the first word line cutting structure LC1 and the second word line cutting structure LC2. The third word line cutting structure LC3 can separate the first string selection line pair SSLa into the first substring selection line SSL1 and the second substring selection line SSL2, and separate the second string selection line pair SSLb into the third substring selection line SSL3 and the fourth substring selection line SSL4. The third word line cutting structure LC3 can have multiple short segments extending parallel to each other along the column direction on the same line.

[0022] The first substring select line SSL1 to the fourth substring select line SSL4 can be electrically connected to each other. For example, the first substring select line SSL1 to the fourth substring select line SSL4 can form a main string select line SSL, and can be electrically enabled and disabled simultaneously. In some example embodiments, the second word line cutting structure LC2 and / or the third word line cutting structure LC3 can be string select line cutting structures.

[0023] Reference Figure 1B ,and Figure 1A Compared to the three-dimensional semiconductor device shown, the three-dimensional semiconductor device according to some example embodiments of this disclosure may include a second word line cut structure LC2 having a short segment structure in the extended region EA. For example, the second word line cut structure LC2 may not extend between the first extended through-hole structures TVE1. Additional first extended through-hole structures TVE1 may be further formed between locations where the second word line cut structure LC2 is omitted, for example, formed between the second word line cut structures LC2.

[0024] Reference Figure 1C A three-dimensional semiconductor device according to some example embodiments of this disclosure may include a cell region CA, a dummy region DA, and an extended region EA. Figure 1ACompared to the three-dimensional semiconductor device shown, the cell region CA may include a first cell region CA1, a second cell region CA2, and a cell through-hole region CTA. The cell through-hole region CTA may be disposed between the first cell region CA1 and the second cell region CA2. The second cell region CA2 may be disposed adjacent to the extension region EA. Multiple vertical channel structures VC may be disposed in the first cell region CA1 and the second cell region CA2. Multiple cell through-hole structures TVC may be disposed in the cell through-hole region CTA. See reference... Figure 1A To understand the other components.

[0025] Reference Figure 1D Further reference Figure 1B and Figure 1C A three-dimensional semiconductor device according to some example embodiments of this disclosure may include a second word line cut structure LC2 having a short segment structure in a cell region CA. For example, the second word line cut structure LC2 may not extend between cell through-hole structures TVC in a cell through-hole region CTA. Additional cell through-hole structures TVC may be further formed at locations where the second word line cut structure LC2 is omitted. (Refer to...) Figures 1A to 1C To understand the other components and more detailed descriptions.

[0026] Figures 2A to 2G This is a schematic longitudinal sectional view of a three-dimensional semiconductor device according to an embodiment of the present disclosure. For example, Figure 2A It is along Figure 1C The longitudinal sectional view taken by line I-I'. Figure 2B and 2C yes Figure 2A An enlarged view of a portion of the three-dimensional semiconductor device shown.

[0027] Reference Figure 2A A three-dimensional semiconductor device according to some example embodiments of the present disclosure may include a logic device layer LD and a memory device layer MD disposed on a substrate 10.

[0028] The logic device layer LD may include multiple transistors 11, multiple logic vias 12, multiple logic conductors 13, multiple via pads (or "solder pads") 14 and an inter-logic layer 15 disposed on the substrate 10.

[0029] The substrate 10 may include a semiconductor layer such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), an epitaxial growth layer, and / or silicon on insulator (SOI).

[0030] Transistor 11 may include a gate insulating layer, a gate electrode, a gate capping layer, and a gate spacer formed on substrate 10. Reference numerals for the gate insulating layer, gate electrode, gate capping layer, and gate spacer have been omitted to avoid complex figures. Additionally, transistor 11 may include a source region, a drain region, and a channel region formed in substrate 10. The source region, drain region, and channel region are not shown to avoid complex figures.

[0031] The logic via 12 may include a conductive via pattern having a cylindrical shape extending in the vertical direction, and the logic conductor 13 may include a plurality of conductor patterns having a line shape extending in the horizontal direction.

[0032] Via pad 14 may include multiple conductive patterns exposed on logic interlayer insulating layer 15. Via pad 14 may have a pad shape, mesa shape, and / or line shape. The gate electrode, logic via 12, logic conductor 13, and via pad 14 of transistor 11 may include conductors, and the gate insulating layer, gate cap layer, and gate spacer of transistor 11, as well as logic interlayer insulating layer 15, may include insulators.

[0033] The logic layer insulating layer 15 can cover the transistor 11, logic via 12, and logic conductor 13 on the substrate 10. The logic layer insulating layer 15 can cover the side and bottom surfaces of the via pad 14.

[0034] The memory device layer MD may include a common source layer 21, a lower word line stack WS1 and a lower step insulating layer 17 in the lower interlayer insulating layer 20, an intermediate interlayer insulating layer 22, an upper word line stack WS2 and an upper step insulating layer 18, an upper interlayer insulating layer 24, a vertical channel structure VC, a cell through-hole structure TVC, a dummy vertical channel structure DVC, a first extended through-hole structure TVE1 and a second extended through-hole structure TVE2, a common source via TCS, and a first word line contact MC1 and a second word line contact MC2. The memory device layer MD may also include cap layers 41 to 43, vertical conductors 51 to 55, and horizontal conductors 61 to 65.

[0035] The lower interlayer insulating layer 20, the middle interlayer insulating layer 22, and the upper interlayer insulating layer 24 may include an insulator such as silicon oxide. In some example embodiments, the lower interlayer insulating layer 20 may include multiple insulating layers, including silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and / or other insulators.

[0036] The common source layer 21 may include a conductor. For example, the common source layer 21 may include N-doped polysilicon, metal silicide, metal compound, and / or metal. The common source layer 21 may be embedded in the underlying interlayer insulating layer 20.

[0037] The lower word line stack WS1 may include alternating horizontally stacked lower molding layers 25 and word lines 30, and the upper word line stack WS2 may include alternating horizontally stacked upper molding layers 27 and word lines 30. The lower molding layers 25 and upper molding layers 27 may include silicon oxide-based insulators. The word lines 30 may include conductors. For example, the word lines 30 may include a word line barrier layer and word line electrodes. The word line barrier layer may include both an insulating barrier layer and a conductive barrier layer. The insulating barrier layer may include an insulator having a higher work function than silicon oxide, such as aluminum oxide (Al2O3), and the conductive barrier layer may include a diffusion-blocking material, such as titanium nitride. The word line electrodes may include metals such as tungsten. The lower word line stack WS1 and the upper word line stack WS2 may have a stepped structure in the extension region EA. In the extension region EA, the stepped structure of the lower word line stack WS1 may be covered by the lower stepped insulating layer 17, and the stepped structure of the upper word line stack WS2 may be covered by the upper stepped insulating layer 18. As indicated herein, the “stepped structure” of the letter lines or other disclosed features will be understood to represent a structure and / or a portion of a structure (e.g., letter line stack WS1) of elements (e.g., lower molding layer 25 and letter lines 30) having different dimensions (e.g., lengths) in one or more directions perpendicular to or substantially perpendicular to the “vertical direction,” wherein the elements of this structure have lengths in one or more directions that vary inversely with their distance from the bottom surface of the substrate 10 in the vertical direction (e.g., letter lines 30 farther from the bottom surface of the substrate 10 have shorter lengths than letter lines 30 closer to the bottom surface of the substrate 10). As a result, at least as Figure 2A As shown, the heights of the stepped structures in the vertical direction are staggered along the vertical direction.

[0038] Although the terms “identical” or “the same” are used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is the same as the other element or value within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0039] The vertical channel structure VC can vertically penetrate the lower word line stack WS1 and upper word line stack WS2 in the first cell region CA1 and the second cell region CA2 in the cell region CA. The vertical channel structure VC can be vertically aligned with the common source layer 21 in the lower interlayer insulating layer 20. The lower end of the vertical channel structure VC can be electrically connected to the common source layer 21 in the lower interlayer insulating layer 20. The vertical channel structure VC can include inner pillars and memory layers. The memory layer can include a barrier layer, a charge trap layer, a tunneling insulating layer, and a channel layer. The channel layer can cover the outer surface of the inner pillar, the tunneling insulating layer can cover the outer surface of the channel layer, the charge trap layer can cover the outer surface of the tunneling insulating layer, and the barrier layer can cover the outer surface of the charge trap layer. The inner pillar can have a columnar shape. The channel layer, the tunneling insulating layer, and the charge trap layer can have a cylindrical shape. The barrier layer can have a spaced-apart (e.g., isolated from each other and not in direct contact) and stacked multi-ring shape.

[0040] The through-cell via (TVC) structure can vertically penetrate the lower word line stack WS1 and the upper word line stack WS2 in the cell region CA and cell region CTA. The TVC structure can also vertically penetrate the intermediate interlayer insulating layer 22 and the lower interlayer insulating layer 20 to electrically connect to the via pad 14 of the logic device layer LD. The TVC structure is fully insulated from the lower word line stack WS1 and the upper word line stack WS2.

[0041] Further reference Figure 2B Each through-hole structure TVC may include a via pad layer 31 and a via plug 32. For example, the via pad layer 31 may include a silicon oxide-based insulator, and the via plug 32 may include a conductor such as N-doped silicon, metal silicide, metal, and / or metal compound. The via plug 32 may have a cylindrical shape. The via pad layer 31 may have a cylindrical shape surrounding the via plug 32. The via pad layer 31 may include a protrusion P that projects horizontally from its outer surface toward word lines 30 between molding layers 25 and between molding layers 27. The protrusion P may be positioned at the same level as the word lines 30. The via pad layer 31 may also include a recess D on its inner surface, the recess D being formed to correspond to the protrusion P, i.e., the point or tip of the recess D may be located at substantially the same level as the center of the corresponding protrusion P, or at another location at the same level as the corresponding protrusion P. The recess D may have an annular or disc shape in a plan view. Therefore, the recess D can take the form of a ring-like seam at the same level, and the seam can have a ring shape or a disc shape in the plan view. A portion 30R of the letter line 30 can be retained between the protruding portions P of the through-hole structure TVC of adjacent units. (Refer to...) Figure 2CIn some example embodiments, the via liner 31 may include a protruding portion P, but may not include it. Figure 2B The second through-hole structure TVE2 may have a recess D. For example, the through-hole liner 31 of the second through-hole structure TVE2 may have vertically flat inner and outer walls. The through-hole liner 31 of the second through-hole structure TVE2 may not have a recess D and a protrusion P. In some example embodiments, the second through-hole structure TVE2 may have a recess D at a selected protrusion P (e.g., alternating protrusions P) or only on one inner wall of the second through-hole structure TVE2.

[0042] A dummy vertical channel structure (DVC) can be located in a dummy region DA between the cell region CA and the extension region EA. The DVC can have a structure substantially the same as a vertical channel structure (VC). For example, the DVC may include inner pillars and memory layers. The DVC can vertically penetrate the upper interlayer insulating layer 24, the upper word line stack WS2, the middle interlayer insulating layer 22, and the lower word line stack WS1 to connect with the common source layer 21 in the lower interlayer insulating layer 20. In a top view, the DVC may have a larger diameter than the VC.

[0043] The first extended through-via structure TVE1 can selectively vertically penetrate the upper interlayer insulating layer 24, upper step insulating layer 18, upper word line stack WS2, middle interlayer insulating layer 22, lower word line stack WS1, lower step insulating layer 17, and lower interlayer insulating layer 20 in the first extended through-via region ETA1 within the extended region EA, to electrically connect with the via pad 14 in the logic device layer LD. The first extended through-via structure TVE1 can have a structure substantially the same as that of the cell through-via structure TVC. Therefore, the first extended through-via structure TVE1 can have a reference... Figure 2B and Figure 2C The structure described. The first extended through-hole region ETA1 can have a flat region FZ with a shape similar to a staircase landing. In the flat region FZ, the word line stacks WS1 and WS2 can have a horizontal extension without a stepped shape. Therefore, the first extended through-hole structure TVE1 can be set within the flat region FZ.

[0044] The second extended through-via structure TVE2 can vertically penetrate the upper interlayer insulating layer 24, the upper stepped insulating layer 18, the middle interlayer insulating layer 22, the lower stepped insulating layer 17, and the lower interlayer insulating layer 20 to electrically connect with the via pad 14 in the logic device layer LD in the second extended through-via region ETA2 in the extended region EA. For example, the second extended through-via structure TVE2 may not penetrate the lower word line stack WS1 and the upper word line stack WS2.

[0045] The common-source via TCS can vertically penetrate the upper interlayer insulation layer 24, the upper stepped insulation layer 18, the middle interlayer insulation layer 22, and the lower stepped insulation layer 17 to electrically connect with the common-source layer 21 in the lower interlayer insulation layer 20 of the second extended through-via region ETA2 in the extended region EA. For example, the common-source via TCS may not penetrate the lower word line stack WS1 and the upper word line stack WS2.

[0046] The first letter contact MC1 and the second letter contact MC2 can selectively penetrate vertically through the upper interlayer insulation layer 24, the upper stepped insulation layer 18, the middle interlayer insulation layer 22 and the lower stepped insulation layer 17 to be electrically connected to the letter 30, respectively.

[0047] Figures 1A to 1D The first dummy contact DMC1 and the second dummy contact DMC2 shown can be disposed in the extension region EA and can have a structure substantially the same as that of the dummy vertical channel structure DVC. For example, the first dummy contact DMC1 and the second dummy contact DMC2 can selectively penetrate vertically through the upper interlayer insulation layer 24, the upper step insulation layer 18, the upper word line stack WS2, the middle interlayer insulation layer 22, the lower word line stack WS1, and the lower step insulation layer 17.

[0048] Cap layers 41 to 43 may include a lower cap layer 41, a middle cap layer 42, and an upper cap layer 43. Vertical conductors 51 to 55 may include a vertical channel via plug 51, a cell through-via post 52, an extended through-via post 53, a common source via plug 54, and a word line via plug 55. Horizontal conductors 61 to 65 may include a bit line 61, a cell through-via connection conductor 62, an extended through-via connection conductor 63, a common source connection conductor 64, and a word line connection conductor 65. Vertical conductors 51-55 and horizontal conductors 61-65 may optionally be omitted. Vertical conductors 51-55 and horizontal conductors 61-65 may not be formed on the dummy vertical channel structure (DVC). Cap layers 41-43 may include an insulating material such as silicon oxide. Vertical conductors 51-55 and horizontal conductors 61-65 may include a conductive material such as metal.

[0049] Reference Figure 2D ,and Figure 2ACompared to the three-dimensional semiconductor device shown, the three-dimensional semiconductor device according to some example embodiments of this disclosure may not include the cell through-hole structure (TVC) in the cell region CA. For example, Figure 2D The three-dimensional semiconductor device shown can have Figure 1A or Figure 1B The layout or top view shown.

[0050] Reference Figure 2E A three-dimensional semiconductor device according to some example embodiments of this disclosure may include a lower interlayer insulating layer 20, a common source layer 21, a via conductor layer 35, a lower word line stack WS1 and a lower step insulating layer 17, an intermediate interlayer insulating layer 22, an upper word line stack WS2 and an upper step insulating layer 18, an upper interlayer insulating layer 24, a vertical channel structure VC, a cell through-hole structure TVC, a dummy vertical channel structure DVC, a first extended through-hole structure TVE1 and a second extended through-hole structure TVE2, a common source via TCS, and a first word line contact MC1 and a second word line contact MC2 on a substrate 10. The memory device layer MD may also include capping layers 41 to 43, vertical conductors 51 to 55, and horizontal conductors 61 to 65. The via conductor layer 35 may include N-doped polysilicon, metal silicide, metal compound, or metal. The via conductor layer 35 may be embedded in the lower interlayer insulating layer 20.

[0051] The common source layer 21 and the via conductor layer 35 can be electrically insulated. The vertical channel structure VC, the dummy vertical channel structure DVC, and the common source via TCS can be electrically connected to the common source layer 21, and the via conductor layer 35 can be electrically connected to the cell through-via structure TVC and the first and second extended through-via structures TVE1 and TVE2.

[0052] Reference Figure 2F and Figure 2G , and reference Figures 2A to 2C Compared to the three-dimensional semiconductor devices shown and described, the three-dimensional semiconductor devices according to some example embodiments of this disclosure may not include any word lines between adjacent through-via structures TVC and TVE1. For example, the protruding portions P of the via pad layers 31 of adjacent through-via structures TVC and TVE1 may be horizontally connected to each other.

[0053] Figures 3 to 18 This is a diagram illustrating a method for forming a three-dimensional memory device according to some exemplary embodiments of the present disclosure. (Refer to...) Figure 3A method for forming a three-dimensional memory device may include forming a logic device layer LD on a substrate 10. The steps of forming the logic device layer LD may include forming transistors 11, logic vias 12, logic conductors 13, via pads 14, and an inter-layer insulating layer 15 on the substrate 10. The substrate 10 may include a semiconductor material layer such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), an epitaxial growth layer, and / or silicon-on-insulator (SOI). The steps of forming transistors 11 may include performing deposition, photolithography, and / or etching processes to form a gate insulating layer, a gate electrode, a gate capping layer, and a gate spacer on the substrate 10. Reference numerals for the gate insulating layer, gate electrode, gate capping layer, and gate spacer have been omitted to avoid... Figure 3 The complexity of the process.

[0054] Additionally, the step of forming transistor 11 may include forming a source region, a drain region, and a channel region in substrate 10 by performing an ion implantation process. To avoid Figure 3 The complexity is shown in the diagram, with the source region, drain region, and channel region not shown.

[0055] The step of forming logic via 12 may include performing a deposition process and a patterning process to form a plurality of conductive via patterns having a vertically extending cylindrical shape. The step of forming logic conductor 13 may include performing a deposition process and a patterning process to form a plurality of conductor patterns having a horizontally extending line shape. The step of forming via pad 14 may include performing a deposition process and a patterning process to form a plurality of conductor patterns exposed on the logic interlayer insulating layer 15.

[0056] Reference Figure 4 The method may include forming a lower interlayer insulating layer 20 and a common source layer 21 on a logic device layer LD. The common source layer 21 may include a conductor in the form of a plate or a wire. For example, the common source layer 21 may include a conductor such as N-doped silicon, a metal, a metal silicide, a metal alloy, and / or a metal compound. N-doped silicon may be polycrystalline silicon doped with N-type impurities such as phosphorus (P), arsenic (As), and / or antimony (Sb). The lower interlayer insulating layer 20 may include a silicon oxide-based material such as SiOC, SiOH, and / or SiCHO. The top surface of the common source layer 21 may be exposed and not covered by the lower interlayer insulating layer 20.

[0057] Reference Figure 5The method may include forming a lower molded stack MS1, a lower stepped insulating layer 17, and an intermediate interlayer insulating layer 22 on a lower interlayer insulating layer 20 and a common source layer 21. The lower molded stack MS1 may include alternately stacked lower molded layers 25 and lower sacrificial layers 26. The lower molded layers 25 and lower sacrificial layers 26 may include different materials to have etch selectivity. For example, the lower molded layer 25 may include silicon oxide, and the lower sacrificial layer 26 may include silicon nitride. In the extended region EA, the lower molded stack MS1 may have a stepped structure. In the second extended through-via region ETA2 of the extended region EA, the common source layer 21 may be exposed and not covered by the lower molded stack MS1. In the extended region EA, the stepped structure of the lower molded stack MS1 may be covered by the lower stepped insulating layer 17. An intermediate interlayer insulating layer 22 may be formed on the lower molded stack MS1 and the lower stepped insulating layer 17. The lower stepped insulating layer 17 and the intermediate interlayer insulating layer 22 may include silicon oxide.

[0058] Reference Figure 6 The method may include forming a lower vertical channel via Hvc1 and a lower dummy vertical channel via Hdvc1, and filling the inner sides of the lower vertical channel via Hvc1 and the lower dummy vertical channel via Hdvc1 with a sacrificial material 16. The lower vertical channel via Hvc1 and the lower dummy vertical channel via Hdvc1 may vertically penetrate the lower molded stack MS1 to expose the upper surface of the common source layer 21. The sacrificial material 16 in the lower vertical channel via Hvc1 and the lower dummy vertical channel via Hdvc1 may include a spin-coated hard mask (SOH), a polymeric organic material, polysilicon, silicon carbide (SiC), silicon germanium (SiGe), silicon oxide, and / or other materials with etch selectivity relative to silicon nitride. In some example embodiments, the sacrificial material 16 in the lower vertical channel via Hvc1 and the lower dummy vertical channel via Hdvc1 may be a single layer or a double layer.

[0059] Reference Figure 7The method may include forming an upper molded stack MS2, an upper stepped insulating layer 18, and an upper interlayer insulating layer 24 on an intermediate interlayer insulating layer 22, and forming an upper vertical channel via Hvc2 and an upper dummy vertical channel via Hdvc2. The upper molded stack MS2 may include alternating stacked upper molded layers 27 and upper sacrificial layers 28. The upper molded layer 27 may include silicon oxide, and the upper sacrificial layer 28 may include silicon nitride. In the extended region EA, the upper molded stack MS2 may have a stepped structure together with the lower molded stack MS1. In the extended region EA, the stepped structure of the upper molded stack MS2 may be covered by the upper stepped insulating layer 18. The upper interlayer insulating layer 24 may be formed on the upper molded stack MS2 and the upper stepped insulating layer 18. The upper stepped insulating layer 18 and the upper interlayer insulating layer 24 may include silicon oxide. The upper vertical channel hole Hvc2 and the upper dummy vertical channel hole Hdvc2 can vertically penetrate the upper molded stack MS2 to align with and connect to the lower vertical channel hole Hvc1 and the lower dummy vertical channel hole Hdvc1, respectively. In the extension region EA, the upper molded stack MS2 can have a flat region FZ. The flat region FZ can have a stepped platform shape. The flat region FZ can overlap with the first extended through-hole region ETA1 in the extension region EA. In some example embodiments, the lower molded stack MS1 and the upper molded stack MS2 can independently have at least one or more flat regions FZ.

[0060] Reference Figure 8 The method may include removing sacrificial material 16 from the lower vertical channel hole Hvc1 and the lower dummy vertical channel hole Hdvc1, and forming a vertical channel structure VC and a dummy vertical channel structure DVC. The step of forming the vertical channel structure VC and the dummy vertical channel structure DVC may include forming a memory layer in the lower vertical channel hole Hvc1, the upper vertical channel hole Hvc2, the lower dummy vertical channel hole Hdvc1, and the upper dummy vertical channel hole Hdvc2.

[0061] Reference Figure 9The method may include forming a unit through-hole Hcv, a first extended through-hole Hev1, a second extended through-hole Hev2, and a common source via Hcs. The step of forming the unit through-hole Hcv may include vertically penetrating the upper molded stack MS2 and the lower molded stack MS1 to expose the upper surface of the via pad 14. The step of forming the first extended through-hole Hev1 may include selectively vertically penetrating the upper interlayer insulation layer 24, the upper stepped insulation layer 18, the upper molded stack MS2, the intermediate interlayer insulation layer 22, and the lower molded stack MS1 to expose the upper surface of the via pad 14 in the flat region FZ. The step of forming the second extended through-hole Hev2 may include vertically penetrating the upper interlayer insulation layer 24, the upper stepped insulation layer 18, the intermediate interlayer insulation layer 22, the lower stepped insulation layer 17, and the lower interlayer insulation layer 20 to expose the upper surface of the via pad 14. The steps of forming the common source via Hcs may include vertically penetrating the upper interlayer insulation layer 24, the upper stepped insulation layer 18, the middle interlayer insulation layer 22 and the lower stepped insulation layer 17 to expose the upper surface of the common source layer 21.

[0062] Reference Figure 10A The method may include performing an extended process to partially remove the upper sacrificial layer 28 and the lower sacrificial layer 26 exposed in the unit through-hole Hcv and the first extended through-hole Hev1. The extended process may include a wet full etch-back process using phosphoric acid (H3PO4).

[0063] Figure 10B and Figure 10C This is a schematic diagram showing the partial removal of the upper sacrificial layer 28 and the lower sacrificial layer 26 exposed in the cell through-hole Hcv and the first extended through-hole Hev1 by an extended process. Figure 10B Is it a top view or a floor plan? Figure 10C This is a longitudinal sectional view. (Refer to...) Figure 10B and Figure 10C The upper sacrificial layer 28 and lower sacrificial layer 26 exposed in the cell through-hole Hcv and the first extended through-hole Hev1 can be removed in a circular or annular shape by an extended process. Therefore, a recess R1 can be formed in the horizontal direction. A portion of the upper sacrificial layer 28 and lower sacrificial layer 26 can remain between adjacent cell through-holes Hcv and adjacent first extended through-holes Hev1.

[0064] Reference Figure 11AThe method may include performing a deposition process to form a via pad material layer 31a on the inner sidewalls of the unit through-hole Hcv, the first extended through-hole Hev1, the second extended through-hole Hev2, and the common source via Hcs. The via pad material layer 31a may fill the inner side of the recess R1 and may be conformally formed on the inner sidewalls and bottom surface of the unit through-hole Hcv, the first extended through-hole Hev1, the second extended through-hole Hev2, and the common source via Hcs, as well as on the upper interlayer insulating layer 24.

[0065] Figure 11B yes Figure 11A A magnified view of a portion of the image. (Refer to...) Figure 11B The through-hole liner material layer 31a may include a recess D formed at a position horizontally aligned with the recess R1. The through-hole liner material layer 31a may include a protrusion P that fills the recess R1.

[0066] Reference Figure 12A The method may include anisotropically etching a via pad material layer 31a to conformally form a via pad layer 31 on the inner walls of the unit through-hole Hcv, the first extended through-hole Hev1, the second extended through-hole Hev2, and the common source via Hcs. The upper surface of the via pad 14 may be exposed. The via pad layer 31 may have a protruding portion P that fills the inner side of the recess R1, and may be conformally formed on the inner walls of the unit through-hole Hcv, the first extended through-hole Hev1, the second extended through-hole Hev2, and the common source via Hcs.

[0067] Figure 12B yes Figure 12A A magnified view of a portion of the image. (Refer to...) Figure 12B The through-hole liner 31 may include a recess D formed at a position horizontally aligned with the recess R1. (See reference...) Figure 11B The recess D can be maintained. As mentioned above, the recess D can be annular or disc-shaped in the top view. That is, the protruding portion P and the recess D can have annular or circular shapes in the plan view or horizontal sectional view. The distance between the through-hole plug 32 and the upper sacrificial layer 28 and lower sacrificial layer 26, which will be formed into the word line 30, can be greater than the distance between the through-hole plug 32 and the molding layers 25 and 27. Therefore, the through-hole plug 32 and the word line 30 can be more electrically insulated.

[0068] Reference Figure 13AThe method may include filling the inside of the unit through-hole Hcv, the first extended through-hole Hev1, the second extended through-hole Hev2, and the common source through-hole Hcs with a conductive material to form a unit through-hole structure TVC, a first extended through-hole structure TVE1, a second extended through-hole structure TVE2, and a common source through-hole TCS. The unit through-hole structure TVC, the first extended through-hole structure TVE1, the second extended through-hole structure TVE2, and the common source through-hole TCS may each include a through-hole liner layer 31 and a through-hole plug 32. The through-hole plug 32 may include a metal, a metal compound, and / or a metal alloy.

[0069] Figure 13B yes Figure 13A A magnified view of a portion of the image. (Refer to...) Figure 13B The through-hole plug 32 may include an edge portion E that fills the recess D. In a horizontal sectional view or a top view, the edge portion E may have an annular or disc-shaped shape. In other embodiments, a small gap may be maintained between the through-hole plug 32 and the recess D.

[0070] Reference Figure 14 The method may include forming word line dicing trenches Tlc in the cell region CA. The word line dicing trenches Tlc may be disposed between vertical channel structures VC in the cell region CA to expose the top surface of the common source layer 21. (See reference...) Figures 1A to 1D The character line cutting groove Tlc can have a line shape or a multi-segment shape in a top view. For example, the character line cutting groove Tlc may include a first groove forming a first character line cutting structure LC1, a second groove forming a second character line cutting structure LC2, and a third groove forming a third character line cutting structure. That is, grooves for forming character line cutting structures LC1, LC2, and LC3 can be formed simultaneously.

[0071] Reference Figure 15 The method may include performing a removal process to remove the upper sacrificial layer 28 and the lower sacrificial layer 26 by cutting a word line trench Tlc. By removing the upper sacrificial layer 28 and the lower sacrificial layer 26, a recess R2 for forming the word line can be formed. The removal process may include a wet full etch process using phosphoric acid (H3PO4).

[0072] Reference Figure 16The method may include performing a word line replacement process to form word lines 30 in a recess R2. Each word line 30 may include a word line barrier layer and a word line electrode. The word line barrier layer may include an insulating barrier layer such as aluminum oxide (Al2O3) and a conductive barrier layer such as titanium nitride (TiN). The word line electrode may include a metal such as tungsten (W). In this process, a lower molding stack MS1 may be formed as a lower word line stack WS1, and an upper molding stack MS2 may be formed as an upper word line stack WS2. Therefore, the lower word line stack WS1 may include alternately stacked lower molding layers 25 and word lines 30, and the upper word line stack WS2 may include alternately stacked upper molding layers 27 and word lines 30.

[0073] Reference Figure 17 The method may include filling the inside of a word line dicing trench Tlc to form a word line dicing structure WL. The step of forming the word line dicing structure WL may include forming a wire-diced structure LC1 including a trench liner layer 33 and a trench plug 34 in the word line dicing trench Tlc. The trench plug 34 may be electrically connected to a common source layer 21. The step of forming the trench liner layer 33 may include performing a deposition process and an etch-back process. The trench liner layer 33 may include an insulator, such as silicon oxide. The step of forming the trench plug 34 may include performing a deposition process and a planarization process. The trench plug 34 may include a conductor such as a metal or doped silicon.

[0074] Reference Figure 18 The method may include forming a first word line contact MC1 and a second word line contact MC2 in an extension region EA. The first word line contact MC1 may be disposed in a first word line contact region MCA1 of the extension region EA, and the second word line contact MC2 may be disposed in a second word line contact region MCA2 of the extension region EA. The first word line contact MC1 and the second word line contact MC2 may selectively penetrate vertically through the upper interlayer insulation layer 24, the upper stepped insulation layer 18, the middle interlayer insulation layer 22, and the lower stepped insulation layer 17 to respectively engage with the ends of the stepped word lines 30.

[0075] Subsequently, referring to Figure 2AThe method may include forming capping layers 41 to 43, vertical conductors 51 to 55, and horizontal conductors 61 to 65 on the upper word line stack WS2. The step of forming capping layers 41-43 may include forming a lower capping layer 41, an intermediate capping layer 42, and an upper capping layer 43. The step of forming vertical conductors 51-55 may include forming a vertical channel via plug 51, a cell through-via post 52, an extended through-via post 53, a common source via plug 54, and a word line via plug 55. The step of forming horizontal conductors 61-65 may include forming a bit line 61, a cell through-via connection conductor 62, an extended through-via connection conductor 63, a common source connection conductor 64, and a word line connection conductor 65. At least one of the vertical conductors 51-55 and at least one of the horizontal conductors 61-65 may be optionally omitted. Capping layers 41-43 may include an insulating material such as silicon oxide. Vertical conductors 51-55 and horizontal conductors 61-65 may include conductive materials such as metals.

[0076] Figures 19A to 19C This is a view illustrating a method of forming a three-dimensional semiconductor device according to some example embodiments of the present disclosure. (Refer to...) Figure 19A and Figure 19B The method for forming a three-dimensional semiconductor device according to some example embodiments of the present disclosure may include performing reference to Figures 3 to 12A and Figure 12B The described process and the execution of the etch-back process to remove Figure 12B The recess D is shown in the figure. The through-hole liner layer 31 may be retained only in the recess R1. For example, only the protrusion P may be formed. The protrusion P may have an annular shape in the top view.

[0077] Reference Figure 19C The method may include forming a via liner layer 31 on the inner walls of the unit through-hole Hcv, the first extended through-hole Hev1, the second extended through-hole Hev2, and the common source via Hcs. The inner sidewall of the via liner layer 31 may be flat without any depressions D.

[0078] Subsequently, the method may include executing a reference. Figure 13A and Figures 13B to 18 The described process and further implementation reference Figure 2A and Figure 2B The described process.

[0079] The three-dimensional semiconductor device according to an example embodiment of the present disclosure does not include a cell region for forming a through-via structure, and because the through-via structure can be formed in a narrow region, the integration density can be improved.

[0080] In a three-dimensional semiconductor device according to an exemplary embodiment of the present disclosure, the device can operate faster and power consumption can be reduced because the width between the word lines and the through-hole structure is widened.

[0081] The method for forming a three-dimensional semiconductor device according to an exemplary embodiment of the present disclosure provides for forming a through-via structure prior to forming a word line dicing structure. Therefore, the process margin for forming the through-via structure can be improved.

[0082] Although exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the disclosure and without changing its essential features. Therefore, the above embodiments should be considered descriptive only and not for limiting purposes.

Claims

1. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: The base has unit regions and extended regions; A letter line stack, located above a base, comprises alternating stacked molded layers and letter lines; Vertical channel structure, vertically penetrating the stacked word lines in the unit area; as well as A first through-hole structure extends vertically through the word line stack in the extended region. The first through-hole structure includes a first through-hole plug and a first through-hole liner surrounding the sidewall of the first through-hole plug. The first through-hole liner includes a first recess located at the same level as the word lines of the word line stack. The first through-hole liner includes a protruding portion extending from the first through-hole plug toward the letter line, and The letter lines, the first recess, and the protruding part are located at the same level and are horizontally aligned with each other.

2. The three-dimensional semiconductor device according to claim 1, wherein, Word line stacking components include lower word line stacking components and upper word line stacking components. The molding layer includes a lower molding layer and an upper molding layer. The character lines include the lower character line and the upper character line. The lower letter bar stack consists of alternating stacked lower molding layers and lower letter bars. The upper lettering stack consists of alternating stacked upper molded layers and upper lettering. The lower and upper letter stacks extend horizontally within the unit area. The lower and upper letter stacks include a stepped structure in the extended area, the stepped structure having a flat area in the shape of a stepped platform, and The first extended through-hole structure is located in a flat region.

3. The three-dimensional semiconductor device according to claim 1, further comprising: The lower interlayer insulating layer is located between the substrate and the word line stack; as well as The common source electrode layer is located in the lower interlayer insulating layer. In this section, the vertical channel structure is vertically aligned with and electrically connected to the common source electrode layer.

4. The three-dimensional semiconductor device according to claim 3, further comprising: A common source via is located in the extended region and is electrically connected to a portion of the common source layer.

5. The three-dimensional semiconductor device according to claim 3, further comprising: The word line cutting structure is located between the vertical channel structures. The word line cutting structure penetrates the word line stack to electrically connect with the common source layer.

6. The three-dimensional semiconductor device according to claim 3, further comprising: A logic device layer is located between the substrate and the insulating layer below. The logic device layer includes transistors and via pads. The via pads are vertically aligned with and electrically connected to a first extended through-via structure.

7. The three-dimensional semiconductor device according to claim 1, further comprising: The unit cell is a through-hole structure, located between vertical channel structures within the unit cell region. Among them, the unit through-hole structure vertically penetrates the stacked letter lines. Each of the unit through-hole structures includes a unit through-hole plug and a unit through-hole liner layer surrounding the sidewall of the unit through-hole plug, and The unit via pad layer includes a second recess located at the same level as the word lines of the word line stack.

8. The three-dimensional semiconductor device according to claim 7, in, The cell via liner includes a protrusion that extends from the cell via plug toward the letter line.

9. The three-dimensional semiconductor device according to claim 1 or 8, in, The protruding portions of the first through-hole liner layer of the adjacent first extension through-hole structure or the protruding portions of the unit through-hole liner layer of the adjacent unit through-hole structure are connected to each other.

10. The three-dimensional semiconductor device according to claim 1, further comprising: The second extension penetrates the through-hole structure, and does not vertically penetrate the letter line stacking components in the extension area. The second extended through-hole structure includes a second through-hole plug and a second through-hole liner layer surrounding the sidewall of the second through-hole plug. The inner wall of the second through-hole liner is vertical and flat.

11. The three-dimensional semiconductor device according to claim 1, wherein, Each of the first recesses has a ring-shaped or disc-shaped form in the plan view.

12. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: A word line stack is located above a base having a cell region and an extension region. The word line stack includes alternating stacked molded layers and word lines. The word line stack extends horizontally in the cell region and has a stepped structure in the extension region. as well as The structure includes a vertical channel structure, a letter line cutting structure, and a first through-hole structure, which vertically penetrates the letter line stack. The first through-hole structure includes a first through-hole plug and a first through-hole liner layer surrounding the sidewall of the first through-hole plug, and a first recess is located on the inner sidewall of the first through-hole liner layer. The first through-hole pad layer also includes a protruding portion that protrudes towards the letter line, and The protruding part and the corresponding first recess are located at the same level and are horizontally aligned with each other.

13. The three-dimensional semiconductor device according to claim 12, wherein, The first indentation is horizontally aligned with the corresponding letter line.

14. The three-dimensional semiconductor device according to claim 12, further comprising: Common source electrode layer and via pad, located between the substrate and the word line stack, Among them, the vertical channel structure and the word line cutting structure are vertically aligned with and electrically connected to the common source layer, and The first through-hole structure is vertically aligned with the through-hole pad and electrically connected.

15. The three-dimensional semiconductor device according to claim 12, further comprising: The unit is a through-hole structure located between vertical channel structures. Among them, the vertical channel structure, the letter line cutting structure, and the unit through-hole structure are located in the unit region, and The first through-hole structure is located in the extended region.

16. The three-dimensional semiconductor device according to claim 15, further comprising: A stepped insulation layer that covers the stepped structure of the word line stack in the extended area; as well as The second through-hole structure and common source via do not vertically penetrate the word line stack but rather vertically penetrate the stepped insulation layer in the extended region. The second through-hole structure includes a second through-hole plug and a second through-hole liner layer surrounding the sidewall of the second through-hole plug. The inner wall of the second through-hole liner is vertical and flat.

17. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: The base has a unit region, a virtual region, and an extended region; A logic device layer, located on the substrate, includes transistors and via pads; The lower interlayer insulating layer is located on the logic device layer; The common source electrode layer is located in the lower interlayer insulating layer; The lower letter stack and the lower step insulation layer are located on the lower interlayer insulation layer; The upper letter line stacking component is located on top of the lower letter line stacking component; The upper stepped insulation layer is located on top of the lower stepped insulation layer; Vertical channel structure and word line cutting structure, vertically penetrating the lower word line stack and the upper word line stack to connect with the common source layer in the cell region; A virtual vertical channel structure is created, which vertically penetrates the lower and upper word line stacks to connect with the common source layer in the virtual region. as well as A first through-hole structure vertically penetrates a portion of the lower letter stack to electrically connect a through-hole pad in an extended region. The first through-hole structure includes a first through-hole plug and a first through-hole pad layer surrounding the sidewalls of the first through-hole plug. The inner sidewall of the first through-hole pad layer includes a seam at the same level as the letter lines of the upper and lower letter stacks, and the seam has an annular or disc-shaped shape in a plan view. The first through-hole pad layer also includes a protruding portion that protrudes towards the letter line, and The letter lines, protruding parts, and corresponding seams are located at the same level and are horizontally aligned with each other.

18. A method for forming a three-dimensional semiconductor device, the method comprising: A logic device layer with via pads is formed on a substrate having cell regions and extension regions; An interlayer insulating layer with a common source layer is formed on the logic device layer; A molded stack with alternating stacked molded layers and sacrificial layers is formed on the lower interlayer insulating layer; An interlayer insulating layer is formed on the molded stacked parts; A vertical channel structure is formed that penetrates the upper interlayer insulation layer and the molded stack to be electrically connected to the common source electrode layer; Forming a through-hole that vertically penetrates the upper interlayer insulation layer, the molded stack, and the lower interlayer insulation layer to expose the upper surface of the via pad; The first recess is formed by partially removing the sacrificial layer of the molded stack through a through-hole; A via liner layer and a via plug are formed to fill the interior of the first recess to form a through-via structure electrically connected to the via liner, wherein the via liner layer includes a protrusion filling the first recess and a recess located at the same level as the corresponding protrusion and horizontally aligned with each other. Vertical word-line cut trenches are formed between the vertical channel structures, penetrating the upper interlayer insulation layer and the molded stack to expose the upper surface of the common source layer; The sacrificial layer of the molded stack is removed by cutting grooves with letter lines to form a second recess; Forming letter lines in the second recess to form letter line stacks; and A groove liner and a groove plug are formed in the word line cutting groove to form a word line cutting structure that is electrically connected to the common source electrode layer.

19. The method according to claim 18, wherein, Each of the through-hole liner layers includes an inner wall corresponding to the first recess and an outer wall corresponding to the protrusion.

20. The method according to claim 18, in, Molded stacked components and letter line stacked components include a stepped structure with flat areas in the extended regions, and The through-hole and through-perforation structures are formed in the flat area.

21. The method according to claim 18, wherein, A portion of the through-hole and through-via structures is formed between the vertical channel structures in the unit region.

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