Display Devices

Abstract

The present disclosure relates to a display device, the display device comprising a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being located on a planarization layer comprising a first via hole and a second via hole. The first sub-pixel comprises a first pixel defining layer, the first pixel defining layer comprising a first opening exposing a portion of a first pixel electrode corresponding to a first emission portion. The first pixel electrode is connected to a first pixel circuit through a first via hole. The second sub-pixel comprises a second pixel defining layer, the second pixel defining layer comprising a second opening exposing a portion of a second pixel electrode corresponding to a second emission portion. The second pixel electrode is connected to a second pixel circuit through a second via hole. The second distance defined as the shortest distance from the inner surface of the second opening to the second via hole is greater than the first distance defined as the shortest distance from the inner surface of the first opening to the first via hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0136907, filed on October 30, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] One or more embodiments relate generally to display devices, and more particularly, to display devices having improved reliability. Background Art

[0004] Among display devices, organic light-emitting display devices have attracted attention as next-generation display devices because they have various advantages such as wide viewing angle, excellent contrast, and fast response time. Typically, in an organic light-emitting display device, a thin film transistor and an organic light-emitting diode are formed on a substrate, and the organic light-emitting diode itself emits light. Such an organic light-emitting display device can be used as a display unit for relatively small products such as mobile phones, or can be used as a display unit for relatively large products such as televisions. In order to improve light extraction efficiency and ensure increased outdoor visibility, the organic light-emitting display device can use a polarizer as a film that can selectively transmit or block vertically or horizontally polarized waves of incident light, or can also use a color filter and a light blocking layer with a polarization function to improve the flexibility of the organic light-emitting display device.

[0005] The above information disclosed in this section is only for understanding the background of the present inventive concept and therefore, the above information may contain information that does not constitute the prior art. Summary of the invention

[0006] In the case of a structure using a color filter having a polarization function and a light blocking layer in a conventional display device, a problem of occurrence of a green reflection color band may occur. Therefore, some aspects attempt to provide a display device capable of improving reliability by preventing occurrence of a green reflection color band.

[0007] Additional aspects will be set forth in the detailed description which follows, and in part will be obvious from the disclosure, or may be learned by practice of the inventive concept.

[0008] According to some aspects, a display device includes a first planarization layer, a first subpixel, and a second subpixel. The first planarization layer includes a first via and a second via. The first subpixel includes a first pixel electrode and a first pixel defining layer. The first pixel electrode is arranged on the first planarization layer and is electrically connected to a first pixel circuit through the first via. The first subpixel also includes a first emission portion and a first non-emission portion surrounding the first emission portion. The first pixel defining layer is arranged on the first pixel electrode and includes a first opening exposing a portion of the first pixel electrode corresponding to the first emission portion. The second subpixel includes a second pixel electrode and a second pixel defining layer. The second pixel electrode is arranged on the first planarization layer and is electrically connected to a second pixel circuit through the second via. The second subpixel also includes a second emission portion and a second non-emission portion surrounding the second emission portion. The second pixel defining layer is arranged on the second pixel electrode and includes a second opening exposing a portion of the second pixel electrode corresponding to the second emission portion. The second distance defined as the shortest distance from the inner surface of the second opening to the second via is greater than the first distance defined as the shortest distance from the inner surface of the first opening to the first via.

[0009] According to some aspects, the first planarization layer also includes a third via hole; and the display device also includes a third sub-pixel, the third sub-pixel including a third pixel electrode and a third pixel defining layer, the third sub-pixel is arranged on the first planarization layer and is electrically connected to a third pixel circuit through the third via hole, the third sub-pixel includes a third emission portion and a third non-emission portion surrounding the third emission portion, the third pixel defining layer is arranged on the third pixel electrode and includes a third opening exposing a portion of the third pixel electrode corresponding to the third emission portion.

[0010] According to some aspects, a third distance defined as the shortest distance from an inner surface of the third opening to the third via hole is smaller than the second distance.

[0011] According to some aspects, the first via, the second via, and the third via are arranged in a zigzag pattern on a plane.

[0012] According to some aspects, the first subpixel also includes: a first intermediate layer, arranged on the portion of the first pixel electrode exposed by the first opening; and a first relative electrode, arranged on the first intermediate layer; the second subpixel also includes: a second intermediate layer, arranged on the portion of the second pixel electrode exposed by the second opening; and a second relative electrode, arranged on the second intermediate layer; and the third subpixel also includes: a third intermediate layer, arranged on the portion of the third pixel electrode exposed by the third opening; and a third relative electrode, arranged on the third intermediate layer.

[0013] According to some aspects, the display device further includes: a thin film encapsulation layer disposed on the first relative electrode, the second relative electrode, and the third relative electrode, the thin film encapsulation layer including at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0014] According to some aspects, the display device also includes: a touch unit, which is directly arranged on the thin film encapsulation layer, wherein the touch unit includes: a first conductive layer; a second conductive layer, which is arranged above the first conductive layer; a first insulating layer, which is arranged between the first conductive layer and the second conductive layer; and a second insulating layer, which is arranged on the second conductive layer.

[0015] According to some aspects, the display device further includes: a color filter layer arranged on the first sub-pixel, the second sub-pixel, and the third sub-pixel, wherein the color filter layer includes a first color filter, a second color filter, and a third color filter.

[0016] According to some aspects, the color filter layer is disposed on the touch unit.

[0017] According to some aspects, the first color filter is disposed over the first emitting portion; the second color filter is disposed over the second emitting portion; and the third color filter is disposed over the third emitting portion.

[0018] According to some aspects, each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer includes a light blocking material.

[0019] According to some aspects, the display device also includes: an interlayer insulating layer; a first contact electrode arranged on the interlayer insulating layer; a second planarization layer arranged on the first contact electrode and including a fourth via, a fifth via and a sixth via; and a second contact electrode arranged between the first planarization layer and the second planarization layer.

[0020] According to some aspects, the first pixel electrode is electrically connected to the first pixel circuit through the first via and the fourth via; the second pixel electrode is electrically connected to the second pixel circuit through the second via and the fifth via; and the third pixel electrode is electrically connected to the third pixel circuit through the third via and the sixth via.

[0021] According to some aspects, in a plan view: the first via and the fourth via are positioned on the same imaginary line; and the second via and the fifth via are spaced apart from each other.

[0022] According to some aspects, the first emitting portion has a first area; and the second emitting portion has a second area smaller than the first area.

[0023] According to some aspects, the first subpixel is a blue subpixel; the second subpixel is a green subpixel; and the third subpixel is a red subpixel.

[0024] According to some aspects, a display device includes a substrate, a first planarization layer, a first pixel electrode, a second pixel electrode, a third pixel electrode, a pixel defining layer, a first intermediate layer, a second intermediate layer, a third intermediate layer, and an opposing electrode. The substrate includes a first region corresponding to a first emission portion, a second region corresponding to a second emission portion, and a third region corresponding to a third emission portion. The first planarization layer is arranged above the substrate. The first planarization layer includes a first via hole, a second via hole, and a third via hole. The first pixel electrode is arranged on the first planarization layer and is electrically connected to a first pixel circuit through the first via hole. The second pixel electrode is arranged on the first planarization layer and is electrically connected to a second pixel circuit through the second via hole. The third pixel electrode is arranged on the first planarization layer and is electrically connected to a third pixel circuit through the third via hole. The pixel defining layer is arranged on the first pixel electrode, the second pixel electrode, and the third pixel electrode. The pixel defining layer includes a first opening exposing a central portion of the first pixel electrode, a second opening exposing a central portion of the second pixel electrode, and a third opening exposing a central portion of the third pixel electrode. The first intermediate layer is arranged on the first pixel electrode. The second intermediate layer is arranged on the second pixel electrode. The third intermediate layer is arranged on the third pixel electrode. The opposite electrode is arranged on the first intermediate layer, the second intermediate layer and the third intermediate layer. The second distance defined as the shortest distance from the inner surface of the second opening to the second via hole is greater than the first distance defined as the shortest distance from the inner surface of the first opening to the first via hole.

[0025] According to some aspects, a third distance defined as the shortest distance from an inner surface of the third opening to the third via hole is smaller than the second distance.

[0026] According to some aspects, the first via, the second via, and the third via are arranged in a zigzag pattern on a plane.

[0027] According to some aspects, the display device further includes: a color filter layer disposed above the opposing electrode.

[0028] Both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0030] Figure 1 is a perspective view schematically showing a display device according to some exemplary embodiments;

[0031] Figure 2 is a plan view schematically showing a portion of a display device according to some exemplary embodiments;

[0032] Figure 3 is a diagram showing an arrangement structure of pixels that may be included in a display device according to some exemplary embodiments;

[0033] Figure 4 and Figure 5 is an equivalent circuit diagram of a sub-pixel that may be included in a display device according to various exemplary embodiments;

[0034] Figure 6 is a plan view showing an arrangement of sub-pixels according to some exemplary embodiments;

[0035] Figure 7 According to some exemplary embodiments, Figure 6 sectional views taken along section lines II-I', II-II' and III-III';

[0036] Figure 8 is a cross-sectional view schematically illustrating a portion of a display device according to some exemplary embodiments;

[0037] Fig. 9 is a cross-sectional view schematically illustrating a portion of a display device according to some exemplary embodiments; and

[0038] Fig.10 is a plan view schematically illustrating locations of via holes according to some exemplary embodiments. DETAILED DESCRIPTION

[0039] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of various exemplary embodiments. As used herein, the terms "embodiment" and "implementation method" can be used interchangeably and are non-limiting examples of one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0040] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of variable details of some exemplary embodiments. Therefore, unless otherwise specified, the various illustrated features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter, individually or collectively referred to as "elements" or "multiple elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0041] It is generally provided that the boundaries between adjacent elements are clarified using cross hatching and / or shading in the drawings. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals refer to the same elements.

[0042] When an element such as a layer is referred to as "on" another element, "connected to" or "coupled to" another element, the element may be directly on the other element, directly connected to or directly coupled to the other element, or there may be an intermediate element. However, when an element is referred to as "directly on" another element, "directly connected to" or "directly coupled to" another element, there is no intermediate element. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent", "on..." versus "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection and / or fluid connection. In addition, the x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0044] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "under" can cover both above and below orientations. In addition, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0045] The terms used herein are for the purpose of describing specific embodiments, rather than being intended to limit. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "a kind of" and "the (the)" are also intended to include plural forms. In addition, when the terms "include", "comprise", "contain" and / or "have" are used in this specification, it is indicated that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, therefore, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0046] Various exemplary embodiments are described herein with reference to cross-sectional views, isometric views, perspective views, plan views, and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of the regions, but rather will include deviations in shape due to, for example, manufacturing. To this end, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and, therefore, are not intended to be limiting.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as such in the text, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formalized sense.

[0048] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings according to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements and wiring connections, which can be formed using semiconductor-based preparation techniques or other manufacturing techniques. In the case where a block, unit and / or module is implemented by a microprocessor or other similar hardware, software (e.g., microcode) can be used to program and control the block, unit and / or module to perform the various functions discussed herein, and the block, unit and / or module can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs other functions. In addition, without departing from the concept of the present invention, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the inventive concept.

[0049] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view schematically illustrating a display device according to some exemplary embodiments.

[0051] Reference Figure 1 The display device 1 may include a display area DA that implements (or presents) an image and a non-display area NDA that does not implement the image. The display device 1 may provide an image by using light emitted from a plurality of pixels P arranged in the display area DA, and the non-display area NDA may be an area where the image is not displayed.

[0052] Hereinafter, although an organic light-emitting display device is described as an example of a display device 1 according to an embodiment, the display device is not limited thereto. In an embodiment, the display device 1 may be an inorganic light-emitting display device (or an inorganic electroluminescent display device), or may be a display device such as a quantum dot light-emitting display device, a micro-light-emitting display device, a nano-light-emitting display device, an electrophoretic display device, and an electrowetting display device. For example, the emission layer of the display element included in the display device 1 may include an organic material, may include an inorganic material, may include quantum dots, may include an organic material and quantum dots, or may include an inorganic material and quantum dots. However, the embodiments are not limited to the aforementioned examples.

[0053] although Figure 1 The display device 1 having a flat display surface is shown, but the embodiment is not limited thereto. In an embodiment, the display device 1 may include a three-dimensional display surface or a curved display surface.

[0054] When the display device 1 includes a three-dimensional display surface, the display device 1 may include a plurality of display areas indicating different directions, and may include, for example, a polygonal columnar display surface. In an embodiment, when the display device 1 includes a curved display surface, the display device 1 may be implemented in various forms such as a flexible display device, a foldable display device, a rollable display device, and a twistable display device.

[0055] In addition, as an exemplary embodiment, Figure 1 A display device 1 that can be applied to a mobile phone terminal is shown. Although not shown, a mobile phone terminal can be constructed by arranging an electronic module, a camera module, and / or a power module, etc. mounted on a main board (or connected to the main board) together with the display device 1 in a bracket / housing, etc. The display device 1 according to some exemplary embodiments can be applied to relatively large electronic devices such as billboards, televisions, monitors, etc., and relatively small and relatively medium-sized electronic devices such as tablet computers, notebook computers, car navigation devices, game consoles, smart watches, etc.

[0056] Figure 1 The case where the display area DA of the display device 1 is rectangular is shown; however, in some exemplary embodiments, the shape of the display area DA may also be circular, elliptical, polygonal such as triangle, pentagon, etc., or irregular.

[0057] Figure 2 is a plan view schematically illustrating a portion of a display device according to some exemplary embodiments.

[0058] Reference Figure 2 , the display panel DP of the display device 1 may include a plurality of pixels P arranged in a display area DA. The plurality of pixels P may each include an organic light emitting diode OLED (eg, see Figure 4 and Figure 5 ) display element. Each pixel P can emit, for example, red light, green light, blue light, or white light through an organic light emitting diode OLED. As described above, the pixel P can be understood as a pixel that emits light of any one of red, green, blue, and white colors, but the exemplary embodiment is not limited thereto. The display area DA can be covered with a thin film encapsulation layer TFE (for example, see Figure 7 ) to protect the display area DA from external air and / or moisture.

[0059] Each pixel P may be electrically connected to one or more peripheral circuits arranged in the non-display area NDA. The first scan driving circuit 110, the second scan driving circuit 120, the pad portion 140, the data driving circuit 150, the first power line 160 and the second power line 170 may be arranged in the non-display area NDA.

[0060] The first scan driving circuit 110 may provide a scan signal to each pixel P through a scan line SL. The first scan driving circuit 110 may provide an emission control signal to each pixel P through an emission control line EL. The second scan driving circuit 120 may be arranged in parallel with the first scan driving circuit 110, with the display area DA interposed between the second scan driving circuit 120 and the first scan driving circuit 110, but exemplary embodiments are not limited thereto. Some pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and other pixels P may be connected to the second scan driving circuit 120. In an embodiment, the second scan driving circuit 120 may be omitted.

[0061] The pad portion 140 may be arranged at one side of the substrate 100. The pad portion 140 may be exposed by not being covered by the insulating layer and may be electrically connected to the printed circuit board PCB. The pad portion PCB-P of the printed circuit board PCB may be electrically connected to the pad portion 140 of the display device 1. The printed circuit board PCB may be configured to transmit power or signals of the controller to the display device 1.

[0062] The control signal generated by the controller may be transmitted to each of the first scan driving circuit 110 and the second scan driving circuit 120 through the printed circuit board PCB. The controller may provide the first power supply voltage ELVDD (eg, see Figure 4 ) and a second power supply voltage ELVSS (eg, see Figure 4 The first power supply voltage ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power supply line 160 , and the second power supply voltage ELVSS may be supplied to an electrode (eg, an opposing electrode) of each pixel P connected to the second power supply line 170 .

[0063] The data driving circuit 150 may be electrically connected to the data line DL. A data signal of the data driving circuit 150 may be provided to each pixel P through a connection line 151 connected to the pad portion 140 and a data line DL connected to the connection line 151. Figure 2The data driving circuit 150 is shown to be disposed on the printed circuit board PCB; however, in some exemplary embodiments, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the pad portion 140 and the first power line 160.

[0064] The first power line 160 may include first and second sub-lines 162 and 163 extending in parallel in the x direction with the display area DA interposed therebetween, but exemplary embodiments are not limited thereto. The second power line 170 may partially surround the display area DA in a ring shape with one side open.

[0065] Figure 3 is a diagram illustrating an arrangement structure of pixels that may be included in a display device according to some exemplary embodiments.

[0066] Reference Figure 3 , the pixel P of the display device 1 according to the embodiment may include a sub-pixel Pr emitting red light, a sub-pixel Pg emitting green light, and a sub-pixel Pb emitting blue light, and in some exemplary embodiments, the pixel P may include two sub-pixels Pg emitting green light. Figure 3 An exemplary Pentile type arrangement including sub-pixels Pr, Pg, and Pb is shown, but the sub-pixels Pr, Pg, and Pb may also be formed in a stripe shape or one or more of various other shapes. Figure 3 It is shown that four sub-pixels Pr, Pg, and Pb are included in the pixel P, but the number of the sub-pixels Pr, Pg, and Pb may be modified and designed according to the resolution of the display area DA.

[0067] Figure 4 and Figure 5 is an equivalent circuit diagram of a sub-pixel that may be included in a display device according to various exemplary embodiments.

[0068] The pixel circuit PC may include a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts may be connected to the scan line SL and the data line DL, and may be configured to transmit a data signal Dm input through the data line DL to the driving thin film transistor Td according to a scan signal Sn input through the scan line SL.

[0069] The storage capacitor Cst may be connected to the switching thin film transistor Ts and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage received from the switching thin film transistor Ts and a first power source voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0070] The driving thin film transistor Td may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a specific brightness according to the driving current.

[0071] although Figure 4 The pixel circuit PC is shown to include two thin film transistors and one storage capacitor, but the embodiment is not limited thereto. Figure 5 As shown in FIG. 1 , the pixel circuit PC_1 may include seven thin film transistors and one storage capacitor. Figure 5 It is shown that one storage capacitor is included, but the pixel circuit PC_1 may include two or more storage capacitors.

[0072] Reference Figure 5 , the sub-pixels Pb, Pg and / or Pr may include a pixel circuit PC_1 and an organic light emitting diode OLED connected to the pixel circuit PC_1. The pixel circuit PC_1 may include a plurality of thin film transistors and a storage capacitor. The thin film transistors and the storage capacitor may be connected to the signal lines SL, SL-1, EL and DL, the initialization voltage line VL and the driving voltage line PL.

[0073] although Figure 5 It is shown that each sub-pixel Pb, Pg and Pr is connected to the signal lines SL, SL-1, EL and DL, the initialization voltage line VL and the driving voltage line PL, but the embodiment is not limited thereto. In some exemplary embodiments, at least one of the signal lines SL, SL-1, EL and DL, the initialization voltage line VL and / or the driving voltage line PL, etc. can be shared by adjacent pixels / sub-pixels.

[0074] The signal lines SL, SL-1, EL, and DL may include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 configured to transmit a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL configured to transmit an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL (but disconnected from the scan line SL) and configured to transmit a data signal Dm. The driving voltage line PL may be configured to transmit a driving voltage (e.g., a first power supply voltage ELVDD) to the driving thin film transistor T1, and the initialization voltage line VL may be configured to transmit an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0075] The driving gate electrode G1 of the driving thin film transistor T1 can be connected to the lower electrode Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 can be connected to the driving voltage line PL via the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 can be electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin film transistor T2, and can drive the driving current I OLED Supply to organic light emitting diode OLED.

[0076] The switching gate electrode G2 of the switching thin film transistor T2 may be connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 may be connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 may be connected to the driving source electrode S1 of the driving thin film transistor T1 and may be connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 may be turned on according to the scan signal Sn received through the scan line SL to perform a switching operation of transmitting the data signal Dm transmitted to the data line DL (or transmitted via the data line DL) to the driving source electrode S1 of the driving thin film transistor T1.

[0077] The compensation gate electrode G3 of the compensation thin film transistor T3 may be connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 may be connected to the driving drain electrode D1 of the driving thin film transistor T1 and may be connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 may be connected to the lower electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 may be turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 to the driving drain electrode D1 of the driving thin film transistor T1 so as to connect the driving thin film transistor T1 in a diode manner.

[0078] The first initialization gate electrode G4 of the first initialization thin film transistor T4 may be connected to the previous scan line SL-1, the first initialization source electrode S4 of the first initialization thin film transistor T4 may be connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 may be connected to the lower electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to perform an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0079] The operation control gate electrode G5 of the operation control thin film transistor T5 can be connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 can be connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 can be connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0080] The emission control gate electrode G6 of the emission control thin film transistor T6 can be connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 can be connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 can be electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0081] The operation control thin film transistor T5 and the emission control thin film transistor T6 may be turned on simultaneously according to the emission control signal En received through the emission control line EL, so that the driving voltage (eg, the first power supply voltage ELVDD) may be transmitted to the organic light emitting diode OLED, thereby driving the current I OLED It can flow through an organic light emitting diode OLED.

[0082] The second initialization gate electrode G7 of the second initialization thin film transistor T7 may be connected to the previous scan line SL-1, the second initialization source electrode S7 of the second initialization thin film transistor T7 may be connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 may be connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0083] although Figure 5 The case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1 is shown, but the embodiment is not limited thereto. In some exemplary embodiments, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 to be driven according to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., a subsequent scan line) to be driven according to a signal transmitted to the separate signal line.

[0084] The upper electrode Cst2 of the storage capacitor Cst may be connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED may be connected to a common voltage (eg, the second power supply voltage ELVSS). Therefore, the organic light emitting diode OLED may receive a driving current I from the driving thin film transistor T1. OLED To emit light so as to display images.

[0085] although Figure 5 It is shown that the compensation thin film transistor T3 and the first initialization thin film transistor T4 have a double gate electrode structure, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have another structure such as a single gate electrode structure.

[0086] Figure 6 is a plan view showing an arrangement of sub-pixels according to some exemplary embodiments. Figure 7 According to some exemplary embodiments, Figure 6 The cross-sectional view is taken along the section lines I-I', II-II' and III-III'. Figure 7 In FIG. 1 , the section line II′ corresponds to a section taken by cutting the first sub-pixel 10, the section line II-II′ corresponds to a section taken by cutting the second sub-pixel 11, and the section line III-III′ corresponds to a section taken by cutting the third sub-pixel 12. Figure 6 In the figure, for the convenience of description, the pixel circuit PC (or PC_1) is omitted.

[0087] Reference Figure 6 , a display device according to an exemplary embodiment may include a first sub-pixel 10, a second sub-pixel 11, and a third sub-pixel 12, and more specifically, the display device may include one first sub-pixel 10, one third sub-pixel 12, and two second sub-pixels 11. The first sub-pixel 10, the second sub-pixel 11, and the third sub-pixel 12 may be a blue sub-pixel Pb, a green sub-pixel Pg, and a red sub-pixel Pr, respectively.

[0088] Reference Figure 6 and Figure 7 , the display device according to the embodiment may include: a first planarization layer 113 including a first via hole VIA1 and a second via hole VIA2; a first sub-pixel 10 including a first pixel electrode 210a arranged on the first planarization layer 113 to be electrically connected to the first pixel circuit PC1 through the first via hole VIA1, and the first sub-pixel 10 includes a first emission portion EA1 and a first non-emission portion NEA1 surrounding the first emission portion EA1, and a first pixel defining layer 180a, the first pixel defining layer 180a is arranged on the first pixel electrode 210a and includes exposing the first pixel electrode 2 10a, and a second sub-pixel 11 including a second pixel electrode 210b arranged on the first planarization layer 113 to be electrically connected to the second pixel circuit PC2 through a second via hole VIA2, and the second sub-pixel 11 includes a second emission portion EA2 and a second non-emission portion NEA2 surrounding the second emission portion EA2, and a second pixel defining layer 180b, the second pixel defining layer 180b being arranged on the second pixel electrode 210b and including a second opening OP2 exposing the second emission portion EA2 of the second pixel electrode 210b. The second distance d2 (defined as the shortest distance from the inner surface of the second opening OP2 to the second via hole VIA2) may be greater than the first distance d1 (defined as the shortest distance from the inner surface of the first opening OP1 to the first via hole VIA1).

[0089] In an embodiment, the first planarization layer 113 may further include a third via hole VIA3, and the display device may further include a third sub-pixel 12, the third sub-pixel 12 includes a third pixel electrode 210c arranged on the first planarization layer 113 to be electrically connected to the third pixel circuit PC3 through the third via hole VIA3, and the third sub-pixel 12 includes a third emission portion EA3 and a third non-emission portion NEA3 surrounding the third emission portion EA3, and a third pixel defining layer 180c, the third pixel defining layer 180c is arranged on the third pixel electrode 210c and includes a third opening OP3 exposing the third emission portion EA3 of the third pixel electrode 210c. The third distance d3 (defined as the shortest distance from the inner surface of the third opening OP3 to the third via hole VIA3) may be less than the second distance d2.

[0090] The first emission portion EA1 may have a first area a1, and the second emission portion EA2 may have a second area a2 smaller than the first area a1. In addition, the third emission portion EA3 may have a third area a3 larger than the second area a2.

[0091] The first via hole VIA1 of the first sub-pixel 10 and the second via hole VIA2 of the second sub-pixel 11 , and the second via hole VIA2 of the second sub-pixel 11 and the third via hole VIA3 of the third sub-pixel 12 may be arranged at different positions in the same row.

[0092] In the following, reference will be made to Figure 7 The stacking order of the layers of the display device according to the embodiment is described in more detail.

[0093] The substrate 100 may include at least one of glass and a polymer resin; however, the embodiment is not limited thereto. The polymer resin may include at least one of polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, bendable, and / or twistable. The substrate 100 may have a multilayer structure including an inorganic layer (not shown) and a layer including one or more of the above-mentioned polymer resins.

[0094] The buffer layer 101 may be positioned on the substrate 100 to reduce or block foreign matter, moisture and / or external air from penetrating from the bottom of the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 101 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite, and may include a single layer or multilayer structure of an inorganic material and an organic material. A barrier layer (not shown) for blocking penetration of external air may also be included between the substrate 100 and the buffer layer 101.

[0095] The first thin film transistor TFT1, the second thin film transistor TFT2 and the third thin film transistor TFT3 and the organic light emitting diodes OLED1, OLED2 and OLED3 can be positioned above the substrate 100, and the organic light emitting diodes OLED1, OLED2 and OLED3 are light emitting devices electrically connected to the first thin film transistor TFT1, the second thin film transistor TFT2 and the third thin film transistor TFT3 respectively.

[0096] Figure 7 The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may correspond to the thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 included in the reference Figure 4 and Figure 5 Any one of the thin film transistors in the described pixel circuit PC or PC_1 (eg, the driving thin film transistor T1 ).

[0097] The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may include a semiconductor layer and a gate electrode 136. The semiconductor layer may include, for example, polysilicon. The semiconductor layer may include a channel region 131 overlapping the gate electrode 136, and a source region 132 and a drain region 133 arranged on both sides of the channel region 131 and including impurities with a higher concentration than the channel region 131. The impurities may include N-type impurities or P-type impurities. The source region 132 and the drain region 133 may be electrically connected to a source electrode and a drain electrode of a thin film transistor, such as the source electrode and the drain electrode of the first thin film transistor TFT1.

[0098] The semiconductor layer may include an oxide semiconductor and / or a silicon semiconductor. When the semiconductor layer includes an oxide semiconductor, the semiconductor layer may include, for example, an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the semiconductor layer may include InSnZnO (ITZO) or InGaZnO (IGZO). When the semiconductor layer includes a silicon semiconductor, the semiconductor layer may include, for example, amorphous silicon (a-Si) or low temperature polycrystalline silicon (LTPS) crystallized from amorphous silicon (a-Si).

[0099] The gate electrode 136 may include a single layer or a multilayer formed of at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 136 may be connected to a gate line for applying an electrical signal to the gate electrode 136.

[0100] The gate insulating layer 103 may be disposed between the semiconductor layer and the gate electrode 136. The gate insulating layer 103 may include, for example, silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) The gate insulating layer 103 may include a single layer or a multi-layer structure, and the single layer or the multi-layer structure includes one or more of the above-mentioned inorganic insulating materials.

[0101] The interlayer insulating layer 107 may be disposed on the gate electrode 136. The interlayer insulating layer 107 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) and may include a single-layer or multi-layer structure.

[0102] The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may include a source electrode 137 connected to the source region 132 of the semiconductor layer, a drain electrode 138 connected to the drain region 133, and first contact electrodes 108a, 108b, and 108c. The source electrode 137 and the drain electrode 138 may be electrically connected to the source region 132 and the drain region 133 of the semiconductor layer through contact holes passing through the gate insulating layer 103 and the interlayer insulating layer 107.

[0103] The first, second, and third thin film transistors TFT1, TFT2, and TFT3 and the organic light emitting diodes OLED1, OLED2, and OLED3 may be electrically connected to one another through the first contact electrodes 108a, 108b, and 108c.

[0104] The source electrode 137, the drain electrode 138, and the first contact electrodes 108a, 108b, and 108c may include aluminum (Al), copper (Cu), and / or titanium (Ti), etc., and may include a multilayer or single-layer structure. For example, the source electrode 137 and the drain electrode 138 may include a multilayer structure such as Ti / Al / Ti or TiN / Al / Ti.

[0105] In an embodiment, in order to increase the distance between the end of the second pixel defining layer 180b and the second via hole VIA2, the first contact electrode 108b arranged in the second sub-pixel 11 can be arranged closer to the second non-emitting portion NEA2 than the first contact electrode 108a arranged in the first sub-pixel 10 and the first contact electrode 108c arranged in the third sub-pixel 12.

[0106] In some embodiments, the data line DL (eg, see Figure 4 ) and the driving voltage line PL (see, for example, Figure 4 ) may be formed of the same material as the source electrode 137, the drain electrode 138, and the first contact electrodes 108a, 108b, and 108c, and may be formed on the same layer as the source electrode 137, the drain electrode 138, and the first contact electrodes 108a, 108b, and 108c.

[0107] The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may be covered with a protective layer, which may prevent wiring including metal such as aluminum that may be damaged by an etchant from being exposed to an etching environment during the display device manufacturing process.

[0108] The first planarization layer 113 may be disposed on the interlayer insulating layer 107. The first planarization layer 113 may planarize upper surfaces of the first, second, and third pixel circuits PC1, PC2, and PC3 to planarize surfaces in which (or on which) the organic light emitting diodes OLED1, OLED2, and OLED3 are to be positioned.

[0109] The first planarization layer 113 may include at least one of a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), poly(methyl methacrylate) (PMMA), and polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, and a vinyl alcohol polymer, and any blends thereof. The first planarization layer 113 may include an inorganic material. The first planarization layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ). When the first planarization layer 113 includes an inorganic material, chemical planarization polishing may be performed in some cases. In some embodiments, the first planarization layer 113 may include both an organic material and an inorganic material.

[0110] The organic light emitting diodes OLED1, OLED2 and OLED3 can be positioned on the first planarization layer 113 of the substrate 100, the organic light emitting diode OLED1 includes a first intermediate layer 220a arranged on the first pixel electrode 210a and a first relative electrode 230a arranged on the first intermediate layer 220a, the organic light emitting diode OLED2 includes a second intermediate layer 220b arranged on the second pixel electrode 210b and a second relative electrode 230b arranged on the second intermediate layer 220b, and the organic light emitting diode OLED3 includes a third intermediate layer 220c arranged on the third pixel electrode 210c and a third relative electrode 230c arranged on the third intermediate layer 220c.

[0111] The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be arranged on the first planarization layer 113. The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be a transparent (or semi-transparent) electrode or a reflective electrode. In some embodiments, the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may include a reflective layer formed of at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr or any compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In some embodiments, the first pixel electrode 210a, the second pixel electrode 210b and the third pixel electrode 210c may be provided as a stack structure of ITO / Ag / ITO.

[0112] The first pixel defining layer 180a, the second pixel defining layer 180b, and the third pixel defining layer 180c may be disposed over the first planarization layer 113. The first pixel defining layer 180a, the second pixel defining layer 180b, and the third pixel defining layer 180c may define the first emission portion EA1, the second emission portion EA2, and the third emission portion EA3, respectively, by including a first opening OP1 exposing a central (or center) portion of the first pixel electrode 210a, a second opening OP2 exposing a central portion of the second pixel electrode 210b, and a third opening OP3 exposing a central portion of the third pixel electrode 210c. In addition, the first pixel defining layer 180a, the second pixel defining layer 180b, and the third pixel defining layer 180c can prevent arcing, etc., from occurring at the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c by increasing the distance between the edges of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c and the first opposing electrode 230a, the second opposing electrode 230b, and the third opposing electrode 230c located above the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c. For example, the first pixel defining layer 180a, the second pixel defining layer 180b, and the third pixel defining layer 180c can be formed of an organic insulating material such as at least one of polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin by spin coating, etc.

[0113] Figure 8 is a cross-sectional view schematically illustrating a portion of a display device according to some exemplary embodiments.

[0114] like Figure 8 As shown in FIG. 1 , the first pixel defining layer 180a_1, the second pixel defining layer 180b_1, and the third pixel defining layer 180c_1 may include (or define) a black matrix as a light blocking material. The black matrix may include various materials such as an organic material mixed with a black pigment, chromium (Cr), and chromium oxide (CrO x ). When the black matrix is ​​formed of chromium or chromium oxide, the black matrix may include a single layer or a multilayer structure of chromium and / or chromium oxide. When the first pixel defining layer 180a_1, the second pixel defining layer 180b_1, and the third pixel defining layer 180c_1 include the black matrix, external light reflection may be sufficiently prevented.

[0115] A spacer may be disposed on the first pixel defining layer 180a_1, the second pixel defining layer 180b_1, and the third pixel defining layer 180c_1. The spacer may prevent the organic light emitting diodes OLED1, OLED2, and OLED3 from being damaged due to the deflection of the mask during the manufacturing process using the mask. For example, the spacer may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin by spin coating, etc., and the spacer may include a single layer or a multilayer structure.

[0116] Return to reference Figure 7 , the first intermediate layer 220a can be arranged on the first pixel electrode 210a exposed by the first pixel defining layer 180a, the second intermediate layer 220b can be arranged on the second pixel electrode 210b exposed by the second pixel defining layer 180b, and the third intermediate layer 220c can be arranged on the third pixel electrode 210c exposed by the third pixel defining layer 180c.

[0117] The first intermediate layer 220a, the second intermediate layer 220b and the third intermediate layer 220c may include an emission layer and a functional layer, such as at least one of a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL), and the functional layer may optionally be further included below and above the emission layer.

[0118] The emission layer may include an organic material including a fluorescent material and / or a phosphorescent material that emits red, green, blue, or white light. The emission layer may include a low molecular weight organic material or a high molecular weight organic material.

[0119] When the emission layer includes a low molecular weight organic material, the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may include a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure, and the low molecular weight organic material may include various organic materials such as copper phthalocyanine (CuPc), N, N'-di (naphthalene-1-yl) -N, N'-diphenylbenzidine (N, N'-di (naphthalene-1-yl) -N, N'-diphenylbenzidine) (NPB) and tri-8-hydroxyquinoline aluminum (Alq3) At least one. These layers can be formed by vacuum deposition.

[0120] When the emission layer includes a high molecular weight organic material, the first intermediate layer 220a, the second intermediate layer 220b and the third intermediate layer 220c may generally have a structure including a hole transport layer (HTL) and an emission layer (EML). In this case, the hole transport layer may include poly (3,4-ethylenedioxythiophene) (PEDOT), and the emission layer may include a high molecular weight material, such as at least one of polyphenylene vinylene (PPV) and polyfluorene. The emission layer may be formed by screen printing, inkjet printing and / or laser induced thermal imaging (LITI), etc.

[0121] The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be provided in plurality, and the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be arranged corresponding to the plurality of first pixel electrodes 210a, the second pixel electrodes 210b, and the third pixel electrodes 210c, respectively. However, the embodiment is not limited thereto. According to some embodiments, the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may include, for example, an integral layer located above the plurality of first pixel electrodes 210a, the second pixel electrodes 210b, and the third pixel electrodes 210c. In an embodiment, the first intermediate layer 220a, the second intermediate layer 220b and the third intermediate layer 220c can be arranged corresponding to the multiple first pixel electrodes 210a, the second pixel electrodes 210b and the third pixel electrodes 210c, respectively, and one or more functional layers other than the first intermediate layer 220a, the second intermediate layer 220b and the third intermediate layer 220c can be integrally formed above the multiple first pixel electrodes 210a, the second pixel electrodes 210b and the third pixel electrodes 210c.

[0122] In a conventional display device, in order to improve light extraction efficiency and ensure outdoor visibility, a polarizer, which is a film that can selectively transmit or block vertically or horizontally polarized waves of incident light, is positioned on the touch unit TU; however, when the polarizer is arranged on the touch unit TU, it is difficult to realize a foldable display due to low flexibility. To solve this problem, a method of improving flexibility by arranging a color filter and a light blocking layer having a polarization function on the touch unit TU instead of the polarizer has been proposed; however, in the case of a structure in which the light blocking layer and the color filter are arranged on the touch unit TU, a pixel electrode (e.g., the second pixel electrode 210b) located on a green sub-pixel (e.g., the second sub-pixel 11) is tilted, and therefore, a reflective color band appears in the green sub-pixel region.

[0123] In order to solve the above-mentioned problem, according to some embodiments, compared with the blue sub-pixel (e.g., the first sub-pixel 10) and the red sub-pixel (e.g., the third sub-pixel 12), the flatness of the green sub-pixel (e.g., the second sub-pixel 11) can be improved by increasing the distance between the via hole (e.g., the second via hole VIA2) of the green sub-pixel (e.g., the second sub-pixel 11) and the end of the pixel defining layer (e.g., the second pixel defining layer 180b) to prevent the occurrence of a green reflective color band.

[0124] like Figure 7 As shown in , the first via hole VIA1 of the first sub-pixel 10 can be defined in the first planarization layer 113 at a first distance d1 from the end of the first pixel defining layer 180a, the second via hole VIA2 of the second sub-pixel 11 can be defined in the first planarization layer 113 at a second distance d2 greater than the first distance d1 from the end of the second pixel defining layer 180b, and the third via hole VIA3 of the third sub-pixel 12 can be defined in the first planarization layer 113 at a third distance d3 less than the second distance d2 from the end of the third pixel defining layer 180c.

[0125] The first opposing electrode 230a may be disposed on the first intermediate layer 220a, the second opposing electrode 230b may be disposed on the second intermediate layer 220b, and the third opposing electrode 230c may be disposed on the third intermediate layer 220c. The first opposing electrode 230a, the second opposing electrode 230b, and the third opposing electrode 230c may be disposed on the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c, respectively, to completely cover the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c.

[0126] The first, second, and third opposing electrodes 230a, 230b, and 230c may be arranged over the entire surface of the display area DA. In some embodiments, the first, second, and third opposing electrodes 230a, 230b, and 230c may be integrally formed to cover a plurality of pixels P.

[0127] The first relative electrode 230a, the second relative electrode 230b, and the third relative electrode 230c may be transparent electrodes or reflective electrodes. In some embodiments, the first relative electrode 230a, the second relative electrode 230b, and the third relative electrode 230c may be transparent or semi-transparent electrodes and may include a thin metal layer having a low work function and may include at least one of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, and Mg and any compound thereof. Metals such as ITO, IZO, ZnO, and In 2 O 3A transparent conductive oxide (TCO) layer of at least one of may be further disposed on the thin metal layer.

[0128] When the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c are reflective electrodes and the first opposing electrode 230a, the second opposing electrode 230b, and the third opposing electrode 230c are transparent electrodes, light emitted from the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be emitted toward the first opposing electrode 230a, the second opposing electrode 230b, and the third opposing electrode 230c, and thus, the display device 1 may be a top emission type display device. In an embodiment, when the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c are transparent or semi-transparent electrodes and the first opposing electrode 230a, the second opposing electrode 230b, and the third opposing electrode 230c are reflective electrodes, light emitted from the first intermediate layer 220a, the second intermediate layer 220b, and the third intermediate layer 220c may be emitted toward the substrate 100, and thus, the display device 1 may be a bottom emission type display device. However, the embodiment is not limited to the foregoing example, and the display device 1 may be a double-side emission type display device that emits light in two directions corresponding to the top side and the bottom side of the display device 1 .

[0129] The thin film encapsulation layer TFE may be arranged on each of the first relative electrode 230a, the second relative electrode 230b, and the third relative electrode 230c to protect the organic light emitting diodes OLED1, OLED2, and OLED3 from external moisture and oxygen. The thin film encapsulation layer TFE may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the thin film encapsulation layer TFE may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330 arranged above the first inorganic encapsulation layer 310, and an organic encapsulation layer 320 positioned between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0130] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials, such as at least one of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include a single layer or a multilayer structure including one or more of the above materials. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include the same material, or may include materials different from each other.

[0131] The organic encapsulation layer 320 may include at least one of a monomer-based material and a polymer-based material. The organic encapsulation layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, and acrylic resin (e.g., poly(methyl methacrylate), polyacrylic acid, etc.), or any combination thereof.

[0132] The touch unit TU may be directly disposed on the thin film encapsulation layer TFE. For example, the touch unit TU may be directly formed on the thin film encapsulation layer TFE without using an adhesive.

[0133] Each touch unit TU may include a first conductive layer 410, a second conductive layer 430 disposed above the first conductive layer 410, a first insulating layer 420 positioned between the first conductive layer 410 and the second conductive layer 430, and a second insulating layer 440 disposed on the second conductive layer 430. The first conductive layer 410 may include a first sensing electrode, and the second conductive layer 430 may include a second sensing electrode. In an embodiment, the first conductive layer 410 and the second conductive layer 430 may have a mesh shape to prevent (or at least reduce) recognition by a user, and may have a three-layer structure of, for example, titanium / aluminum / titanium.

[0134] The first conductive layer 410 and the second conductive layer 430 may have a single layer structure, or may have a stacked multilayer structure. The single layer conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include at least one of molybdenum, silver, titanium, copper and aluminum, or may include any alloy of at least one of the foregoing materials. The transparent conductive layer may include a transparent conductive oxide, such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO). In some embodiments, the transparent conductive layer may include at least one conductive polymer, such as PEDOT, metal nanowires and graphene. The multilayer conductive layer may include a multilayer metal layer. The multilayer metal layer may have a three-layer structure of, for example, Ti / Al / Ti. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0135] Each of the first insulating layer 420 and the second insulating layer 440 may have a single layer or a multilayer structure. Each of the first insulating layer 420 and the second insulating layer 440 may include an inorganic material, an organic material, or a composite material. In some embodiments, at least one of the first insulating layer 420 and the second insulating layer 440 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In some embodiments, at least one of the first insulating layer 420 and the second insulating layer 440 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0136] The touch unit TU may sense external input, for example, by a capacitive method; however, an operation method of the touch unit TU is not particularly limited, and the touch unit TU according to some embodiments may sense external input by an electromagnetic induction method, a pressure sensing method, etc.

[0137] The color filter layer may be disposed on the touch unit TU. The color filter layer may include first, second, and third light blocking layers 510a, 510b, and 510c and first, second, and third color filters 520a, 520b, and 520c.

[0138] The color filter layer may be arranged on each of the first sub-pixel 10, the second sub-pixel 11, and the third sub-pixel 12. The first color filter 520a of the color filter layer may be arranged on the first light blocking layer 510a exposing the central portion thereof, the second color filter 520b may be arranged on the second light blocking layer 510b exposing the central portion thereof, and the third color filter 520c may be arranged on the third light blocking layer 510c exposing the central portion thereof. The first light blocking layer 510a may overlap with the first pixel defining layer 180a, the second light blocking layer 510b may overlap with the second pixel defining layer 180b, and the third light blocking layer 510c may overlap with the third pixel defining layer 180c.

[0139] The first light blocking layer 510a, the second light blocking layer 510b, and the third light blocking layer 510c may include various materials such as an organic material mixed with a black pigment, chromium (Cr), and chromium oxide (CrO x). When the first light blocking layer 510a, the second light blocking layer 510b and the third light blocking layer 510c are formed of chromium or chromium oxide, the first light blocking layer 510a, the second light blocking layer 510b and the third light blocking layer 510c may include a single layer or a multilayer structure of chromium or chromium oxide. In an embodiment, the first light blocking layer 510a, the second light blocking layer 510b and the third light blocking layer 510c may include the same material.

[0140] The first color filter 520a, the second color filter 520b, and the third color filter 520c may include an organic material pattern including a dye and / or a pigment. The first color filter 520a may include a blue color filter, the second color filter 520b may include a green color filter, and the third color filter 520c may include a red color filter. The first color filter 520a may be arranged on the first emission portion EA1, the second color filter 520b may be arranged on the second emission portion EA2, and the third color filter 520c may be arranged on the third emission portion EA3. The first color filter 520a may overlap with the first pixel electrode 210a, the second color filter 520b may overlap with the second pixel electrode 210b, and the third color filter 520c may overlap with the third pixel electrode 210c.

[0141] A display device according to some embodiments may have improved flexibility by using a light blocking layer and a color filter instead of a polarizer.

[0142] Fig. 9 is a cross-sectional view schematically illustrating a portion of a display device according to some exemplary embodiments. Fig. 9 There is a difference in the structure under the organic light emitting diode. Figure 7 Hereinafter, repeated descriptions will be mainly avoided, and the differences will be mainly described.

[0143] Reference Fig. 9 , the first planarization layer 113 may be disposed on the interlayer insulating layer 107 , and the second planarization layer 115 may be disposed on the first planarization layer 113 .

[0144] The first and second planarization layers 113 and 115 may planarize upper surfaces of the first, second, and third pixel circuits PC1, PC2, and PC3 to planarize surfaces in which the organic light emitting diodes OLED1, OLED2, and OLED3 are to be positioned.

[0145] The first planarization layer 113 and the second planarization layer 115 may include at least one of a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), poly(methyl methacrylate) (PMMA) and polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer and a vinyl alcohol polymer and any blends thereof. The first planarization layer 113 and the second planarization layer 115 may include an inorganic material. The first planarization layer 113 and the second planarization layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ). When the first planarization layer 113 and the second planarization layer 115 include an inorganic material, chemical planarization polishing may be performed in some cases. The first planarization layer 113 and the second planarization layer 115 may include both an organic material and an inorganic material.

[0146] The first contact electrodes 108 a , 108 b , and 108 c may be positioned between the interlayer insulating layer 107 and the first planarization layer 113 , and the second contact electrodes 109 a , 109 b , and 109 c may be positioned between the first planarization layer 113 and the second planarization layer 115 .

[0147] The first planarization layer 113 may include a first via VIA1 , a second via VIA2 , and a third via VIA3 , and the second planarization layer 115 may include a fourth via VIA4 , a fifth via VIA5 , and a sixth via VIA6 .

[0148] The first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c may be disposed on the second planarization layer 115. The first pixel electrode 210a may be electrically connected to the first pixel circuit PC1 through the first via hole VIA1 and the fourth via hole VIA4, the second pixel electrode 210b may be electrically connected to the second pixel circuit PC2 through the second via hole VIA2 and the fifth via hole VIA5, and the third pixel electrode 210c may be electrically connected to the third pixel circuit PC3 through the third via hole VIA3 and the sixth via hole VIA6.

[0149] The first via hole VIA1 and the fourth via hole VIA4 may be arranged on the same imaginary line (e.g., aligned concentrically with each other), the second via hole VIA2 and the fifth via hole VIA5 may be spaced apart from each other (e.g., aligned non-concentrically with each other), and the third via hole VIA3 and the sixth via hole VIA6 may be arranged on the same imaginary line (e.g., aligned concentrically with each other). In an embodiment, the second contact electrode 109b of the second sub-pixel 11 may extend to one side of the second non-emitting portion NEA2 to increase the distance between the end of the second pixel defining layer 180b and the fifth via hole VIA5.

[0150] Fig.10 is a plan view schematically illustrating locations of via holes according to some exemplary embodiments.

[0151] like Fig.10 As shown in , as indicated by the dotted lines, on a plane, the first via hole VIA1 of the first sub-pixel 10, the second via hole VIA2 of the second sub-pixel 11, and the third via hole VIA3 of the third sub-pixel 12 may be arranged substantially in a zigzag pattern in the row direction (e.g., the x direction). In addition, on a plane, the fourth via hole VIA4, the fifth via hole VIA5, and the sixth via hole VIA6 may be arranged substantially in a zigzag pattern in the row direction.

[0152] The display device according to the embodiment may include: a substrate 100 including a first emission part EA1, a second emission part EA2 and a third emission part EA3; a first planarization layer 113 arranged above the substrate 100 and including a first via hole VIA1, a second via hole VIA2 and a third via hole VIA3; a first pixel electrode 210a arranged on the first planarization layer 113 and electrically connected to the first pixel circuit PC1 through the first via hole VIA1; a second pixel electrode 210b arranged on the first planarization layer 113 and electrically connected to the second pixel circuit PC2 through the second via hole VIA2; a third pixel electrode 210c arranged on the first planarization layer 113 and electrically connected to the third pixel circuit PC3 through the third via hole VIA3; a first pixel defining layer 180a, a second pixel defining layer 180b and The third pixel defining layer 180c is arranged on the first pixel electrode 210a, the second pixel electrode 210b and the third pixel electrode 210c and includes a first opening OP1 exposing a central portion of the first pixel electrode 210a, a second opening OP2 exposing a central portion of the second pixel electrode 210b, and a third opening OP3 exposing a central portion of the third pixel electrode 210c; the first intermediate layer 220a is arranged on the first pixel electrode 210a; the second intermediate layer 220b is arranged on the second pixel electrode 210b; the third intermediate layer 220c is arranged on the third pixel electrode 210c; and the first relative electrode 230a, the second relative electrode 230b and the third relative electrode 230c are arranged on the first intermediate layer 220a, the second intermediate layer 220b and the third intermediate layer 220c. In this way, the second distance d2 defined as the shortest distance from the inner surface of the second opening OP2 to the second via VIA2 can be greater than the first distance d1 defined as the shortest distance from the inner surface of the first opening OP1 to the first via VIA1, and the third distance d3 defined as the shortest distance from the inner surface of the third opening OP3 to the third via VIA3 can be less than the second distance d2.

[0153] The display device may further include a second planarization layer 115 disposed on the first planarization layer 113 , and the second planarization layer 115 may include a fourth via hole VIA4 , a fifth via hole VIA5 , and a sixth via hole VIA6 .

[0154] The first via VIA1 , the second via VIA2 , and the third via VIA3 may be arranged in a zigzag pattern on a plane, and the fourth via VIA4 , the fifth via VIA5 , and the sixth via VIA6 may be arranged in a zigzag pattern on a plane.

[0155] A color filter layer may be further disposed over the first, second, and third opposing electrodes 230a, 230b, and 230c. The color filter layer may include first, second, and third light blocking layers 510a, 510b, and 510c, and first, second, and third color filters 520a, 520b, and 520c.

[0156] According to some exemplary embodiments, in order to solve the problem of the occurrence of a green reflective color band in the case of using a conventional structure of a color filter and a light blocking layer having a polarization function in a display device, the display device can be configured to increase the distance between the via hole of the green sub-pixel and the end of the pixel defining layer compared to the blue sub-pixel and the red sub-pixel to improve the flatness of the green sub-pixel. In this way, a display device having improved reliability while preventing the occurrence of a green reflective color band can be provided.

[0157] Although only the display device has been mainly described above, the embodiments are not limited thereto. For example, a method of manufacturing a display device is also within the scope of the present disclosure.

[0158] According to some embodiments, by increasing the distance between the via hole of the green sub-pixel and the end of the pixel defining layer compared to the blue sub-pixel and the red sub-pixel to improve the flatness of the green sub-pixel, a display device having improved reliability while preventing the occurrence of green reflective color bands can be achieved. However, the scope of the present disclosure is not limited to these effects.

[0159] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the present disclosure and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, wherein: The display device comprises: A first planarization layer, comprising a first via hole, a second via hole, and a third via hole; The first sub-pixel includes a first pixel electrode and a first pixel defining layer, wherein the first pixel electrode is arranged on the first planarization layer and is electrically connected to the first pixel circuit through the first via hole, and the first sub-pixel further includes a first emission portion and a first non-emission portion surrounding the first emission portion, wherein the first pixel defining layer is arranged on the first pixel electrode and includes a first opening exposing a portion of the first pixel electrode corresponding to the first emission portion; The second sub-pixel includes a second pixel electrode and a second pixel defining layer, wherein the second pixel electrode is arranged on the first planarization layer and is electrically connected to the second pixel circuit through the second via hole, and the second sub-pixel further includes a second emission portion and a second non-emission portion surrounding the second emission portion, wherein the second pixel defining layer is disposed on the second pixel electrode and includes a second opening exposing a portion of the second pixel electrode corresponding to the second emission portion; and A third sub-pixel includes a third pixel electrode and a third pixel defining layer, The third sub-pixel is arranged on the first planarization layer and electrically connected to a third pixel circuit through the third via hole, and the third sub-pixel includes a third emission portion and a third non-emission portion surrounding the third emission portion. wherein the third pixel defining layer is arranged on the third pixel electrode and includes a third opening exposing a portion of the third pixel electrode corresponding to the third emission portion, wherein a second distance defined as the shortest distance from an inner surface of the second opening to the second via hole is greater than a first distance defined as the shortest distance from an inner surface of the first opening to the first via hole, Wherein, a third distance defined as the shortest distance from the inner surface of the third opening to the third via hole is smaller than the second distance.

2. The display device according to claim 1, wherein: The first via hole, the second via hole, and the third via hole are arranged in a zigzag pattern on a plane.

3. The display device according to claim 1, wherein: The first subpixel further includes: a first intermediate layer disposed on the portion of the first pixel electrode exposed by the first opening; and a first opposing electrode disposed on the first intermediate layer; The second sub-pixel further includes: a second intermediate layer disposed on the portion of the second pixel electrode exposed by the second opening; and a second opposing electrode disposed on the second intermediate layer; and The third subpixel further includes: a third intermediate layer disposed on the portion of the third pixel electrode exposed by the third opening; and a third opposing electrode disposed on the third intermediate layer.

4. The display device according to claim 3, wherein: The display device further includes: A thin film encapsulation layer is disposed on the first relative electrode, the second relative electrode and the third relative electrode, and the thin film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer.

5. The display device according to claim 4, wherein: The display device further includes: A touch unit is directly arranged on the thin film encapsulation layer, Wherein, the touch unit comprises: a first conductive layer; a second conductive layer, arranged above the first conductive layer; a first insulating layer disposed between the first conductive layer and the second conductive layer; and The second insulating layer is arranged on the second conductive layer.

6. The display device according to claim 5, wherein: The display device further includes: a color filter layer disposed on the first sub-pixel, the second sub-pixel and the third sub-pixel, Wherein, the color filter layer includes a first color filter, a second color filter and a third color filter.

7. The display device according to claim 6, wherein: The color filter layer is disposed on the touch unit.

8. The display device according to claim 6, wherein: The first color filter is disposed above the first emitting portion; the second color filter being disposed over the second emitting portion; and The third color filter is disposed over the third emission portion.

9. The display device according to claim 1, wherein: Each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer includes a light blocking material.

10. The display device according to claim 1, wherein: The display device further includes: Interlayer insulation layer; A first contact electrode is arranged on the interlayer insulating layer; a second planarization layer disposed on the first contact electrode and comprising a fourth via hole, a fifth via hole, and a sixth via hole; and The second contact electrode is arranged between the first planarization layer and the second planarization layer.

11. The display device according to claim 10, wherein: The first pixel electrode is electrically connected to the first pixel circuit through the first via hole and the fourth via hole; The second pixel electrode is electrically connected to the second pixel circuit through the second via hole and the fifth via hole; and The third pixel electrode is electrically connected to the third pixel circuit through the third via hole and the sixth via hole.

12. The display device according to claim 10, wherein: In floor plan: The first via hole and the fourth via hole are located on the same imaginary line; and The second via hole and the fifth via hole are spaced apart from each other.

13. The display device according to claim 1, wherein: The first emitting portion has a first area; and The second emitting portion has a second area that is smaller than the first area.

14. The display device according to claim 1, wherein: The first sub-pixel is a blue sub-pixel; The second sub-pixel is a green sub-pixel; and The third sub-pixel is a red sub-pixel.

15. A display device, wherein: The display device comprises: a substrate including a first region corresponding to the first emission portion, a second region corresponding to the second emission portion, and a third region corresponding to the third emission portion; A first planarization layer, arranged above the substrate, the first planarization layer comprising a first via hole, a second via hole and a third via hole; a first pixel electrode, arranged on the first planarization layer and electrically connected to a first pixel circuit through the first via hole; a second pixel electrode, arranged on the first planarization layer and electrically connected to a second pixel circuit through the second via hole; a third pixel electrode, arranged on the first planarization layer and electrically connected to a third pixel circuit through the third via hole; a pixel defining layer disposed on the first pixel electrode, the second pixel electrode and the third pixel electrode, the pixel defining layer comprising a first opening exposing a central portion of the first pixel electrode, a second opening exposing a central portion of the second pixel electrode and a third opening exposing a central portion of the third pixel electrode; A first intermediate layer, arranged on the first pixel electrode; A second intermediate layer, arranged on the second pixel electrode; A third intermediate layer, arranged on the third pixel electrode; and a counter electrode disposed on the first intermediate layer, the second intermediate layer and the third intermediate layer, wherein a second distance defined as the shortest distance from the inner surface of the second opening to the second via hole is greater than a first distance defined as the shortest distance from the inner surface of the first opening to the first via hole, Wherein, a third distance defined as the shortest distance from the inner surface of the third opening to the third via hole is smaller than the second distance.

16. The display device according to claim 15, wherein: The first via hole, the second via hole, and the third via hole are arranged in a zigzag pattern on a plane.

17. The display device according to claim 15, wherein: The display device further includes: A color filter layer is arranged above the opposite electrode.

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