Display panel and display device comprising the same

Abstract

A display panel and a display device including the same are provided. The display panel includes a substrate including a component area and a display area surrounding the component area, the component area including a first area and a second area surrounding the first area; a plurality of first display elements at the display area; a plurality of pixel groups spaced apart from each other in an island shape at the first area, each of the plurality of pixel groups including a plurality of second display elements; a plurality of transmission areas at the first area and adjacent to the plurality of pixel groups; and a plurality of first wires extending in a first direction and electrically connected to the plurality of first display elements, the plurality of first wires running around the first area at the second area.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0136892, filed on October 30, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display panel and a display device including the display panel, and more specifically, to a display panel and a display device including the display panel in which the display area is enlarged such that an image can be displayed even in an area in which components are arranged (e.g., in an area in which components are arranged or on an area in which components are arranged). Background Technology

[0003] Recently, the purposes of display devices have been diversifying. Furthermore, as display devices have become thinner and lighter, their applications have been expanding.

[0004] Because display devices are used in various ways, they can be designed in a variety of shapes. Furthermore, the number of functions that can be combined with or related to display devices is increasing.

[0005] The information disclosed above in this background section is intended to enhance the understanding of the background art of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] One or more exemplary embodiments of this disclosure relate to a display device including a first region, wherein components (such as sensors and / or cameras, for example) may be arranged in the first region (e.g., in or on the first region), and the display region surrounds the first region, such that additional functionality may be added that can be combined with or associated with the display device.

[0007] However, this disclosure is not limited to the aspects and features described above, and additional aspects and features will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing one or more exemplary embodiments of this disclosure.

[0008] According to one or more example embodiments of the present disclosure, a display panel includes: a substrate including a component region and a display region surrounding the component region, the component region including a first region and a second region surrounding the first region; a plurality of first display elements at the display region; a plurality of pixel groups spaced apart from each other in an island-like manner at the first region, each of the plurality of pixel groups including a plurality of second display elements; a plurality of transmissive regions at the first region and adjacent to the plurality of pixel groups; and a plurality of first wirings extending in a first direction and electrically connected to the plurality of first display elements, the plurality of first wirings being located at the second region and circumferentially surrounding the first region.

[0009] In the example embodiment, the resolution of the component area per unit area may be half or less of the resolution of the display area per unit area.

[0010] In an example embodiment, the display panel may further include: a plurality of second wirings extending in a first direction and electrically connected to a plurality of second display elements, the plurality of second wirings being superimposed on at least a portion of a plurality of transmissive regions.

[0011] In an example embodiment, multiple second wirings superimposed on at least a portion of multiple transmission regions may be biased on one side of the multiple transmission regions.

[0012] In an example embodiment, multiple first wirings and multiple second wirings can be configured to transmit data signals to multiple first display elements and multiple second display elements.

[0013] In an example embodiment, the display panel may further include: a plurality of third wirings extending in a second direction intersecting the first direction and circumnavigating along the edge of the first region.

[0014] In an example embodiment, multiple third wirings may be configured to transmit scan signals to multiple first display elements.

[0015] In an example embodiment, the display panel may further include: a first conductive layer on a substrate; a second conductive layer on the first conductive layer; a first insulating layer between the first conductive layer and the second conductive layer; and a plurality of second wirings extending in a first direction and electrically connected to a plurality of second display elements, the plurality of second wirings being superimposed on at least a portion of a plurality of transmissive regions. The plurality of second wirings may include the same material as the first conductive layer.

[0016] In an example embodiment, each of the plurality of first wirings may include an extension portion at a display area and a bypass portion at a second area, and the extension portion may be connected to the bypass portion through a contact hole defined in a first insulating layer.

[0017] In an example embodiment, the extension portion may include the same material as the first conductive layer, and the bypass portion may include the same material as the second conductive layer.

[0018] In an example embodiment, each of the plurality of second display elements may be electrically connected to a pixel circuit including a thin-film transistor and a storage capacitor. The thin-film transistor may include a semiconductor layer, a gate electrode stacked with the semiconductor layer, and an electrode layer connected to the semiconductor layer. The storage capacitor may include a bottom electrode and a top electrode stacked with the bottom electrode. The gate electrode of the thin-film transistor serves as the bottom electrode of the storage capacitor.

[0019] In an example embodiment, the first conductive layer may include the same material as the electrode layer.

[0020] In an example embodiment, each of the plurality of second display elements may include: a pixel electrode; a counter electrode on the pixel electrode; and an intermediate layer between the pixel electrode and the counter electrode. The pixel circuit may also include a contact metal layer connected to the electrode layer at its bottom and connected to the pixel electrode at its top.

[0021] In an example embodiment, the second conductive layer may include the same material as the contact metal layer.

[0022] In the example embodiment, some of the multiple pixel groups may be surrounded by multiple transmissive regions.

[0023] In the example embodiment, some of the multiple pixel groups may be surrounded by multiple transmission regions and a second region.

[0024] In an example embodiment, the display panel may further include at least one insulating layer on a substrate, and the at least one insulating layer may have openings corresponding to a plurality of transmissive regions respectively.

[0025] In an example embodiment, some of the first wirings in the plurality of first wirings may be arranged around at least some of the pixel groups in the plurality of pixel groups, and may be superimposed on some of the transmission regions in the plurality of transmission regions.

[0026] In the example embodiment, the transmittance of multiple transmission regions can be greater than that of the second region.

[0027] In the example embodiment, the display panel may further include multiple metal layers in the component area, and the multiple metal layers may correspond to multiple pixel groups respectively.

[0028] In an example embodiment, each of a plurality of second display elements may be electrically connected to a thin-film transistor, the thin-film transistor including a semiconductor layer and a gate electrode stacked thereon, and a plurality of metal layers may be positioned between a substrate and the semiconductor layer.

[0029] According to one or more example embodiments of this disclosure, a display device includes: a display panel including a substrate, the substrate including a component region and a display region surrounding the component region, the component region including a first region and a second region surrounding the first region; and electronic components at the component region of the display panel. The display panel includes: a plurality of first display elements at the display region; a plurality of pixel groups spaced apart from each other in an island-like manner at the first region, each of the plurality of pixel groups including a plurality of second display elements; a plurality of transmissive regions at the first region and adjacent to the plurality of pixel groups; and a plurality of first wirings extending in a first direction and electrically connected to the plurality of first display elements, the plurality of first wirings at the second region and arranged around the first region.

[0030] In an example embodiment, the electronic component may include an imaging element. Attached Figure Description

[0031] The above and other aspects and features of this disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a perspective view of a display device according to an embodiment;

[0033] Figure 2 This is a cross-sectional view of a display device according to an embodiment;

[0034] Figure 3 This is a plan view of the display panel according to an embodiment;

[0035] Figures 4A to 4C It is a plan view of a pixel arrangement structure according to one or more embodiments;

[0036] Figures 5A to 5B It is an equivalent circuit diagram that can be included in the main pixels and / or auxiliary pixels in a display panel according to one or more embodiments;

[0037] Figure 6 This is a cross-sectional view of the pixel circuitry of the pixel according to an embodiment;

[0038] Figure 7 This is a plan view showing the arrangement of pixels and wiring in a display device according to an embodiment;

[0039] Figure 8 yes Figure 7 A magnified plan view of a local area;

[0040] Figure 9 It is along Figure 8 A sectional view of the local area intercepted by line III-III';

[0041] Figure 10 This is a plan view showing the arrangement of pixels and wiring in a display device according to an embodiment; and

[0042] Figure 11 This is a plan view showing the arrangement of pixels and wiring in a display device according to an embodiment. Detailed Implementation

[0043] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are unnecessary for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Furthermore, a particular process sequence may differ from the described process sequence when specific embodiments can be implemented differently. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or the two consecutively described processes may be performed in the reverse order of their description. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description need not be repeated.

[0044] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature as shown in the drawings to another (or other) element or feature. It will be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will subsequently be positioned “above” other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein should be interpreted accordingly. In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0045] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first part described below may be referred to as a second element, second component, second region, second layer, or second part.

[0046] It will be understood that when an element, layer, or component (e.g., such as a membrane, region, and / or plate) is referred to as being "on," "connected to," or "bonded to" another element, layer, or component, the element, layer, or component may be directly on, directly connected to, or directly bonded to the other element, layer, or component, or one or more intermediate elements, layers, or components may be present. Furthermore, it will be understood that when an element, layer, or component is referred to as being "between" two elements, two layers, or two components, the element, layer, or component may be the only element, only layer, or only component between the two elements, two layers, or two components, or one or more intermediate elements, intermediate layers, or intermediate components may be present.

[0047] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular form “a” is intended to include the plural form as well. It will also be understood that when the terms “comprising,” “including,” “having,” and “comprise” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, “A and / or B” means A or B, or A and B. When expressions such as “at least one of…” follow a list of elements, the entire list of elements is modified, not any individual element in the list. For example, the expression "at least one of a, b and c" can indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0048] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively. Additionally, the term “exemplary” is intended to indicate an example or illustration.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0050] Figure 1 This is a perspective view of the display device 1 according to an embodiment.

[0051] Reference Figure 1The display device 1 includes a component region CA, a display region DA, and a peripheral region PA. The display region DA may at least partially surround the component region CA (e.g., around the periphery of the component region CA), and the peripheral region PA may be outside the display region DA. For example, in an embodiment, the peripheral region PA may at least partially surround the display region DA (e.g., around the periphery of the display region DA). The display device 1 can provide an image (e.g., a predetermined image) by using light emitted from a plurality of pixels arranged in the display region DA and the component region CA (e.g., arranged in or on the display region DA and the component region CA). In an embodiment, as... Figure 1 As shown, a component region CA can be arranged within (e.g., inside) the display region DA. However, this disclosure is not limited thereto, and in another embodiment, the number of component regions CA can be two or more, and the shapes and / or sizes of the multiple component regions CA can be the same or substantially the same as each other or can be different from each other. A peripheral region PA can define (e.g., it can be a type of) a non-display area where no pixels are arranged (e.g., in or on the non-display area). In an embodiment, the display region DA can be (e.g., around the periphery of the display region DA) completely surrounded by the peripheral region PA.

[0052] In the following description, the display device 1 according to the embodiments can be described as an organic light-emitting display device by way of example. However, this disclosure is not limited thereto. For example, in other embodiments, the display device 1 can be a variety of suitable types of display devices, such as inorganic light-emitting display devices and / or quantum dot light-emitting display devices. For example, in various embodiments, the emitting layer of the display element of the display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots and / or inorganic materials and quantum dots, etc.

[0053] although Figure 1 The component region CA is shown to have a circular or approximately circular shape in a plan view (e.g., in a view from a direction perpendicular to or substantially perpendicular to the main surface of the substrate), but this disclosure is not limited thereto. For example, in other embodiments, the shape of the component region (e.g., each component region) CA in the plan view can be modified to any suitable shape, such as polygonal shapes (e.g., including quadrilateral shapes, star shapes and / or rhomboid shapes, etc.), circular shapes and / or elliptical shapes, etc.

[0054] although Figure 1The diagram illustrates that the component region CA can be arranged at the center or central area of ​​one side (e.g., the upper side) of the display region DA (e.g., arranged at the center or central area of ​​one side of the display region DA or arranged on the center or central area of ​​one side of the display region DA). The display region DA can have a quadrilateral shape in the plan view, but this disclosure is not limited thereto. For example, in other embodiments, when the display region DA has a quadrilateral shape in the plan view, the component region CA can be arranged at the center or central area of ​​the upper right, upper left, and lower sides of the display region DA, the lower right, lower left, right side, and / or left side, etc. (arranged in the center or central area of ​​the upper right, upper left, and lower sides of the display region DA, the lower right, lower left, right side, and / or left side, etc., or arranged on the center or central area of ​​the upper right, upper left, and lower sides of the display region DA, the lower right, lower left, right side, and / or left side, etc.). Furthermore, the shape of the display area DA in the plan view is not limited to a quadrilateral shape, and the display area DA can have any suitable shape in the plan view, such as another polygonal shape (e.g., square, rhombus, pentagon and / or star, etc.), circular shape and / or elliptical shape, etc.

[0055] The display device 1 can provide a main image by using light emitted from a plurality of main pixels Pm arranged in the display area DA (e.g., arranged in or on the display area DA).

[0056] The display device 1 includes a component area CA within the display area DA (e.g., internally). See below for reference. Figure 2 In more detail, the component region CA can be the area beneath which a component (such as a sensor and / or imaging element, for example) is disposed. For example, a sensor may use visible light or sound, and an imaging element may include a camera. The component region CA may include (e.g., may be) a transmissive region TA through which light emitted from the component toward the outside and / or light propagating from the outside toward the component can be transmitted (e.g., may pass through) the transmissive region TA. In embodiments where infrared light passes through the component region CA, the transmittance of the component region CA may be 10% (e.g., about 10%) or greater. For example, in various embodiments, the transmittance of the component region CA may be 20% (e.g., about 20%) or greater, 25% (e.g., about 25%) or greater, 50% (e.g., about 50%) or greater, 85% (e.g., about 85%) or greater, or 90% (e.g., about 90%) or greater.

[0057] exist Figure 1In the illustrated embodiment, a plurality of auxiliary pixels Pa may be arranged at the component region CA (e.g., arranged in or on the component region CA). The display device 1 can provide an image (e.g., a predetermined image) by using light emitted from the plurality of auxiliary pixels Pa. The image provided from the component region CA may be an auxiliary image, and the resolution of the auxiliary image may be less than the resolution of the image provided from the display region DA. In other words, the component region CA may include a transmission region TA through which light and / or sound can be transmitted (e.g., passed through). In some embodiments, pixels (e.g., auxiliary pixels Pa) may not be arranged at the transmission region TA (e.g., not arranged in or on the transmission region TA). Because auxiliary pixels Pa may not be arranged in the transmission region TA (e.g., not arranged in or on the transmission region TA), the number of auxiliary pixels Pa per unit area that can be arranged in the component region CA (e.g., in or on the component region CA) can be less than the number of main pixels Pm per unit area that can be arranged in the display region DA (e.g., in or on the display region DA).

[0058] The component region CA may include a first region A1 and a second region A2. The first region A1 typically refers to the central portion (e.g., the central area) of the component region CA, and the second region A2 typically refers to the edge portion (e.g., the peripheral portion) of the component region CA. The second region A2 may be a region that at least partially surrounds the first region A1 (e.g., around the periphery of the first region A1). Multiple auxiliary pixels Pa and a transmission region TA may be located at the first region A1 (e.g., located within or on the first region A1).

[0059] Figure 2 This is a cross-sectional view of the display device 1 according to an embodiment. Figure 2 Can be along Figure 1 The cross-section of display device 1 is corresponding to the line A-A'.

[0060] Reference Figure 2 The display device 1 may include a display panel 10 containing a display element (e.g., OLED) and an electronic component 20 (which may also be referred to as a component) positioned below the display panel 10 and corresponding to the component region CA.

[0061] The display panel 10 may include a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 that seals the display element layer 200 as a sealing member. The display panel 10 may also include a bottom protective film 175 disposed below (e.g., under) the substrate 100.

[0062] The substrate 100 may comprise glass or a polymeric resin. In embodiments, the substrate 100 may comprise a polymeric resin (such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate). The substrate 100 comprising a polymeric resin may be flexible, rollable, and / or bendable. The substrate 100 may have a multilayer structure comprising, for example, a layer containing a polymeric resin and an inorganic layer.

[0063] The display element layer 200 may include a circuit layer, an organic light-emitting diode (OLED) as a display element, and an insulating layer IL between the circuit layer and the OLED. The circuit layer may include a thin-film transistor (TFT).

[0064] The main pixel Pm is disposed at the display area DA (e.g., disposed in or on the display area DA). The main pixel Pm may include a thin-film transistor TFT and an organic light-emitting diode OLED connected to the thin-film transistor TFT. In other words, the main pixel Pm may include a main thin-film transistor TFT in the display area DA and a main organic light-emitting diode OLED connected to the main thin-film transistor TFT (see [link to relevant documentation]). Figure 6 Furthermore, wiring (e.g., scan lines, data lines, transmit control lines, and / or power lines, etc.) can be arranged at the display area DA (e.g., arranged in or on the display area DA) and can be electrically connected to the main pixel Pm and / or the auxiliary pixel Pa.

[0065] The auxiliary pixel Pa can be disposed at the component region CA (e.g., disposed in or on the component region CA). The auxiliary pixel Pa can include a thin-film transistor (TFT) and an organic light-emitting diode (OLED) connected to the TFT; in other words, the auxiliary pixel Pa can include an auxiliary TFT' in the component region CA and an auxiliary OLED' connected to the auxiliary TFT' (see [reference needed]). Figure 6 The component region CA may include a first region A1 and a second region A2 that at least partially surrounds the first region A1 (e.g., around the periphery of the first region A1). An auxiliary pixel Pa may be located at the first region A1 (e.g., within or on the first region A1). The second region A2 may be an area where a wiring WL extending around the first region A1 (e.g., around a row around the first region A1) may be arranged (e.g., within or on).

[0066] The transmissive region TA, where the thin-film transistor TFT and auxiliary pixel Pa are not disposed therein (e.g., not disposed therein or not disposed on therein), can be disposed at the component region CA (e.g., disposed in or disposed on the component region CA). The transmissive region TA can be the area through which light / signal emitted from electronic element 20 and / or incident light / signal to electronic element 20 is transmitted (e.g., passes through).

[0067] Electronic component 20 may be located at component region CA (e.g., located in or on component region CA). Electronic component 20 may be an electronic component or device that uses light and / or sound. For example, electronic component 20 may be an imaging element such as a camera, a sensor such as an infrared sensor that emits and / or receives light, a sensor that outputs and senses light and / or sound to measure distance or identify fingerprints, a lamp (e.g., a small light) that outputs light, and / or a speaker that outputs sound, etc. Electronic component 20 that uses light may use light of various wavelengths, such as visible light, infrared light, and ultraviolet light. Electronic component 20 arranged at component region CA (e.g., arranged in or on component region CA) may be configured as a single electronic component or multiple electronic components. For example, light-emitting elements and light-receiving elements may be arranged (e.g., arranged together) as multiple electronic components 20 at one or more component regions CA (e.g., in or on one or more component regions CA). In another example, an electronic component 20 may include a light emitter and a light receiver concurrently (e.g., simultaneously or at the same time) as a single electronic component 20.

[0068] The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, Figure 2 The thin-film encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0069] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic insulating material selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may comprise a polymeric material. The polymeric material may comprise, for example, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate and / or polyacrylic acid, etc.) or any suitable combination thereof.

[0070] A bottom protective film 175 may be attached below (e.g., beneath) the substrate 100 to support and protect the substrate 100. The bottom protective film 175 may include an opening 175OP corresponding to the component region CA. Because the opening 175OP can be provided in the bottom protective film 175, the light transmittance of the component region CA can be increased. The bottom protective film 175 may include polyethylene terephthalate or polyimide.

[0071] The area (e.g., size) of component region CA can be larger than the area where electronic component 20 is arranged (e.g., arranged therein or on it). Although in Figure 2 The diagram shows that the area (e.g., size) of component region CA is equal to or substantially equal to the area (e.g., size) of opening 175OP, but this disclosure is not limited thereto. The area of ​​opening 175OP disposed in the bottom protective film 175 may not be equal to or substantially equal to the area of ​​component region CA. For example, in another embodiment, the area of ​​opening 175OP may be smaller than the area of ​​component region CA.

[0072] In some embodiments, various elements (such as input sensing elements for sensing touch input, anti-reflective elements (e.g., including polarizers, delayers, color filters and / or black matrices, etc.) and / or transparent windows, etc.) may be further arranged on the display panel 10.

[0073] although Figure 2 The thin-film encapsulation layer 300 is shown to be used as an encapsulation component for sealing the display element layer 200, but this disclosure is not limited thereto. For example, a sealing substrate attached to the substrate 100 by using a sealant or glass frit can be used as a component for sealing the display element layer 200.

[0074] Figure 3 This is a plan view of the display panel 10 according to an embodiment.

[0075] Reference Figure 3 Various types of elements, including those constituting the display panel 10, can be arranged on the substrate 100. The substrate 100 includes a display area DA and a peripheral area PA surrounding the display area DA (e.g., around the periphery of the display area DA). The display area DA includes a display area (e.g., a main display area) where a main image can be displayed (e.g., displayed therein or on it) and a component area CA where auxiliary images can be displayed (e.g., displayed therein or on it). The component area CA may include a transmissive area TA located therein.

[0076] Multiple main pixels Pm are arranged at the display area DA (e.g., arranged in or on the display area DA). Each of the main pixels Pm may include a display element, such as an organic light-emitting diode (OLED). Each main pixel Pm may emit light or white light having a suitable or desired color (such as red, green, or blue) through the OLED. In an embodiment, the main pixel Pm may be a pixel that emits red, green, blue, or white light. The display area DA may be as described above. Figure 2 The described encapsulation component covers and can be protected from external air and / or moisture.

[0077] The component region CA can be arranged within the display region DA (e.g., inside), and multiple auxiliary pixels Pa can be arranged at the component region CA (e.g., arranged in or on the component region CA). Each of the multiple auxiliary pixels Pa can include a display element (such as an organic light-emitting diode OLED). Each auxiliary pixel Pa can emit light or white light with a suitable or desired color (such as red, green, or blue, for example) from the organic light-emitting diode OLED. In an embodiment, the auxiliary pixel Pa can be a pixel that emits red, green, blue, or white light.

[0078] The transmissive region TA may be located at the component region CA (e.g., within or on the component region CA) on one side of the plurality of auxiliary pixels Pa (e.g., located in or on one side of the plurality of auxiliary pixels Pa). In one embodiment, the transmissive region TA may surround the plurality of auxiliary pixels Pa (e.g., around the periphery of the plurality of auxiliary pixels Pa). In another embodiment, the transmissive region TA may be arranged in a lattice configuration with the plurality of auxiliary pixels Pa.

[0079] Because the component region CA includes the transmission region TA, the resolution of the component region CA can be smaller than the resolution of the display region DA. For example, the resolution of the component region CA can be about 1 / 2, 1 / 4, or 3 / 8 of the resolution of the display region DA. In an embodiment, the resolution of the display region DA can be about 400 pixels per inch (ppi) or greater, and the resolution of the component region CA can be about 200 ppi or about 100 ppi.

[0080] Each of the main pixel Pm and the auxiliary pixel Pa can be electrically connected to external circuitry arranged at the peripheral region PA (e.g., arranged in or on the peripheral region PA). For example, the first scan drive circuit 110, the second scan drive circuit 120, the transmit control drive circuit 130, the terminal 140, the first power supply line 160, and the second power supply line 170 can be arranged at the peripheral region PA (e.g., arranged in or on the peripheral region PA).

[0081] The first scan driving circuit 110 can provide scan signals to each of the main pixel Pm and auxiliary pixel Pa via corresponding scan lines SL. The first scan driving circuit 110 can also provide transmission control signals to each of the main pixel Pm and auxiliary pixel Pa via corresponding transmission control lines EL. The second scan driving circuit 120 can be arranged parallel to the first scan driving circuit 110, with a display area DA between the second scan driving circuit 120 and the first scan driving circuit 110. In one embodiment, some of the main pixels Pm and auxiliary pixels Pa can be electrically connected to the first scan driving circuit 110, and others of the main pixels Pm and auxiliary pixels Pa (e.g., the remaining or surplus main pixels Pm and auxiliary pixels Pa) can be electrically connected to the second scan driving circuit 120. In another embodiment, the second scan driving circuit 120 can be omitted.

[0082] Terminal 140 may be disposed on one side (e.g., the underside) of substrate 100 (e.g., in one side of substrate 100 or on one side of substrate 100). Terminal 140 may be exposed without being covered by an insulating layer and may be electrically connected to a printed circuit board (PCB). For example, terminal PCB-P of the PCB may be electrically connected to terminal 140 of display panel 10. The PCB is configured to transmit signals and / or power from the controller to display panel 10. Control signals generated by the controller may be transmitted via the PCB to the first scan drive circuit 110 and the second scan drive circuit 120. The controller may provide a first power voltage ELVDD and a second power voltage ELVSS to the first power supply line 160 and the second power supply line 170 respectively via the first connection line 161 and the second connection line 171 (e.g., see...). Figure 5A and Figure 5B The first power voltage ELVDD can be provided to each of the main pixel Pm and the auxiliary pixel Pa through the drive voltage line PL connected to the first power supply line 160, and the second power voltage (or common voltage) ELVSS can be provided to the counter electrode of each of the main pixel Pm and the auxiliary pixel Pa connected to the second power supply line 170.

[0083] The data driving circuit 150 is electrically connected to the data line DL. The data signal from the data driving circuit 150 can be provided to each of the main pixel Pm and the auxiliary pixel Pa via the corresponding third connection line 151 and the corresponding data line DL. For example, the third connection line 151 can be connected to terminal 140, and the data line DL can be connected to the third connection line 151. Although in Figure 3 The data driving circuit 150 is shown to be arranged on a printed circuit board (PCB), but this disclosure is not limited thereto. In another embodiment, the data driving circuit 150 may be arranged on a substrate 100. For example, in this case, the data driving circuit 150 may be arranged on the substrate 100 between the terminal 140 and the first power supply line 160.

[0084] The first power supply line 160 may include a first sub-line 162 and a second sub-line 163 extending in the x-axis direction. The first sub-line 162 and the second sub-line 163 may be parallel to each other, and a display area DA is located between the first sub-line 162 and the second sub-line 163. The second power supply line 170 may have a loop shape containing an open side and may partially surround the display area DA (e.g., around the periphery of the display area DA).

[0085] Figures 4A to 4C It is a plan view of a pixel arrangement structure according to one or more embodiments. Figure 4A The pixel arrangement structure within the display area DA is shown, and Figure 4B and Figure 4C The pixel arrangement structure inside the component region CA is shown.

[0086] Reference Figure 4A Multiple main pixels Pm can be arranged at the display area DA (e.g., arranged in or on the display area DA). Each of the multiple main pixels Pm can include a display element, such as an organic light-emitting diode (OLED). The main pixel Pm can be a sub-pixel that emits red, green, blue, or white light.

[0087] The plurality of main pixels Pm arranged at the display area DA (e.g., arranged in or on the display area DA) may include a main pixel Pr emitting red light, a main pixel Pg emitting green light, and a main pixel Pb emitting blue light. Although Figure 4A A plurality of principal pixels Pm are shown arranged in a pentile pattern, but this disclosure is not limited thereto. The plurality of principal pixels Pm may be arranged in a striped pattern or in various suitable shapes and / or arrangements.

[0088] Reference Figure 4BMultiple auxiliary pixels Pa can be arranged at the component region CA (e.g., arranged in or on the component region CA). Each of the multiple auxiliary pixels Pa can include a display element, such as an organic light-emitting diode (OLED). The auxiliary pixel Pa can be a sub-pixel that emits red, green, blue, or white light.

[0089] The component region CA may include a pixel group PG and a transmission region TA. The pixel group PG may include at least one auxiliary pixel Pa. The pixel group PG and the transmission region TA may be arranged alternately on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. In this case, multiple pixel groups PG and multiple transmission regions TA may be disposed at the component region CA (e.g., arranged in or on the component region CA), and multiple pixel groups PG may be spaced apart from each other in an island-like manner in a first region A1 of the component region CA.

[0090] A pixel group PG can be defined as a set of pixels (e.g., a pixel set) in which multiple auxiliary pixels Pa are grouped in units (e.g., predetermined units). Although Figure 4B and Figure 4C The illustration shows that a pixel group PG may include eight auxiliary pixels Pa, but this disclosure is not limited thereto. For example, the number of auxiliary pixels Pa included in the pixel group PG may be modified differently depending on the resolution of the component region CA.

[0091] Pixel group PG may include auxiliary pixels Pr that emit red light, auxiliary pixels Pg that emit green light, and auxiliary pixels Pb that emit blue light. Although Figure 4B An auxiliary pixel Pa with a pentile arrangement is shown, but this disclosure is not limited thereto. The auxiliary pixel Pa can be formed in a striped arrangement or in various suitable shapes and / or arrangements.

[0092] The transmissive region TA can be arranged on one side (e.g., a side edge) of the pixel group PG (e.g., in one side of the pixel group PG or on one side of the pixel group PG). Although Figure 4B This disclosure illustrates that multiple transmissive regions TA and multiple pixel groups PG can be arranged alternately in a lattice structure; however, this disclosure is not limited thereto, and the transmissive regions TA can be arranged, for example, as shown in... Figure 4C The ground shown is around the pixel group PG (e.g., around the periphery of the pixel group PG).

[0093] The auxiliary pixel Pa may not be located at the transmissive region TA (e.g., not located in or on the transmissive region TA). The absence of an auxiliary pixel Pa may mean that the auxiliary pixel Pa does not include a display element (such as an organic light-emitting diode OLED). In other words, the pixel electrode, intermediate layer, and counter electrode may define (e.g., may constitute) the organic light-emitting diode OLED, and the pixel circuitry electrically connected to the organic light-emitting diode OLED may not be located at the transmissive region TA (e.g., not located in or on the transmissive region TA). Some signal lines PL, DL, SL, and EL (e.g., see [reference needed]) are connected to the auxiliary pixel Pa located at (e.g., located in or on the pixel region) to supply signals to it. Figure 3 The signal lines PL, DL, SL, and EL can be positioned across the transmission region TA to increase the transmittance of the transmission region TA. Even in this case, in order to increase the transmittance of the transmission region TA, the signal lines PL, DL, SL, and EL can extend around the central portion (e.g., the central region) of the transmission region TA (e.g., they can be arranged in a row around the central portion of the transmission region TA) and can be arranged to be biased on one side of the transmission region TA.

[0094] In an embodiment, a metal layer may be disposed on the substrate 100 to correspond to the pixel group PG of the component region CA. The metal layer may be disposed below (e.g., under or beneath) the auxiliary pixel Pa and may be positioned, for example, between the thin-film transistor TFT of the auxiliary pixel Pa and the substrate 100. The metal layer may block or substantially block incident pixel circuitry PC emitted from the electronic element 20 onto the auxiliary pixel Pa (e.g., see...). Figure 5A and Figure 5B External light. Because a constant or substantially constant voltage or signal can be applied to the metal layer, damage to the pixel circuit PC due to electrostatic discharge can be prevented or substantially prevented. Multiple metal layers can be configured within the component region CA (e.g., internally). Depending on the display device 1 or application, the metal layers can each receive different voltages.

[0095] Figure 4B and Figure 4C The display unit DU shown can be repeatedly arranged at component region CA (e.g., arranged in component region CA or arranged on component region CA). In this case, when Figure 4B and Figure 4CWhen display units DU are repeatedly arranged in component region CA (e.g., arranged in component region CA or arranged on component region CA), the display units DU at the central portion of component region CA (e.g., in the central portion of component region CA or on the central portion of component region CA) may have the same or substantially the same (or similar) structure as each other, but may have a different structure than the display units DU at the edge portions of component region CA. In other words, in Figure 4B In the display unit DU, the pixel group PG of the component region CA can be adjacent to (e.g., can be close to) the main pixel Pm at the display region DA (e.g., in the display region DA or on the display region DA). On the other hand, in Figure 4C In the display unit DU, because the transmissive region TA surrounds the pixel group PG (e.g., around the periphery of the pixel group PG), the transmissive region TA can be positioned at the edge portion of the component region CA. In this case, the main pixel Pm can surround the outside of the transmissive region TA (e.g., around the periphery of the transmissive region TA). In embodiments, because the wiring WL can be arranged at the transmissive region TA at the edge portion of the component region CA (e.g., in or on the transmissive region TA), the resolution of the component region CA can be maintained or substantially maintained, and the non-display area between the component region CA and the display region DA can be minimized or reduced.

[0096] Figure 5A and Figure 5B It is an equivalent circuit diagram that can be included in the main pixel Pm and / or auxiliary pixel Pa in the display panel 10 according to the embodiment.

[0097] Reference Figure 5A Each of the main pixel Pm and / or auxiliary pixel Pa includes a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC. The pixel circuit PC can be connected to a scan line SL and a data line DL.

[0098] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The storage capacitor Cst can refer to the main storage capacitor Cst or the auxiliary storage capacitor Cst' (see...). Figure 6 The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and can be configured to transmit the data signal Dm input through the data line DL to the driving thin-film transistor T1 in response to the scan signal Sn input through the scan line SL.

[0099] The storage capacitor Cst is connected to the switching thin-film transistor T2 and the drive voltage line PL, and can be configured to store a voltage corresponding to the difference between the voltage delivered from the switching thin-film transistor T2 and the first power voltage ELVDD (e.g., the drive voltage) supplied to the drive voltage line PL.

[0100] A driving thin-film transistor T1 is connected to a driving voltage line PL and a storage capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) in response to the voltage stored in the storage capacitor Cst. The OLED can emit light with a desired or suitable brightness (e.g., a predetermined brightness) depending on the driving current.

[0101] Despite Figure 5A The pixel circuit PC shown includes two thin-film transistors and a storage capacitor, but this disclosure is not limited thereto. For example, as Figure 5B As shown, the pixel circuit PC can include seven thin-film transistors and a storage capacitor. Furthermore, although in Figure 5A The image shows a pixel circuit PC including a storage capacitor, but this disclosure is not limited thereto; the pixel circuit PC may include two or more storage capacitors.

[0102] Reference Figure 5B Each of the main pixel Pm and / or auxiliary pixel Pa includes a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC. The pixel circuit PC may include multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7 and a storage capacitor Cst. The thin-film transistors T1, T2, T3, T4, T5, T6, and T7 and the storage capacitor Cst may be connected to signal lines SL, SL-1, EL, and DL, initialization voltage line VL, and drive voltage line PL.

[0103] Despite Figure 5B The diagram illustrates that each of the primary pixel Pm and / or auxiliary pixel Pa is connected to signal lines SL, SL-1, EL and DL, initialization voltage line VL, and drive voltage line PL, but this disclosure is not limited thereto. For example, in another embodiment, at least one of the signal lines SL, SL-1, EL and DL, initialization voltage line VL, and drive voltage line PL may be shared by pixels that are adjacent to each other (e.g., neighboring).

[0104] Signal lines SL, SL-1, EL, and DL include a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL. The scan line SL can be configured to transmit a scan signal Sn, and the previous scan line SL-1 can be configured to transmit the previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7. The emission control line EL can be configured to transmit an emission control signal En to the operation control thin-film transistor T5 and the emission control thin-film transistor T6. The data line DL can be configured to transmit a data signal Dm and can cross the scan line SL. The drive voltage line PL can be configured to transmit a drive voltage ELVDD to the drive thin-film transistor T1, and the initialization voltage line VL can be configured to transmit an initialization voltage Vint used to initialize the drive thin-film transistor T1 and the pixel electrodes of the organic light-emitting diode (OLED).

[0105] The driving gate electrode G1 of the driving thin-film transistor T1 is connected to the bottom electrode Cst1 of the storage capacitor Cst. The bottom electrode Cst1 can refer to either the first bottom electrode CE1 or the second bottom electrode CE1' (see...). Figure 6 The driving source electrode S1 of the driving thin-film transistor T1 is connected to the driving voltage line PL via the operation control thin-film transistor T5. The driving drain electrode D1 of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 is configured to receive the data signal Dm according to (e.g., depending on) the switching operation of the switching thin-film transistor T2, and to drive the driving current I... OLED Supply to organic light-emitting diodes (OLEDs).

[0106] The switching gate electrode G2 of the switching thin-film transistor T2 is connected to the scan line SL, and the switching source electrode S2 of the switching thin-film transistor T2 is connected to the data line DL. The switching drain electrode D2 of the switching thin-film transistor T2 is connected to the driving source electrode S1 of the driving thin-film transistor T1, and is connected to the driving voltage line PL via the operation control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and is configured to perform a switching operation that transmits the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin-film transistor T1.

[0107] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1, and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the bottom electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn transmitted via the scan line SL, and is configured to diode-connect the driving thin-film transistor T1 by electrically connecting the driving gate electrode G1 of the driving thin-film transistor T1 to the driving drain electrode D1.

[0108] The first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the previous scan line SL-1. The first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin-film transistor T7 and the initialization voltage line VL. The first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the bottom electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the driving gate electrode G1 of the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and is configured to perform an initialization operation that initializes the voltage of the driving gate electrode G1 of the driving thin-film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin-film transistor T1.

[0109] The operation control gate electrode G5 of the operating control thin-film transistor T5 is connected to the emitter control line EL, and the operation control source electrode S5 of the operating control thin-film transistor T5 is connected to the drive voltage line PL. The operation control drain electrode D5 of the operating control thin-film transistor T5 is connected to the drive source electrode S1 of the driving thin-film transistor T1 and the switch drain electrode D2 of the switching thin-film transistor T2.

[0110] The emission control gate electrode G6 of the emission control thin-film transistor T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control thin-film transistor T6 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and the compensation source electrode S3 of the compensation thin-film transistor T3. The emission control drain electrode D6 of the emission control thin-film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin-film transistor T7 and the pixel electrode of the organic light-emitting diode (OLED).

[0111] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 are concurrently (e.g., simultaneously) turned on in response to the emission control signal En transmitted via the emission control line EL, to allow the drive voltage ELVDD to be transmitted to the organic light-emitting diode OLED, and thus, to allow the drive current I... OLED It flows through an organic light-emitting diode (OLED).

[0112] The second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization thin-film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode (OLED). The second initialization drain electrode D7 of the second initialization thin-film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 and is configured to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0113] although Figure 5B The illustration shows a first initialization thin-film transistor T4 and a second initialization thin-film transistor T7 connected to a previous scan line SL-1, but this disclosure is not limited thereto. For example, in an embodiment, the first initialization thin-film transistor T4 may be connected to the previous scan line SL-1 and can be driven in response to a previous scan signal Sn-1, and the second initialization thin-film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and can be driven in response to a signal transmitted through said separate signal line.

[0114] The top electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light-emitting diode (OLED) is connected to the common voltage ELVSS. The top electrode Cst2 can refer to either the first top electrode CE2 or the second top electrode CE2' (see...). Figure 6 Therefore, an organic light-emitting diode (OLED) can be configured to receive a driving current I from a driving thin-film transistor T1. OLED It can also emit light to display images.

[0115] Despite Figure 5B The diagram shows that each of the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 has dual gate electrodes, but this disclosure is not limited thereto, and at least one of the compensation thin-film transistor T3 and the first initialization thin-film transistor T4 may have a single gate electrode (e.g., a single gate electrode).

[0116] Figure 6 This is a cross-sectional view of the pixel circuit PC of the pixel according to an embodiment. Figure 6 It is along Figure 4A The line I-I' and Figure 4C The sectional view taken from line II-II'. Figure 6 The structures of the thin-film transistors TFT and TFT' shown are similar to Figure 5B The structures of the driving thin-film transistor T1 shown are the same or substantially the same.

[0117] Reference Figure 6 The display device 1 according to the embodiment includes a display area DA and a component area CA. A main pixel Pm is arranged in the display area DA (e.g., arranged in or on the display area DA), and an auxiliary pixel Pa and a transmissive area TA are arranged in the component area CA (e.g., arranged in or on the component area CA).

[0118] The main pixel Pm may include a main thin-film transistor (TFT), a main storage capacitor Cst, and a main organic light-emitting diode (OLED). The auxiliary pixel Pa may include an auxiliary thin-film transistor (TFT'), an auxiliary storage capacitor Cst', and an auxiliary organic light-emitting diode (OLED'). The transmission region TA may include a transmission aperture (e.g., a transmission opening) TAH corresponding to the transmission region TA.

[0119] The first metal layer BSM1 can be disposed below (e.g., below or beneath) the main thin-film transistor TFT of the main pixel Pm, such that the first metal layer BSM1 is stacked with the main thin-film transistor TFT. The second metal layer BSM2 can be disposed below (e.g., below or beneath) the auxiliary thin-film transistor TFT' of the auxiliary pixel Pa, such that the second metal layer BSM2 is stacked with the auxiliary thin-film transistor TFT'. However, this disclosure is not limited thereto. For example, in an embodiment, with... Figure 6 The embodiment shown is different, and the first metal layer BSM1 stacked with the main thin-film transistor TFT can be omitted.

[0120] In the following description, the structure in which the elements included in the display device 1 are stacked is described according to an embodiment.

[0121] The substrate 100 may include a polymer resin. For example, the substrate 100 may include a matrix layer and an inorganic layer, the matrix layer of which may include a polymer resin. In an embodiment, the substrate 100 may include a first matrix layer 101, a first inorganic layer 102, a second matrix layer 103, and a second inorganic layer 104 that are sequentially stacked on top of each other.

[0122] Each of the first matrix layer 101 and the second matrix layer 103 may include a polymer resin. For example, the first matrix layer 101 and the second matrix layer 103 may include a polymer resin (such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and / or cellulose acetate propionate (CAP)). The polymer resin may be transparent or substantially transparent.

[0123] The first inorganic layer 102 and the second inorganic layer 104 may be inorganic layers for preventing or substantially preventing the penetration of external foreign matter, and may include a single-layer structure or a multi-layer structure, wherein the single-layer structure or multi-layer structure comprises inorganic materials, such as silicon nitride (SiN). x ) and / or silicon dioxide (SiO2) x For example, ).

[0124] A buffer layer 111 may be positioned on the substrate 100. The buffer layer 111 may reduce or block the penetration of foreign matter, moisture, and / or outside air from below (e.g., below or beneath) the substrate 100, and may provide a flat or substantially flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials (such as oxides or nitrides), organic materials, or organic / inorganic composite materials, and may comprise a single-layer or multi-layer structure comprising inorganic and / or organic materials.

[0125] exist Figure 6 In the illustrated embodiment, the first metal layer BSM1 and the second metal layer BSM2 may be disposed between the substrate 100 and the buffer layer 111, for example, between the second inorganic layer 104 and the buffer layer 111. However, this disclosure is not limited thereto, and in another embodiment, the first metal layer BSM1 and the second metal layer BSM2 may be disposed below (e.g., beneath) the second inorganic layer 104. For example, the first metal layer BSM1 and the second metal layer BSM2 may be disposed between the second substrate layer 103 and the second inorganic layer 104. In another embodiment, at least one of the first metal layer BSM1 and the second metal layer BSM2 may be disposed in a layer different from or different from the layers described above (e.g., disposed in or on a layer different from or different from the layers described above).

[0126] The second metal layer BSM2 may be disposed below (e.g., below or beneath) the auxiliary pixel Pa to prevent or substantially prevent damage to the auxiliary thin film transistor TFT' disposed at the auxiliary pixel Pa (e.g., disposed in or on the auxiliary pixel Pa), and / or to prevent or substantially prevent the characteristics of the auxiliary thin film transistor TFT' from being degraded.

[0127] The first metal layer BSM1 may be disposed below (e.g., beneath or under) the main pixel Pm to prevent or substantially prevent damage to the main thin-film transistor TFT disposed at the main pixel Pm (e.g., disposed in or on the main pixel Pm), and / or to prevent or substantially prevent degradation of the characteristics of the main thin-film transistor TFT. However, this disclosure is not limited thereto. For example, in embodiments, the first metal layer BSM1 may be omitted depending on (e.g., depending on) the situation or application of the display device 1.

[0128] The first metal layer BSM1 can be connected to the second metal layer BSM2 via a conductive line CL and a contact hole. The conductive line CL can be arranged on a different layer than the layer where the first metal layer BSM1 and the second metal layer BSM2 are disposed (e.g., in a different layer or on a different layer). The first metal layer BSM1 and the second metal layer BSM2 can receive a constant or substantially constant voltage or signal from the conductive line CL. For example, the first metal layer BSM1 and the second metal layer BSM2 can receive a drive voltage ELVDD or a scan signal Sn from the conductive line CL. Because the first metal layer BSM1 and the second metal layer BSM2 can receive a constant or substantially constant voltage or signal, the probability of electrostatic discharge that may occur can be reduced (e.g., significantly reduced). However, this disclosure is not limited thereto, and various modifications can be made as those skilled in the art will know. For example, in another embodiment, one or both of the first metal layer BSM1 and the second metal layer BSM2 may not receive electrical signals. In another example, in an embodiment, at least one of the first metal layer BSM1 and the second metal layer BSM2 may be electrically levitated. In yet another example, in an embodiment, one of the first metal layer BSM1 and the second metal layer BSM2 may be electrically levitated, and the other of the first metal layer BSM1 and the second metal layer BSM2 may receive electrical signals.

[0129] The first metal layer BSM1 and the second metal layer BSM2 may comprise at least one material selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first metal layer BSM1 and the second metal layer BSM2 may comprise a single-layer structure or a multi-layer structure containing one or more of the materials described above.

[0130] The main thin-film transistor (TFT) and the auxiliary thin-film transistor (TFT') can be disposed on the buffer layer 111. The main TFT includes a first semiconductor layer AL1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary TFT' includes a second semiconductor layer AL2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main TFT can be connected to the main organic light-emitting diode (OLED) at the display region DA (e.g., in or on the display region DA) and can drive the main OLED. The auxiliary TFT' can be connected to the auxiliary OLED' at the component region CA (e.g., in or on the component region CA) and can drive the auxiliary OLED'.

[0131] The first semiconductor layer AL1 and the second semiconductor layer AL2 can be disposed on the buffer layer 111 and can include, for example, polycrystalline silicon. In another embodiment, the first semiconductor layer AL1 and the second semiconductor layer AL2 can include, for example, amorphous silicon. In another embodiment, the first semiconductor layer AL1 and the second semiconductor layer AL2 can include, for example, oxides, which include at least one from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Each of the first semiconductor layer AL1 and the second semiconductor layer AL2 can include a channel region, a source region, and a drain region. The source region and the drain region can be doped with impurities.

[0132] A first semiconductor layer AL1 may be stacked with a first metal layer BSM1, with a buffer layer 111 between the first semiconductor layer AL1 and the first metal layer BSM1. In an embodiment, the width of the first semiconductor layer AL1 (e.g., the width in the x-axis direction) may be smaller than the width of the first metal layer BSM1 (e.g., the width in the x-axis direction). Therefore, when viewed from a direction perpendicular to or substantially perpendicular to the substrate 100 (e.g., when viewed in a plan view), the entire first semiconductor layer AL1 may be stacked with the first metal layer BSM1.

[0133] The second semiconductor layer AL2 may be stacked with the second metal layer BSM2, and a buffer layer 111 is provided between the second semiconductor layer AL2 and the second metal layer BSM2. In an embodiment, the width of the second semiconductor layer AL2 (e.g., the width in the x-axis direction) may be smaller than the width of the second metal layer BSM2 (e.g., the width in the x-axis direction). Therefore, when viewed from a direction perpendicular to the substrate 100 (e.g., when viewed in a plan view), the entire second semiconductor layer AL2 may be stacked with the second metal layer BSM2.

[0134] The first gate insulating layer 112 may cover the first semiconductor layer AL1 and the second semiconductor layer AL2. The first gate insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x Examples include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). The first gate insulating layer 112 may include a single-layer structure or a multilayer structure comprising one or more of the inorganic insulating materials mentioned above.

[0135] The first gate electrode G1 and the second gate electrode G2 may be disposed on the first gate insulating layer 112 to correspond to the first semiconductor layer AL1 and the second semiconductor layer AL2, respectively. The first gate electrode G1 and the second gate electrode G2 may include a single-layer structure or a multi-layer structure comprising at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). For example, in an embodiment, the first gate electrode G1 and the second gate electrode G2 may include a single layer of Mo.

[0136] The second gate insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x Examples include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). The second gate insulating layer 113 may include a single-layer structure or a multi-layer structure containing one or more inorganic insulating materials.

[0137] The first top electrode CE2 of the main storage capacitor Cst and the second top electrode CE2' of the auxiliary storage capacitor Cst' can be arranged on the second gate insulating layer 113.

[0138] The first top electrode CE2 may be stacked on top of the first gate electrode G1 below it at the display area DA (e.g., in or on the display area DA). For example, the first gate electrode G1 and the first top electrode CE2 may be stacked on top of each other, with a second gate insulating layer 113 between them. The first gate electrode G1 and the first top electrode CE2 may define (e.g., may constitute) a main storage capacitor Cst. For example, the first gate electrode G1 may serve as the first bottom electrode CE1 of the main storage capacitor Cst.

[0139] The second top electrode CE2' may be stacked with the second gate electrode G2 below it at the component region CA (e.g., in or on the component region CA). For example, the second gate electrode G2 and the second top electrode CE2' may be stacked on top of each other, with a second gate insulating layer 113 between the second gate electrode G2 and the second top electrode CE2'. The second gate electrode G2 and the second top electrode CE2' may define (e.g., may constitute) an auxiliary storage capacitor Cst'. For example, the second gate electrode G2 may serve as the second bottom electrode CE1' of the auxiliary storage capacitor Cst'.

[0140] The first top electrode CE2 and the second top electrode CE2' may comprise at least one material selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first top electrode CE2 and the second top electrode CE2' may comprise a single-layer or multi-layer structure containing one or more of the materials described above.

[0141] Interlayer insulating layer 115 may cover the first top electrode CE2 and the second top electrode CE2'. Interlayer insulating layer 115 may include, for example, silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2).

[0142] The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 can be collectively referred to as the inorganic insulating layer IL. When the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may include a first aperture H1 corresponding to the transmission region TA. The first aperture H1 may expose the top surface of the buffer layer 111 or the top surface of the substrate 100. The first aperture H1 may include openings of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 corresponding to the transmission region TA, and the openings may be stacked on top of each other. The openings may be formed during their respective individual processes, or they may be formed concurrently (e.g., simultaneously) with each other during the same process. In the case where the openings are formed during the individual process, a step difference may be formed on the inner surface of the first aperture H1.

[0143] In another embodiment, the inorganic insulating layer IL may include a groove instead of the first hole H1 that exposes the buffer layer 111.

[0144] In another embodiment, the inorganic insulating layer IL may not include the first hole H1 corresponding to the transmission region TA. In this case, since the inorganic insulating layer IL can typically include an inorganic insulating material with high transmittance (e.g., excellent transmittance), even without providing the first hole H1 corresponding to the transmission region TA, it is possible to achieve the effect that can be achieved by component 20 (e.g., see...) Figure 2 The transmittance of emitted and / or received light.

[0145] Source electrodes S1 and S2, and drain electrodes D1 and D2, can be disposed on interlayer insulating layer 115. Source electrodes S1 and S2, and drain electrodes D1 and D2 can comprise conductive materials including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti). Source electrodes S1 and S2, and drain electrodes D1 and D2 can comprise single-layer or multi-layer structures comprising one or more of the above materials. For example, in an embodiment, source electrodes S1 and S2, and drain electrodes D1 and D2 can have a Ti / Al / Ti multilayer structure.

[0146] The source electrodes S1 and S2 and the drain electrodes D1 and D2 can be covered by the first planarization layer 117. The first planarization layer 117 may have a flat or substantially flat top surface, such that the first pixel electrode 221 and the second pixel electrode 221' disposed on (e.g., above) the first planarization layer 117 can be formed as flat or substantially flat.

[0147] The second planarization layer 118 can be disposed on the first planarization layer 117. Contact metal layers CM and CM' can be disposed between the first planarization layer 117 and the second planarization layer 118. The contact metal layers CM and CM' can electrically connect the drain electrodes D1 and D2 to the first pixel electrode 221 and the second pixel electrode 221', respectively, through contact holes formed in the first planarization layer 117.

[0148] The first planarization layer 117 and the second planarization layer 118 may comprise a single-layer or multi-layer structure containing, for example, organic or inorganic materials. The first planarization layer 117 and the second planarization layer 118 may comprise, for example, general-purpose polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), and / or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, and / or combinations thereof (e.g., blends). The first planarization layer 117 and the second planarization layer 118 may comprise, for example, silicon oxide (SiO2) or silicon nitride (SiN). x The materials used are silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO2). After forming the first planarization layer 117 and the second planarization layer 118, chemical mechanical polishing can be performed to provide a flat or substantially flat top surface.

[0149] The first planarization layer 117 and the second planarization layer 118 may include a second aperture (e.g., a second opening) H2 corresponding to the transmission region TA. The second aperture H2 may be stacked with the first aperture H1. Although in Figure 6 The diagram shows that the second hole H2 is larger than the first hole H1 (e.g., the second hole H2 has a width or a circumference larger than the width or circumference of the first hole H1), but this disclosure is not limited thereto. For example, in an embodiment, the first planarization layer 117 and the second planarization layer 118 may cover the edge (e.g., the inner surface) of the first hole H1 in the inorganic insulating layer IL. Therefore, in this case, the width of the second hole H2 (e.g., the width in the x-axis direction) may be smaller than the width of the first hole H1 (e.g., the width in the x-axis direction).

[0150] The first planarization layer 117 and the second planarization layer 118 may include an opening that exposes one of the first source electrode S1 and the first drain electrode D1 of the main thin-film transistor TFT. The first pixel electrode 221 may be electrically connected to the main thin-film transistor TFT through the opening. For example, the first pixel electrode 221 may be electrically connected to the main thin-film transistor TFT by contacting the first source electrode S1 or the first drain electrode D1 through the opening (or by contacting a contact metal layer CM disposed in the opening and located between the first pixel electrode 221 and the first source electrode S1 or the first drain electrode D1).

[0151] Furthermore, the first planarization layer 117 and the second planarization layer 118 may include an opening that exposes one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin-film transistor TFT'. The second pixel electrode 221' can be electrically connected to the auxiliary thin-film transistor TFT' through the opening. For example, the second pixel electrode 221' can be electrically connected to the auxiliary thin-film transistor TFT' through the opening by contacting the second source electrode S2 or the second drain electrode D2 (or by contacting the contact metal layer CM' disposed in the opening and located between the second pixel electrode 221' and the second source electrode S2 or the second drain electrode D2).

[0152] The first pixel electrode 221 and the second pixel electrode 221' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In another embodiment, the first pixel electrode 221 and the second pixel electrode 221' may include a reflective layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or combinations thereof (e.g., mixtures). In another embodiment, the first pixel electrode 221 and the second pixel electrode 221' may also include, for example, a layer comprising ITO, IZO, ZnO, and / or In2O3 on or below (e.g., under) the reflective layer. In another embodiment, the first pixel electrode 221 and the second pixel electrode 221' may have an ITO / Ag / ITO stacked structure.

[0153] The pixel defining layer 119 may cover the edges of the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 includes a first opening OP1 and a second opening OP2 that are respectively superimposed on the first pixel electrode 221 and the second pixel electrode 221' and define pixel regions. The pixel defining layer 119 can prevent or substantially prevent the occurrence (e.g., formation) of electric arcs at the edges of the first pixel electrode 221 and the second pixel electrode 221' by increasing the distance between the edges of the first pixel electrode 221 and the second pixel electrode 221' and the counter electrode 223 disposed on the first pixel electrode 221 and the second pixel electrode 221' (e.g., disposed above the first pixel electrode 221 and the second pixel electrode 221'). The pixel defining layer 119 may include at least one of polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin. The pixel defining layer 119 may be formed by any suitable method (e.g., spin coating).

[0154] The pixel defining layer 119 may include a third aperture H3 positioned at the transmissive region TA (e.g., positioned in or on the transmissive region TA). The third aperture H3 may be stacked with the first aperture H1 and the second aperture H2. Because the first aperture H1, the second aperture H2, and the third aperture H3 are formed, the light transmittance of the transmissive region TA can be improved. The counter electrode 223, described in more detail below, may be disposed on the inner walls of the first aperture H1, the second aperture H2, and the third aperture H3 (e.g., disposed on the inner walls of the first aperture H1, the second aperture H2, and the third aperture H3).

[0155] The first functional layer 222a may cover the pixel defining layer 119. The first functional layer 222a may include a single-layer structure or a multi-layer structure. In one embodiment, the first functional layer 222a may include a hole transport layer (HTL) that may have a single-layer structure. In another embodiment, the first functional layer 222a may include a hole injection layer (HIL) and an HTL. The first functional layer 222a may be configured as a single unit to correspond to the primary pixel Pm and the secondary pixel Pa at the display area DA and the component area CA (e.g., in or on the display area DA and the component area CA).

[0156] The first emitting layer 222b and the second emitting layer 222b' can be disposed on the first functional layer 222a. The first emitting layer 222b and the second emitting layer 222b' can correspond to the first pixel electrode 221 and the second pixel electrode 221', respectively. The first emitting layer 222b and the second emitting layer 222b' can include, for example, polymer materials or low molecular weight materials, and can emit red light, green light, blue light or white light.

[0157] The second functional layer 222c may be formed on the first emission layer 222b and the second emission layer 222b'. The second functional layer 222c may include a single-layer structure or a multi-layer structure. For example, the second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 222c may be configured as a single unit to correspond to the primary pixel Pm and the auxiliary pixel Pa at the display area DA and the component area CA (e.g., in or on the display area DA and the component area CA). In another embodiment, the first functional layer 222a and / or the second functional layer 222c may be omitted.

[0158] Counter electrode 223 may be disposed on the second functional layer 222c. Counter electrode 223 may comprise a conductive material having a low work function. For example, counter electrode 223 may comprise a (semi-)transparent layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or combinations thereof (e.g., alloys). In embodiments, counter electrode 223 may also comprise a layer comprising, for example, ITO, IZO, ZnO, or In2O3, which may be disposed on and / or beneath a (semi-)transparent layer comprising one or more of the materials mentioned above. Counter electrode 223 may be configured integrally to correspond to the main pixel Pm and auxiliary pixel Pa at the display area DA and component area CA (e.g., in or on the display area DA and component area CA).

[0159] The layer formed at the display region DA (e.g., formed in or on the display region DA) from the first pixel electrode 221 to the counter electrode 223 can define (e.g., constitute) a main organic light-emitting diode (OLED). The layer formed at the component region CA (e.g., formed in or on the component region CA) from the second pixel electrode 221' to the counter electrode 223 can define (e.g., constitute) an auxiliary organic light-emitting diode (OLED').

[0160] A capping layer 250 may be formed on the counter electrode 223. In one embodiment, the capping layer 250 may include, for example, LiF. In another embodiment, the capping layer 250 may include an inorganic insulating material (such as silicon nitride) and / or an organic insulating material. However, this disclosure is not limited thereto, and in another embodiment, the capping layer 250 may be omitted.

[0161] exist Figure 6In the illustrated embodiment, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 250 may all include a transmission aperture TAH corresponding to the transmission region TA. In other words, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 250 may all include an opening corresponding to the transmission region TA. In the embodiment, the width (e.g., the width in the x-axis direction) of the opening defining (e.g., constituting) the transmission aperture TAH may be the same as or substantially the same as each other. For example, the width (e.g., the width in the x-axis direction) of the opening of the counter electrode 223 may be equal to or substantially equal to the width (e.g., the width in the x-axis direction) of the transmission aperture TAH.

[0162] As used herein, the transmission aperture TAH corresponding to the transmission region TA can refer to a case where the transmission aperture TAH overlaps with the transmission region TA. In this case, the area of ​​the transmission aperture TAH can be smaller than the area of ​​the first aperture H1 formed in the inorganic insulating layer IL. For example, as... Figure 6 As shown, the width Wt of the transmission aperture TAH can be smaller than the width W1 of the first aperture H1. Here, the areas of the transmission aperture TAH and the first aperture H1 can be defined as the areas of the openings with the minimum area.

[0163] Because of the transmission aperture TAH, a portion of the counter electrode 223 can be removed from the transmission region TA, and the transmittance of the transmission region TA can be improved (e.g., significantly improved). For example, the counter electrode 223 located at the transmission region TA (e.g., located in or on the transmission region TA) can be formed by removing the portion of the counter electrode 223 corresponding to the transmission aperture TAH using a laser lift-off process, or by a fine metal mask (FMM) patterning process. In the following description, the counter electrode 223 can be formed at the component region CA (e.g., in or on the component region CA) using an FMM patterning process. Figure 6 The embodiment shown.

[0164] The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED) can be sealed by a thin-film encapsulation layer 300. The thin-film encapsulation layer 300 can be disposed on the capping layer 250. The thin-film encapsulation layer 300 can prevent or substantially prevent external moisture and / or foreign matter from penetrating into the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED).

[0165] The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, such as Figure 6As shown, the thin-film encapsulation layer 300 may have a structure in which a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 are stacked on top of each other. However, this disclosure is not limited thereto, and in another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order (e.g., stacking sequence) may be modified in various ways.

[0166] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each comprise at least one inorganic insulating material selected from, for example, alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed using, for example, chemical vapor deposition (CVD). The organic encapsulation layer 320 may comprise, for example, a polymeric material. The polymeric material may comprise, for example, silicone resins, acrylic resins, epoxy resins, polyimides, and / or polyethylene.

[0167] The first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 can be integrally formed to cover the display area DA and the component area CA. Therefore, the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 can be arranged within the transmission aperture TAH (e.g., inside).

[0168] In another embodiment, the organic encapsulation layer 320 may be integrally formed to cover the display region DA and the component region CA, and the organic encapsulation layer 320 may not be disposed at the transmissive region TA (e.g., not disposed in or on the transmissive region TA). In other words, the organic encapsulation layer 320 may include an opening corresponding to the transmissive region TA. In this case, the first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 within (e.g., inside) the transmissive aperture TAH.

[0169] Figure 7 This is a plan view showing the arrangement of pixels and wiring in the display device 1 according to the embodiment. Figure 8 yes Figure 7 A magnified plan view of a local area. Figure 9 It is along Figure 8 A sectional view of a local area intercepted by line III-III'. For example, Figure 7 The component area CA and a portion of the adjacent display area DA are shown.

[0170] Reference Figure 7Multiple pixels P can be arranged in the display area DA and the component area CA (e.g., arranged in or on the display area DA and the component area CA). Multiple pixels P can be arranged in the first direction DR1 and the second direction DR2. Multiple main pixels Pm from the multiple pixels P can be arranged continuously in the display area DA (e.g., arranged in or on the display area DA).

[0171] In addition to the transmission region TA, multiple auxiliary pixels Pa from multiple pixels P can be arranged at the component region CA (e.g., arranged in or on the component region CA) (e.g., and not arranged at the transmission region TA). In other words, at least a portion of the area where the multiple auxiliary pixels Pa are not arranged (e.g., not arranged therein or not arranged on) can be defined as the transmission region TA. The multiple auxiliary pixels Pa can be arranged at a first region A1 of the component region CA (e.g., arranged in or on the first region A1 of the component region CA). In this case, the multiple auxiliary pixels Pa may not be arranged at a second region A2 of the component region CA surrounding the first region A1 (e.g., around the periphery of the first region A1) (e.g., in or on the second region A2). Although Figure 7 This illustrates a continuous arrangement (e.g., clustered and repeated) of components at region CA. Figure 4C The present disclosure is not limited to the construction of four display units DU. In another embodiment, more than four display units DU can be arranged continuously at component region CA (e.g., they can be clustered and repeated at component region CA).

[0172] Multiple auxiliary pixels Pa at component region CA (e.g., within or on component region CA) can form a group and can define (e.g., constitute) a pixel group PG. Pixel group PG can be set as multiple pixel groups. In an embodiment, as... Figure 7 As shown, a pixel group PG (e.g., each in a pixel group PG) may include eight auxiliary pixels Pa, but this disclosure is not limited thereto.

[0173] Multiple second wirings WL2 extending along the first direction DR1 can be arranged at the display area DA and the component area CA (e.g., arranged in or on the display area DA and component area CA). The multiple second wirings WL2 can be connected to multiple auxiliary pixels Pa respectively. Furthermore, the multiple second wirings WL2 can extend along the first direction DR1 and can be connected to multiple main pixels Pm arranged in the same column as the columns of the multiple auxiliary pixels Pa (e.g., arranged in or on the same column as the columns of the multiple auxiliary pixels Pa). In this case, when the element is referred to as being connected to a pixel, it can be connected to the pixel circuit PC of the pixel to supply signals or power to the pixel. In embodiments, the multiple second wirings WL2 can correspond to (e.g., may be) data lines DL or drive voltage lines PL.

[0174] Multiple second wirings WL2 may extend along the first direction DR1 and may extend across (e.g., through) the transmission region TA. In other words, at least some of the multiple second wirings WL2 may overlap with the transmission region TA. In the region of the transmission region TA where the multiple second wirings WL2 overlap (e.g., in the region of the transmission region TA where the multiple second wirings WL2 overlap or on the region of the transmission region TA where the multiple second wirings WL2 overlap), the multiple second wirings WL2 may be arranged on one side of the transmission region TA (e.g., arranged to be biased on one side of the transmission region TA). In this case, although the transmittance of the region of the transmission region TA where the multiple second wirings WL2 overlap with the transmission region TA may be less than the transmittance of other regions of the transmission region TA (e.g., other regions of the transmission region TA where the multiple second wirings WL2 do not overlap with the transmission region TA), high transmittance can be ensured in other regions of the transmission region TA.

[0175] Multiple first wirings WL1 extending along the first direction DR1 can be arranged at a second region A2 of the display region DA and the component region CA (e.g., arranged in or on the second region A2 of the display region DA and the component region CA). The multiple first wirings WL1 can be connected to multiple main pixels Pm respectively. Unlike the multiple second wirings WL2, the multiple first wirings WL1 may not be connected to multiple auxiliary pixels Pa. In other words, the auxiliary pixels Pa may not be arranged at the component region CA (e.g., in or on the same column) along the first direction DR1 where the multiple first wirings WL1 extend (e.g., along or on them). For example, a transmissive region TA can be arranged at the component region CA (e.g., in or on the same column) along the same column where the first wirings WL1 extend (e.g., along or on them).

[0176] exist Figure 7 In the illustrated embodiment, the plurality of first wirings WL1 may include an extension portion WL-C and a bypass portion WL-R. The extension portion WL-C may be arranged at the display area DA (e.g., arranged in or on the display area DA), and the bypass portion WL-R may be arranged at the second area A2 of the component area CA (e.g., arranged in or on the second area A2 of the component area CA). In other words, at the component area CA, the plurality of first wirings WL1 may be arranged to extend across (e.g., through) the second area A2 and to circle around the first area A1 of the component area CA. As described above, because the transmission area TA may be arranged at the first area A1 (e.g., arranged in or on the first area A1), the transmittance of the transmission area TA may be reduced due to the plurality of first wirings WL1 when the plurality of first wirings WL1 are arranged to extend across (e.g., through) the first area A1 without the bypass portion WL-R. Furthermore, since the first region A1 can be the central part of the component region CA, and the first region A1 can be the region in which the component is arranged or substantially arranged and can affect (e.g., can directly affect) the light transmittance for the operation of the component, ensuring the light transmittance of the first region A1 may be desirable (e.g., may be very important).

[0177] In a display device 1 according to one or more example embodiments, a plurality of first wirings WL1 may be arranged at a second region A2 (e.g., arranged in or on the second region A2) to bypass the edge (e.g., periphery) of the component region CA, and the plurality of first wirings WL1 may connect a plurality of main pixels Pm arranged in a first direction DR1 having the component region CA between them. In this case, signals or power can be transmitted (e.g., can be effectively transmitted) to the plurality of main pixels Pm arranged at the display region DA (e.g., arranged in or on the display region DA) without reducing or significantly reducing the light transmittance of the transmissive region TA of the component region CA.

[0178] like Figure 7 As shown, multiple second wirings WL2 can extend along a first direction DR1 and can be positioned at a second region A2 (e.g., positioned within or on the second region A2) (e.g., extending across the second region A2). In this case, to allow multiple first wirings WL1 to circumnavigate the second region A2 as described above, the multiple first wirings WL1 can be electrically insulated from some of the multiple second wirings WL2 that extend across the second region A2 (e.g., through the second region A2). Therefore, the extension portions WL-C and the bypass portions WL-R of the multiple first wirings WL1 can be arranged in different layers (e.g., arranged in or on different layers) and can be electrically connected to each other through contact holes CNT. For example, as Figure 7 As shown, the contact hole CNT can be located at the second region A2 (e.g., located in or on the second region A2).

[0179] Figure 8 yes Figure 7 An enlarged plan view of the lower left portion of component area CA.

[0180] Multiple pixel groups PG1, PG2, and PG3 can be arranged in the first region A1 of the component region CA and the display region DA (e.g., arranged in the first region A1 of the component region CA and the display region DA or arranged on the first region A1 of the component region CA and the display region DA). Each of the multiple pixel groups PG1, PG2, and PG3 can include multiple primary pixels Pm1 and Pm2 or multiple auxiliary pixels Pa.

[0181] although Figure 8The diagram illustrates a structure in which multiple main pixels Pm1 and Pm2 and multiple auxiliary pixels Pa are arranged in a pentile pattern, but this disclosure is not limited thereto. In another embodiment, the arrangement of the multiple main pixels Pm1 and Pm2 may differ from the arrangement of the multiple auxiliary pixels Pa. For example, the multiple main pixels Pm1 and Pm2 may be arranged in a pentile pattern, and the multiple auxiliary pixels Pa may be arranged in a striped pattern. Figure 8 It is shown that each of pixels Pa, Pm1, and Pm2 is defined as Figure 6 The pixel-defined layer 119 has openings OP1 and OP2 with emission regions PE. The emission regions PE can be areas that emit or substantially emit light, and can be set to various suitable shapes (e.g., such as...). Figure 8 (The shape shown).

[0182] although Figure 8 The diagram shows that each of the multiple pixel groups PG1, PG2 and PG3 includes eight pixels Pa, Pm1 and Pm2, but this disclosure is not limited thereto.

[0183] Multiple pixel groups PG1, PG2, and PG3 may include a first pixel group PG1 and a second pixel group PG2 located at display area DA (e.g., in or on display area DA), and a third pixel group PG3 located at component area CA (e.g., in or on component area CA). The first pixel group PG1 at display area DA (e.g., in or on display area DA) may be arranged in the same column (e.g., in the same column or on the same column) as the third pixel group PG3 located at component area CA (e.g., in or on component area CA). In other words, the first pixel group PG1 may be arranged in the same column as the third pixel group PG3. An auxiliary pixel Pa is not located in the same column (e.g., in the same column or on the same column) of component area CA as the second pixel group PG2 located at display area DA (e.g., in or on component area CA). In other words, the auxiliary pixel Pa is not set in the component region CA in the same column as the second pixel group PG2 (e.g., in or on the component region CA).

[0184] Multiple second wirings WL2 extending along the first direction DR1 can be connected to a first pixel group PG1 at the display area DA (e.g., in or on the display area DA) and a third pixel group PG3 at the component area CA (e.g., in or on the component area CA), wherein the first pixel group PG1 and the third pixel group PG3 are arranged in the same column as each other (e.g., in or on the same column as each other). In one embodiment, the multiple second wirings WL2 may include data lines DL. In another embodiment, the multiple second wirings WL2 may include drive voltage lines PL.

[0185] Multiple second wirings WL2 may extend in the first direction DR1 at the display area DA (e.g., in or on the display area DA) and may extend beyond the second area A2 of the component area CA to the first area A1. In this case, some of the multiple second wirings WL2 may be arranged to be biased on one side of the transmission area TA to improve the light transmittance of the transmission area TA.

[0186] Multiple first wirings WL1 extending in the first direction DR1 can be connected to the second pixel group PG2 at the display area DA (e.g., in or on the display area DA). Although in Figure 8 Not shown, but multiple first wirings WL1 can be connected to the fourth pixel group, which is located on the side of the component region CA opposite to the side of the second pixel group PG2, with the component region CA between the fourth pixel group and the second pixel group PG2.

[0187] Multiple first wirings WL1 may extend in a first direction DR1 at the display area DA (e.g., in or on the display area DA) and may circumvent the second area A2. In other words, the multiple first wirings WL1 may not overlap with the first area A1 of the component area CA. As used herein, multiple first wirings WL1 not overlapping with the first area A1 may refer to the case where the multiple first wirings WL1 do not overlap with the transmission area TA of the first area A1. Therefore, in this case, the transmittance of the transmission area TA can be increased (e.g., can be effectively increased).

[0188] Multiple first wirings WL1 may include a first conductive layer CL1 and a second conductive layer CL2 electrically connected to the first conductive layer CL1. An insulating layer may be disposed between the first conductive layer CL1 and the second conductive layer CL2. The first conductive layer CL1 may be electrically connected to the second conductive layer CL2 through contact holes CNT defined in the insulating layer. In an embodiment, the insulating layer may be disposed on the first conductive layer CL1, and the second conductive layer CL2 may be disposed on the insulating layer.

[0189] Reference Figure 9 The first conductive layer CL1 can be defined in an insulating layer (e.g., such as...). Figure 6 The contact hole CNT in the first planarization layer 117 shown is electrically connected to the second conductive layer CL2. Figure 9 The stacked structure can be with Figure 6 The stacking structure corresponds to this.

[0190] In an embodiment, the first conductive layer CL1 may comprise the same or substantially the same material as the source electrodes S1 and S2 and / or drain electrodes D1 and D2 of the thin-film transistors TFT and TFT'. In an embodiment, the second conductive layer CL2 may comprise the same or substantially the same material as the contact metal layers CM and CM'. In this case, the third conductive layer CL3 defining (e.g., constituting) multiple second wirings WL2 may be disposed in the same layer as the first conductive layer CL1 disposed therein (e.g., disposed therein or disposed on therein). In other words, the third conductive layer CL3 may comprise the same or substantially the same material as the first conductive layer CL1.

[0191] In an embodiment, it may be sufficient for the first conductive layer CL1 and the second conductive layer CL2 to be disposed in different layers from each other (e.g., disposed in different layers or disposed on different layers). This is because the second conductive layer CL2 may include a bypass portion WL-R (e.g., see...). Figure 7 It can also be superimposed on other wiring (e.g., second wiring WL2) arranged in the second region A2 (e.g., arranged in or on the second region A2), so that the second conductive layer CL2 can be arranged on a different layer than the layer where other wiring is arranged (e.g., arranged in or on the other layer), such that the second conductive layer CL2 can be electrically isolated from other wiring (e.g., the second conductive layer CL2 can not be electrically short-circuited with other wiring) or can be designed to avoid other wiring.

[0192] In another embodiment, where the area (e.g., size) of the second region A2 may be insufficient for the bypass portion WL-R of the first wiring WL1 to be arranged thereon (e.g., it may not be large enough for the bypass portion WL-R of the first wiring WL1 to be arranged thereon), a portion of the bypass portion WL-R of the first wiring WL1 may be arranged at the edge region (e.g., the peripheral region) of the first region A1 (e.g., in the edge region or on the edge region). In this case, a portion of the bypass portion WL-R of the first wiring WL1 may be superimposed on the transmission region TA. Even in this case, because the area where a portion of the bypass portion WL-R of the first wiring WL1 is arranged thereon (e.g., arranged thereon or on it) can be the outer portion (e.g., the peripheral portion) of the first region A1, even when a portion of the bypass portion WL-R is arranged at the outer portion (e.g., arranged in the outer portion or arranged on the outer portion), there may be little effect on the component (e.g., a camera arranged in the component region CA), and thus the component can maintain or substantially maintain its performance.

[0193] Figure 10 This is a plan view showing the arrangement of pixels and wiring in the display device 1 according to an embodiment. Figure 10 It can be shown Figure 7 A modified embodiment.

[0194] For example, Figure 10 The embodiments shown can be compared with Figure 7 The difference in the illustrated embodiment is that the shape of the component region CA can be different. For example, although Figure 7 The diagram shows a structure in which component region CA has a quadrilateral or approximately quadrilateral shape in a planar view, but... Figure 10 The diagram shows that the component region CA can have a circular shape in the plan view. Figure 10 In, with Figure 7 Elements that are identical or substantially identical are represented by the same or similar reference numerals, thus simplifying or avoiding the repetition of redundant descriptions.

[0195] Reference Figure 10Multiple pixels P can be arranged at the display area DA and the component area CA (e.g., arranged in or on the display area DA and the component area CA). Multiple pixels P can be arranged along a first direction DR1 and a second direction DR2. Multiple main pixels Pm from among the multiple pixels P arranged at the display area DA (e.g., arranged in or on the display area DA) can be arranged continuously. Because the component area CA can be set to a circular shape, pixels P outside the component area CA (e.g., adjacent to the component area CA) at the display area DA (e.g., in or on the display area DA) can be arranged in a stepped manner.

[0196] The component region CA can have a circular shape in a plan view. A first region A1 can be located at the center of the component region CA (e.g., in or on the center portion), and a second region A2 can have an annular shape surrounding the first region A1 (e.g., around the periphery of the first region A1). Various modifications can be made to the width of the second region A2, but in embodiments, the width of the second region A2 can not exceed (e.g., can not be greater than) the width of the pixel group PG.

[0197] In addition to the transmission region TA, multiple auxiliary pixels Pa, derived from multiple pixels P, may be arranged at the component region CA (e.g., arranged in or on the component region CA). In other words, at least a portion of the area of ​​the component region CA where the multiple auxiliary pixels Pa are not arranged (e.g., not disposed therein or not disposed on) can be defined as the transmission region TA. The multiple auxiliary pixels Pa may be arranged at a first region A1 of the component region CA (e.g., arranged in or on the first region A1 of the component region CA). In this case, the multiple auxiliary pixels Pa may not be arranged at a second region A2 of the component region CA surrounding the first region A1 (e.g., around the periphery of the first region A1) (e.g., in or on the second region A2).

[0198] Multiple auxiliary pixels Pa can form a group to define (e.g., to constitute) a pixel group PG at (e.g., in or on) a component region CA. Pixel group PG can be configured as multiple pixel groups. In embodiments, although... Figure 10 The diagram shows that each pixel group PG may include three auxiliary pixels Pa, but this disclosure is not limited thereto.

[0199] Multiple second wirings WL2 extending along the first direction DR1 can be arranged at the display area DA and the component area CA (e.g., arranged in or on the display area DA and the component area CA). The multiple second wirings WL2 can be connected to multiple auxiliary pixels Pa, respectively. Furthermore, the multiple second wirings WL2 can extend along the first direction DR1 and can also be connected to multiple main pixels Pm arranged in the same column as the columns of the multiple auxiliary pixels Pa (e.g., in or on the same column). In an embodiment, the multiple second wirings WL2 may include data lines DL or drive voltage lines PL.

[0200] Multiple second wirings WL2 may extend along the first direction DR1 and may extend across (e.g., through) the transmission region TA. In areas of the transmission region TA where the multiple second wirings WL2 overlap (e.g., in the area of ​​the transmission region TA where the multiple second wirings WL2 overlap or on the area of ​​the transmission region TA where the multiple second wirings WL2 overlap), the multiple second wirings WL2 may be arranged to be biased to one side of the transmission region TA. The transmittance of the area of ​​the transmission region TA where the multiple second wirings WL2 extend across (e.g., through) it may be less than the transmittance of other areas of the transmission region TA (e.g., areas of the transmission region TA that do not overlap with the second wirings WL2).

[0201] Multiple first wirings WL1 can be arranged in the second region A2 of the display region DA and the component region CA (e.g., arranged in or on the second region A2 of the display region DA and the component region CA), and can extend in the first direction DR1. The multiple first wirings WL1 can be connected to multiple main pixels Pm respectively. Unlike multiple second wirings WL2, the multiple first wirings WL1 may not be connected to multiple auxiliary pixels Pa.

[0202] exist Figure 10In the illustrated embodiment, each of the plurality of first wirings WL1 may include an extension portion WL-C and a bypass portion WL-R. The extension portion WL-C may be arranged at the display area DA (e.g., in or on the display area DA), and the bypass portion WL-R may be arranged at the second area A2 of the component area CA (e.g., in or on the second area A2 of the component area CA). In other words, at the component area CA (e.g., in or on the component area CA), the plurality of first wirings WL1 may be arranged to extend only across (e.g., through) the second area A2, and to loop around the first area A1 at the component area CA (e.g., in or on the component area CA). As described above, since the transmission region TA can be arranged at the first region A1 (e.g., arranged in or on the first region A1), the transmittance of the transmission region TA can be reduced by the multiple first wires WL1 when multiple first wires WL1 are arranged to extend across (e.g., through) the first region A1 without bypassing the portion WL-R.

[0203] In contrast, in display device 1 according to one or more example embodiments, a plurality of first wirings WL1 may be arranged at a second region A2 (e.g., arranged in or on the second region A2) to bypass the edge (e.g., periphery) of the component region CA, and the plurality of first wirings WL1 may connect a plurality of main pixels Pm arranged in a first direction DR1 having the component region CA between them. In this case, signals or power can be transmitted (e.g., can be effectively transmitted) to the plurality of main pixels Pm arranged at the display region DA (e.g., arranged in or on the display region DA) without reducing or significantly reducing the light transmittance of the transmissive region TA of the component region CA.

[0204] like Figure 10 As shown, multiple second wirings WL2 may extend along a first direction DR1 and may be positioned in a second region A2 (e.g., within or on the second region A2). For example, in some embodiments, the multiple second wirings WL2 may extend across (e.g., through) the second region A2. As described above, in order to allow multiple first wirings WL1 to circumnavigate the second region A2, the multiple first wirings WL1 may be electrically insulated from some of the multiple second wirings WL2 that extend across (e.g., through) the second region A2.

[0205] Therefore, the extensions WL-C and bypasses WL-R of multiple first wirings WL1 can be arranged on different layers (e.g., in different layers or on different layers) and can be electrically connected to each other through contact holes CNT. For example, as Figure 10 As shown, the contact hole CNT can be located at the second region A2 (e.g., located in or on the second region A2).

[0206] Figure 11 This is a plan view showing the arrangement of pixels and wiring in the display device 1 according to an embodiment.

[0207] In addition to Figure 11 In the embodiment shown, in addition to multiple third wirings WL3 and multiple fourth wirings WL4 extending on a second direction DR2 that intersects with the first direction DR1, Figure 11 The structure of the embodiment shown can be compared with... Figure 7 The embodiments shown have the same or substantially the same structure. In one embodiment, the plurality of third wirings WL3 and the plurality of fourth wirings WL4 may include (e.g., may define) scan lines (e.g., a plurality of scan lines) SL. In another embodiment, the plurality of third wirings WL3 and the plurality of fourth wirings WL4 may include (e.g., may define) transmit control lines (e.g., a plurality of transmit control lines) EL.

[0208] Reference Figure 11 Multiple fourth wirings WL4 can be arranged at the component region CA and the display region DA (e.g., arranged in or on the component region CA and the display region DA), and can extend in the second direction DR2. The multiple fourth wirings WL4 can be connected to multiple auxiliary pixels Pa respectively. Furthermore, the multiple fourth wirings WL4 can extend in the second direction DR2 and can also be connected to multiple main pixels Pm (e.g., multiple main pixels Pm from multiple main pixels Pm arranged in the same row as the auxiliary pixels Pa).

[0209] Multiple fourth wires WL4 may extend in the second direction DR2 and may be arranged to extend across (e.g., through) the transmission region TA. In the region of the transmission region TA where the multiple fourth wires WL4 overlap (e.g., in the region of the transmission region TA where the multiple fourth wires WL4 overlap or on the region of the transmission region TA where the multiple fourth wires WL4 overlap), the multiple fourth wires WL4 may be arranged to be biased to one side of the transmission region TA. Compared to the transmittance of the region of the transmission region TA where the multiple fourth wires WL4 overlap, the transmittance of the portion of the transmission region TA where the multiple fourth wires WL4 do not extend across (e.g., do not through) it may be increased (e.g., may be significantly increased).

[0210] Multiple third wirings WL3 can be arranged at the second region A2 of the display region DA and the component region CA (e.g., arranged in or on the second region A2 of the display region DA and the component region CA), and can extend in the second direction DR2. The multiple third wirings WL3 can be connected to multiple main pixels Pm respectively. Unlike multiple fourth wirings WL4, the multiple third wirings WL3 may not be connected to multiple auxiliary pixels Pa.

[0211] exist Figure 11 In the illustrated embodiment, the plurality of third wirings WL3 may include an extension portion WL-C' and a bypass portion WL-R'. The extension portion WL-C' may be arranged at the display area DA (e.g., in or on the display area DA), and the bypass portion WL-R' may be arranged at the second area A2 of the component area CA (e.g., in or on the second area A2 of the component area CA). In other words, at the component area CA (e.g., in or on the component area CA), the plurality of third wirings WL3 may be arranged to extend only across (e.g., through) the second area A2, and to bypass the first area A1 at the component area CA (e.g., in or on the component area CA). As described above, since the transmission region TA can be arranged at the first region A1 (e.g., arranged in or on the first region A1), the transmittance of the transmission region TA can be reduced by the multiple third wirings WL3 when they are arranged to extend across (e.g., through) the first region A1 without bypassing the portion WL-R'.

[0212] In contrast, in display device 1 according to one or more example embodiments, a plurality of third wirings WL3 may be arranged at the second region A2 (e.g., arranged in or on the second region A2) to surround the edge (e.g., periphery) of the component region CA, and the plurality of third wirings WL3 may connect a plurality of main pixels Pm arranged in the second direction DR2 with the component region CA between them. In this case, signals or power can be transmitted (e.g., can be effectively transmitted) to the plurality of main pixels Pm arranged at the display region DA (e.g., arranged in or on the display region DA) without reducing or substantially reducing the light transmittance of the transmissive region TA of the component region CA.

[0213] like Figure 11As shown, multiple fourth wirings WL4 may extend along the second direction DR2 and may be arranged in the second region A2 (e.g., arranged in or on the second region A2). For example, in some embodiments, the multiple fourth wirings WL4 may extend across (e.g., pass through) the second region A2. As described above, in order to allow multiple third wirings WL3 to be in the second region A2 and to surround the first region A1, the multiple third wirings WL3 may be electrically insulated from some of the fourth wirings WL4 that extend across (e.g., pass through) the second region A2.

[0214] Therefore, the extensions WL-C' and bypasses WL-R' of multiple third wirings WL3 can be arranged on different layers (e.g., in different layers or on different layers) and can be electrically connected to each other through contact holes CNT. Although Figure 11 The contact hole CNT is shown to be positioned at a second region A2 (e.g., positioned in or on the second region A2), but this disclosure is not limited thereto. Similar to Figure 9 In the embodiment shown, the multiple third wirings WL3 may include a fourth conductive layer and a fifth conductive layer. The fourth conductive layer can be electrically connected to the fifth conductive layer through contact holes, and an insulating layer is provided between the fourth and fifth conductive layers.

[0215] Although a display device has been primarily described according to one or more exemplary embodiments of the present disclosure, the present disclosure is not limited thereto. For example, methods of manufacturing a display device according to one or more exemplary embodiments of the present disclosure may also be used within the spirit and scope of the present disclosure.

[0216] According to one or more example embodiments of this disclosure, a display panel and a display device including the display panel can be implemented, comprising an enlarged display area such that images can be displayed even in the area where components are arranged (e.g., in the area where components are arranged or on the area where components are arranged). However, the spirit and scope of this disclosure are not limited thereto.

[0217] Although some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications are possible in the exemplary embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be understood that the foregoing is a description of various exemplary embodiments and is not to be construed as limiting to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the spirit and scope of this disclosure as defined in the claims and their equivalents.

Claims

1. A display panel, the display panel comprising: The substrate includes a component region and a display region surrounding the component region, the component region including a first region and a second region surrounding the first region; Multiple first display elements are located in the display area; Multiple pixel groups are spaced apart from each other in an island-like manner in the first region, each of the multiple pixel groups including multiple second display elements; Multiple transmission regions are located in the first region and are adjacent to the multiple pixel groups; as well as Multiple first wirings extend in a first direction and are electrically connected to the multiple first display elements, the multiple first wirings being located in the second region and circling around the first region, and Multiple second wirings extend in the first direction, are electrically connected to the multiple second display elements, and pass through the first region. The multiple second wirings overlap with at least a portion of the multiple transmissive regions. The plurality of second wirings superimposed on the at least part of the transmission region are arranged around the central portion of the at least part of the transmission region by bending at least twice on one side of the at least part of the transmission region, and are biased on the one side of the at least part of the transmission region.

2. The display panel according to claim 1, wherein, The resolution of the component area per unit area is half or less of the resolution of the display area per unit area.

3. The display panel according to claim 1, wherein, The plurality of first wirings and the plurality of second wirings are configured to transmit data signals to the plurality of first display elements and the plurality of second display elements.

4. The display panel according to claim 1, further comprising: Multiple third wirings extend in a second direction that intersects the first direction and wind around the edge of the first region.

5. The display panel according to claim 4, wherein, The plurality of third wirings are configured to transmit scan signals to the plurality of first display elements.

6. The display panel according to claim 1, further comprising: A first conductive layer is disposed on the substrate; A second conductive layer is disposed on the first conductive layer; A first insulating layer is located between the first conductive layer and the second conductive layer; as well as Multiple second wirings extend in the first direction and are electrically connected to the multiple second display elements, the multiple second wirings overlapping at least a portion of the multiple transmissive regions. The plurality of second wirings are made of the same material as the first conductive layer.

7. The display panel according to claim 6, wherein, Each of the plurality of first wirings includes an extension portion at the display area and a bypass portion at the second area, and The extension portion is connected to the bypass portion through a contact hole defined in the first insulating layer.

8. The display panel according to claim 7, wherein, The extension portion comprises the same material as the first conductive layer, and The bypass portion comprises the same material as the second conductive layer.

9. The display panel according to claim 6, wherein, Each of the plurality of second display elements is electrically connected to a pixel circuit that includes a thin-film transistor and a storage capacitor. The thin-film transistor includes a semiconductor layer, a gate electrode stacked with the semiconductor layer, and an electrode layer connected to the semiconductor layer. The storage capacitor includes a bottom electrode and a top electrode stacked on top of the bottom electrode, and the gate electrode of the thin-film transistor serves as the bottom electrode of the storage capacitor.

10. The display panel according to claim 9, wherein, The first conductive layer comprises the same material as the electrode layer.

11. The display panel according to claim 9, wherein, Each of the plurality of second display elements includes: Pixel electrode; Counter electrode, on the pixel electrode; and The intermediate layer is located between the pixel electrode and the counter electrode. The pixel circuit further includes a contact metal layer, which is connected to the electrode layer at its bottom and to the pixel electrode at its top.

12. The display panel according to claim 11, wherein, The second conductive layer comprises the same material as the contact metal layer.

13. The display panel according to claim 1, wherein, Some of the pixel groups are surrounded by the multiple transmissive regions.

14. The display panel according to claim 1, wherein, Some of the pixel groups are surrounded by the multiple transmissive regions and the second region.

15. The display panel according to claim 1, further comprising at least one insulating layer on the substrate. in, The at least one insulating layer has openings that correspond to the plurality of transmission regions, respectively.

16. The display panel according to claim 1, wherein, Some of the multiple first wirings are arranged around at least some of the multiple pixel groups and are superimposed on some of the multiple transmission regions.

17. The display panel according to claim 1, wherein, The transmittance of the plurality of transmission regions is greater than that of the second region.

18. The display panel of claim 1, further comprising a plurality of metal layers in the component region. in, The plurality of metal layers correspond to the plurality of pixel groups respectively.

19. The display panel according to claim 18, wherein, Each of the plurality of second display elements is electrically connected to a thin-film transistor, the thin-film transistor including a semiconductor layer and a gate electrode stacked thereon, and The plurality of metal layers are positioned between the substrate and the semiconductor layer.

20. A display device, the display device comprising: A display panel includes a substrate, the substrate including a component region and a display region surrounding the component region, the component region including a first region and a second region surrounding the first region; as well as Electronic components, located in the component area of ​​the display panel. The display panel includes: a plurality of first display elements in the display area; a plurality of pixel groups spaced apart from each other in an island-like manner in the first area, each of the plurality of pixel groups including a plurality of second display elements; a plurality of transmissive areas in the first area and adjacent to the plurality of pixel groups; a plurality of first wirings extending in a first direction and electrically connected to the plurality of first display elements, the plurality of first wirings circling around the first area in the second area; and a plurality of second wirings extending in the first direction, electrically connected to the plurality of second display elements and passing through the first area, the plurality of second wirings overlapping at least a portion of the plurality of transmissive areas. The plurality of second wirings superimposed on the at least part of the transmission region are arranged around the central portion of the at least part of the transmission region by bending at least twice on one side of the at least part of the transmission region, and are biased on the one side of the at least part of the transmission region.

21. The display device according to claim 20, wherein, The electronic components include imaging elements.

Images