Coherent integration method and device applied to satellite signal acquisition

Abstract

The application discloses a coherent integration method and device applied to satellite signal acquisition, and comprises the following steps: combining data bits to be coherently integrated into a data bit sequence; performing coherent integration operation on the data bit sequence one by one; performing correlation operation on a current data bit in the data bit sequence to obtain a correlation value of the current data bit; and performing addition or subtraction operation according to the phase of the current data bit and the operation result of a previous data bit to obtain an operation result of the current data bit; in this way, after the coherent integration operation of all data bits in a data bit sequence is completed, the operation result of the last data bit is the coherent integration value of the data bit sequence; and the maximum value in the coherent integration value is found to be applied to subsequent processing of satellite signal acquisition. The application can reduce the hardware resource requirement in long-time coherent integration, thereby saving resources and reducing chip area.

Description

Technical Field

[0001] This invention relates to the field of navigation technology, and more particularly to a coherent integration method and apparatus for satellite signal acquisition. Background Technology

[0002] Navigation technology has played a vital role in the development of human history, and with continuous social progress, this technology, especially satellite navigation and positioning technology, is becoming increasingly intertwined with people's lives. Currently, the world's major satellite navigation systems include the Global Positioning System (GPS), BD2 (BeiDou-2), GLONASS, and Galileo. Both GPS and BD2 utilize CDMA (Code Division Multiple Access) technology, and their physical layer frame structures share many similarities. Therefore, their receiver designs are similar, both including radio frequency front-end processing, baseband digital signal processing, and positioning and navigation calculations. The baseband digital signal processing typically includes acquisition, tracking, bit synchronization, and frame synchronization.

[0003] The process of satellite navigation receivers acquiring satellite signals includes mixing, correlation, coherent / incoherent integration, and decision-making. The principle of navigation signal acquisition is as follows: Figure 1 As shown.

[0004] To improve the signal-to-noise ratio (SNR) of the tested data or signal, especially for capturing and tracking weaker satellite navigation signals in indoor environments, receivers typically perform coherent and incoherent integration. However, while incoherent integration increases SNR, the squaring operations preceding integration introduce squared loss, thus limiting the SNR improvement. Furthermore, as the number of incoherent integration iterations increases, the SNR increase from squared loss becomes insufficient to offset the latency and computational overhead incurred during incoherent integration. Increasing the coherent integration time, on the other hand, significantly improves SNR gain. Therefore, when choosing a strategy combining coherent integration duration and the number of iterations, the coherent integration time is often extended as much as possible. However, due to the limitation of each data bit length and the existence of phase transitions between adjacent data bits, the traditional coherent integration time is often very limited. This is because if the integration period spans multiple data bits, and the data levels (phases) of different bits are different signs, then the input data from different parts will be added and subtracted during the correlation and coherent integration process, canceling each other out and weakening the effect of coherent integration. Therefore, how to extend the coherent integration time as much as possible is very important for improving the acquisition sensitivity of satellite navigation receivers. Summary of the Invention

[0005] This invention provides a coherent integration method and apparatus for satellite signal acquisition, which can at least reduce the hardware resource requirements for coherent integration over very long periods of time.

[0006] This invention provides a coherent integration method for satellite signal acquisition, comprising:

[0007] Combine the data bits to be coherently integrated into a data bit sequence;

[0008] The data bit sequence is subjected to coherent integration operation one by one: for the current data bit in the data bit sequence, the correlation operation within the bit is performed to obtain the correlation value of the current data bit, and the operation result of the current data bit and the previous data bit are added or subtracted according to the phase of the current data bit to obtain the operation result of the current data bit; in this way, after the coherent integration operation of all data bits in a data bit sequence is completed, the operation result of the last data bit is the coherent integration value of the data bit sequence;

[0009] Find the maximum value among the coherent integral values ​​so that it can be applied to subsequent processing of satellite signal acquisition.

[0010] The present invention also provides a coherent integrator for satellite signal acquisition, comprising:

[0011] Combining unit, used to combine data bits to be coherently integrated into a data bit sequence;

[0012] The arithmetic unit is used to perform coherent integration operations on each data bit sequence: for the current data bit in the data bit sequence, perform intra-bit correlation operations to obtain the correlation value of the current data bit, and perform addition or subtraction operations according to the phase of the current data bit and the operation result of the previous data bit to obtain the operation result of the current data bit; in this way, after completing the coherent integration operation of all data bits in a data bit sequence, the operation result of the last data bit is the coherent integration value of the data bit sequence;

[0013] The lookup unit is used to find the maximum value among the coherent integral values ​​so that it can be applied to subsequent processing of satellite signal acquisition.

[0014] The present invention also provides a navigation receiver, which includes the coherent integrator device described above for satellite signal acquisition.

[0015] The embodiments of the present invention can realize the function of ultra-long coherent integration with a small amount of hardware resources, which can reduce the hardware resource requirements for ultra-long coherent integration, thereby saving resources and reducing chip area.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.

[0018] Figure 1 This is a schematic diagram illustrating the principle of navigation signal acquisition.

[0019] Figure 2 This is a schematic diagram of the coherent integration method applied to satellite signal acquisition in Example 1;

[0020] Figure 3 This is a flowchart illustrating an exemplary processing method of the coherent integration method in Embodiment 1;

[0021] Figure 4 This is a schematic diagram of the coherent integrator device applied to satellite signal acquisition in Embodiment 2. Detailed Implementation

[0022] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0023] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0024] Taking the GPS system as an example, considering the C / A code period is 1ms long and the digital correlator generally performs correlation operations with a minimum time unit of 1ms, the receiver still uses 1ms as the basic time unit for coherent integration during the signal acquisition phase. To improve acquisition sensitivity, signal acquisition usually requires extending the coherent integration time of the received signal. Because the receiver does not yet know the position of the data bit edges in the received signal during the signal acquisition phase, the relative position between the coherent integration start edge and the data bit edge can be considered random. In related technologies, strategies for extending the coherent integration time are generally divided into two types: the first is to take a region with the longest possible coherent integration time without data bit transitions within a data bit range; the second is to overcome the transitions between data bits to achieve ultra-long coherent integration of multiple data bits.

[0025] For the first approach, when signal acquisition uses a 1ms coherent integration time, even if a certain 1ms coherent integration period crosses a data bit edge, it can be guaranteed that the next 19 1ms coherent integration periods will not cross any data bit edges, which can be used for signal detection and acquisition. A coherent integration time of 10ms can also be used, which guarantees that at least one of any two adjacent 10ms coherent integration values ​​will not be affected by data bit transitions. In practical applications, coherent integration times greater than 20ms are often required to obtain greater gain and thus improve sensitivity. In this case, the receiver must overcome the problem of random data bit transitions in the received satellite signal, which is the scenario discussed in this application.

[0026] In coherent integration scenarios with durations greater than 20ms, how can receivers overcome the problem of random bit jumps in the received satellite signal? The following methods are commonly used to achieve this:

[0027] First, the repetitiveness of satellite navigation message subframes is utilized. The content of the first, second, and third subframes of the satellite navigation message repeats every 30 seconds and is generally updated every two hours, while the content of the fourth and fifth subframes repeats only once every 12.5 minutes, with even longer update cycles. This repetitiveness of the navigation message content creates conditions for the receiver to predict the next navigation message bit values ​​it will receive in the satellite signal, thus achieving correct padding and long-term coherent integration. For example, after the receiver has obtained a complete navigation message subframe data, it should then be able to accurately predict the data bit values ​​of subframes with the same subframe number. However, when applying this data stripping technique, the receiver not only needs to acquire the original navigation message data in advance but also needs to promptly detect whether the tracked satellite is beginning to broadcast a new set of navigation message data to avoid discrepancies between the data previously obtained by the receiver and the data currently being broadcast by the satellite, which would undermine the effect of coherent integration. This method would then be impractical.

[0028] Second, data assistance. This method requires an external system to obtain navigation message data bits in real time and transmit them to the GPS receiver promptly, such as an AGPS network. This method requires the assistance of an external network and cannot be used with ordinary GPS systems.

[0029] Third, the "guess first, check later" method. Considering that each data bit has only two possible values ​​(0 or 1), the "guess first, check later" method continues the coherent integration process when the current bit value is guessed to be either 0 or 1. One coherent integration involves addition, while the other involves subtraction. Then, considering that one guess is necessarily correct and the other is necessarily incorrect, the "guess first, check later" method checks and compares the two coherent integration results. The one with the larger absolute value is considered the coherent integration result corresponding to the correct guess of the current bit value, and this is precisely the coherent integration value after the receiver overcomes the difficulty of random data bit transitions. Therefore, it can be seen that this method requires storing two copies of the calculation result for each coherent integration, a strategy that sacrifices storage space and computation time for longer coherent integration time.

[0030] Fourth, differential correlation, also known as the delayed multiplication method. This method first uses the complex signal from the original baseband digital signal processing module and its delayed complex conjugate signal as input to the baseband digital signal processing module. Simultaneously, the C / A code copied internally by the receiver is also multiplied by its delayed complex conjugate. Then, correlation operations are performed between the two. In this method, multiplying the received signal by its delayed conjugate increases noise, which is detrimental to the receiver's ability to capture weak signals.

[0031] In summary, to achieve continuous, ultra-long-duration coherent integration of multiple data bits, current strategies often involve reserving more hardware resources for storing or intermediately processing such large amounts of data. This can be achieved by designing multiple independent hardware channels, each processing a single possible bit phase combination. However, once these hardware resources are allocated, they remain indefinitely, which is a waste of resources in scenarios where ultra-long coherent integration times are not required. Furthermore, for chips, the amount of hardware resources is usually closely related to chip size, which is a crucial indicator in product market competition.

[0032] To address the problem of resource waste and large chip area caused by reserving more hardware resources for storing or processing ultra-long data in related technologies, this application proposes the following technical solution. In this solution, each data bit phase combination is treated as a code sequence. A hardware channel is then used to sequentially search all these code sequences in chronological order, performing coherent integration directly. The result with the largest coherent integration value is then selected as the correct coherent integration value for subsequent detection and comparison. This solution achieves ultra-long coherent integration with minimal hardware resources, reducing hardware resource requirements for ultra-long coherent integration, thereby saving resources and reducing chip area.

[0033] The implementation method of the technical solution of this application will be described in detail below.

[0034] Example 1

[0035] like Figure 2 As shown, a coherent integration method for satellite signal acquisition may include:

[0036] Step 201: Combine the data bits to be coherently integrated into multiple data bit sequences according to possible phases;

[0037] Step 202 involves performing coherent integration operations on each of the multiple data bit sequences, including: performing intra-bit correlation operations on the current data bit in a single data bit sequence to obtain the correlation value of the current data bit; and performing addition or subtraction operations on the phase of the current data bit and the operation result of the previous data bit to obtain the operation result of the current data bit. In this way, after completing the coherent integration operations on all data bits in a data bit sequence, the operation result of the last data bit is the coherent integration value of the data bit sequence.

[0038] Step 203: Find the maximum value among the coherent integral values ​​of the multiple data bit sequences and apply it to the subsequent processing of satellite signal acquisition.

[0039] In this embodiment, the data bits to be coherently integrated are first arranged into sequences of possible phase combinations, each representing a possible data bit phase combination. These data bit sequences are then sequentially fed into a coherent integrator for coherent integration. For each data bit in a sequence, correlation operations are performed within the bit, and then addition or subtraction is performed based on the data bit's phase (i.e., 0 or 1) and the result of the previous data bit's operation. This process is repeated to complete the coherent integration of all data bits within a sequence. The coherent integration value for each data bit sequence is then calculated using this method. This allows for the implementation of ultra-long coherent integration with minimal hardware resources, reducing hardware resource requirements for ultra-long coherent integration, thereby saving resources and reducing chip area.

[0040] It should be noted that when a data bit is the first data bit in the current data bit sequence, its correlation value is the result of the operation. When a data bit is not the first data bit in the current data bit sequence, the result of the operation on that data bit is the value obtained by adding or subtracting the correlation value of that data bit from the result of the operation on the previous data bit.

[0041] In one implementation, the addition or subtraction operation based on the phase of the current data bit and the result of the operation with the previous data bit may include: when the current data bit is 0, adding the negative value of the relevant value of the current data bit to the result of the operation with the previous data bit; when the current data bit is 1, adding the relevant value of the current data bit to the result of the operation with the previous data bit. It should be noted that this implementation is merely an exemplary implementation of this embodiment. Other implementations are also possible in this embodiment, which will not be elaborated upon here.

[0042] In this embodiment, combining the data bits to be coherently integrated into a data bit sequence may include: when the correlation integration length is M, arranging the data bits to be coherently integrated according to all possible phase combinations to form the plurality of data bit sequences, wherein the plurality of data bit sequences contain M data bits. For example, to achieve coherent integration with a time length of 20ms*5, the data bit sequence contains 5 data bits. In other words, the data bit sequence is a data bit sequence composed of all possible phase combinations of 5 data bits, and each of these data bit sequences represents a possible data bit phase combination.

[0043] The following example illustrates this embodiment using a coherent integral with a time length of 20ms*5.

[0044] Assuming we want to achieve a coherent integral with a time duration of 20ms*5, an exemplary calculation process is as follows: Figure 3 As shown, it may include:

[0045] Step 301: Form a data bit sequence;

[0046] Specifically, the data bits to be coherently integrated are arranged into a series of data bit sequences according to possible phase combinations. When coherent integration with a time length of 20ms*5 is to be achieved, the data bit sequences are shown in Table 1. Table 1 contains data bit sequences consisting of all possible phase combinations of 5 data bits. Each of these data bit sequences represents a possible data bit phase combination.

[0047] Sequence 1 00000 Sequence 9 01000 Sequence 17 10000 Sequence 25 11000 Sequence 2 00001 Sequence 10 01001 Sequence 18 10001 Sequence 26 11001 Sequence 3 00010 Sequence 11 01010 Sequence 19 10010 Sequence 27 11010 Sequence 4 00011 Sequence 12 01011 Sequence 20 10011 Sequence 28 11011 Sequence 5 00100 Sequence 13 01100 Sequence 21 10100 Sequence 29 11100 Sequence 6 00101 Sequence 14 01101 Sequence 22 10101 Sequence 30 11101 Sequence 7 00110 Sequence 15 01110 Sequence 23 10110 Sequence 31 11110 Sequence 8 00111 Sequence 16 01111 Sequence 24 10111 Sequence 32 11111

[0048] Table 1

[0049] Step 302: Send a data bit sequence to the coherent integrator;

[0050] Step 303: The coherent integrator performs intra-bit correlation operations on each data bit to obtain the correlation value within each data bit;

[0051] Step 304: Perform coherent integration based on the phase of each data bit in the data bit sequence;

[0052] Specifically, by adding or subtracting the phase (i.e., 0 or 1) of a data bit from the correlation value in the previous data bit, the coherent integral value of all data bits in a data bit sequence is calculated in this way.

[0053] Step 305: Determine whether all data bit sequences have been coherently integrated; if yes, continue to step 306; otherwise, return to step 302 and continue to send the next data bit sequence to the coherent integrator.

[0054] Step 306: End the loop, find the data bit sequence with the largest coherent integral value, and send the coherent integral value of the data bit sequence to the subsequent processing stage (e.g., incoherent integration) to continue the subsequent processing of satellite signal acquisition.

[0055] like Figure 3 In the exemplary processing flow shown, all data bit sequences are sequentially sent to a coherent integrator for coherent integration. The above calculation process is performed on each data bit sequence to calculate the coherent integration value of each data bit sequence in sequence.

[0056] In one implementation, it can be agreed that data bit 1 can directly use its correlation value to participate in the coherent integration operation, while data bit 0 should use the negative value of its correlation value to participate in the coherent integration operation. Taking data bit sequence 20 as an example, the five data bits in this data bit sequence are sequentially sent to the coherent integrator for coherent integration. First, perform a correlation operation on the first data bit 1 in this data bit sequence, and directly save the correlation value obtained from the correlation operation as the result of the first data bit 1. Then, perform a correlation operation on the second data bit 0 in this data bit sequence, and add the negative value of the correlation value obtained from this correlation operation to the result of the first data bit to obtain the result of the second data bit. Then, perform a correlation operation on the third data bit 0 in this data bit sequence, and add the negative value of the correlation value obtained from this correlation operation to the result of the second data bit to obtain the result of the third data bit. Then, perform intra-bit correlation on the fourth data bit (1) of this data bit sequence, and add the correlation value obtained from this operation directly to the result of the operation on the third data bit to obtain the result of the operation on the fourth data bit. Then, perform intra-bit correlation on the fifth data bit (1) of this data bit sequence, and add the correlation value obtained from this operation directly to the result of the operation on the fourth data bit. The final result of these five additions, which is the result of the operation on the fifth data bit, is the coherent integral value of the current data bit sequence.

[0057] Following the calculation method described above, data bit sequences 1 through 32 are sequentially fed into the coherent integrator, resulting in coherent integral values ​​for each of the 32 possible data bit phase combinations. Finally, the largest of these 32 coherent integral values ​​is selected as the final coherent integral value, which will then participate in subsequent incoherent integration operations. The data bit sequence (or data bit phase combination) corresponding to this largest coherent integral value is the most likely correct data bit phase combination.

[0058] The method described in this embodiment achieves ultra-long coherent integration by arranging the data bits to be coherently integrated into sequences of data bits according to different phase combinations, and then sequentially feeding these sequences of data bits into hardware resources to complete the relevant calculations. This is a time-for-space tradeoff method, with the advantage of requiring only a small amount of hardware resources to achieve ultra-long coherent integration. Since hardware resources are difficult to change once allocated, while computation time can gradually decrease with technological advancements and increased computation speed, the method in this embodiment has greater practical application value compared to related technologies.

[0059] It should be noted that this embodiment is applicable to scenarios involving ultra-long coherent integration of multiple data bit lengths. Furthermore, this idea of ​​arranging the bits to be calculated into bit sequences based on different phase combinations, and then sequentially calculating these sequences to reduce hardware resources, can also be applied to other similar scenarios, such as the acquisition of NH codes from the BeiDou system.

[0060] The method in this embodiment can be applied to navigation receivers, specifically to baseband digital signal processing modules, and is particularly suitable for capturing GPS satellite signals.

[0061] Example 2

[0062] A coherent integrator for satellite signal acquisition, such as Figure 4 As shown, it may include:

[0063] Combination unit 41 is used to combine the data bits to be coherently integrated into multiple data bit sequences according to possible phases;

[0064] The arithmetic unit 42 is used to perform coherent integration operations on the plurality of data bit sequences one by one, including: performing intra-bit correlation operations on the current data bit in the data bit sequence to obtain the correlation value of the current data bit; and performing addition or subtraction operations on the phase of the current data bit and the operation result of the previous data bit to obtain the operation result of the current data bit. In this way, after completing the coherent integration operation of all data bits in a data bit sequence, the operation result of the last data bit is the coherent integration value of the data bit sequence.

[0065] The lookup unit 43 is used to find the maximum value among the coherent integral values ​​of the plurality of data bit sequences, which is then applied to the subsequent processing of satellite signal acquisition.

[0066] In one implementation, the arithmetic unit 42 is used to perform addition or subtraction operations based on the phase of the current data bit and the result of the operation with the previous data bit. This can include: when the current data bit is 0, adding the negative value of the relevant value of the current data bit to the result of the operation with the previous data bit; when the current data bit is 1, adding the relevant value of the current data bit to the result of the operation with the previous data bit. It should be noted that this implementation is only an exemplary implementation of this embodiment. Other implementations are also possible in this embodiment, which will not be elaborated here.

[0067] In one implementation, the combining unit 41 is used to combine the data bits to be coherently integrated into a data bit sequence, which may include: when the correlation integration length is M, arranging the data bits to be correlated and integrated according to all possible phase combinations to form the plurality of data bit sequences, wherein the plurality of data bit sequences contain M data bits.

[0068] In practical applications, the coherent integrator used for satellite signal acquisition in this embodiment can be implemented through a navigation receiver or integrated within the navigation receiver. In one implementation, the coherent integrator can be implemented using the baseband digital signal processing module of the navigation receiver. The combination unit 41, the arithmetic unit 42, and the lookup unit 43 can be software, hardware, or a combination of both. In another implementation, the coherent integrator is responsible for implementing… Figure 1 The coherent integral in the equation can be implemented using the coherent integrator described above.

[0069] Other technical details of this embodiment can be found in Embodiment 1.

[0070] Example 3

[0071] This application also provides a navigation receiver that includes the coherent integrator described above for satellite signal acquisition. Specific technical details can be found in Embodiments 1 and 2.

[0072] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A coherent integration method for satellite signal acquisition, comprising: The data bits to be coherently integrated are combined into multiple data bit sequences according to their phases, wherein each of the multiple data bit sequences represents a data bit phase combination; The coherent integration operation is performed on each of the multiple data bit sequences, including: performing intra-bit correlation operation on the current data bit in a single data bit sequence to obtain the correlation value of the current data bit; performing addition or subtraction operation on the phase of the current data bit and the operation result of the previous data bit to obtain the operation result of the current data bit; in this way, after completing the coherent integration operation on all data bits in a data bit sequence, the operation result of the last data bit is the coherent integration value of the data bit sequence; Find the maximum value among the coherent integral values ​​of the multiple data bit sequences, and apply it to the subsequent processing of satellite signal acquisition; The operation of adding or subtracting based on the phase of the current data bit and the result of the operation with the previous data bit includes: When the current data bit is 0, add the negative value of the relevant value of the current data bit to the result of the operation of the previous data bit; When the current data bit is 1, add the relevant value of the current data bit to the result of the operation of the previous data bit.

2. The method according to claim 1, characterized in that, The step of combining the data bits to be coherently integrated into multiple data bit sequences according to their phase includes: When the correlation integration length is M, the data bits to be correlated and integrated are arranged according to phase combination to form the plurality of data bit sequences, wherein the plurality of data bit sequences contain M data bits.

3. A coherent integrator for satellite signal acquisition, characterized in that, include: A combination unit is used to combine the data bits to be coherently integrated into multiple data bit sequences according to their phases, wherein each of the multiple data bit sequences represents a data bit phase combination. The arithmetic unit is used to perform coherent integration operations on each of the plurality of data bit sequences, including: performing intra-bit correlation operations on the current data bit in a single data bit sequence to obtain the correlation value of the current data bit; performing addition or subtraction operations on the phase of the current data bit and the operation result of the previous data bit to obtain the operation result of the current data bit; thus, after completing the coherent integration operation on all data bits in a data bit sequence, the operation result of the last data bit is the coherent integration value of the data bit sequence; The lookup unit is used to find the maximum value among the coherent integral values ​​of the plurality of data bit sequences, which is applied to the subsequent processing of satellite signal acquisition; The arithmetic unit is used to perform addition or subtraction operations based on the phase of the current data bit and the result of the operation with the previous data bit, including: When the current data bit is 0, add the negative value of the relevant value of the current data bit to the result of the operation of the previous data bit; When the current data bit is 1, add the relevant value of the current data bit to the result of the operation of the previous data bit.

4. The coherent integrator according to claim 3, characterized in that, The combining unit is used to combine the data bits to be coherently integrated into multiple data bit sequences according to their phase, including: When the correlation integration length is M, the data bits to be correlated and integrated are arranged according to phase combination to form the plurality of data bit sequences, wherein the plurality of data bit sequences contain M data bits.

5. A navigation receiver, characterized in that, The navigation receiver includes a coherent integrator for satellite signal acquisition as described in claim 3 or 4.

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