Flash memory device and computing device

Abstract

A flash memory device and a computing device are provided. The flash memory device includes a first pad, a second pad, a third pad, a memory cell array, a row decoder block, a buffer block storing a command and an address received from an external semiconductor chip through the first pad and providing the address to the row decoder block, a page buffer block connected to the memory cell array through a bit line, connected to the third pad through a data line, and exchanging a data signal with the external semiconductor chip through the data line and the third pad, and a control logic block receiving the command from the buffer block, receiving a control signal from the external semiconductor chip through the second pad, and controlling the row decoder block and the page buffer block based on the received command and the received control signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0130745, filed on October 21, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The apparatus and methods consistent with one or more exemplary embodiments relate to a semiconductor device, and more specifically, to a flash memory device providing ultra-wide bandwidth for neural processing and a computing device including flash memory cells. Background Technology

[0003] With the development of technologies associated with machine learning, there are attempts to apply machine learning to environments. As an example of these attempts, processing and storage components suitable for machine learning are being developed.

[0004] Machine learning is characterized by its use of large amounts of sequential data. Because large amounts of sequential data can be transmitted at high speed or with wide bandwidth, the performance of applications employing machine learning can be improved, and utilization can be increased. Furthermore, to reduce unnecessary power consumption, non-volatile memory elements can be used as storage elements for machine learning.

[0005] Non-volatile storage devices capable of transmitting large amounts of sequential data at high speeds or with wide bandwidths suitable for machine learning have not yet been developed. Therefore, there is an increasing demand for non-volatile storage devices capable of transmitting large amounts of sequential data at high speeds or with wide bandwidths suitable for machine learning. Summary of the Invention

[0006] One or more exemplary embodiments provide a flash memory device that has performance suitable for machine learning by transmitting large amounts of sequential data at high speed or wide bandwidth, and a computing device including flash memory cells.

[0007] According to an exemplary embodiment, a flash memory device includes: a first pad configured to be bonded to an external semiconductor chip; a second pad configured to be bonded to an external semiconductor chip; a third pad configured to be bonded to an external semiconductor chip; a memory cell array including memory cells; a row decoder block connected to the memory cell array via word lines and configured to select one of the word lines provided to the row decoder block based on an address; a buffer block configured to store commands and addresses received from the external semiconductor chip via the first pad and to provide addresses to the row decoder block; a page buffer block connected to the memory cell array via bit lines and connected to the third pad via data lines and configured to exchange data signals with the external semiconductor chip via the data lines and the third pad; and a control logic block configured to receive commands from the buffer block, receive control signals from the external semiconductor chip via the second pad, and control the row decoder block and the page buffer block based on the received commands and the received control signals.

[0008] According to another exemplary embodiment, a computing device includes: a memory cell chip including flash memory cells; a peripheral circuit chip configured to access the flash memory cells; and a logic chip configured to store first data in the flash memory cells via the peripheral circuit chip, read second data from the flash memory cells, and perform at least one operation by using the first data and the second data, wherein the peripheral circuit chip is stacked on the logic chip, and the memory cell chip is stacked on the peripheral circuit chip.

[0009] According to another exemplary embodiment, a computing device includes: a neural processor chip; and a flash memory chip connected to the neural processor chip, wherein the flash memory chip includes: a first pad bonded to the neural processor chip; a second pad bonded to the neural processor chip; a third pad bonded to the neural processor chip; a memory cell array including memory cells; a row decoder block connected to the memory cell array via word lines and configured to select one of the word lines based on an address provided to the row decoder block; a buffer block configured to store commands and addresses received from the neural processor chip via the first pad and to provide addresses to the row decoder block; a page buffer block connected to the memory cell array via bit lines and connected to the third pad via data lines and configured to exchange data signals with the neural processor chip via the data lines and the third pad; and a control logic block configured to receive commands from the buffer block, receive control signals from the neural processor chip via the second pad, and control the row decoder block and the page buffer block based on the received commands and the received control signals.

[0010] According to another exemplary embodiment, a flash memory device includes: a memory cell; a first pad configured to be bonded to an external semiconductor chip and configured to receive commands and addresses from the external semiconductor chip for read or write operations on the memory cell; a second pad configured to be bonded to the external semiconductor chip and configured to receive control signals from the external semiconductor chip; a third pad configured to be bonded to the external semiconductor chip; and a page buffer block connected to the memory cell via bit lines, connected to the third pad via data lines, and configured to exchange data signals with the external semiconductor chip via the data lines and the third pad. Attached Figure Description

[0011] The above and other objects will become clear from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 An example of a neural network implemented based on machine learning is shown;

[0013] Figure 2 It shows in Figure 1 An example of performing machine learning on a neural network;

[0014] Figure 3 It shows in Figure 1 An example of performing inference at a neural network;

[0015] Figure 4 This is a perspective view showing a flash memory device according to an exemplary embodiment;

[0016] Figure 5 It shows Figure 4 An example of a flash memory device rotated up to 180 degrees around a second direction;

[0017] Figure 6 An example of a flash memory device connected to an external device (e.g., a neural processor (NPU)) according to an exemplary embodiment is shown;

[0018] Figure 7 This is a block diagram illustrating a flash memory device according to an exemplary embodiment;

[0019] Figure 8 The construction of a page buffer block according to an exemplary embodiment is shown;

[0020] Figure 9 The construction of a page buffer block according to an exemplary embodiment is shown;

[0021] Figure 10 The construction of a page buffer block according to an exemplary embodiment is shown;

[0022] Figure 11An example of a flash memory device based on a cell-over-peri (COP) structure according to an exemplary embodiment is shown;

[0023] Figure 12 An example of a circuit diagram of a memory cell array according to an exemplary embodiment is shown;

[0024] Figure 13 An example of a flash memory device implemented according to an exemplary embodiment is shown by bonding; and

[0025] Figure 14 This is a block diagram illustrating a computing device according to an exemplary embodiment. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail and clearly to the extent that one or more inventive concepts can be readily implemented by those skilled in the art.

[0027] Figure 1 An example of a neural network (NN) implemented based on machine learning is shown. For example, a neural network (NN) can include different implementations (such as artificial neural networks (ANN), convolutional neural networks (CNN), recurrent neural networks (RNN), etc.).

[0028] Reference Figure 1 The neural network NN includes first input nodes IN1 to fourth input nodes IN4 (i.e., first input node IN1, second input node IN2, third input node IN3, and fourth input node IN4), first hidden nodes HN1 to tenth hidden nodes HN10 (i.e., first hidden node HN1, second hidden node HN2, third hidden node HN3, fourth hidden node HN4, fifth hidden node HN5, sixth hidden node HN6, seventh hidden node HN7, eighth hidden node HN8, ninth hidden node HN9, and tenth hidden node HN10), and an output node ON. When constructing the neural network, the number of input nodes, the number of hidden nodes, and the number of output nodes can be predetermined.

[0029] The first input nodes IN1 to the fourth input node IN4 form the input layer. The first hidden nodes HN1 to the fifth hidden nodes HN5 form the first hidden layer. The sixth hidden nodes HN6 to the tenth hidden nodes HN10 form the second hidden layer. The output node ON forms the output layer. When constructing a neural network, the number of hidden layers can be predetermined.

[0030] Data used for learning or inference can be input to the first input nodes IN1 through the fourth input node IN4. The value of each input node is transmitted via a branch (or synapse) to the first hidden nodes HN1 through the fifth hidden nodes HN5 of the first hidden layer. Each branch (or synapse) can be assigned a corresponding synaptic value or a corresponding weight. Computations (e.g., multiplication) can be performed on the value of each input node and the synaptic value or weight of the corresponding branch (or synapse), and the results of the computation can be transmitted to the first hidden layer.

[0031] Computations (e.g., multiplications) can be performed on the values ​​and weights (or synaptic values) of the first hidden nodes HN1 through the fifth hidden nodes HN5, and the results can be passed to the sixth hidden nodes HN6 through the tenth hidden nodes HN10 of the second hidden layer. Computations (e.g., multiplications) can also be performed on the inputs and weights (or synaptic values) of the sixth hidden nodes HN6 through the tenth hidden nodes HN10, and the results can be passed to the output node ON. The value of the output node ON can indicate the result of the learning or inference.

[0032] Figure 2 It shows in Figure 1 An example of performing machine learning at a neural network (NN). See [reference]. Figure 1 and Figure 2 In operation S110, initial synaptic data (or initial weight data) can be set or provided to the neural network NN. The initial synaptic data (or initial weight data) may include multiple initial synaptic values ​​(or initial weight values) corresponding to multiple synapses (or branches).

[0033] For example, initial synaptic data (or initial weight data) is read from a storage element (or storage device, memory, etc.) and loaded onto a neural processing unit (NPU). The initial synaptic data (or initial weight data) can be a large amount of data, such as tens of megabytes (MB) or more.

[0034] In operation S120, sample data for machine learning is input to the NPU. The sample data can be input to the NPU via communication means or devices (such as a modem, communication interface, network interface, etc.). Optionally, the sample data can be input to the NPU from a storage element. In this case, the sample data can be read from the storage element and loaded onto the NPU. The sample data can be a large amount of data, such as tens of megabytes (MB) or more.

[0035] In operation S130, the NPU can acquire output data. The output data can be transmitted or sent to a remote station via communication means or devices (such as a modem, communication interface, network interface, etc.), or the output data can be stored in a storage element. In this case, output data can be received from the NPU, and the received output data can be stored in a storage element. The output data can be a large amount of data, such as several megabytes (MB) or more.

[0036] In operation S140, the synaptic data (or weight data) can be updated based on the difference between the output data and the sample data. In this case, the synaptic data (or weight data) existing in the storage element is overwritten. The synaptic data (or weight data) can be a large amount of data, such as tens of megabytes (MB) or more.

[0037] Figure 3 It shows in Figure 1 An example of performing inference at the neural network NN. See [reference]. Figure 1 and Figure 3 In operation S210, synaptic data (or weight data) can be set or provided to the NPU. In this case, synaptic data (or weight data) is read from the storage element and loaded onto the NPU. The synaptic data (or weight data) can be a large amount of data, such as tens of megabytes (MB) or more.

[0038] In operation S220, the inference data used for inference is input to the NPU. The inference data can be input to the NPU via communication means or devices (such as a modem, communication interface, network interface, etc.). Optionally, the inference data can be input to the NPU from a storage element. In this case, the inference data can be read from the storage element and loaded onto the NPU. The inference data can be a large amount of data, such as tens of megabytes (MB) or more.

[0039] In operation S230, the NPU can acquire output data (or inference results). The output data can be sent to a remote station via communication means (such as a modem), or the output data can be stored in a storage element. In this case, output data can be received from the NPU, and the received output data can be stored in a storage element. The output data can be a large amount of data, such as several megabytes (MB) or more.

[0040] When additional inference is subsequently performed using the same inference model, operations S220 and S230 can be repeated. When the current inference model (e.g., an image recognition model) is changed to another inference model (e.g., a speech recognition model), operations S210 to S230 can be repeated.

[0041] For reference Figure 2 and Figure 3 As described, in machine learning and inference processing, read and write operations (or bulk read and write operations) for large amounts of data can be performed on the storage elements associated with the NPU. Because read and write operations for large amounts of data (or bulk read and write operations) are associated with each of the synaptic data (or weight data), sample data, inference data, and output data, they have a sequential rather than a random characteristic.

[0042] One or more exemplary embodiments provide flash memory devices and computing devices that support sequential read and write operations for large amounts of data by providing ultra-wide bandwidth associated with data through an interface that is associated with command, address, and control signals. Therefore, a flash memory device suitable for an NPU can be provided that minimizes or suppresses the additional costs associated with changes to the interface of existing flash memory devices.

[0043] Figure 4 This is a perspective view showing a flash memory device 100 according to an exemplary embodiment. (Refer to...) Figure 4 The flash memory device 100 may include a first layer 110 and a second layer 120. Each of the first layer 110 and the second layer 120 may be parallel to a plane defined by a first direction and a second direction. Each of the first layer 110 and the second layer 120 may have an upper surface facing a third direction and a lower surface facing away from the upper surface.

[0044] For ease of description, Figure 4 The example shown illustrates a first layer 110 and a second layer 120 that are separate from each other. However, the first layer 110 and the second layer 120 can be tightly attached along a third direction to achieve this using a single structure.

[0045] The first layer 110 may be a memory cell array including flash memory cells. The first layer 110 may include a first array 111, a second array 112, a third array 113, a fourth array 114, and an outer region 115 surrounding the first array 111 to the fourth array 114. Each of the first array 111 to the fourth array 114 may include a plurality of memory cells and select lines, word lines, and bit lines connected to the plurality of memory cells.

[0046] The second layer 120 may be or include peripheral circuitry for accessing flash memory cells. The second layer 120 may include a first internal region 121, a second internal region 122, a third internal region 123, and a fourth internal region 124. The second layer 120 may also include a first row decoder 131 extending along a second direction on the side of the first internal region 121 and the second internal region 122 opposite to the first direction.

[0047] The second layer 120 may further include a second row decoder 132 and a third row decoder 133, which are sequentially arranged along a first direction between the first inner region 121 and the third inner region 123 and between the second inner region 122 and the fourth inner region 124, and extend along a second direction. The second layer 120 may also include a fourth row decoder 134 extending along the second direction on the side of the third inner region 123 and the fourth inner region 124 facing the first direction.

[0048] The second layer 120 may also include a first page buffer 141 and a second page buffer 142, which are sequentially arranged between the first inner region 121 and the second inner region 122 along a second direction, and the first page buffer 141 and the second page buffer 142 extend along a first direction.

[0049] The second layer 120 may also include a third page buffer 143 and a fourth page buffer 144, which are arranged sequentially along a second direction between the third inner region 123 and the fourth inner region 124, and extend along a first direction.

[0050] The second layer 120 may also include an outer region 151, which extends along the first direction on the side opposite to the second direction of the first row decoder 131 to the fourth row decoder 134 and the second inner region 122 and the fourth inner region 124.

[0051] For example, the flash memory device 100 may be based on a cell-over-periphery (COP) structure. A first active region may be formed on a semiconductor substrate, and a second layer 120 may be formed on the first active region. A second active region may be formed on the second layer 120, and a first layer 110 may be formed on the second active region.

[0052] The first row decoder 131 to the fourth row decoder 134 can be electrically connected to the word lines and select lines of the first layer 110 via vias (e.g., through-hole vias (THVs)) extending along a third direction and penetrating corresponding portions of the outer region 115 of the first layer 110. The first page buffer 141 to the fourth page buffer 144 can be electrically connected to the bit lines of the first layer 110 via vias extending along a third direction and penetrating corresponding portions of the outer region 115 of the first layer 110.

[0053] For example, the portions of the first row decoder 131 and the second row decoder 132 facing the second direction, as well as the first page buffer 141, can be connected to the select line, word line, and bit line of the first array 111, respectively. The remaining portions of the first row decoder 131 and the second row decoder 132 facing away from the second direction, as well as the second page buffer 142, can be connected to the select line, word line, and bit line of the second array 112, respectively.

[0054] The portions of the third-row decoder 133 and the fourth-row decoder 134 facing the second direction, as well as the third-page buffer 143, can be connected to the select line, word line, and bit line of the third array 113, respectively. The remaining portions of the third-row decoder 133 and the fourth-row decoder 134 facing away from the second direction, as well as the fourth-page buffer 144, can be connected to the select line, word line, and bit line of the fourth array 114, respectively.

[0055] The positions of the first internal region 121 to the fourth internal region 124 of the second layer 120 can correspond to the positions of the first array 111 to the fourth array 114 of the first layer 110, respectively. The first internal region 121 to the fourth internal region 124 may include circuitry for controlling access to the first array 111 to the fourth array 114.

[0056] As another example, the flash memory device 100 can be implemented via wafer-level bonding. The first layer 110 can be implemented using one of the dies on a separate wafer (e.g., a first wafer). The select lines, word lines, and bit lines of the first layer 110 can extend in a direction away from a third direction to the lower surface of the first layer 110 and can be connected to pads (or solder bumps) respectively.

[0057] The second layer 120 can be implemented using one of the dies on a separate wafer (e.g., a second wafer). The first row decoder 131 to the fourth row decoder 134 and the first page buffer 141 to the fourth page buffer 144 of the second layer 120 can be connected to pads (or solder bumps) on the upper surface of the second layer 120 respectively via wiring extending along a third direction.

[0058] The positions of the pads (or solder bumps) of the first layer 110 on the first wafer can correspond to the positions of the pads (or solder bumps) of the second layer 120 on the second wafer. The dies on the first wafer and the dies on the second wafer can be connected to each other by bonding the first wafer and the second wafer.

[0059] The flash memory device 100 can be implemented by dicing interconnected wafers. In this case, the first layer 110 of the flash memory device 100 can be regarded as a flash memory cell chip, and the second layer 120 of the flash memory device 100 can be regarded as a peripheral circuit chip.

[0060] Figure 5 It shows Figure 4 An example of a flash memory device 100 rotated approximately 180 degrees about a second direction. Figure 5 In the example shown, the first layer 110 and the second layer 120 are tightly attached along a third direction to utilize a structure.

[0061] Reference Figure 4 and Figure 5 A first pad 161 (or solder bump) and a second pad 162 (or solder bump) are disposed on the lower surface of the outer region 151 of the second layer 120 (or disposed on the surface of the outer region 151 facing away from a third party). The first pad 161 and the second pad 162 can be connected to an external device (e.g., an NPU).

[0062] The first pad 161 can be configured to receive commands and addresses from the flash memory device 100. The second pad 162 can be configured to receive and output control signals from the flash memory device 100. The first pad 161 and the second pad 162 can receive and transmit commands, addresses, and control signals according to a general flash memory device interface.

[0063] A third pad 163 (or solder bump) is disposed on the lower surface of the first page buffer 141 to the fourth page buffer 144 of the second layer 120 (or disposed on the third-opposite surface of the first page buffer 141 to the fourth page buffer 144). The third pad 163 can be connected to an external device (e.g., an NPU). The third pad 163 can be directly connected to the internal circuitry of the first page buffer 141 to the fourth page buffer 144 without passing through any other components. The third pad 163 can support direct communication between the external device (e.g., an NPU) and the first page buffer 141 to the fourth page buffer 144, thus providing ultra-wide bandwidth for data.

[0064] In this exemplary embodiment, the flash memory device 100 is described as being implemented using a COP structure or by wafer bonding. However, it is understood that one or more other exemplary embodiments are not limited to a COP structure or the manner of wafer bonding. For example, the flash memory device 100 may be implemented such that the first pad 161, the second pad 162, and the third pad 163 are disposed on the same surface for connection to an external device (e.g., an NPU).

[0065] Figure 6 An example is shown of a flash memory device 100 connected to an external device (e.g., a neural processor (NPU) 200) according to an exemplary embodiment. (Refer to...) Figure 6 In the right portion, NPU 200 may include an upper surface that is parallel to the first and second directions and formed to face the third direction. NPU 200 may also include a lower surface formed to face away from the third direction.

[0066] The first pad 211 (or solder bump), the second pad 212 (or solder bump), and the third pad 213 (or solder bump) can be disposed on the upper surface of the NPU 200. The positional relationship of the first pad 211, the second pad 212, and the third pad 213 of the NPU 200 can be related to the position of the first pad 211, the second pad 212, and the third pad 213 on the upper surface of the NPU 200. Figure 6 On the lower surface of the flash memory device 100 in the left portion (e.g., on the left side) Figure 6 The first pad 161, the second pad 162, and the third pad 163 of the flash memory device 100 in the left part are in the same (or corresponding) positional relationship on the surface that is parallel to the first direction and the second direction and away from the third direction.

[0067] As shown by the first bonding line B1 to the third bonding line B3, the flash memory device 100 can be rotated approximately 180 degrees about the second direction, and the lower surface of the flash memory device 100 can be connected to the upper surface of the NPU 200.

[0068] As shown by the second bonding line B2, a first pad 161 (or solder bump) on the lower surface of the flash memory device 100 can be bonded to a first pad 211 (or solder bump) on the upper surface of the NPU 200. The NPU 200 can transmit commands and addresses to the flash memory device 100 via the first pads 211 and 161. For example, commands and addresses can be transmitted in units of one byte (i.e., 8 bits) in one cycle (e.g., a clock cycle or the equivalent of a clock cycle for a trigger signal).

[0069] As shown by the third bonding line B3, the second pad 162 (or solder bump) on the lower surface of the flash memory device 100 can be bonded to the second pad 212 (or solder bump) on the upper surface of the NPU 200. Through the second pads 212 and 162, the NPU 200 can transmit control signals to the flash memory device 100 and receive control signals from the flash memory device 100.

[0070] As shown by the first bonding line B1, a third pad 163 (or solder bump) on the lower surface of the flash memory device 100 can be bonded to a third pad 213 (or solder bump) on the upper surface of the NPU 200. The NPU 200 can perform data communication with the flash memory device 100 via the third pads 213 and 163. For example, data can be transferred in units of hundreds of bytes or more (or thousands of bytes or more) (e.g., one hundred bytes or more) in one cycle (e.g., a clock cycle or a period equivalent to a clock cycle of a trigger signal).

[0071] In an exemplary embodiment, the flash memory device 100 and the NPU 200 can be connected via wafer-level bonding. For example, a wafer including a die of the flash memory device 100 (e.g., a COP die or a die bonded at the wafer level) and a wafer including a die of the NPU 200 can be connected and then diced.

[0072] As another example, the flash memory device 100 and the NPU 200 can be connected via chip-level bonding. For example, the chips of the flash memory device 100 (e.g., COP chips or chips implemented through wafer-level bonding and debonding) and the chips of the NPU 200 can be manufactured separately. The chips of the flash memory device 100 and the chips of the NPU 200 can then be connected via bonding.

[0073] Furthermore, as another example, the flash memory device 100 and the NPU 200 can be connected via chip-level bonding and wafer-level bonding. For example, chips of the flash memory device 100 can be manufactured (e.g., COP chips or chips implemented through wafer-level bonding and separation). Chips of the flash memory device 100 can be attached to wafers including dies of the NPU 200 for each die, and the dies can be separated.

[0074] The NPU 200 may also include pads (or solder bumps) on its lower surface or on its upper surface not covered by the flash memory device 100, for connection to another external device (e.g., a host device such as an application processor or central processing unit). In this case, a hierarchical structure can be implemented in which the NPU 200 performs learning or inference using the flash memory device 100 upon request from the host device.

[0075] Figure 7This is a block diagram illustrating a flash memory device 300 according to an exemplary embodiment. Figure 7 It shows the reference Figures 4 to 6 A block diagram of a corresponding component in one of the first arrays 111 to the fourth array 114 of the described flash memory device 100. (Refer to...) Figure 4 and Figure 7 The flash memory device 300 may include a memory cell array 310, row decoder blocks 320a and 320b, page buffer block 330, buffer block 340, control logic block 350, first pad 161, second pad 162 and third pad 163.

[0076] Memory cell array 310 may correspond to one of the first arrays 111 to the fourth array 114. Memory cell array 310 includes multiple memory blocks BLK1 to BLKz. Each of memory blocks BLK1 to BLKz includes multiple memory cells. Each of memory blocks BLK1 to BLKz can be connected to line decoder blocks 320a and 320b via at least one ground select line GSL, a word line WL, and at least one string select line SSL. The ground select line and the string select line may be included in the reference... Figure 4 The selection line is described.

[0077] Some of the word lines WL can be used as dummy word lines. Each of the memory blocks BLK1 to BLKz can be connected to the page buffer block 330 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz can be connected together via multiple bit lines BL.

[0078] In an exemplary embodiment, each of the memory blocks BLK1 to BLKz can be a unit of an erase operation. Memory cells belonging to each of the memory blocks BLK1 to BLKz can be erased simultaneously. As another example, each of the multiple memory blocks BLK1 to BLKz can be divided into multiple sub-blocks. Each of the multiple sub-blocks can correspond to a unit of an erase operation.

[0079] Line decoder blocks 320a and 320b can be used Figure 4 The first row decoder 131 to the fourth row decoder 134 are implemented using the portion corresponding to a specific array (e.g., the array corresponding to memory cell array 310). Row decoder blocks 320a and 320b are connected to memory cell array 310 via ground select line GSL, word line WL, and serial select line SSL. Row decoder blocks 320a and 320b operate under the control of control logic block 350.

[0080] Line decoder blocks 320a and 320b can decode the address ADDR received from buffer block 340 and can control the voltage to be applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded address.

[0081] Page buffer block 330 can be implemented using one of the page buffers 141 to 144 that corresponds to a specific array (e.g., the array corresponding to memory cell array 310). Page buffer block 330 is connected to memory cell array 310 via multiple bit lines BL. Page buffer block 330 is connected to third pad 163 via multiple data lines DL. Page buffer block 330 operates under the control of control logic block 350.

[0082] Buffer block 340 can receive commands (CMD) and addresses (ADDR) from an external device (e.g., an NPU) via a first channel CH1 implemented by the first pad 161. Buffer block 340 can operate under the control of control logic block 350. Buffer block 340 can transmit commands (CMD) to control logic block 350. Buffer block 340 can transmit addresses (ADDR) to line decoder blocks 320a and 320b.

[0083] Control logic block 350 can exchange control signals CTRL with external devices (e.g., NPUs) via a second channel CH2 implemented by the second pad 162. Control logic block 350 can allow buffer block 340 to route commands CMD and addresses ADDR.

[0084] During a write operation, page buffer block 330 can receive and store data to be written to the memory cell via the third pad 163. Furthermore, during a write operation, buffer block 340 can receive command CMD and address ADDR via the first pad 161.

[0085] Because data in a write operation is received via a third pad 163, which is separate from the first pad 161 through which the command CMD and address ADDR are received, the flash memory device 300 can receive data asynchronously relative to the command CMD and address ADDR. For example, the flash memory device 300 can receive the command CMD and address ADDR via the first pad 161 before or after receiving data via the third pad 163.

[0086] During a write operation, page buffer block 330 can apply voltages to multiple bit lines BL based on the stored data. Row decoder blocks 320a and 320b can apply voltages for the write operation to the serial select line SSL, word line WL, and ground select line GSL based on the address ADDR.

[0087] During a read operation, row decoder blocks 320a and 320b can apply voltages for the read operation to the serial select line SSL, word line WL, and ground select line GSL based on the address ADDR. Page buffer block 330 can latch (e.g., digitize) and store the voltage of the bit line BL, and can output the stored data to an external device (e.g., an NPU) via the third pad 163.

[0088] The flash memory device 300 performs write and read operations on a page-by-page basis. A page may include memory cells connected to a word line. Typically, thousands to tens of thousands of memory cells may be connected to a word line, and the number of memory cells connected to a word line can be further increased with technological advancements.

[0089] During a write operation, the flash memory device 300 can write two or more logical pages to a single page. A logical page is a virtual page created when two or more bits are written to a memory cell. The nth logical page (where n is a positive integer) can be implemented using the nth bit of the bits written to the memory cell.

[0090] In a read operation, the flash memory device 300 can read two or more logical pages from a single page. That is, the flash memory device 300 is capable of writing and reading bits whose number is a multiple of the number of memory cells contained in a page. Therefore, due to its sequential nature, the flash memory device 300 has a significant advantage in reading and writing data that is considered a single data block.

[0091] Synaptic data (or weighted data), sample data, inference data, etc., used at the NPU are characterized by large volume and sequentiality. According to an exemplary embodiment, the flash memory device 300 may include a third pad 163 implemented at the page buffer block 330 for communication with the NPU, and the flash memory device 300 may provide the NPU with superior performance in writing and reading sequential data based on its structural and operational characteristics.

[0092] In an exemplary embodiment, a portion of the third pad 163 can be used to transmit a synchronization signal for data input and output synchronization. For example, the synchronization signal can be triggered when data is input from the NPU to the page buffer block 330 via the third pad 163, thereby notifying the page buffer block 330 of the data latch timing. Alternatively, the synchronization signal can be triggered when data is output from the page buffer block 330 to the NPU via the third pad 163, thereby notifying the NPU of the data latch timing.

[0093] Figure 8 The construction of a page buffer block 400 according to an exemplary embodiment is shown. For example, Figure 8 The page buffer block 400 can be used with Figure 7 This corresponds to page buffer block 330. (See reference...) Figure 7 and Figure 8 Page buffer block 400 may include first page buffer unit 411 to m-th page buffer unit 41m (m is a positive integer). Each of the first page buffer unit 411 to m-th page buffer unit 41m may be connected to a data line.

[0094] Each page buffer unit may include a first page buffer 421 to an nth page buffer 42n (n is a positive integer). In the first page buffer unit 411 to the mth page buffer unit 41m, the first page buffer 421 may be connected to the first signal line S1, the second page buffer 422 may be connected to the second signal line S2, the third page buffer 423 may be connected to the third signal line S3, and the nth page buffer 42n may be connected to the nth signal line Sn.

[0095] Each of the first page buffer unit 411 to the m-th page buffer unit 41m can be connected to "n" bit lines and can be connected to one data line. That is, the ratio of the number of bit lines BL to the number of data lines DL can be n:1.

[0096] When the first signal line S1 is activated, each of the first page buffer unit 411 to the m-th page buffer unit 41m can connect the first bit line of the corresponding bit line to the corresponding data line. When the second signal line S2 is activated, each of the first page buffer unit 411 to the m-th page buffer unit 41m can connect the second bit line of the corresponding bit line to the corresponding data line.

[0097] When the third signal line S3 is activated, each of the first page buffer unit 411 to the m-th page buffer unit 41m can connect the third bit line of the corresponding bit line to the corresponding data line. When the n-th signal line Sn is activated, each of the first page buffer unit 411 to the m-th page buffer unit 41m can connect the n-th bit line of the corresponding bit line to the corresponding data line.

[0098] In cases where it is difficult to implement the third pad 163 at all page buffers belonging to page buffer block 400 (e.g., due to issues such as space or cost), such as Figure 8 As shown, an n:1 relationship can be provided between the bit line BL and the data line DL (e.g., multiplexing in the case of receiving data and demultiplexing in the case of output data).

[0099] exist Figure 8 In this structure, data can be input to page buffer block 330 in "n" cycles. Furthermore, data can be output from page buffer block 330 in "n" cycles.

[0100] In an exemplary embodiment, the bit line BL is shown as a relatively thick line, and the data line DL is shown as a relatively thin line. The bit line BL is affected by write and read operations of the memory cell array 310, and in some cases, high voltage may occur.

[0101] Conversely, the data line DL is unaffected by write and read operations of the memory cell array 310, and no high voltage is generated. Therefore, as a signal line to be connected to the third pad 163, the data line DL passing through the page buffer is preferred over the bit line BL.

[0102] Figure 9 The construction of a page buffer block 500 according to an exemplary embodiment is shown. For example, Figure 9 The page buffer block 500 can be used with Figure 7 This corresponds to page buffer block 330. (See reference...) Figure 7 and Figure 9 Page buffer block 500 may include first page buffer unit 511 to m-th page buffer unit 51m (m is a positive integer).

[0103] Each page buffer unit may include a first page buffer 521 to an nth page buffer 52n (n is a positive integer). The first page buffer 521 to the nth page buffer 52n may be connected to different data lines. That is, bit lines BL may be connected to data lines whose number is equal to the number of bit lines BL through the page buffer block 500, and may be connected to a third pad 163 whose number is equal to the number of bit lines / data lines.

[0104] exist Figure 9 In this structure, data can be input to page buffer block 500 in one cycle. Furthermore, data can be output from page buffer block 500 in one cycle.

[0105] Figure 10 The construction of a page buffer block 600 according to an exemplary embodiment is shown. For example, Figure 10 The page buffer block 600 can be used with Figure 7 This corresponds to page buffer block 330. (See reference...) Figure 7 and Figure 10 Page buffer block 600 may include first page buffer unit 611 to m-th page buffer unit 61m (m is a positive integer). Except that first page buffer unit 611 to m-th page buffer unit 61m are connected to the first data line DL1 instead of the data line DL, first page buffer unit 611 to m-th page buffer unit 61m may be connected to... Figure 8 The buffer units 411 on the first page to 41m on the m-th page are the same.

[0106] and Figure 8 Compared to the page buffer block 400, Figure 10 The page buffer block 600 may also include a selector 630 connected to the first data line DL1. The selector 630 may operate in response to a select signal SS. (Refer to the above...) Figure 8 As described in the first page buffer unit 411 to the m-th page buffer unit 41m, in response to the selection signal SS, the selector 630 can (e.g., by multiplexing in the case of receiving data and demultiplexing in the case of output data) connect the first data line DL1 to the second data line DL2 in a k:1 relationship (k is a positive integer).

[0107] In other words, the page buffer block 600 can be implemented to provide a hierarchical structure that provides an n:1 relationship (e.g., multiplexing in the case of receiving data and demultiplexing in the case of output data) at the first page buffer unit 611 to the m-th page buffer unit 61m, and a k:1 relationship (e.g., multiplexing in the case of receiving data and demultiplexing in the case of output data) at the selector 630. The second data line DL2 can be connected to the third pad 163. Finally, the bit line BL can be connected to the third pad 163 via an nk:1 relationship (e.g., by multiplexing in the case of receiving data and demultiplexing in the case of output data).

[0108] Figure 11 A flash memory device 700 based on a COP structure, according to an exemplary embodiment, is shown. (See also...) Figure 1 and Figure 11 The flash memory device 700 may include a first layer 800 and a second layer 900.

[0109] The second layer 900 may include a first active region 910 and elements 920, 930, and 940 on the first active region 910. The first active region 910 may be formed or disposed on a semiconductor substrate. Element 920 may be a transistor connected to a first via 841 (e.g., first transistor 920), and element 930 may be a transistor connected to a second via 842 (e.g., second transistor 930). Element 940 may be a third transistor connected to a pad 963. Pad 963 may be included in one of the first pad 161, the second pad 162, and the third pad 163.

[0110] The first transistor 920 may include a gate 921, an insulating layer 922, a first junction 923, and a second junction 924. The second transistor 930 may include a gate 931, an insulating layer 932, a first junction 933, and a second junction 934. The third transistor 940 may include a gate 941, an insulating layer 942, a first junction 943, and a second junction 944.

[0111] The first junction 923 of the first transistor 920 can be connected to the first peripheral circuit via 951. The first peripheral circuit via 951 can be connected to wiring. The second junction 924 of the first transistor 920 can be connected to the first through-hole 841. For example, the first through-hole 841 can be a through-hole via (THV).

[0112] The first junction 933 of the second transistor 930 can be connected to the second peripheral circuit via 952. The second peripheral circuit via 952 can be connected to wiring. The second junction 934 of the second transistor 930 can be connected to the second through-hole 842. For example, the second through-hole 842 can be a through-hole via (THV).

[0113] The first junction 943 of the third transistor 940 can be connected to the third peripheral circuit via 953. The third peripheral circuit via 953 can be connected to wiring. The second junction 944 of the third transistor 940 can be connected to the third via 962 via conductive connector 961.

[0114] In an exemplary embodiment, Figure 11 Only the components of the second layer 900 connected to the first through hole 841, the second through hole 842 and the third through hole 962 are shown. Figure 11 Additional elements not shown can be added to the second layer 900.

[0115] The first layer 800 may include a second active region 810 and a vertical structure on the second active region 810. The vertical structure may have the following structure: pairs of insulating layers 821 and conductive layers 822 are sequentially stacked on the second active region 810 along a third direction.

[0116] Vertical channels 831, 832, 833, 834, and 835 can penetrate the vertical structure in the third direction. Vertical channels 831, 832, 833, 834, and 835 can form, together with the vertical structure, a stack of cell transistors (e.g., including memory cell transistors (or memory cells) and select transistors) in the third direction.

[0117] The vertical structure may have a stepped shape in which the width in the first direction gradually decreases as it ascends in a third direction. In an exemplary embodiment, an information storage layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer may be formed between the vertical structure and vertical channels 831, 832, 833, 834, and 835. The conductive layer 822 of the vertical structure may be wiring that extends along the first direction and connects the unit transistors.

[0118] The first via 841 can penetrate the second active region 810 and can extend upwards in a third direction. The first via 841 can be connected to the first memory cell via 861 on the uppermost conductive layer 822 through the first upper conductive layer 851. The second via 842 can penetrate the second active region 810 and can extend upwards in a third direction. The second via 842 can be connected to the second memory cell via 862 on the uppermost conductive layer 822 through the second upper conductive layer 852.

[0119] exist Figure 11 The diagram shows a first through-hole 841 and a second through-hole 842, but multiple through-holes can be added to connect the second layer 900 to the conductive layer 822 of the vertical structure. Additionally, a pad 963 (or solder bump) and a third through-hole 962 are shown, but multiple pads (or solder bumps) and through-holes can be added to connect the second layer 900 to the third pad 963.

[0120] Figure 12 An example circuit diagram of a portion of a memory block BLKi in a memory cell array 310 is shown. (Refer to...) Figure 7 , Figure 11 and Figure 12 Multiple cell strings CS11, CS12, CS21, CS22, CS31, and CS32 can be disposed on the second active region 810. The multiple cell strings CS11, CS12, CS21, CS22, CS31, and CS32 can be connected together to a common source pole line CSL formed on (or in) the second active region 810.

[0121] Unit strings CS11, CS21, and CS31 can be connected to the first bit line BL1, and unit strings CS12, CS22, and CS32 can be connected to the second bit line BL2. Unit strings CS11, CS12, CS21, CS22, CS31, and CS32 are implemented with multiple rows and multiple columns. In an exemplary embodiment, the direction in which bit lines BL1 and BL2 extend can be the column direction, and the direction in which string selection lines SSL1, SSL2, and SSL3 extend can be the row direction.

[0122] The cell strings in each row can be connected together to the ground select line GSL, and can also be connected to the corresponding string select lines among the first string select lines SSL1 to the third string select lines SSL3. The cell strings in each column can be connected to the corresponding bit lines among the first bit line BL1 and the second bit line BL2.

[0123] Each cell string may include at least one ground select transistor GST connected to the ground select line GSL, multiple memory cell transistors MC1 to MC4 connected to multiple word lines WL1 to WL4 respectively, and a string select transistor SST1, SST2 or SST3 connected to the corresponding string select line SSL1, SSL2 or SSL3.

[0124] The ground select transistor GST can correspond to the vertical channels 831 to 835 and the portion of the bottommost conductive layer 822 adjacent to the vertical channels 831 to 835. The ground select line GSL can correspond to the bottommost conductive layer 822. Similarly, the first memory cell transistors MC1 to the fourth memory cell transistor MC4 and the word lines WL1 to WL4 can correspond to the second to fifth conductive layers 822 from the bottommost layer and the vertical channels 831 to 835.

[0125] The uppermost conductive layer 822 can be divided into three parts, each corresponding to one of the first select lines SSL1 to one of the third select lines SSL3. The first select lines SSL1 to the third select lines SSL3 can correspond to the divided parts of the uppermost conductive layer 822 and the vertical channels 831 to 835.

[0126] Figure 12 The example shown includes six unit transistors in a single unit string. However, it is understood that the number of unit transistors included in a single unit string is not limited. As the number of layers in the vertical structure increases, the number of unit transistors included in a single unit string can also increase.

[0127] Furthermore, the number of cell transistors belonging to a cell string that will be used as ground selection transistors, memory cell transistors, or string selection transistors can be variable. Some of the cell transistors belonging to a cell string can be used as dummy memory cell transistors that do not store data.

[0128] Figure 13 An example of a flash memory device 100 implemented according to an exemplary embodiment is shown by bonding. (Refer to...) Figure 11 and Figure 13 , Figure 13 The first layer 110 can be rotated approximately 180 degrees around the second direction. Figure 11 The first layer 800 corresponds to this. The first memory cell via 861 and the second memory cell via 862 may not be connected to the first through hole 841 and the second through hole 842, but the first memory cell via 861 and the second memory cell via 862 may extend in a direction perpendicular to the second active region 810 to connect to the pad (or solder bump).

[0129] Furthermore, the remaining conductive layer 822 may extend in a direction perpendicular to the second active region 810 to connect with the pad (or solder bump). Additionally, vertical channels 831 to 835 may extend in a direction perpendicular to the second active region 810 to connect with the pad (or solder bump). Figure 13 The first layer 110 pad 116 (or solder bump) can be with Figure 11 The first layer 800, the conductive layer 822, is connected to the vertical channels 831 to 835.

[0130] Figure 13 The second layer 120 can have Figure 11 The second layer has a shape of 900. Figure 11 The first transistor 920 and the second transistor 930 may not be connected to the first via 841 and the second via 842, but instead be connected to a conductive element extending in a direction perpendicular to the first active region 910, so as to... Figure 13 Connect the pad 164 (or solder bump).

[0131] The flash memory device 100 can be implemented by connecting the pads 116 of the first layer 110 and the pads 164 of the second layer 120 via bonding (e.g., wafer-level bonding).

[0132] Figure 14 This is a block diagram illustrating a computing device 1000 according to an exemplary embodiment. (Refer to...) Figure 14 The computing device 1000 may include a processor 1100 and a flash memory device 1200. For example, the processor 1100 may include a neural processor or a graphics processor.

[0133] The processor 1100 and flash memory device 1200 can be based on a reference. Figure 6 The example described is used for connection. Processor 1100 can be connected with... Figure 6 The NPU 200 is compatible, and the flash memory device 1200 can be used with... Figure 6 The flash memory device 100 is compatible.

[0134] Flash memory device 1200 can provide a path for data input and output to processor 1100 via the third pad 163 of the data line DL connected to page buffer block 330 (see reference). Figure 7 Therefore, data transfer with ultra-wide bandwidth can be achieved between the processor 1100 and the flash memory device 1200.

[0135] The flash memory device 1200 can provide the processor 1100 with a first pad 161 and a second pad 162 that support the transfer of commands CMD and addresses ADDR according to the interface of a general-purpose flash memory device. Therefore, there is no need for the cost (or time or resources) required to design additional interfaces.

[0136] In the above description of the exemplary embodiments, some components are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., can be used to distinguish components from each other without additionally limiting one or more inventive concepts. For example, the terms "first," "second," "third," etc., do not specify an order or any form of numerical meaning.

[0137] In the above description of exemplary embodiments, components can be described using blocks. Blocks can be implemented using various hardware devices (such as integrated circuits, application-specific integrated circuits (ASCIs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in the hardware devices, software (such as applications), or a combination of hardware devices and software. Furthermore, blocks can include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0138] According to an exemplary embodiment, the flash memory device can receive command, address, and control signals through a general-purpose input and output interface, and can exchange data through pads directly connected to data lines. The pads of the flash memory device can be directly connected to the pads of the processor. Therefore, a flash memory device and a computing device are provided that can provide ultra-wide bandwidth for data while suppressing changes in the interface of command, address, and control signals.

[0139] Although exemplary embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of one or more inventive concepts as set forth in the claims.

Claims

1. A flash memory device, comprising: The first pad is configured to bond to an external semiconductor chip; The second pad is configured to bond to an external semiconductor chip; The third pad is configured to be bonded to an external semiconductor chip; A memory cell array, comprising memory cells; The row decoder block is connected to the memory cell array via word lines and is configured to select one of the address selection word lines provided to the row decoder block; The buffer block is configured to store commands and addresses received from an external semiconductor chip via a first pad and to provide the addresses to the line decoder block; The page buffer block is connected to the memory cell array via bit lines and to the third pad via data lines, and is configured to exchange data signals with an external semiconductor chip via the data lines and the third pad; as well as The control logic block is configured to receive commands from the buffer block, receive control signals from an external semiconductor chip via a second pad, and control the line decoder block and the page buffer block based on the received commands and control signals. in: A page buffer block includes page buffer units that are connected to two or more bit lines and one data line, respectively. Each of the page buffer units includes two or more page buffers, each connected to a bit line and together connected to a data line; as well as The two or more page buffers are configured to be electrically connected in sequence to a data line.

2. The flash memory device according to claim 1, wherein, The first pad, the second pad, and the third pad are configured to connect to an external semiconductor chip via wafer-to-wafer bonding.

3. The flash memory device according to claim 1, further comprising: The peripheral circuit area is located on the first active area, and the line decoder block, buffer block, page buffer block and control logic block are implemented in the peripheral circuit area. as well as The memory cell region is located on the second active region above the peripheral circuit region, and the memory cell array is implemented in the memory cell region. The first pad, the second pad, and the third pad are disposed below the first active region and penetrate the first active region to be electrically connected to the peripheral circuit region.

4. The flash memory device according to claim 1, further comprising: Peripheral circuit chips; as well as Memory cell chip, The peripheral circuit chip includes a first active region, on which the line decoder block, buffer block, page buffer block, and control logic block are implemented. The memory cell chip includes a second active region, and the memory cell array is implemented on the second active region.

5. The flash memory device according to claim 4, wherein, The first pad, the second pad, and the third pad are disposed below the first active region and penetrate the first active region to be electrically connected to the peripheral circuit chip.

6. The flash memory device according to claim 5, wherein: The peripheral circuit chip also includes a fourth pad disposed on the line decoder block, buffer block, page buffer block, and control logic block; and The memory cell chip also includes a fifth pad disposed on the memory cell array and configured to be bonded to the fourth pad.

7. The flash memory device according to claim 1, wherein, Page buffer blocks exchange data signals asynchronously with respect to commands and addresses.

8. A flash memory device, comprising: The first pad is configured to bond to an external semiconductor chip; The second pad is configured to bond to an external semiconductor chip; The third pad is configured to be bonded to an external semiconductor chip; A memory cell array, comprising memory cells; The row decoder block is connected to the memory cell array via word lines and is configured to select one of the address selection word lines provided to the row decoder block; The buffer block is configured to store commands and addresses received from an external semiconductor chip via a first pad and to provide the addresses to the line decoder block; The page buffer block is connected to the memory cell array via bit lines and to the third pad via data lines, and is configured to exchange data signals with an external semiconductor chip via the data lines and the third pad; as well as The control logic block is configured to receive commands from the buffer block, receive control signals from an external semiconductor chip via a second pad, and control the line decoder block and the page buffer block based on the received commands and control signals. in: A page buffer block includes page buffer units that are connected to two or more bit lines and one intermediate data line. Each of the page buffer units includes two or more page buffers, each connected to a bit line and together connected to an intermediate data line; The two or more page buffers are configured to be electrically connected sequentially to an intermediate data line; and The page buffer block also includes a selector configured to select a portion of the intermediate data line for electrical connection with the data line.

9. A computing device, comprising: Memory unit chips, including flash memory units; The peripheral circuit chip is configured to access the flash memory cell; as well as A logic chip is configured to store first data in a flash memory cell via peripheral circuitry, read second data from the flash memory cell, and perform at least one operation using the first and second data. In this configuration, peripheral circuit chips are stacked on top of logic chips, and memory cell chips are stacked on top of peripheral circuit chips. The memory cell chip also includes word lines and bit lines connected to the flash memory cells. The peripheral circuitry includes a row decoder block connected to the word lines via a first pad and a page buffer block connected to the bit lines via a second pad. The peripheral circuit chip also includes a third pad that is connected to the page buffer block via a data line and coupled to the logic chip, and in: A page buffer block includes page buffer units that are connected to two or more bit lines and one data line, respectively. Each of the page buffer units includes two or more page buffers, each connected to a bit line and together connected to a data line; and The two or more page buffers are configured to be electrically connected in sequence to a data line.

10. The computing device according to claim 9, wherein, The logic chip is also configured to transmit commands and addresses to the peripheral circuit chip via the first pad, transmit control signals to the peripheral circuit chip via the second pad, and exchange first data and second data with the logic chip via the third pad.

11. The computing device according to claim 10, wherein, The first pad transmits information in bytes, and the third pad exchanges the first and second data in units of one hundred bytes or more.

12. The computing device according to claim 9, wherein, Logic chips include graphics processors or neural processors.

13. A computing device, comprising: Memory unit chips, including flash memory units; The peripheral circuit chip is configured to access the flash memory cell; as well as A logic chip is configured to store first data in a flash memory cell via peripheral circuitry, read second data from the flash memory cell, and perform at least one operation using the first and second data. In this configuration, peripheral circuit chips are stacked on top of logic chips, and memory cell chips are stacked on top of peripheral circuit chips. The memory cell chip also includes word lines and bit lines connected to the flash memory cells. The peripheral circuitry includes a row decoder block connected to the word lines via a first pad and a page buffer block connected to the bit lines via a second pad. The peripheral circuit chip also includes a third pad that is connected to the page buffer block via a data line and coupled to the logic chip, and in: A page buffer block includes page buffer units that are connected to two or more bit lines and one intermediate data line. Each of the page buffer units includes two or more page buffers, each connected to a bit line and together connected to an intermediate data line; The two or more page buffers are configured to be electrically connected sequentially to an intermediate data line; and The page buffer block also includes a selector configured to select a portion of the intermediate data line for electrical connection with the data line.

14. A computing device, comprising: Neural processor chip; as well as Flash memory chip, connected to neural processor chip, The flash memory chips include: The first pad is attached to the neural processor chip; The second pad is attached to the neural processor chip; The third pad is attached to the neural processor chip; A memory cell array, comprising memory cells; The row decoder block is connected to the memory cell array via word lines and is configured to select one of the address selection word lines provided to the row decoder block; The buffer block is configured to store commands and addresses received from the neural processor chip via the first pad and to provide the addresses to the line decoder block; Page buffer blocks, connected to the memory cell array via bit lines and to the third pad via data lines, are configured to exchange data signals with the neural processor chip via the data lines and the third pad; and The control logic block is configured to receive commands from the buffer block, receive control signals from the neural processor chip via the second pad, and control the line decoder block and page buffer block based on the received commands and control signals. in: A page buffer block includes page buffer units that are connected to two or more bit lines and one data line, respectively. Each of the page buffer units includes two or more page buffers, each connected to a bit line and together connected to a data line; and The two or more page buffers are configured to be electrically connected in sequence to a data line.

15. The computing device according to claim 14, wherein, The first pad transmits information in bytes, and the third pad exchanges data signals in units of one hundred bytes or more.

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