Semiconductor devices

Abstract

Various embodiments of this disclosure relate to semiconductor devices. One semiconductor device includes: a semiconductor chip including a field-effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected via a metal plate to a pad for a source electrode of the semiconductor chip; a lead coupling portion integrally formed with the lead; and a sealing portion for sealing them. A back surface electrode for a drain electrode of the semiconductor chip is bonded to the die pad via the first bonding material, the metal plate is bonded to the pad for the source electrode of the semiconductor chip via a second bonding material, and the metal plate is bonded to the lead coupling portion via a third bonding material. The first, second, and third bonding materials are conductive, and the elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

Description

[0001] Cross-references to related applications

[0002] The entire disclosure of Japanese Patent Application No. 2019-192015, filed on October 21, 2019, including the specification, drawings and abstract, is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device in which a semiconductor chip comprising a field-effect transistor for switching is sealed. Background Technology

[0004] An inverter circuit, widely used as an example of a power supply circuit, has the following configuration: a power MOSFET for high-side switching and a power MOSFET for low-side switching are connected in series between a terminal supplied with the power supply voltage and a terminal supplied with the ground voltage. The power supply voltage can be converted by the inverter circuit by controlling the gate voltages of the power MOSFETs for high-side switching and low-side switching using a control circuit.

[0005] Patent document 1 discloses a technology relating to a semiconductor device in which: a semiconductor chip including a power MOSFET for high-side switching, a semiconductor chip including a power MOSFET for low-side switching, and a semiconductor chip for controlling them are sealed.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2018-121035 Summary of the Invention

[0008] It is desirable to improve the reliability of semiconductor devices that contain semiconductor chips including field-effect transistors for switching.

[0009] Other objectives and new features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to an embodiment, a semiconductor device includes: a first semiconductor chip including a first field-effect transistor for switching; a first chip mounting portion on which the first semiconductor chip is mounted via a first bonding material; a first lead electrically connected via a first metal plate to a first pad for a source electrode of the first semiconductor chip; a first metal portion integrally formed with the first lead; and a sealing body for sealing them. A first back surface electrode for a drain electrode of the first semiconductor chip is bonded to the first chip mounting portion via the first bonding material, the first metal plate is bonded to the first pad for a source electrode of the first semiconductor chip via a second bonding material, and the first metal plate is bonded to the first metal portion via a third bonding material. The first, second, and third bonding materials are conductive. The elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

[0011] According to the embodiments, the reliability of semiconductor devices can be improved. Attached Figure Description

[0012] Figure 1 This is a circuit diagram showing an inverter circuit using a semiconductor device according to an embodiment;

[0013] Figure 2 This is a top view of a semiconductor device according to an embodiment;

[0014] Figure 3 This is a bottom view of a semiconductor device according to an embodiment;

[0015] Figure 4 This is a plan perspective view of a semiconductor device according to an embodiment;

[0016] Figure 5 This is a plan perspective view of a semiconductor device according to an embodiment;

[0017] Figure 6 This is a plan perspective view of a semiconductor device according to an embodiment;

[0018] Figure 7 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0019] Figure 8 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0020] Figure 9 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0021] Figure 10 This is a cross-sectional view of a semiconductor device according to an embodiment;

[0022] Figure 11This is a plan view of a semiconductor device according to an embodiment during the manufacturing process;

[0023] Figure 12 It is from Figure 11 A plan view of the semiconductor device during the ongoing manufacturing process;

[0024] Figure 13 In the context of Figure 12 Cross-sectional view of a semiconductor device manufactured using the same process;

[0025] Figure 14 In the context of Figure 12 Cross-sectional view of a semiconductor device manufactured using the same process;

[0026] Figure 15 In the context of Figure 12 Cross-sectional view of a semiconductor device manufactured using the same process;

[0027] Figure 16 It is from Figure 12 A plan view of the semiconductor device during the ongoing manufacturing process;

[0028] Figure 17 In the context of Figure 16 Cross-sectional view of a semiconductor device manufactured using the same process;

[0029] Figure 18 In the context of Figure 16 Cross-sectional view of a semiconductor device manufactured using the same process;

[0030] Figure 19 In the context of Figure 16 Cross-sectional view of a semiconductor device manufactured using the same process;

[0031] Figure 20 It is from Figure 16 A plan view of the semiconductor device during the ongoing manufacturing process;

[0032] Figure 21 It is from Figure 20 Cross-sectional view of a semiconductor device during the ongoing manufacturing process;

[0033] Figure 22 In the context of Figure 21 Cross-sectional view of a semiconductor device manufactured using the same process;

[0034] Figure 23 It is from Figure 21 Cross-sectional view of a semiconductor device during the ongoing manufacturing process;

[0035] Figure 24 In the context of Figure 23 Cross-sectional view of a semiconductor device manufactured using the same process;

[0036] Figure 25 It is from Figure 23 Cross-sectional view of a semiconductor device during the ongoing manufacturing process;

[0037] Figure 26 In the context of Figure 25 Cross-sectional view of a semiconductor device manufactured using the same process;

[0038] Figure 27 This is a cross-sectional view showing an example of mounting a semiconductor device according to an embodiment;

[0039] Figure 28 This is a cross-sectional view showing an example of mounting a semiconductor device according to an embodiment;

[0040] Figure 29 This is a cross-sectional view showing an example of mounting a semiconductor device according to an embodiment;

[0041] Figure 30 This is a cross-sectional view showing an example of mounting a semiconductor device according to an embodiment;

[0042] Figure 31 It is a table summarizing the characteristics of low-elasticity and high-elasticity bonded materials for comparison; and

[0043] Figure 32 This is a table summarizing the bonding materials in each of the embodiments in this example and another example. Detailed Implementation

[0044] In the following embodiments, for convenience, the invention will be described in multiple sections or embodiments as needed. However, unless otherwise stated, these sections or embodiments are not unrelated to each other, and one section or embodiment is related to the whole or part of another section or embodiment as a modification, detail, or supplementary explanation of another section or embodiment. Similarly, in the following embodiments, unless otherwise stated or except where the quantity is obviously limited to a specific quantity in principle, when referring to the quantity of elements (including number of pieces, values, quantities, ranges, etc.), the quantity of elements is not limited to a specific quantity, and quantities greater than or less than that specific quantity may also apply. Furthermore, in the following embodiments, it is self-evident that components (including element steps) are not always indispensable unless otherwise stated or except where the component is obviously indispensable in principle. Similarly, in the following embodiments, when referring to the shape of components, the positional relationship of components, etc., generally approximate and similar shapes are included unless otherwise stated or except where it can be imagined that they are obviously excluded in principle. This also applies to the following numerical values ​​and ranges.

[0045] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same function are denoted by the same reference numerals, and repeated descriptions of these components will be omitted. Furthermore, unless specifically required by the following embodiments, descriptions of the same and similar parts will generally not be repeated.

[0046] Similarly, in some of the figures used in the following embodiments, shading lines are even omitted in the cross-sectional views to make the figures easier to observe. Additionally, shading lines are even used in the plan views to make the figures easier to observe.

[0047] Furthermore, in this application, field-effect transistors are described as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or simply MOS, but this does not mean that non-oxide films are excluded as gate insulating films. That is, when MOSFETs are mentioned in this application, MOSFETs include not only MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) that use an oxide film (silicon oxide film) as the gate insulating film, but also MISFETs that use an insulating film other than an oxide film (silicon oxide film) as the gate insulating film.

[0048] (First Embodiment)

[0049] <Circuit Configuration>

[0050] Figure 1 This is a circuit diagram illustrating an example of an electronic device using a semiconductor device (semiconductor package) PKG according to this embodiment, and a circuit diagram showing the case where the inverter circuit INV is configured using the semiconductor device PKG. Figure 1 In the semiconductor chip CPH, a portion surrounded by a dashed line represented by CPH is formed; in the semiconductor chip CPL, a portion surrounded by a dashed line represented by CPL is formed; in the semiconductor chip CPC, a portion surrounded by a dashed line represented by CPC is formed; and in the semiconductor device PKG, a portion surrounded by a single-dot dashed line represented by PKG is formed.

[0051] exist Figure 1The semiconductor device PKG used in the inverter circuit INV shown includes two power MOSFETs 1 and 2, a sensing MOSFET 3 for sensing the current flowing in power MOSFET 1, a sensing MOSFET 4 for sensing the current flowing in power MOSFET 2, and a control circuit CLC. The control circuit CLC is formed in a semiconductor chip (control semiconductor chip) CPC, power MOSFET 1 and sensing MOSFET 3 are formed in a semiconductor chip (high-side semiconductor chip, power chip) CPH, and power MOSFET 2 and sensing MOSFET 4 are formed in a semiconductor chip (low-side semiconductor chip, power chip) CPL. These three semiconductor chips, CPC, CPH, and CPL, are then sealed in the same package to form the semiconductor device PKG.

[0052] The control circuit CLC includes a high-side driver circuit for controlling the gate potential of power MOSFET 1 and a low-side driver circuit for controlling the gate potential of power MOSFET 2. The control circuit CLC is configured to control the operation of power MOSFETs 1 and 2 by controlling the corresponding gate potentials of power MOSFETs 1 and 2 according to signals provided to the control circuit CLC from the control circuit CT outside the semiconductor device PKG.

[0053] The gate of power MOSFET 1 is connected to the high-side driver circuit of the control circuit CLC, and the gate of power MOSFET 2 is connected to the low-side driver circuit of the control circuit CLC. The drain D1 of power MOSFET 1 is connected to terminal TE1, the source S1 of power MOSFET 1 is connected to terminal TE2, the drain D2 of power MOSFET 2 is connected to terminal TE3, and the source S2 of power MOSFET 2 is connected to terminal TE4. The control circuit CLC is connected to terminal TE5, and terminal TE5 is connected to the control circuit CT located outside the semiconductor device PKG. Terminals TE1, TE2, TE3, TE4, and TE5 are all external connection terminals of the semiconductor device PKG and are formed by leads LD as described below. Terminal TE1 is provided with a power supply potential (VIN), and terminal TE4 is provided with a reference potential lower than the power supply potential (e.g., ground potential (GND)). Terminals TE2 and TE3 are externally electrically connected to the semiconductor device PKG. Therefore, power MOSFET 1 and power MOSFET 2 are connected in series between terminal TE1, which provides the power supply potential, and terminal TE4, which provides the reference potential.

[0054] The connection point TE6 between the source S1 of power MOSFET 1 and the drain D2 of power MOSFET 2 is located outside the semiconductor device PKG (e.g., on the wiring board on which the semiconductor device PKG is mounted), and the connection TE6 is connected to the load (in this case, the coil CL of the motor MOT). The DC power supplied to the inverter circuit INV by the semiconductor device PKG is converted into AC power by the inverter circuit INV and then supplied to the load (in this case, the coil CL of the motor MOT).

[0055] Power MOSFET 1 corresponds to a field-effect transistor for high-side switching (high-potential-side switching), and power MOSFET 2 corresponds to a field-effect transistor for low-side switching (low-potential-side switching). Each of power MOSFETs 1 and 2 can be considered as a power transistor used for switching.

[0056] The current flowing in power MOSFET 1 is sensed by sensing MOSFET 3, and power MOSFET 1 is controlled based on the current flowing in sensing MOSFET 3. Similarly, the current flowing in power MOSFET 2 is sensed by sensing MOSFET 4, and power MOSFET 2 is controlled based on the current flowing in sensing MOSFET 4.

[0057] The drain D3 of sensing MOSFET 3 is electrically connected to the drain D1 of power MOSFET 1, and the gate of sensing MOSFET 3 is electrically connected to the gate of power MOSFET 1. The source S3 of sensing MOSFET 3 is connected to the control circuit CLC. The drain D4 of sensing MOSFET 4 is electrically connected to the drain D2 of power MOSFET 2, and the gate of sensing MOSFET 4 is electrically connected to the gate of power MOSFET 2. The source S4 of sensing MOSFET 4 is connected to the control circuit CLC.

[0058] <Structure of Semiconductor Devices>

[0059] Figure 2 This is a top view of the semiconductor device PKG according to this embodiment. Figure 3 This is a bottom view (rear view) of a semiconductor device PKG. Figures 4 to 6 It is a planar perspective view of a semiconductor device PKG, and Figures 7 to 10 This is a cross-sectional view of a semiconductor device PKG. Figure 4 A plan perspective view of the semiconductor device PKG, viewed from the lower surface side through the sealing portion MR, is shown. Similarly, Figure 5 A planar perspective view of the semiconductor device PKG on its lower surface side is shown, wherein (also omitted) Figure 4The other wires BW and metal plates MP1 and MP2 are used to observe the semiconductor device PKG. Additionally, Figure 6 A planar perspective view of the semiconductor device PKG on its lower surface side is shown, wherein (also omitted) Figure 5 The semiconductor chips CPC, CPH, and CPL are observed in the semiconductor device PKG. Figures 3 to 6 In this context, the semiconductor device PKG has the same orientation. Furthermore, in... Figures 4 to 6 In the diagram, the outer periphery of the sealing portion MR is indicated by a dashed line. The semiconductor device PKG... Figures 2 to 4 The cross section at position A1-A1 in the middle almost corresponds to Figure 7 Semiconductor device PKG in Figures 2 to 4 The cross section at position A2-A2 in the middle almost corresponds to Figure 8 Semiconductor device PKG in Figures 2 to 4 The cross section at position A3-A3 in the middle almost corresponds to Figure 9 And semiconductor device PKG in Figures 2 to 4 The cross section at position A4-A4 in the middle almost corresponds to Figure 10 Note that in each plan view, the reference numeral X indicates a first direction (hereinafter referred to as the X direction), and the reference numeral Y indicates a second direction orthogonal to the first direction X (hereinafter referred to as the Y direction). That is, the X direction and the Y direction are orthogonal to each other.

[0060] Figures 2 to 10 The semiconductor device (semiconductor package) PKG shown according to this embodiment is a resin-sealed semiconductor package type semiconductor device, and in this case, it is an SOP (small package) type semiconductor device. Reference will be made below. Figures 2 to 10 Describe the configuration of the semiconductor device PKG.

[0061] Figures 2 to 10 The semiconductor device PKG shown according to this embodiment includes: die pads (chip mounting portions) DPC, DPH and DPL; semiconductor chips CPC, CPH and CPL mounted on the main surfaces of the die pads DPC, DPH and DPL; metal plates MP1 and MP2; multiple wires (bonding wires) BW; multiple leads LD; and a sealing portion (sealing body) MR that seals them.

[0062] The sealing part MR, which is a resin seal (resin seal body), is made of resin material such as thermosetting resin material and may contain fillers. For example, the sealing part MR can be formed by using epoxy resin containing fillers. In addition to epoxy resin, for example, for the purpose of reducing stress, biphenyl thermosetting resin with added phenolic curing agent, silicone rubber, filler, etc. can be used as the material of the sealing part MR.

[0063] The sealing portion MR has a main surface (upper surface) MRa, a back surface (lower surface, bottom surface) MRb located on the side opposite to the main surface MRa, and side surfaces MRc1, MRc2, MRc3, and MRc4 intersecting the main surface MRa and the back surface MRb. That is, the sealing portion MR has the appearance of a thin plate shape surrounded by the main surface MRa, the back surface MRb, and the side surfaces MRc1, MRc2, MRc3, and MRc4. Among the side surfaces MRc1, MRc2, MRc3, and MRc4 of the sealing portion MR, side surfaces MRc1 and MRc3 are located on opposite sides, side surfaces MRc2 and MRc4 are located on opposite sides, side surface MRc1 intersects with side surfaces MRc2 and MRc4, and side surface MRc3 intersects with side surfaces MRc2 and MRc4. Side surfaces MRc1 and MRc3 are approximately parallel to the X direction, and side surfaces MRc2 and MRc4 are approximately parallel to the Y direction. Similarly, each of the main surface MRa and the back surface MRb is a surface that is parallel to both the X and Y directions.

[0064] The planar shape of the sealing part MR is, for example, a rectangle, that is, the planar shapes of the main surface MRa and the back surface MRb of the sealing part MR are, for example, rectangles. Note that the rectangle constituting the planar shape of the sealing part MR is a rectangle having a side parallel to the X direction and a side parallel to the Y direction, and the dimension of the sealing part MR in the X direction is larger than its dimension in the Y direction.

[0065] Each of the multiple lead LDs has a portion sealed within a sealing portion MR and another portion protruding outward from the side surface of the sealing portion MR. Hereinafter, the portion of the lead LD located within the sealing portion MR is referred to as the inner lead portion, and the portion of the lead LD located outside the sealing portion MR is referred to as the outer lead portion. A plating layer (not shown), such as a solder plating layer, can be formed on the outer lead portion of the lead LD. Therefore, mounting the semiconductor device PKG onto a wiring board or similar surface (solder mounting) becomes easy.

[0066] Note that the semiconductor device PKG according to this embodiment has a structure in which a portion of each lead LD (outer lead portion) protrudes from the side surface of the seal portion MR, which will be described below. However, the structure of the semiconductor device PKG is not limited to this. For example, a configuration in which each lead LD hardly protrudes from the side surface of the seal portion MR, and a portion of each lead LD is exposed on the back surface MRb of the seal portion MR (SON (Small Outline Leadless Package) configuration).

[0067] The plurality of lead LDs includes a lead LD disposed on the side surface MRc1 near the sealing portion MR and a lead LD disposed on the side surface MRc3 near the sealing portion MR. Figures 2 to 10 In the illustrated case, the leads LD are not arranged on the side of the seal MR near the side surface MRc2 and the side of the seal MR near the side surface MRc4. In the plan view, the plurality of leads LD arranged on the side of the seal MR near the side surface MRc1 extend in the Y direction and are arranged at predetermined intervals in the X direction. Similarly, in the plan view, the plurality of leads LD arranged on the side of the seal MR near the side surface MRc3 extend in the Y direction and are arranged at predetermined intervals in the X direction. The outer lead portion of each lead LD is bent such that the lower surface near the end of the outer lead portion lies on a plane substantially the same as the back surface MRb of the seal MR. The outer lead portion of the lead LD serves as an external connection terminal (external terminal) of the semiconductor device PKG. Note that the plurality of leads LD of the semiconductor device PKG include leads LD1, LD2, LD3, LD4, LD5a, LD5b, LD6, LD7 and LD8 described below.

[0068] Die pads (DPC, DPH, and DPL) are chip mounting sections for mounting semiconductor chips (CPC, DPH, and DPL). Each die pad in DPC, DPH, and DPL has a planar shape, for example, a rectangle with sides parallel to the X-direction and sides parallel to the Y-direction. Figures 2 to 10 In this case, since the size of each semiconductor chip in CPC, CPH, and CPL is larger in the Y direction than in the X direction, the size of each die pad in DPC, DPH, and DPL is larger in the Y direction than in the X direction.

[0069] Die pads DPH, DPC, and DPL are arranged in this order in the X direction. Therefore, die pad DPC is positioned between die pads DPH and DPL. Die pads DPH and DPC are adjacent to each other in the X direction but do not contact each other, and are separated by a predetermined interval, with a portion of the seal MR located between die pads DPH and DPC. Similarly, die pads DPC and DPL are adjacent to each other in the X direction but do not contact each other, and are separated by a predetermined interval, with another portion of the seal MR located between die pads DPC and DPL.

[0070] The die pads DPC, DPH, and DPL, as well as the multiple leads LD, are made of a conductive material (metallic material), and preferably of copper (Cu) or a copper alloy. Furthermore, the die pads DPC, DPH, and DPL, the multiple leads LD, and the lead coupling portions LB1, LB2, LB3, and LB4 are preferably formed of the same material (the same metallic material), thereby facilitating the fabrication of a lead frame coupling the die pads DPC, DPH, and DPL with the multiple leads LD, and making it easier to fabricate a semiconductor device PKG using the lead frame.

[0071] The die pad DPC has a main surface DPCa on which the semiconductor chip CPC is mounted, and a back surface DPCb located on the side opposite to the main surface DPCa. Similarly, the die pad DPH has a main surface DPHa on which the semiconductor chip CPH is mounted, and a back surface DPHb located on the side opposite to the main surface DPHa. Furthermore, the die pad DPL has a main surface DPLa on which the semiconductor chip CPL is mounted, and a back surface DPLb located on the side opposite to the main surface DPLa.

[0072] At least a portion of each of the die pads DPC, DPH, and DPL is sealed by a sealing portion MR, and in this embodiment, the back surface DPCb of die pad DPC, the back surface DPHb of die pad DPH, and the back surface DPLb of die pad DPL are exposed from the main surface MRa of the sealing portion MR. Therefore, the heat generated during the operation of the semiconductor chips CPC, CPH, and CPL can be dissipated primarily from the back surfaces of the semiconductor chips CPC, CPH, and CPL to the outside of the semiconductor device PKG via the die pads DPC, DPH, and DPL.

[0073] Furthermore, in the die pads DPC, DPH, and DPL, the leads LD, and the lead coupling sections LB2 and LB4, a plating layer made of silver (Ag) or the like can be formed (not shown) in the areas where semiconductor chips CPC, CPH, and CPL are mounted, in the areas where wires BW are connected, and in the areas where metal plates MP1 and MP2 are connected. Therefore, the semiconductor chips CPC, CPH, and CPL, the metal plates MP1 and MP2, and the wires BW can be more accurately connected to the die pads DPC, DPH, and DPL, the leads LD, and the lead coupling sections LB2 and LB4.

[0074] The semiconductor chip CPH is mounted on the main surface DPHa of the die pad DPH, with its back surface pointing towards the die pad DPH. The semiconductor chip CPH is mounted on the main surface DPHa of the die pad DPH via a conductive bonding material (adhesive layer) BD1. A back surface electrode (electrode, drain electrode, back surface drain electrode) BEH is formed on the back surface (the entire back surface) of the semiconductor chip CPH, and the back surface electrode BEH is bonded and electrically connected to the die pad DPH via the conductive bonding material BD1.

[0075] Similarly, the semiconductor chip CPL is mounted on the main surface DPLa of the die pad DPL, with its back surface pointing towards the die pad DPL. The semiconductor chip CPL is mounted on the main surface DPLa of the die pad DPL via a conductive bonding material (adhesive layer) BD2. Back surface electrodes (electrodes, drain electrodes, back surface drain electrodes) BEL are formed on the back surface (the entire back surface) of the semiconductor chip CPL, and the back surface electrodes BEL are bonded and electrically connected to the die pad DPL via the conductive bonding material BD2.

[0076] Additionally, the semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC, with its back surface facing the die pad DPC. The semiconductor chip CPC is mounted on the main surface DPCa of the die pad DPC via a bonding material (adhesive layer) BD3, but the bonding material BD3 can be conductive or insulating.

[0077] Each of the semiconductor chips CPC, CPH, and CPL has a planar shape, for example, that of a rectangle, and more specifically, a rectangle having sides parallel to the X-direction and sides parallel to the Y-direction. The planar dimensions (planar area) of the die pad DPH are larger than the planar dimensions of the semiconductor chip CPH, the planar dimensions of the die pad DPL are larger than the planar dimensions of the semiconductor chip CPL, and the planar dimensions of the die pad DPC are larger than the planar dimensions of the semiconductor chip CPC. Therefore, in the planar diagram, the semiconductor chip CPH is included in the main surface DPHa of the die pad DPH, the semiconductor chip CPL is included in the main surface DPLa of the die pad DPL, and the semiconductor chip CPC is included in the main surface DPCa of the die pad DPC. The semiconductor chips CPC, CPH, and CPL are sealed within a sealing portion MR and do not protrude from the sealing portion MR.

[0078] The back surface electrode BEH of semiconductor chip CPH serves as the drain electrode of power MOSFET 1 and the drain electrode of sensing MOSFET 3. Therefore, the back surface electrode BEH of semiconductor chip CPH is electrically connected to the drain (D1) of power MOSFET 1 and the drain (D3) of sensing MOSFET 3 formed in semiconductor chip CPH. Similarly, the back surface electrode BEL of semiconductor chip CPL serves as the drain electrode of power MOSFET 2 and the drain electrode of sensing MOSFET 4. Therefore, the back surface electrode BEL of semiconductor chip CPL is electrically connected to the drain (D2) of power MOSFET 2 and the drain (D4) of sensing MOSFET 4 formed in semiconductor chip CPL.

[0079] The bonding materials BD1 and BD2 are preferably made of a paste conductive bonding material, such as silver paste (silver paste bonding material). In the semiconductor device PKG, the paste conductive bonding material constituting each of the bonding materials BD1 and BD2 is already in a solidified state.

[0080] On the front surface of the semiconductor chip CPH (the main surface on the side opposite to where the back surface electrode BEH is formed), there are: a bonding pad PDHG for the gate, bonding pads PDHS1 and PDHS2 for the source, a bonding pad PDHA for the anode of the temperature sensing diode, and a bonding pad PDHC for the cathode of the temperature sensing diode. Similarly, on the front surface of the semiconductor chip CPL (the main surface on the side opposite to where the back surface electrode BEH is formed), there are: a bonding pad PDLG for the gate, bonding pads PDLS1 and PDLS2 for the source, a bonding pad PDLA for the anode of the temperature sensing diode, and a bonding pad PDLC for the cathode of the temperature sensing diode. In addition, on the front surface of the semiconductor chip CPC (the main surface on the side opposite to the back surface), there are multiple bonding pads PDC. In the following text, "bonding pad", "bonding pad electrode", "pad electrode" or "electrode" is simply referred to as "pad".

[0081] The pads PDC of the semiconductor chip CPC are electrically connected to the control circuit CLC formed in the semiconductor chip CPC through the internal wiring of the semiconductor chip CPC.

[0082] The PDHG pad for the gate of the CPH semiconductor chip is electrically connected to the gate electrode of the power MOSFET 1 and the gate electrode of the sensing MOSFET 3 formed in the CPH semiconductor chip. Similarly, the PDHS1 pad for the source of the CPH semiconductor chip is electrically connected to the source of the power MOSFET 1 formed in the CPH semiconductor chip (S1), and the PDHS2 pad for the source of the CPH semiconductor chip is electrically connected to the source of the sensing MOSFET 3 formed in the CPH semiconductor chip (S3). In the CPH semiconductor chip, the planar dimension (area) of the PDHS1 pad for the source is larger than the planar dimension (area) of each of the other pads PDHG, PDHS2, PDHA, and PDHC.

[0083] Furthermore, the PDLG pad for the gate of the CPL semiconductor chip is electrically connected to the gate electrode of the power MOSFET 2 and the gate electrode of the sensing MOSFET 4 formed in the CPL semiconductor chip. Similarly, the PDLS1 pad for the source of the CPL semiconductor chip is electrically connected to the source of the power MOSFET 2 formed in the CPL semiconductor chip (S2), and the PDLS2 pad for the source of the CPL semiconductor chip is electrically connected to the source of the sensing MOSFET 4 formed in the CPL semiconductor chip (S4). In the CPL semiconductor chip, the planar dimension (area) of the PDLS1 pad for the source is larger than the planar dimension (area) of each of the other pads PDLG, PDLS2, PDLA, and PDLC.

[0084] Note that multiple unit transistor cells constituting power MOSFET 1 are formed on a semiconductor substrate constituting semiconductor chip CPH, and power MOSFET 1 is formed by connecting multiple unit transistor cells in parallel. Similarly, multiple unit transistor cells constituting power MOSFET 2 are formed on a semiconductor substrate constituting semiconductor chip CPL, and power MOSFET 2 is formed by connecting multiple unit transistor cells in parallel. Each unit transistor cell is made of, for example, a trench-gate MISFET. In each of the semiconductor chips CPH and CPL, the source-drain current of the power MOSFETs (1, 2) flows in the thickness direction of the semiconductor substrate constituting the semiconductor chip.

[0085] In the semiconductor chip CPH, not only are power MOSFET 1 and sensing MOSFET 3 formed, but a temperature sensing diode is also formed. Pad PDHA is electrically connected to the anode of the temperature sensing diode, and pad PDHC is electrically connected to the cathode of the temperature sensing diode. Similarly, in the semiconductor chip CPL, not only are power MOSFET 2 and sensing MOSFET 4 formed, but a temperature sensing diode is also formed. Pad PDLA is electrically connected to the anode of the temperature sensing diode, and pad PDLC is electrically connected to the cathode of the temperature sensing diode. Note that in... Figure 1 The circuit diagram omits the illustration of the temperature sensing diode.

[0086] On the front surface of the semiconductor chip CPH, pads other than the source pad PDHS1 (in this case, pads PDHG, PDHS2, PDHA, and PDHC) are arranged along the side facing the semiconductor chip CPC. Then, the pads PDHG, PDHS2, PDHA, and PDHC, excluding the source pad PDHS1 for the semiconductor chip CPH, are electrically connected to the semiconductor chip CPC's pad PDC via wires BW. That is, one end of wire BW is connected to pads PDHG, PDHS2, PDHA, and PDHC, while the other end of wire BW is connected to the semiconductor chip CPC's pad PDC.

[0087] Similarly, on the front surface of the semiconductor chip CPL, pads other than the source pad PDLS1 (in this case, pads PDLG, PDLS2, PDLA, and PDLC) are arranged along the side facing the semiconductor chip CPC. Then, the pads PDLG, PDLS2, PDLA, and PDLC, except for the source pad PDHS1 for the semiconductor chip CPH, are electrically connected to the pad PDC of the semiconductor chip CPC via wires BW. That is, one end of wire BW is connected to pads PDLG, PDLS2, PDLA, and PDLC, while the other end of wire BW is connected to the pad PDC of the semiconductor chip CPC.

[0088] The bonding wire (BW) is a conductive connection component, and more specifically, a conductive wire. Since the bonding wire (BW) is made of metal, it can also be considered a metallic wire (a thin metallic wire). Gold (Au) wire, copper (Cu) wire, aluminum (Al) wire, etc., can be suitably used as the bonding wire (BW). The bonding wire (BW) is sealed within a sealing portion (MR) and does not protrude from the sealing portion (MR). The portion of each lead (LD) that connects to the bonding wire (BW) is the inner lead portion located within the sealing portion (MR).

[0089] The pad PDHS1, used as the source electrode of the semiconductor chip CPH, is electrically connected to the lead coupling section (lead wiring section, metal section) LB2 via a metal plate MP1. Specifically, the metal plate MP1 is bonded to the pad PDHS1 of the source electrode of the semiconductor chip CPH via a conductive bonding material (adhesive layer) BD4, and the metal plate MP1 is bonded to the lead coupling section LB2 via a conductive bonding material (adhesive layer) BD5. The lead coupling section LB2 can also be considered as a metal section for bonding the metal plate MP1 via the bonding material BD5.

[0090] The pad PDLS1, used for the source electrode of the semiconductor chip CPL, is electrically connected to the lead coupling section (lead wiring section, metal section) LB4 via a metal plate MP2. Specifically, the metal plate MP2 is bonded to the pad PDLS1 of the source electrode of the semiconductor chip CPL via a conductive bonding material (adhesive layer) BD6, and the metal plate MP2 is bonded to the lead coupling section LB4 via a conductive bonding material (adhesive layer) BD7. The lead coupling section LB4 can also be considered as a metal section for bonding the metal plate MP2 via the bonding material BD7.

[0091] By replacing the wire used to electrically connect the source pad PDHS1 of the semiconductor chip CPH to the lead LD2 with a metal plate MP1, the on-resistance of power MOSFET 1 can be reduced. Similarly, by replacing the wire used to electrically connect the source pad PDLS1 of the semiconductor chip CPL to the lead LD4 with a metal plate MP2, the on-resistance of power MOSFET 2 can be reduced. Therefore, package resistance can be reduced, and conductivity losses can be decreased.

[0092] The bonding materials BD4, BD5, BD6, and BD7 are preferably made of a paste-like conductive bonding material such as silver paste (silver paste bonding material). In the semiconductor device PKG, the paste-like conductive bonding material constituting each of the bonding materials BD4, BD5, BD6, and BD7 is already in a solidified state.

[0093] Metal plates MP1 and MP2 are conductor plates made of conductive material, and preferably formed of the same material (same metallic material) as the bare die pads DPH, DPL, and DPC, the leads LD, and the lead coupling portions LB1, LB2, LB3, and LB4. Therefore, metal plates MP1 and MP2 are preferably made of copper (Cu) or a copper (Cu) alloy. The dimensions (width) of each metal plate in metal plates MP1 and MP2 in the X and Y directions are larger than the diameter of the conductor BW.

[0094] The heat generated in semiconductor chips CPH and CPL is dissipated from the front surface of semiconductor chips CPH and CPL through metal plates MP1 and MP2, and from the back surface of semiconductor chips CPH and CPL through bare die pads DPH and DPL. Therefore, the heat dissipation of semiconductor chips CPH and CPL can be improved.

[0095] Among the multiple pads (PDCs) of the semiconductor chip CPC, the PDCs not connected to the pads of the semiconductor chip CPH and the semiconductor chip CPL are electrically connected to leads LD5a and LD5b among the multiple leads (LDs) of the semiconductor device PKG. That is, one end of the wire BW is connected to the PDC of the semiconductor chip CPC that is not connected to the pads of the semiconductor chip CPH and the semiconductor chip CPL, and the other end of the wire BW is connected to the inner lead portion of lead LD5a or the inner lead portion of lead LD5b. Each of leads LD5a and LD5b can be used as a signal transmission path between the semiconductor chip CPC in the semiconductor device PKG and the control circuit CT outside the semiconductor device PKG.

[0096] Of the multiple leads LD5a and LD5b, lead LD5a is arranged on the side surface MRc1 near the seal MR, and lead LD5b is arranged on the side surface MRc3 near the seal MR. Each lead of LD5a and LD5b is isolated and not connected by a conductor to any bare die pads DPC, DPH and DPL, leads LD1, LD2, LD3 and LD4, or lead coupling portions LB1, LB2, LB3 and LB4.

[0097] Lead coupling portion LB2 is adjacent to the die pad DPH in the Y direction and extends in the X direction along the side MRc3 within the sealing portion MR, but is separated from the die pad DPH. Similarly, lead coupling portion LB4 is adjacent to the die pad DPL in the Y direction and extends in the X direction along the side MRc1 within the sealing portion MR, but is separated from the die pad DPL. Lead coupling portions LB2 and LB4 are sealed within the sealing portion MR and do not protrude from it.

[0098] In the semiconductor device PKG, multiple leads LD2 are collectively connected (coupled) to a lead coupling portion LB2. That is, the lead coupling portion LB2 is integrally formed with the leads LD2. The multiple leads LD2 are adjacent to each other in the X direction, and the inner lead portions of the multiple leads LD2 are coupled through the lead coupling portion LB2 extending in the X direction within the sealing portion MR. The multiple leads LD2 and the lead coupling portion LB2 are electrically connected to the pads PDHS1 of the semiconductor chip CPH via a metal plate MP1, thereby electrically connecting to the source (S1) of the power MOSFET 1 formed in the semiconductor chip CPH, corresponding to the aforementioned terminal TE2.

[0099] Similarly, the leads LD4 of the multiple leads LD of the semiconductor device PKG are collectively connected (coupled) to the lead coupling portion LB4. That is, the lead coupling portion LB4 is integrally formed with the leads LD4. The multiple leads LD4 are adjacent to each other in the X direction, and the inner lead portions of the multiple leads LD4 are coupled through the lead coupling portion LB4 extending in the X direction in the sealing portion MR. The multiple leads LD4 and the lead coupling portion LB4 are electrically connected to the pads PDLS1 of the semiconductor chip CPL through the metal plate MP2, etc., thereby electrically connecting to the source (S2) of the power MOSFET 2 formed in the semiconductor chip CPL, and corresponding to the aforementioned terminal TE4.

[0100] Since multiple leads LD2 are connected together to the lead coupling section LB2, the volume can be increased compared to the case where multiple leads LD2 are separate, thereby reducing wiring resistance and the conduction loss of power MOSFET 1. This also applies to multiple leads LD4 and the lead coupling section LB4.

[0101] In the semiconductor device PKG, among the multiple leads LD, lead LD1 is integrally formed with the die pad DPH. Therefore, the multiple leads LD1 are electrically connected to the back surface electrode BEH of the semiconductor chip CPH through the die pad DPH and the conductive bonding material BD1, and correspond to the aforementioned terminal TE1.

[0102] Similarly, in the multiple leads LD of the semiconductor device PKG, the lead LD3 is integrally formed with the die pad DPL. Therefore, the multiple leads LD3 are electrically connected to the back surface electrode BEL of the semiconductor chip CPL through the die pad DPL and the conductive bonding material BD2, and correspond to the aforementioned terminal TE3.

[0103] When only the semiconductor device PKG is observed, the multiple leads LD2 and LD4 of the semiconductor device PKG are not electrically connected. However, when the semiconductor device PKG is used to form an inverter circuit INV, the multiple leads LD2 and LD4 of the semiconductor device PKG are electrically connected via wiring on a wiring board or the like by mounting the semiconductor device PKG on the wiring board.

[0104] Multiple leads LD1 are arranged on one side of the side surface MRc1 near the seal MR, such that they are adjacent to the die pad DPH in the Y direction, and multiple leads LD3 are arranged on one side of the side surface MRc3 near the seal MR, such that they are adjacent to the die pad DPL in the Y direction.

[0105] Multiple leads LD1 are adjacent to each other in the X direction, and the inner lead portions of the multiple leads LD1 are coupled through lead coupling portions LB1 extending in the X direction within the sealing portion MR. The lead coupling portions LB1 are integrally connected to the bare die pad DPH via coupling portions LB1a extending in the Y direction.

[0106] Similarly, multiple leads LD3 are adjacent to each other in the X direction, and the inner lead portions of the multiple leads LD3 are coupled through lead coupling portions LB3 extending in the X direction within the sealing portion MR. The lead coupling portions LB3 are integrally connected to the bare die pad DPL via coupling portions LB3a extending in the Y direction.

[0107] Similarly, multiple leads LD8 are integrally coupled to the die pad DPC. When manufacturing the semiconductor device PKG, these leads LD8 are used to support the die pad DPC to the frame body of the lead frame. Additionally, lead LD6 is integrally coupled to the die pad DPH. When manufacturing the semiconductor device PKG, this lead LD6 is used to support the die pad DPH to the frame body of the lead frame. Furthermore, lead LD7 is integrally coupled to the die pad DPL. When manufacturing the semiconductor device PKG, this lead LD7 is used to support the die pad DPL to the frame body of the lead frame.

[0108] Similarly, a suspension lead TL integrally coupled to the die pad DPH is arranged on the side surface MRc2 of the seal portion MR, and a suspension lead TL integrally coupled to the die pad DPL is arranged on the side surface MRc4 of the seal portion MR. When manufacturing the semiconductor device PKG, these suspension leads TL are used to support the die pads DPH and DPL to the frame body of the lead frame. The suspension leads TL are not exposed from the side surface of the seal portion MR.

[0109] In the semiconductor device PKG, when power MOSFET 1 is in the ON state, current flows through the semiconductor chip CPH (power MOSFET 1) from the drain lead LD1 to the source lead LD2. Similarly, in the semiconductor device PKG, when power MOSFET 2 is in the ON state, current flows through the semiconductor chip CPL (power MOSFET 2) from the drain lead LD3 to the source lead LD4.

[0110] <Semiconductor Device Manufacturing Process>

[0111] The above will be described next. Figures 2 to 10 The manufacturing process (assembly process) of the semiconductor device PKG shown. Figures 11 to 26 These are plan views and cross-sectional views taken during the manufacturing process of the semiconductor device PKG according to this embodiment. Figures 11 to 26 middle, Figure 11 , Figure 12 , Figure 16 and Figure 20 It is a floor plan, and Figures 13 to 15 , Figures 17 to 19 ,as well as Figures 21 to 26 This is a cross-sectional view. Note that... Figure 13 , Figure 17 , Figure 21 , Figure 23 and Figure 25 Corresponding to in Figure 7 Cross-sectional view at the corresponding cross-sectional location, Figure 14 and Figure 18 Corresponding to in Figure 8 Cross-sectional view at the corresponding cross-sectional location, and Figure 15 , Figure 19 , Figure 22 , Figure 24 and Figure 26 Corresponding to in Figure 9 Cross-sectional view at the corresponding cross-sectional location.

[0112] To manufacture a semiconductor device PKG, firstly, a lead frame LF is prepared, and then semiconductor chips CPC, CPH, and CPL are prepared. The order in which the lead frame LF and semiconductor chips CPC, CPH, and CPL are prepared is not particularly restricted, and the lead frame LF and semiconductor chips CPC, CPH, and CPL can be prepared simultaneously.

[0113] like Figure 11As shown, the leadframe LF generally includes a frame body (not shown), die pads DPC, DPH, and DPL, multiple leads LD, lead coupling sections LB1, LB2, LB3, and LB4, and suspension leads TL. One end of each lead LD is coupled to the frame body. Die pad DPC is coupled to the frame body via lead LD8, die pad DPH is coupled to the frame body via leads LD1 and LD6 and suspension leads TL, and die pad DPL is coupled to the frame body via leads LD3 and LD7 and suspension leads TL. The leadframe LF is preferably made of a metallic material mainly composed of copper (Cu), and specifically of copper (Cu) or a copper (Cu) alloy. Figure 11 The area from which a semiconductor device PKG is fabricated is shown in the lead frame LF.

[0114] Note that the following process is performed with the main surfaces DPCa, DPHa, and DPLa of the bare die pads DPC, DPH, and DPL of the lead frame LF facing upwards until the seal MR is formed by the molding process.

[0115] Next, as Figures 12 to 15 As shown, the die bonding process for semiconductor chips CPH, CPL, and CPC is performed. Specifically, semiconductor chip CPH is mounted (arranged) on the main surface DPHa of the die pad DPH of the lead frame LF using bonding material BD1a; semiconductor chip CPL is mounted (arranged) on the main surface DPLa of the die pad DPL of the lead frame LF using bonding material BD2a; and semiconductor chip CPC is mounted (arranged) on the main surface DPCa of the die pad DPC of the lead frame LF using bonding material BD3a. For example, after applying (providing) bonding material BD1a to the main surface DPHa of the die pad DPH, applying (providing) bonding material BD2a to the main surface DPLa of the die pad DPL, and applying (providing) bonding material BD3a to the main surface DPCa of the die pad DPC, semiconductor chips CPH, CPL, and CPC can be mounted on the main surfaces DPHa, DPLa, and DPCa of the die pads DPH, DPL, and DPC, respectively. At this point, semiconductor chips CPH, CPL, and CPC are mounted such that the back surfaces of semiconductor chips CPH, CPL, and CPC point towards the main surfaces DPHa, DPLa, and DPCa of bare die pads DPH, DPL, and DPC. Each of the bonding materials BD1a, BD2a, and BD3a is a paste-like bonding material (adhesive material), and preferably silver paste, but not yet cured.

[0116] Next, the process of arranging metal plates MP1 and MP2 is performed. Specifically, firstly, bonding material BD5a is applied (provided) to the lead coupling portion LB2, bonding material BD7a is applied (provided) to the lead coupling portion LB4, bonding material BD4a is applied (provided) to the pad PDHS1 for the source electrode of the semiconductor chip CPH, and bonding material BD6a is applied (provided) to the pad PDLS1 for the source electrode of the semiconductor chip CPL. Then, as... Figures 16 to 19 As shown, a metal plate MP1 is arranged (mounted) on the semiconductor chip CPH and the lead coupling portion LB2, and a metal plate MP2 is arranged on the semiconductor chip CPL and the lead coupling portion LB4. At this time, the metal plate MP1 is arranged such that a portion of the metal plate MP1 is placed on the pad PDHS1 of the source electrode of the semiconductor chip CPH via bonding material BD4a, and another portion of the metal plate MP1 is placed on the lead coupling portion LB2 via bonding material BD5a. Similarly, the metal plate MP2 is arranged such that a portion of the metal plate MP2 is placed on the pad PDLS1 of the source electrode of the semiconductor chip CPL via bonding material BD6a, and another portion of the metal plate MP2 is placed on the lead coupling portion LB4 via bonding material BD7a. Each of the bonding materials BD4a, BD5a, BD6a, and BD7a is a paste-like bonding material (adhesive material), and preferably silver paste, but not yet cured.

[0117] Next, a process (heat treatment) is performed to cure the bonding materials BD1a, BD2a, BD3a, BD4a, BD5a, BD6a, and BD7a. Thus, a bonding material (adhesive layer) BD1, a bonding material (adhesive layer) BD2, and a bonding material (adhesive layer) BD3, made of cured bonding material BD1a, are formed. Furthermore, a bonding material (adhesive layer) BD4, a bonding material (adhesive layer) BD5, a bonding material (adhesive layer) BD6, a bonding material (adhesive layer) BD6, and a bonding material (adhesive layer) BD7, made of cured bonding material BD7a, are also formed. Semiconductor chip CPH is bonded and fixed to die pad DPH using bonding material BD1. Semiconductor chip CPL is bonded and fixed to die pad DPL using bonding material BD2. Semiconductor chip CPC is bonded and fixed to die pad DPC using bonding material BD3. Metal plate MP1 is bonded and fixed to pad PDHS1, the source electrode of semiconductor chip CPH, using bonding material BD4. Metal plate MP1 is bonded and fixed to lead coupling section LB2 using bonding material BD5. Metal plate MP2 is bonded and fixed to pad PDLS1, the source electrode of semiconductor chip CPL, using bonding material BD6. Metal plate MP2 is bonded and fixed to lead coupling section LB4 using bonding material BD7.

[0118] Next, as Figure 20 As shown, the wire bonding process is performed. Specifically, multiple pads (PDHG, PDHS2, PDHA, PDHC) of semiconductor chip CPH are electrically connected to multiple pads (PDC) of semiconductor chip CPC via wire BW; multiple pads (PDLG, PDLS2, PDLA, PDLC) of semiconductor chip CPL are electrically connected to multiple pads (PDC) of semiconductor chip CPC via wire BW; and multiple pads (PDC) of semiconductor chip CPC and multiple leads (LD5a, LD5b) of lead frame LF are electrically connected via wire BW.

[0119] Various types of wires made of different materials can also be used as wires (BW). For example, multiple pads (PDC) of a semiconductor chip CPC can be electrically connected to multiple leads (LD5a, LD5b) of a lead frame LF using wires (BW) made of copper (Cu). Then, multiple pads (PDHG, PDHS2, PDHA, PDHC) of a semiconductor chip CPH can be electrically connected to multiple pads (PDC) of a semiconductor chip CPC using wires (BW) made of gold (Au), and multiple pads (PDLG, PDLS2, PDLA, PDLC) of a semiconductor chip CPL can be electrically connected to multiple pads (PDC) of a semiconductor chip CPC using wires (BW) made of gold (Au).

[0120] Next, the molding process (the process of forming the sealing part MR) is performed. Specifically, firstly, as... Figure 21 and Figure 22 As shown, the lead frame LF is sandwiched between forming molds (lower forming mold) KG1 and forming mold (upper forming mold) KG2. At this time, the lead frame LF is sandwiched between forming molds KG1 and KG2, such that the die pads DPH, DPL, and DPC, the semiconductor chip CPH, CPL, and CPC, the metal plates MP1 and MP2, the conductor BW, the inner lead portion of the lead LD, and the lead coupling portions LB1, LB2, LB3, and LB4 are arranged in the cavity CAV between forming molds KG1 and KG2. Each of the back surfaces DPCb, DPHb, and DPLb of the die pads DPH, DPL, and DPC is in contact with the upper surface of forming mold KG1. The outer lead portion of the lead LD is located outside the cavity CAV and is sandwiched between forming molds KG1 and KG2. Then, as... Figure 23 and Figure 24 As shown, resin material MR1, used to form the sealing portion MR, is injected (introduced) into the cavity CAV between molding dies KG1 and KG2. The resin material MR1 to be injected is made of, for example, a thermosetting resin material and may contain fillers, etc. Thereafter, a process of curing (heat treatment) is performed on the resin material MR1 injected into the cavity CAV. Thus, the sealing portion MR made of the cured resin material MR1 is formed. Then, molding dies KG1 and KG2 are separated, and as shown... Figure 25 and Figure 26 As shown, the lead frame LF and the sealing part MR are removed together.

[0121] Through the above molding process, a sealing portion MR is formed, which seals semiconductor chips CPC, CPH, and CPL, bare die pads DPC, DPH, and DPL, multiple wires BW, metal plates MP1 and MP2, lead coupling portions LB1, LB2, LB3, and LB4, and the inner lead portions of multiple leads LD. Figure 25 and Figure 26 As can be seen, the sealing part MR is formed in the molding process, so that the back surfaces DPCb, DPHb and DPLb of the bare die pads DPC, DPH and DPL are exposed from the main surface MRa of the sealing part MR.

[0122] Note that the molding process is performed with the main surfaces DPCa, DPHa, and DPLa of the die pads DPC, DPH, and DPL facing upwards. Therefore, during the stage of forming the seal MR through the molding process, the back surface MRb of the seal MR faces upwards. However, when the manufactured semiconductor device PKG is mounted on a wiring board, the semiconductor device PKG is mounted on the wiring board such that the back surface MRb of the seal MR faces the wiring board.

[0123] Next, as needed, a plating layer (not shown) is formed on each of the outer lead portions of the lead LD that are exposed from the sealing portion MR. After that, the top and bottom (front and back) of the lead frame LF are inverted together with the sealing portion MR, and then the lead LD is cut at a predetermined position outside the sealing portion MR, separating the lead LD from the frame body of the lead frame.

[0124] Next, the outer lead portion of the lead LD protruding from the sealing part MR is bent (lead processing, lead formation).

[0125] Manufacturing in accordance with the above method Figures 2 to 10 The semiconductor device PKG is shown.

[0126] <Installation Example of Semiconductor Device PKG>

[0127] Figures 27 to 30 This is a cross-sectional view showing the semiconductor device PKG mounted on the wiring board PB1. Note that... Figure 27 Corresponding to in Figure 7 Cross-sectional view at the corresponding cross-sectional location, Figure 28 Corresponding to in Figure 8 Cross-sectional view at the corresponding cross-sectional location, Figure 29 Corresponding to in Figure 9 Cross-sectional view at the corresponding cross-sectional location, and Figure 30 Corresponding to in Figure 10 Cross-sectional view at the corresponding cross-sectional location.

[0128] like Figures 27 to 30As shown, the semiconductor device PKG is mounted on the main surface PB1a of the wiring board PB1, and the back surface MRb of the sealing portion MR points towards the main surface (upper surface) PB1a of the wiring board PB1. Similarly, multiple leads LD of each semiconductor device PKG are bonded and fixed to multiple terminals (electrodes) TM formed on the main surface PB1a of the wiring board PB1 via a conductive bonding material SD, such as solder. That is, multiple leads LD of each semiconductor device PKG are electrically connected to multiple terminals TM formed on the main surface PB1a of the wiring board PB1 via the conductive bonding material SD. The bonding material SD is preferably made of solder.

[0129] In addition, Figures 27 to 30 In this case, a heat sink (base) HS is arranged (mounted) on the main surface MRa of the sealing portion MR of the semiconductor device PKG mounted on the wiring substrate PB1 via an insulating adhesive material BD11. For example, a thermally conductive grease with insulating properties can be used as the insulating adhesive material BD11. For example, a finned heat sink can be used as the heat sink HS.

[0130] In the semiconductor device PKG, the back surfaces DPCb, DPHb, and DPLb of the die pads DPC, DPH, and DPL are exposed from the main surface MRa of the seal MR, and the back surfaces DPCb, DPHb, and DPLb of the die pads DPC, DPH, and DPL are bonded to the heat sink HS via insulating bonding material BD11. Therefore, the heat generated in the semiconductor chips CPC, CPH, and CPL in the semiconductor device PKG can be dissipated to the heat sink HS through the die pads DPC, DPH, and DPL and the adhesive material BD11 (thermal grease).

[0131] Similarly, by attaching the heat sink HS to the semiconductor device PKG using the insulating adhesive BD11, the heat sink HS with a large heat capacity (large volume) can be attached to the semiconductor device PKG while preventing the bare die pads DPC, DPH and DPL of the semiconductor device PKG from being electrically connected to each other through the adhesive BD11 and the heat sink HS.

[0132] <Main Features and Effects>

[0133] The main feature of this embodiment is that the elastic modulus of the bonding materials (adhesive layers) BD1, BD2, BD3, BD4, BD5, BD6, and BD7 in the semiconductor device PKG is appropriately set. Specifically, the elastic modulus of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 is lower than that of each of the bonding materials BD5 and BD7. That is, bonding materials BD1, BD2, BD3, BD4, and BD6 have low elastic modulus, while bonding materials BD5 and BD7 have high elastic modulus. In other words, low-elasticity bonding materials are used as bonding materials BD1, BD2, BD3, BD4, and BD6, and high-elasticity bonding materials are used as bonding materials BD5 and BD7.

[0134] Note that bonding materials BD1, BD2, BD4, BD5, BD6, and BD7 are conductive, while bonding material BD3 may be conductive or insulating depending on the situation. However, more preferably, bonding material BD3 (BD3a) is made of the same material as bonding materials BD1 and BD2 (BD1a, BD2a). Therefore, the manufacturing process of the semiconductor device PKG (more specifically, the die bonding process) can be simplified, and the manufacturing cost of the semiconductor device PKG can be reduced. When bonding material BD3 (BD3a) is made of the same material as bonding materials BD1 and BD2 (BD1a, BD2a), bonding material BD3 is also conductive.

[0135] Figure 31 It is a table summarizing the characteristics of low-elasticity and high-elasticity bonded materials for comparison, and Figure 31 This illustrates cases where both low-elasticity and high-elasticity bonding materials are made of silver paste.

[0136] Low-elasticity bonded materials have a lower elastic modulus than high-elasticity bonded materials. Similarly, from... Figure 31 As can be seen from the table, low-elasticity bonded materials have a lower silver (Ag) content than high-elasticity bonded materials. This is because when the proportion of silver (Ag) in the bonded material is reduced, the proportion of resin components in the bonded material increases, thus reducing the elastic modulus.

[0137] Similarly, from Figure 31 As can be seen from the table, low-elasticity bonded materials exhibit lower thermal conductivity and higher volume resistivity compared to high-elasticity bonded materials. This is because when the silver (Ag) content is low, thermal conductivity decreases and volume resistivity increases, resulting in low-elasticity bonded materials with lower silver (Ag) content exhibiting lower thermal conductivity and higher volume resistivity compared to high-elasticity bonded materials with higher silver (Ag) content.

[0138] Considering the respective characteristics of low-elasticity and high-elasticity bonding materials, in this embodiment, high-elasticity bonding materials are used for bonding materials BD5 and BD7, while low-elasticity bonding materials are used for bonding materials BD1, BD2, BD3, BD4, and BD6. As a result, the overall reliability of the semiconductor device PKG can be improved, and the reasons for this will be described in detail below.

[0139] First, focus on the bonding materials BD1, BD2, and BD3. Each of BD1, BD2, and BD3 is a bonding material used to bond semiconductor chips (CPH, CPL, CPC) to die pads (DPH, DPL, DPC). As mentioned above, since both semiconductor chips CPH and CPL are semiconductor chips in which field-effect transistors (power transistors) for switching are formed, a large amount of heat is generated during operation. Therefore, semiconductor chips CPH and CPL can be heat sources. Similarly, since the die pads (DPH, DPL, DPC) and semiconductor chips (CPH, CPL, CPC) are made of different materials, the coefficients of thermal expansion of the die pads (DPH, DPL, DPC) and the semiconductor chips (CPH, CPL, CPC) are different from each other. Therefore, when the temperatures of the semiconductor chips CPH and CPL, bonding materials BD1 and BD2, and die pads DPH and DPL rise due to heat generated during operation of the semiconductor chips CPH and CPL, strong stresses are generated in the bonding materials BD1 and BD2 between the die pads DPH and DPL and the semiconductor chips CPH and CPL due to the difference in the coefficients of thermal expansion between them. This stress may lead to cracks in the bonding materials BD1 and BD2. Since cracks in the bonding materials BD1 and BD2 between the die pads DPH and DPL and the semiconductor chips CPH and CPL may reduce the reliability of the semiconductor device PKG, it is desirable to prevent this.

[0140] Therefore, in this embodiment, it is preferable to reduce the elastic modulus of bonding materials BD1 and BD2. Thus, it is preferable to use low-elasticity bonding materials as bonding materials BD1 and BD2. If the elastic modulus of bonding materials BD1 and BD2 is reduced, even if the temperatures of semiconductor chips CPH and CPL, bonding materials BD1 and BD2, and die pads DPH and DPL rise due to the heating of semiconductor chips CPH and CPL, and stress is generated in bonding materials BD1 and BD2 due to the difference in the coefficients of thermal expansion between die pads DPH and DPL and semiconductor chips CPH and CPL, cracks are unlikely to occur in bonding materials BD1 and BD2. In other words, when comparing the cases where the elastic moduli of bonding materials BD1 and BD2 are low with those where they are high, the cases where the elastic moduli of bonding materials BD1 and BD2 are low make it less likely that cracks will occur in bonding materials BD1 and BD2 due to stress generated by heat generation in the semiconductor chip CPH and CPL. By reducing the elastic moduli of bonding materials BD1 and BD2, the stress (strain) generated in bonding materials BD1 and BD2 due to the difference in the coefficients of thermal expansion between the bare die pads DPH and DPL and the semiconductor chip CPH and CPL when the semiconductor chip CPH and CPL heat up can be suppressed, thereby suppressing the occurrence of cracks in bonding materials BD1 and BD2. Since the occurrence of cracks in bonding materials BD1 and BD2 can be suppressed, the reliability of the semiconductor device PKG can be improved. For example, when cracks appear in the bonding materials BD1 and BD2, the connection resistance between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH, and the connection resistance between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL, increases. This leads to an increase in the on-resistance (resistance when turned on) of the power MOSFETs 1 and 2. Similarly, when cracks appear in the bonding materials BD1 and BD2, the ratio (sensing ratio) between the current flowing in the sensing MOSFETs 3 and 4 and the current flowing in the power MOSFETs 1 and 2 changes, thereby reducing the sensing accuracy of the current of the power MOSFETs 1 and 2 by the sensing MOSFETs 3 and 4. Since the elastic modulus of the bonding materials BD1 and BD2 is reduced in this embodiment, the occurrence of cracks in the bonding materials BD1 and BD2 can be suppressed, thus preventing this problem.

[0141] Compared to semiconductor chips CPH and CPL, less heat is generated in semiconductor chip CPC during operation. Therefore, even without reducing the elastic modulus of bonding material BD3, the risk of cracking in bonding material BD3 is lower. Therefore, either low-elasticity or high-elasticity bonding materials can be applied to bonding material BD3. Furthermore, bonding material BD3 can be conductive or insulating. However, in the manufacture of semiconductor device PKG, it is preferable to use the same material as bonding materials BD1 and BD2 (BD1a, BD2a) to form bonding material BD3 (BD3a). Therefore, similar to bonding materials BD1 and BD2, it is preferable to apply a low-elasticity bonding material to bonding material BD3. By using the same material as bonding materials BD1 and BD2 (BD1a, BD2a) to form bonding material BD3 (BD3a), the manufacturing process of semiconductor device PKG (more specifically, the die bonding process) can be simplified, and the manufacturing cost of semiconductor device PKG can be reduced.

[0142] Next, we focus on the bonding materials BD4 and BD6. Bonding materials BD4 and BD6 are used to bond metal plates MP1 and MP2 to the pads PDHS1 and PDLS1 of semiconductor chips CPH and CPL. As mentioned above, a large amount of heat is generated in semiconductor chips CPH and CPL, and semiconductor chips CPH and CPL can be heat sources. Also, since metal plates MP1 and MP2 and semiconductor chips CPH and CPL are made of different materials, the coefficients of thermal expansion of metal plates MP1 and MP2 are different from those of semiconductor chips CPH and CPL. Therefore, when the temperature of semiconductor chips CPH and CPL, bonding materials BD4 and BD6, and metal plates MP1 and MP2 rises due to heat generated during the operation of semiconductor chips CPH and CPL, strong stress is generated in the bonding materials BD4 and BD6 between metal plates MP1 and MP2 and semiconductor chips CPH and CPL due to the difference in the coefficients of thermal expansion between metal plates MP1 and MP2 and semiconductor chips CPH and CPL. This stress may cause cracks in the bonding materials BD4 and BD6. Since cracks in the bonding materials BD4 and BD6, which lie between the metal plates MP1 and MP2 and the pads PDHS1 and PDLS1 of the semiconductor chips CPH and CPL, could reduce the reliability of the semiconductor device PKG, it is desirable to prevent this.

[0143] Therefore, in this embodiment, it is preferable to reduce the elastic modulus of bonding materials BD4 and BD6. Thus, it is preferable to use low-elasticity bonding materials as bonding materials BD4 and BD6. If the elastic modulus of bonding materials BD4 and BD6 is reduced, even if the temperatures of semiconductor chips CPH and CPL, bonding materials BD4 and BD6, and metal plates MP1 and MP2 increase due to the heating of semiconductor chips CPH and CPL, and stress is generated in bonding materials BD4 and BD6 due to the difference in the coefficients of thermal expansion between metal plates MP1 and MP2 and semiconductor chips CPH and CPL, cracks are unlikely to occur in bonding materials BD4 and BD6. That is, when comparing the case of low elastic modulus of bonding materials BD4 and BD6 with the case of high elastic modulus of bonding materials BD4 and BD6, cracks caused by stress generated in bonding materials BD4 and BD6 due to the heating of semiconductor chips CPH and CPL are less likely to occur in bonding materials BD4 and BD6 when the elastic modulus of bonding materials BD4 and BD6 is low. By reducing the elastic modulus of bonding materials BD4 and BD6, the stress (strain) generated in bonding materials BD4 and BD6 due to the difference in the coefficients of thermal expansion between metal plates MP1 and MP2 and semiconductor chips CPH and CPL when semiconductor chips CPH and CPL heat up can be suppressed, thereby suppressing the occurrence of cracks in bonding materials BD4 and BD6. Since the occurrence of cracks in bonding materials BD4 and BD6 can be suppressed, the reliability of the semiconductor device PKG can be improved. For example, when cracks occur in bonding materials BD4 and BD6, the connection resistance between pad PDHS1 of semiconductor chip CPH and metal plate MP1, and the connection resistance between pad PDSL1 of semiconductor chip CPL and metal plate MP2, increases, which leads to an increase in the on-resistance (resistance when turned on) of power MOSFETs 1 and 2. Since the elastic modulus of bonding materials BD4 and BD6 is reduced in this embodiment, the occurrence of cracks in bonding materials BD4 and BD6 can be suppressed, thus preventing this problem.

[0144] Next, we focus on the bonding materials BD5 and BD7. Bonding materials BD5 and BD7 are used to bond metal plates MP1 and MP2 to lead coupling portions LB2 and LB4. As mentioned above, a large amount of heat is generated in the semiconductor chips CPH and CPL, and the semiconductor chips CPH and CPL can be heat sources. Since metal plates MP1 and MP2 are bonded to the pads PDHS1 and PDLS1 of the semiconductor chips CPH and CPL via bonding materials BD4 and BD6, the heat generated in the semiconductor chips CPH and CPL is transferred to metal plates MP1 and MP2 through bonding materials BD4 and BD6, and further transferred to lead coupling portions LB2 and LB4 through bonding materials BD5 and BD7. However, metal plates MP1 and MP2, as well as lead coupling portions LB2 and LB4, are made of the same material (the same metallic material). Metal plates MP1 and MP2, as well as lead coupling portions LB2 and LB4, are preferably made of copper or a copper alloy. Therefore, the coefficients of thermal expansion of metal plates MP1 and MP2 are approximately equal to those of lead coupling portions LB2 and LB4. Thus, even when heat generated in the semiconductor chips CPH and CPL is transferred to metal plates MP1 and MP2 and lead coupling portions LB2 and LB4, and the temperatures of metal plates MP1 and MP2, bonding materials BD5 and BD7, and lead coupling portions LB2 and LB4 increase, the stress generated in the bonding materials BD5 and BD7 between metal plates MP1 and MP2 and lead coupling portions LB2 and LB4 will not increase significantly. Therefore, even when heat generated in the semiconductor chips CPH and CPL is transferred to metal plates MP1 and MP2 and lead coupling portions LB2 and LB4, the risk of cracking in the bonding materials BD5 and BD7 between metal plates MP1 and MP2 and lead coupling portions LB2 and LB4 is low. That is, unlike this embodiment, when bonding materials with the same elastic modulus are used for all bonding materials BD1, BD2, BD3, BD4, BD5, BD6 and BD7, the risk of cracking in bonding materials BD5 and BD7 due to heat generated in the semiconductor chips CPH and CPL is much lower than the risk of cracking in bonding materials BD1, BD2, BD3, BD4 and BD6 due to heat generated in the semiconductor chips CPH and CPL.

[0145] As described above, in order to reduce the risk of cracking in bonding materials BD1, BD2, BD3, BD4, and BD6 due to heat generated in the semiconductor chips CPH and CPL, it is desirable to reduce the elastic modulus of bonding materials BD1, BD2, BD3, BD4, and BD6. On the other hand, since the risk of cracking in bonding materials BD5 and BD7 due to heat generated in the semiconductor chips CPH and CPL is inherently low, it is not necessary to reduce the elastic modulus of bonding materials BD5 and BD7 to prevent cracking caused by heat generated in the semiconductor chips CPH and CPL. Instead, it is desirable to increase the elastic modulus of bonding materials BD5 and BD7 for the following reasons.

[0146] That is, the bonding area between metal plate MP1 and lead coupling portion LB2 (planar area of ​​bonding material BD5) is smaller than the bonding area between semiconductor chip CPH and bare die pad DPH (planar area of ​​bonding material BD1) and the bonding area between semiconductor chip CPL and bare die pad DPL (planar area of ​​bonding material BD2). Similarly, the bonding area between metal plate MP1 and lead coupling portion LB2 (planar area of ​​bonding material BD5) is smaller than the bonding area between metal plate MP1 and pad PDHS1 of semiconductor chip CPH (planar area of ​​bonding material BD4) and the bonding area between metal plate MP2 and pad PDLS1 of semiconductor chip CPL (planar area of ​​bonding material BD6). In addition, the bonding area between metal plate MP2 and lead coupling portion LB4 (planar area of ​​bonding material BD7) is smaller than the bonding area between semiconductor chip CPH and bare die pad DPH (planar area of ​​bonding material BD1) and the bonding area between semiconductor chip CPL and bare die pad DPL (planar area of ​​bonding material BD2). Furthermore, the bonding area between metal plate MP2 and lead coupling portion LB4 (planar area of ​​bonding material BD7) is smaller than the bonding area between metal plate MP1 and pad PDHS1 of semiconductor chip CPH (planar area of ​​bonding material BD4) and the bonding area between metal plate MP2 and pad PDLS1 of semiconductor chip CPL (planar area of ​​bonding material BD6). That is, while the planar dimensions (planar areas) of each of bonding materials BD1, BD2, BD3, BD4, and BD6 are relatively large, the planar dimensions (planar areas) of each of bonding materials BD5 and BD7 are relatively small. Therefore, if the resistivity (volume resistivity) of bonding materials BD5 and BD7, which have small planar dimensions (planar areas), is low, the connection resistance between metal plate MP1 and lead coupling portion LB2 via bonding material BD5 and the connection resistance between metal plate MP2 and lead coupling portion LB4 via bonding material BD7 increases, which is undesirable.

[0147] Therefore, for bonding materials BD5 and BD7, which have smaller planar dimensions (planar areas) than bonding materials BD1, BD2, BD3, BD4, and BD6, it is preferable to reduce resistivity (volume resistivity), and thus a high-elasticity bonding material is used. As described above, since the high-elasticity bonding material has a high silver content, it has a low resistivity (volume resistivity). Therefore, the resistivity (volume resistivity) of bonding materials BD5 and BD7 can be reduced by using a high-elasticity bonding material for bonding materials BD5 and BD7. Therefore, the connection resistance between metal plate MP1 and lead coupling portion LB2 via bonding material BD5, and the connection resistance between metal plate MP2 and lead coupling portion LB4 via bonding material BD7, can be suppressed. Therefore, the performance of the semiconductor device PKG can be improved.

[0148] Simultaneously, even when the resistivity (volume resistivity) of bonding materials BD1, BD2, BD3, BD4, and BD6 is increased by using low-elasticity bonding materials, the planar dimensions (planar area) of bonding materials BD1, BD2, BD3, BD4, and BD6 are still relatively large. Therefore, the resistance (conductivity resistance) of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 can be suppressed. Thus, the connection resistance between the back surface electrode BEH of semiconductor chip CPH and the die pad DPH, the connection resistance between the back surface electrode BEL of semiconductor chip CPL and the die pad DPL, the connection resistance between metal plate MP1 and the pad PDHS1 of semiconductor chip CPH, and the connection resistance between metal plate MP2 and the pad PDLS1 of semiconductor chip CPL can be reduced.

[0149] Therefore, it is preferable to use low-elasticity bonding materials for bonding materials BD1, BD2, BD3, BD4, and BD6 to reduce the risk of cracking in these materials due to heat generated in the semiconductor chip CPH and CPL. Meanwhile, it is preferable to use high-elasticity bonding materials for bonding materials BD5 and BD7 to suppress the connection resistance between metal plate MP1 and lead coupling portion LB2 via bonding material BD5, and the connection resistance between metal plate MP2 and lead coupling portion LB4 via bonding material BD7.

[0150] Another reason for the expectation of using highly elastic bonding materials as bonding materials BD5 and BD7 will be described further.

[0151] During the molding process (the process of forming the sealing part MR), the lead frame LF is clamped between molding mold KG1 and molding mold KG2, and at the same time, the outer lead portion of each lead LD is clamped between molding mold KG1 and molding mold KG2. Lead coupling part LB2 is integrally formed with lead LD2, and lead coupling part LB4 is integrally formed with lead LD4, and the outer lead portions of leads LD2 and LD4 are also clamped between molding mold KG1 and molding mold KG2 (see...). Figure 21 and Figure 22 Since lead LD2 and lead coupling portion LB2 are integrally formed, stress is generated in the bonding material BD5 that bonds lead coupling portion LB2 to metal plate MP1 because the position of lead LD2 is slightly moved when the outer lead portion of lead LD2 is sandwiched between molding die KG1 and molding die KG2. For the same reason, stress is generated in the bonding material BD7 that bonds lead coupling portion LB4 to metal plate MP2. Furthermore, when lead frame LF is sandwiched between molding die KG1 and molding die KG2, molding die KG1 and molding die KG2 are heated to a predetermined temperature, for example, 160°C to 190°C, more preferably about 170°C to 180°C. The heating temperature of molding die KG1 and molding die KG2 is higher than the temperature reached when the temperature of semiconductor chips CPH and CPL rises due to the heat generated in semiconductor chips CPH and CPL during the operation of semiconductor device PKG (the temperature reached by semiconductor chips CPH and CPL). Therefore, when the lead frame LF is sandwiched between the molding die KG1 and the molding die KG2, stress is generated in the bonding materials BD5 and BD7, and the bonding materials BD5 and BD7 are heated.

[0152] Both highly elastic and low-elasticity bonding materials tend to soften and weaken at high temperatures. However, compared to low-elasticity bonding materials, highly elastic bonding materials exhibit a less significant decrease in strength at high temperatures, resulting in higher strength at high temperatures. This is because highly elastic bonding materials have a higher silver (Ag) content and a lower resin content compared to low-elasticity bonding materials. Furthermore, the strength reduction at high temperatures is less pronounced in highly elastic bonding materials with a lower resin content compared to those with a higher resin content. Therefore, it is preferable to use highly elastic bonding materials as bonding materials BD5 and BD7, thereby increasing their strength at high temperatures. Therefore, even when the lead frame LF is sandwiched between molding dies KG1 and KG2 during the molding process, stress is generated in the bonding material BD5 that bonds the lead coupling portion LB2 to the metal plate MP1 and in the bonding material BD7 that bonds the lead coupling portion LB4 to the metal plate MP2. Problems caused by this stress (e.g., cracking of bonding materials BD5 and BD7) can be suppressed or prevented. Thus, the manufacturing yield of the semiconductor device PKG can be improved, and the manufacturing cost of the semiconductor device PKG can be reduced. Similarly, the reliability of the semiconductor device PKG can be improved.

[0153] On the other hand, when the leadframe LF is sandwiched between molding dies KG1 and KG2 during the molding process, the stress generated in bonding materials BD1, BD2, BD3, BD4, and BD6 is relatively small compared to the stress generated in bonding materials BD5 and BD7. This is because the back surfaces DPCb, DPHb, and DPLb of the die pads DPH, DPL, and DPC arranged on molding die KG1 in the leadframe LF are in contact with the upper surface of molding die KG1, thus the positions of the die pads DPH, DPL, and DPC, as well as the positions of the semiconductor chips CPH, CPL, and CPC mounted on the die pads DPH, DPL, and DPC, are stable. Therefore, in bonding materials BD1, BD2, BD3, BD4, and BD6, the stress generated due to the outer lead portion of the leadframe LF being sandwiched between molding dies KG1 and KG2 during the molding process is relatively small. Therefore, considering the stress generated when the outer lead portion of the lead frame LF is clamped between the molding die KG1 and the molding die KG2 during the molding process, it is not necessary to apply highly elastic bonding materials to the bonding materials BD1, BD2, BD3, BD4 and BD6.

[0154] Similarly, by sandwiching the lead frame LF in the molding process, the temperatures of the die pads DPH, DPL, and DPC, the semiconductor chips CPH, CPL, and CPC, the metal plates MP1 and MP2, and the bonding materials BD1, BD2, BD3, BD4, and BD6 increase. As a result, stresses may be generated in bonding materials BD1, BD2, and BD3 due to the difference in the coefficients of thermal expansion between the die pads DPH, DPL, and DPC and the semiconductor chips CPH, CPL, and CPC, and stresses may be generated in bonding materials BD4 and BD6 due to the difference in the coefficients of thermal expansion between the semiconductor chips CPH and CPL and the metal plates MP1 and MP2. However, by using low-elasticity bonding materials for bonding materials BD1, BD2, and BD3, the stresses generated in bonding materials BD1, BD2, and BD3 due to the difference in the coefficients of thermal expansion between the die pads DPH, DPL, and DPC and the semiconductor chips CPH, CPL, and CPC during the molding process can be suppressed. Similarly, by using low-elasticity bonding materials for bonding materials BD4 and BD6, stress generation in bonding materials BD4 and BD6 due to the difference in the coefficients of thermal expansion between the semiconductor chips CPH and CPL and the metal plates MP1 and MP2 during the molding process can be suppressed. Therefore, problems (e.g., cracking) in bonding materials BD1, BD2, BD3, BD4, and BD6 during the molding process can be suppressed or prevented.

[0155] On the other hand, since the lead coupling portion LB2 is separated from the molding dies KG1 and KG2 and is in a floating state, the position of the lead coupling portion LB2 is unstable. Therefore, compared with bonding materials BD1, BD2, BD3, BD4, and BD6, the stress generated in bonding materials BD5 and BD7 is relatively large because the outer lead portion of the lead of the lead frame LF is sandwiched between the molding dies KG1 and KG2 during the molding process. Therefore, it is desirable to improve the strength of bonding materials BD5 and BD7 at high temperatures, and it is preferable to use highly elastic bonding materials to achieve this. Furthermore, since the metal plates MP1 and MP2 are made of the same material as the lead coupling portions LB2 and LB4, almost no stress is generated in the bonding materials BD5 and BD7 due to the difference in the coefficients of thermal expansion between the metal plates MP1 and MP2 and the lead coupling portions LB2 and LB4 during the molding process.

[0156] For the reasons described above, the elastic modulus of the bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 in the semiconductor device PKG is appropriately set. As mentioned above, it is preferable to apply low-elasticity bonding materials to bonding materials BD1, BD2, BD3, BD4, and BD6, and each of the bonding materials BD1, BD2, BD3, BD4, and BD6 has a low elastic modulus. Meanwhile, it is preferable to apply high-elasticity bonding materials to bonding materials BD5 and BD7, and each of the bonding materials BD5 and BD7 has a high elastic modulus.

[0157] Therefore, as a key feature of this embodiment, the elastic modulus of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 is lower than that of each of the bonding materials BD5 and BD7. In other words, the elastic modulus of each of the bonding materials BD5 and BD7 is higher than that of each of the bonding materials BD1, BD2, BD3, BD4, and BD6. Therefore, since the elastic modulus of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 can be reduced, while the elastic modulus of each of the bonding materials BD5 and BD7 can be increased, the aforementioned effects can be achieved, and the overall reliability and performance of the semiconductor device PKG can be improved.

[0158] Similarly, it is preferable to use the same (common) bonding material for bonding materials BD1, BD2, BD3, BD4, and BD6. That is, it is preferable to use the same (common) bonding material for the aforementioned bonding materials BD1a, BD2a, BD3a, BD4a, and BD6a. Therefore, the manufacturing process of the semiconductor device PKG can be easily performed, and the manufacturing cost of the semiconductor device can be reduced. Note that when the same bonding material is used for bonding materials BD1, BD2, BD3, BD4, and BD6, the elastic modulus of bonding material BD1, the elastic modulus of bonding material BD2, the elastic modulus of bonding material BD3, the elastic modulus of bonding material BD4, and the elastic modulus of bonding material BD6 are almost equal to each other.

[0159] Similarly, it is preferable to use the same (common) bonding material for bonding materials BD5 and BD7. That is, it is preferable to use the same (common) bonding material as the aforementioned bonding materials BD5a and BD7a. Therefore, the manufacturing process of the semiconductor device PKG can be easily performed, and the manufacturing cost of the semiconductor device can be reduced. Note that when the same bonding material is used for bonding materials BD5 and BD7, the elastic modulus of bonding material BD5 and the elastic modulus of bonding material BD7 are almost equal to each other.

[0160] Furthermore, more preferably, the elastic modulus (elastic modulus at 25°C) of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 is approximately 1 GPa to 3 GPa (gigapascals). Additionally, more preferably, the elastic modulus (elastic modulus at 25°C) of each of the bonding materials BD5 and BD7 is approximately 10 GPa to 20 GPa (gigapascals). Therefore, the bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 can be optimized, and the aforementioned effects can be accurately obtained.

[0161] As described above, in the case of silver paste, silver content and elastic modulus are related, and the elastic modulus decreases as the silver content decreases. Therefore, the main feature of this embodiment is that the elastic modulus of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 is lower than that of each of the bonding materials BD5 and BD7. This can be expressed in another way as follows: That is, when expressing the main feature of this embodiment in another way, silver paste (silver paste bonding material) is used as the bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7, and the silver (Ag) content of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 is lower than that of each of the bonding materials BD5 and BD7. Therefore, since the elastic modulus of each of the bonding materials BD1, BD2, BD3, BD4 and BD6 can be reduced, and the elastic modulus of each of the bonding materials BD5 and BD7 can be increased, the above-mentioned effects can be achieved, and the overall performance and reliability of the semiconductor device PKG can be improved.

[0162] More preferably, the silver (Ag) content of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 is approximately 82 wt% to 88 wt%. Similarly, more preferably, the silver (Ag) content of each of the bonding materials BD5 and BD7 is approximately 90 wt% to 96 wt%. Therefore, the bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 can be optimized, and the aforementioned effects can be accurately obtained.

[0163] To simplify the semiconductor device manufacturing process, unlike this embodiment, it is more advantageous to use the same (common) material for all bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7. However, in this case, all bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 are formed with either a low elastic modulus or a high elastic modulus. If the elastic modulus of all bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 is high, there is a risk of problems (cracks) occurring in bonding materials BD1, BD2, BD3, BD4, and BD7 due to the heat generated during the operation of the semiconductor chip CPH and CPL. Furthermore, if the elastic moduli of all bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 are low, there is a risk of the aforementioned problems occurring in bonding materials BD5 and BD7 (increased connection resistance and cracking during the molding process). The inventors of this application have investigated the problems arising from the differences in the elastic moduli of each of the bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7, and as a result, adopted a configuration, as in this embodiment, where the elastic moduli of each of the bonding materials BD1, BD2, BD3, BD4, and BD6 are lower than the elastic moduli of each of the bonding materials BD5 and BD7. This can be achieved because the problems arising from the differences in the elastic moduli of each of the bonding materials BD1, BD2, BD3, BD4, BD5, BD6, and BD7 have been investigated.

[0164] Similarly, this embodiment has described the case where semiconductor chips CPH, CPL, and CPC are sealed and packaged together. As another embodiment, semiconductor chips CPH, CPL, and CPC can be sealed and packaged individually. In this case, for example, the cross-sectional structure of the semiconductor device (semiconductor package) including semiconductor chip CPH is different from... Figure 7The structure shown is identical, and the semiconductor device includes a semiconductor chip CPH, a die pad DPH, a metal plate MP1, multiple leads LD (including leads LD1, LD2, and LD6), lead coupling portions LB1 and LB2, bonding materials BD1, BD4, and BD5, and a sealing portion MR that seals them. In this case, the pads PDHA, PDHC, PDHG, and PDHS2 of the semiconductor chip CPH are electrically connected to the leads LD via wires BW. Similarly, in this case, in the semiconductor device including the semiconductor chip CPH, the elastic modulus of each of the bonding materials BD1 and BD4 is lower than that of the bonding material BD5, and from another perspective, the silver (Ag) content of each of the bonding materials BD1 and BD4 is lower than that of the bonding material BD5. However, in this case, the semiconductor device (semiconductor package) including the semiconductor chip CPH does not include the semiconductor chips CPL and CPC, the die pads DPL and DPC, the metal plate MP2, the leads LD3, LD4, LD5a, LD5b, LD7 and LD8, the lead coupling portions LB3 and LB4, and the bonding materials BD2, BD3, BD6 and BD7.

[0165] (Second Embodiment)

[0166] Figure 32 It is a table summarizing the bonding materials BD1, BD2, BD3, BD4, BD5, BD6 and BD7 in each embodiment of the first and second embodiments.

[0167] In the first embodiment, as described above, low-elasticity bonding materials are applied to bonding materials BD1, BD2, BD3, BD4 and BD6, and high-elasticity bonding materials are applied to bonding materials BD5 and BD7.

[0168] In the second embodiment, low-elasticity bonding materials are applied to bonding materials BD1, BD2, and BD3, and high-elasticity bonding materials are applied to bonding materials BD4, BD5, BD6, and BD7. That is, in the second embodiment, the elastic modulus of each of bonding materials BD1, BD2, and BD3 is lower than that of each of bonding materials BD4, BD5, BD6, and BD7. From another perspective, in the second embodiment, the silver (Ag) content of each of bonding materials BD1, BD2, and BD3 is lower than that of each of bonding materials BD4, BD5, BD6, and BD7. Since the second embodiment is otherwise substantially the same as the first embodiment, a repeated description of the second embodiment will be omitted here.

[0169] In the second embodiment, similar to the first embodiment, a low-elasticity bonding material is applied to the bonding materials BD1, BD2, and BD3 used to bond semiconductor chips CPH, CPL, and CPC to die pads DPH, DPL, and DPC. The reason for applying the low-elasticity bonding material to bonding materials BD1, BD2, and BD3 in the second embodiment is the same as in the first embodiment. Also in the second embodiment, by reducing the elastic modulus of bonding materials BD1 and BD2, the stress (strain) generated in bonding materials BD1 and BD2 due to the difference in the coefficients of thermal expansion between die pads DPH and DPL and semiconductor chips CPH and CPL when semiconductor chips CPH and CPL heat up can be suppressed, and the occurrence of cracks in bonding materials BD1 and BD2 can be suppressed as in the first embodiment. Since the occurrence of cracks in bonding materials BD1 and BD2 can be suppressed, the reliability of the semiconductor device PKG can be improved. Furthermore, also in the second embodiment, similar to the first embodiment, it is preferable that the low-elasticity bonding material is applied not only to bonding materials BD1 and BD2 but also to bonding material BD3. Therefore, the bonding material BD3 (BD3a) can be formed from the same bonding material as the bonding materials BD1 and BD2 (BD1a, BD2a), thereby simplifying the manufacturing process of the semiconductor device PKG (more specifically, the die bonding process) and reducing the manufacturing cost of the semiconductor device PKG.

[0170] Similarly, the bonding area between the back surface electrode BEH of semiconductor chip CPH and the die pad DPH (corresponding to the planar area of ​​bonding material BD1) is substantially the same as the area of ​​semiconductor chip CPH, and is relatively large. Furthermore, the bonding area between the back surface electrode BEL of semiconductor chip CPL and the die pad DPL (corresponding to the planar area of ​​bonding material BD2) is substantially the same as the area of ​​semiconductor chip CPL, and is relatively large. The large bonding area between the back surface electrode BEH of semiconductor chip CPH and the die pad DPH is used to reduce the connection resistance between the back surface electrode BEH of semiconductor chip CPH and the die pad DPH via bonding material BD1. Likewise, the large bonding area between the back surface electrode BEL of semiconductor chip CPL and the die pad DPL is used to reduce the connection resistance between the back surface electrode BEL of semiconductor chip CPL and the die pad DPL via bonding material BD2. Therefore, even when a low-elasticity bonding material is used as bonding material BD1, the connection resistance between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH via bonding material BD1 can be easily suppressed, and even when a low-elasticity bonding material is used as bonding material BD2, the connection resistance between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL via bonding material BD2 can be easily suppressed.

[0171] Meanwhile, bonding materials BD4 and BD6 are used to bond metal plates MP1 and MP2 to the pads PDHS1 and PDLS1 of semiconductor chips CPH and CPL. The bonding area between metal plate MP1 and the pad PDHS1 of semiconductor chip CPH (corresponding to the planar area of ​​bonding material BD4) is smaller than the bonding area between the back surface electrode BEH of semiconductor chip CPH and the die pad DPH (corresponding to the planar area of ​​bonding material BD1). Similarly, the bonding area between metal plate MP2 and the pad PDLS1 of semiconductor chip CPL (corresponding to the planar area of ​​bonding material BD6) is smaller than the bonding area between the back surface electrode BEL of semiconductor chip CPL and the die pad DPL (corresponding to the planar area of ​​bonding material BD2). That is, the planar dimension (planar area) of each of bonding materials BD4 and BD6 is smaller than the planar dimension (planar area) of each of bonding materials BD1 and BD2. Therefore, the connection resistance via bonding material BD4 between the metal plate MP1 and the pad PDHS1 of the semiconductor chip CPH tends to be greater than the connection resistance via bonding material BD1 between the back surface electrode BEH of the semiconductor chip CPH and the die pad DPH. Similarly, the connection resistance via bonding material BD6 between the metal plate MP2 and the pad PDLS1 of the semiconductor chip CPL tends to be greater than the connection resistance via bonding material BD2 between the back surface electrode BEL of the semiconductor chip CPL and the die pad DPL.

[0172] Therefore, in the second embodiment, highly elastic bonding materials are applied to bonding materials BD4 and BD6, with the focus on reducing the connection resistance via bonding material BD4 between the metal plate MP1 and the pad PDHS1 of the semiconductor chip CPH, and via bonding material BD6 between the metal plate MP2 and the pad PDLS1 of the semiconductor chip CPL. As described above, highly elastic bonding materials have a high silver content and therefore a low resistivity (volume resistivity), and the resistivity (volume resistivity) of bonding materials BD4 and BD6 can be reduced by using highly elastic bonding materials as bonding materials BD4 and BD6. Therefore, the connection resistance via bonding material BD4 between the metal plate MP1 and the pad PDHS1 of the semiconductor chip CPH, and via bonding material BD6 between the metal plate MP2 and the pad PDLS1 of the semiconductor chip CPL, can be suppressed. As a result, the on-resistance (resistance when turned on) of semiconductor chip CPH (power MOSFET 1) and semiconductor chip CPL (power MOSFET 2) can be further reduced.

[0173] Similarly, in the second embodiment, as in the first embodiment described above, highly elastic bonding materials are applied to bonding materials BD5 and BD7 for the same reasons as in the first embodiment. Therefore, a repeated description of bonding materials BD5 and BD7 will be omitted here.

[0174] The first embodiment described above (where bonding materials BD1, BD2, BD4, and BD6 are low-elasticity bonding materials) is advantageous when the focus is on preventing cracking in the bonding materials BD1, BD2, BD4, and BD6 due to heat generation during the operation of the semiconductor chips CPH and CPL, and on maximizing the reliability of the semiconductor device PKG. Meanwhile, the second embodiment (where bonding materials BD1 and BD2 are low-elasticity bonding materials, and bonding materials BD4 and BD6 are high-elasticity bonding materials) is advantageous when the focus is on reducing the connection resistance via the bonding materials to a certain extent while ensuring the reliability of the semiconductor device PKG (specifically, reducing the on-resistance of the semiconductor chips CPH and CPL).

[0175] Furthermore, in the second embodiment, highly elastic bonding materials are applied to the bonding materials BD4, BD5, BD6, and BD7 of the bonding metal plates MP1 and MP2. Therefore, the same (common) bonding materials can be used for BD4, BD5, BD6, and BD7 used for the bonding metal plates MP1 and MP2. Thus, the manufacturing process of the semiconductor device PKG can be easily performed, and the manufacturing cost of the semiconductor device can be reduced. Note that when the same bonding material is used for bonding materials BD4, BD5, BD6, and BD7, the elastic modulus of bonding material BD4, the elastic modulus of bonding material BD5, the elastic modulus of bonding material BD6, and the elastic modulus of bonding material BD7 are almost equal to each other.

[0176] The invention made by the inventors of this application has been specifically described above based on the embodiments. However, it is self-evident that the invention is not limited to the above embodiments and various modifications can be made without departing from the spirit of the invention.

Claims

1. A semiconductor device, comprising: The first semiconductor chip includes a first field-effect transistor for switching; First chip mounting section, on which the first semiconductor chip is mounted via a first bonding material; The first lead is electrically connected to the first pad for the source of the first semiconductor chip via a first metal plate; The first metal portion is integrally formed with the first lead; as well as The first semiconductor chip, the first metal plate, the first metal portion, at least a portion of the first chip mounting portion, and a portion of the first lead are sealed within the sealing body. The first back surface electrode of the drain of the first semiconductor chip is bonded to the first chip mounting portion via the first bonding material. The first metal plate is bonded to the first pad for the source electrode of the first semiconductor chip via a second bonding material. The first metal plate and the first metal part are bonded together via a third bonding material. The first bonding material, the second bonding material, and the third bonding material are electrically conductive. The elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material. Each of the first bonding material, the second bonding material, and the third bonding material is a silver paste bonding material, and The silver content of each of the first and second bonding materials is lower than the silver content of the third bonding material.

2. The semiconductor device according to claim 1, further comprising: The second semiconductor chip includes a second field-effect transistor for switching; The second chip mounting section, on which the second semiconductor chip is mounted via a fourth bonding material; The second lead is electrically connected to the second pad for the source electrode of the second semiconductor chip via the second metal plate; as well as The second metal portion is integrally formed with the second lead. The sealing body seals at least a portion of the second semiconductor chip, the second metal plate, the second metal portion, the second chip mounting portion, and a portion of the second lead. The second back surface electrode for the drain of the second semiconductor chip is bonded to the second chip mounting portion via the fourth bonding material. The second metal plate is bonded to the second pad for the source electrode of the second semiconductor chip via a fifth bonding material. The second metal plate and the second metal part are bonded together via a sixth bonding material. The fourth, fifth, and sixth bonding materials are conductive, and The elastic modulus of each of the first bonding material, the second bonding material, the fourth bonding material, and the fifth bonding material is lower than the elastic modulus of each of the third bonding material and the sixth bonding material.

3. The semiconductor device according to claim 2, The first field-effect transistor is used for high-side switching, and The second field-effect transistor is used for low-side switching.

4. The semiconductor device according to claim 3, further comprising: A third semiconductor chip includes circuitry configured to control each of the first and second semiconductor chips. as well as The third chip mounting section, on which the third semiconductor chip is mounted via a seventh bonding material. The sealing body seals at least a portion of the third semiconductor chip and the third chip mounting portion.

5. The semiconductor device according to claim 4, The elastic modulus of the seventh bonding material is lower than that of each of the third and sixth bonding materials.

6. The semiconductor device according to claim 5, The first bonding material, the second bonding material, the fourth bonding material, the fifth bonding material, and the seventh bonding material are all made of the same bonding material, and The third bonding material and the sixth bonding material are made of the same bonding material.

7. The semiconductor device according to claim 6, The silver content of each of the fourth, fifth, and seventh bonding materials is lower than the silver content of each of the third and sixth bonding materials.

8. The semiconductor device according to claim 5, The elastic modulus of each of the first, second, fourth, fifth, and seventh bonding materials is between 1 GPa and 3 GPa. The elastic modulus of each of the third and sixth bonding materials is between 10 GPa and 20 GPa.

9. The semiconductor device according to claim 4, The first metal plate, the second metal plate, the first metal part, and the second metal part are made of the same material.

10. The semiconductor device according to claim 4, The first metal plate, the second metal plate, the first metal part, and the second metal part are made of copper or copper alloy.

11. The semiconductor device according to claim 4, The back surfaces of the first chip mounting portion, the second chip mounting portion, and the third chip mounting portion are exposed from the sealing body.

12. The semiconductor device according to claim 4, There are multiple of each type of the first lead and the second lead. The first metal portion couples with a plurality of the first leads, and The second metal portion is coupled with a plurality of the second leads.

13. The semiconductor device according to claim 4, The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are used to form the inverter circuit.

14. The semiconductor device according to claim 1, The first metal plate and the first metal part are made of the same material.

15. A semiconductor device, comprising: The first semiconductor chip includes a first field-effect transistor for switching; First chip mounting section, on which the first semiconductor chip is mounted via a first bonding material; The first lead is electrically connected to the first pad for the source of the first semiconductor chip via a first metal plate; The first metal portion is integrally formed with the first lead; as well as The first semiconductor chip, the first metal plate, the first metal portion, at least a portion of the first chip mounting portion, and a portion of the first lead are sealed within the sealing body. The first back surface electrode of the drain of the first semiconductor chip is bonded to the first chip mounting portion via the first bonding material. The first metal plate is bonded to the first pad for the source electrode of the first semiconductor chip via a second bonding material. The first metal plate and the first metal part are bonded together via a third bonding material. The first bonding material, the second bonding material, and the third bonding material are conductive. The elastic modulus of the first bonding material is lower than that of each of the second and third bonding materials, and The bonding area via the second bonding material between the first metal plate and the first pad for the source of the first semiconductor chip is smaller than the bonding area via the first bonding material between the first chip mounting portion and the first back surface electrode for the drain of the first semiconductor chip.

16. The semiconductor device of claim 15, further comprising: The second semiconductor chip includes a second field-effect transistor for switching; The second chip mounting section, on which the second semiconductor chip is mounted via a fourth bonding material; The second lead is electrically connected to the second pad for the source electrode of the second semiconductor chip via the second metal plate; as well as The second metal portion is integrally formed with the second lead. The sealing body seals at least a portion of the second semiconductor chip, the second metal plate, the second metal portion, the second chip mounting portion, and a portion of the second lead. The second back surface electrode for the drain of the second semiconductor chip is bonded to the second chip mounting portion via the fourth bonding material. The second metal plate is bonded to the second pad for the source electrode of the second semiconductor chip via a fifth bonding material. The second metal plate and the second metal part are bonded together via a sixth bonding material. The fourth, fifth, and sixth bonding materials are conductive. The elastic modulus of each of the first and fourth bonding materials is lower than that of each of the second, third, fifth, and sixth bonding materials, and The bonding area via the fifth bonding material between the second metal plate and the second pad for the source of the second semiconductor chip is smaller than the bonding area via the fourth bonding material between the second chip mounting portion and the second back surface electrode for the drain of the second semiconductor chip.

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