Semiconductor memory device

Abstract

The present disclosure relates to a semiconductor memory device. As miniaturization of a semiconductor memory device, resistance and parasitic capacitance of a wiring become large, which prevents the semiconductor memory device from accelerating. In the semiconductor memory device, the semiconductor device has: a semiconductor substrate having a main surface; a first memory cell row having a plurality of first memory cells arranged on the main surface in parallel with a first direction in a plan view; a first word line connected to the plurality of first memory cells; a first word line driver for changing a potential of the first word line; and a control circuit for outputting a first pre-decode signal to the first word line driver via a first pre-decode line in response to a clock signal and an address signal; and a repeater inserted between the control circuit and the first word line driver.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-203634, filed on November 11, 2019, including this specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Technology

[0003] This invention relates to semiconductor memory devices, and for example to techniques that are effective when applied to semiconductor memory devices with pre-decoders.

[0004] In semiconductor memory devices, the following configuration is typically used: In this configuration, when data is input to / output from a memory cell, the pre-decoder decodes the address signal to select a pre-decode line, and the main decoder selects a single word line based on the selection result of the pre-decode line.

[0005] For semiconductor memory devices using sophisticated components (such as FinFETs), wiring resistance is high due to the narrow width of the wiring, resulting in significant delays in signal transmission through the wiring. Specifically, in addition to the influence of wiring resistance, pre-decoding lines are also significantly affected by parasitic capacitances caused by circuitry (such as decoders or drivers connected to the pre-decoding lines), leading to a substantial delay in the pre-decoding signal transmitted through the pre-decoding lines. Therefore, there is a considerable delay in the process from inputting the address signal into the memory circuitry to transmitting the pre-decoding signal through the pre-decoding lines and selecting the word line based on the pre-decoding signal. Consequently, the input and output of data to and from memory cells are also delayed. In other words, as semiconductor memory devices miniaturize, the wiring resistance and parasitic capacitance of the wiring increase, hindering the speed of semiconductor memory devices.

[0006] In this regard, the following techniques exist.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2013-149332

[0008] Other issues and novel features will become clear from the description in this specification and the accompanying drawings. Summary of the Invention

[0009] The semiconductor memory device according to an embodiment includes: a semiconductor substrate having a main surface; a first memory cell row having a plurality of first memory cells arranged on the main surface parallel to a first direction in a plan view; a first word line connected to the plurality of first memory cells; a first word line driver for changing the potential of the first word line; and control circuitry for outputting a first pre-decoding signal to the first word line driver via the first pre-decoding line in response to a clock signal and an address signal; and a repeater inserted between the control circuitry and the first word line driver.

[0010] A semiconductor memory device according to another embodiment includes: a semiconductor substrate having a main surface; a first memory cell row having a plurality of first memory cells arranged on the main surface parallel to a first direction in a plan view; a first word line connected to the plurality of first memory cells; a first word line driver arranged in the first direction along an extension direction of the first memory cell row and changing the potential of the first word line in the first direction; a memory well connector region arranged in the second direction along an extension direction of the first memory cell row and feeding wells to the first memory cells; and a peripheral well connector region arranged along an extension direction of the word line driver and feeding wells to the word line driver in the first direction, and also arranged in the first direction along an extension direction of the memory well connector region; control circuitry having a first pre-decoding signal responsive to a clock signal and an address signal, the first pre-decoding signal being output to the first word line driver via a first pre-decoding line; and the first pre-decoding line including: a first portion from the control circuitry to a first repeater disposed in the peripheral well connector region, and a second portion from the first repeater to the first word line driver.

[0011] In a semiconductor memory device according to one embodiment, the operating speed of the semiconductor memory device can be improved. Attached Figure Description

[0012] Figure 1 This is an example of a perspective view of a semiconductor memory device according to the first embodiment;

[0013] Figure 2 This is an example of a block diagram of the semiconductor memory device in the first embodiment;

[0014] Figure 3 This is an example of a circuit diagram of the main part of a semiconductor memory device according to the first embodiment;

[0015] Figure 4 This is an example of a circuit diagram of a repeater according to the first embodiment;

[0016] Figure 5 This is an example of a planar layout diagram of a semiconductor memory device according to the first embodiment;

[0017] Figure 6A It is a diagram illustrating the problem;

[0018] Figure 6B This is a schematic diagram illustrating the effectiveness of the first embodiment;

[0019] Figure 7 This is an example of a circuit diagram of the main part of a semiconductor memory device according to the second embodiment;

[0020] Figure 8 This is an example of a floor plan layout of the second embodiment;

[0021] Figure 9 This is a schematic diagram used to explain the problem in the second embodiment;

[0022] Figure 10 This is a schematic diagram illustrating the effect of the second embodiment;

[0023] Figure 11 This is an example of a circuit diagram of the main part of a semiconductor memory device according to the third embodiment;

[0024] Figure 12 This is an example of a floor plan layout of the third embodiment;

[0025] Figure 13 This is an example of a detailed circuit diagram and plan layout of the third embodiment;

[0026] Figure 14 This is a schematic diagram illustrating the effect of the third embodiment;

[0027] Figure 15 This is a cross-sectional view of a semiconductor memory device according to the first embodiment. Detailed Implementation

[0028] In the following, a semiconductor memory device according to an embodiment will be described in detail with reference to the accompanying drawings. In this specification and the drawings, the same or corresponding constituent elements are indicated by the same reference numerals, and repeated descriptions thereof are omitted. In the drawings, configurations may be omitted or simplified for ease of description. Furthermore, embodiments and at least a portion of each modification can be arbitrarily combined with each other.

[0029] Figure 1 This is a perspective view of a semiconductor chip SCP included in a semiconductor memory device (SDV) according to a first embodiment. Figure 15This is a cross-sectional view of a semiconductor memory device (SDV) according to a first embodiment. The semiconductor memory device (SDV) includes a semiconductor chip (SCP), a package (PKG), and a package substrate (PSB).

[0030] On one surface of a semiconductor chip SCP, multiple bumps BP are formed, which serve as external electrodes for the semiconductor chip SCP. The bumps BP are made of a conductive material. The semiconductor chip SCP is then connected to one surface of a package substrate PSB via the bumps BP. The package substrate PSB has conductive wiring (not shown). On another surface of the package substrate PSB, multiple metal balls MBL are formed. The metal balls MBL are made of, for example, a conductive metal (such as solder). The package substrate PSB is mounted on another wiring board (not shown) via the metal balls MBL. Signals can be input to and output from the semiconductor chip SCP from the outside of the semiconductor memory device SDV via the metal balls MBL, the conductive wiring on the package substrate PSB, and the bumps BP. The semiconductor chip is then sealed in a package PKG using a sealant SL made of an insulator (such as resin), the package PKG being configured to cover one surface of the package substrate.

[0031] The semiconductor chip SCP has a semiconductor substrate SUB. The semiconductor substrate SUB is made of semiconductor (such as silicon). The semiconductor substrate SUB has a main surface MS, on which multiple wiring layers (not shown) are formed. The multiple wiring layers include multiple wiring layers, each of which is insulated from each other by an interlayer insulating film of an insulator. Further, the wiring included in each wiring layer is electrically connected to each other via conductive vias formed through the interlayer insulating film. When the main surface is viewed from a direction perpendicular to the main surface, it is referred to below as a plan view. Then, in the plan view, when the first direction on the main surface is the X direction, the direction intersecting the X direction is referred to as the Y direction. A central processing unit (CPU) and a memory circuitry MCT are formed on the main surface MS. The CPU and the MCT are connected to each other via a bus BS, which serves as a path for transmitting signals. The CPU uses data stored in the MCT to perform arithmetic processing.

[0032] Figure 2 This is a block diagram of the memory circuit MCT according to the first example. The memory circuit MCT has a memory cell array ARY, a control circuit CTRL, a row selection circuit RSEL, and input / output circuits I / O. Figure 3 This is a detailed circuit diagram of the row selection circuit RSEL and the control circuit CTRL.

[0033] The memory cell array ARY consists of multiple memory cell rows (MR), multiple word lines (WL), and multiple bit line pairs (BLP).

[0034] Each memory cell row MR comprises multiple memory cells MC arranged parallel to the X direction in the plan view. Starting from the side closer to the control circuit CTRL in the Y direction, the memory cell rows are arranged in the order of 0th memory cell row MR[0], 1st memory cell row MR[1], and nth memory cell row MR[n]. Hereafter, unless otherwise stated, n represents an integer equal to or greater than 0. Additionally, if no symbol follows the square brackets [], it indicates any component in the row. For example, the symbol MR for a memory cell row refers to any memory cell row.

[0035] The memory cell MC is, for example, static random access memory (SRAM). The transistors that make up the memory cell MC are, for example, fin field-effect transistors (FinFETs). Each memory cell row MR includes multiple memory cells MC arranged parallel to the X direction in the plan view.

[0036] Word lines WL are connected to multiple memory cells MC in each memory cell row MR. More specifically, word lines WL are connected to the gate electrode of an access transistor (not shown) included in the memory cell MC. Bit line pairs BLP consist of a pair of bit lines BT and BB, and are provided to each memory cell row consisting of multiple memory cells MC arranged parallel to the Y direction. Bit lines BT and BB are collectively connected to multiple memory cells MC included in each column. Word lines WL and bit line pairs BLP are included in any routing layer of a multi-layer routing layer. The routing layer including word lines WL and the routing layer including bit line pairs BLP are different routing layers from each other.

[0037] The control circuit CTRL has a first pre-decoder FPD, a clock driver CLKD, and logic circuit LC.

[0038] The first pre-decoder FPD responds to the input address signal A by outputting an internal address signal IA to the logic circuit LC, and outputs a second pre-decode signal PDS2 to the second pre-decoder line PDL2, and a third pre-decode signal PDS3 to the third pre-decoder line PDL3. Furthermore, the first pre-decoder FPD responds to the address signal A by outputting a column select signal CSEL to the input-output circuit I / O. Each of the first to third pre-decoder lines PDL1, PDL2, and PDL3 consists of multiple wirings. Figure 3 In the example shown, N is a positive integer, and the first to third pre-decoding lines PDL1, PDL2 and PDL3 are each composed of N wirings.

[0039] The repeater RPT is inserted into the first pre-decoding line PDL1, located between the control circuit CTRL and the main decoder MD. In the following text, k is an integer 0 or greater, and m is an integer greater than k. Figure 2 In the example shown, the repeater RPT is positioned between memory cell row MR[k] in row k and memory cell row MR[m] in row m. In other words, the repeater RPT is inserted into the portion of the first pre-decoding line PDL1 located between the control circuit CTRL and the word line driver WLD[m], but not into the portion located between the control circuit CTRL and the word line driver WLD[k]. The first pre-decoding line PDL1 has a first portion P1 from the repeater to the control circuit, and a portion P2 from the repeater to the main decoder.

[0040] The repeater RPT was not inserted into the second pre-decoding line PDL2 and the third pre-decoding line PDL3.

[0041] The repeater RPT responds to a signal from the first portion P1 of the first pre-decoding line PDL1 by supplying either a power supply potential VDD (e.g., 0.8V) or a ground potential VSS (e.g., 0V) to the second portion P2 of the first pre-decoding line PDL1. For example, when a high-level first pre-decoding signal (power supply potential VDD) is input to the repeater RPT from the first portion P1, the repeater supplies the second portion with a power supply potential VDD corresponding to the high level. Conversely, when a low-level first pre-decoding signal (ground potential VSS) is input to the repeater RPT from the first portion P1, the repeater supplies the second portion with a ground potential VSS corresponding to the low level.

[0042] As in Figure 4 The repeater RPT shown is configured as an even number of CMOS inverters INV connected in series. Each CMOS inverter INV has the following configuration: a p-channel field-effect transistor (PMOS) and an n-channel field-effect transistor (NMOS) are connected in series between the power supply potential VDD and the ground potential VSS. The power supply potential VDD is supplied to the source of the p-channel field-effect transistor PMOS. The ground potential VSS is supplied to the source of the p-channel field-effect transistor NMOS. The drains of the p-channel field-effect transistor PMOS and the n-channel field-effect transistor NMOS are connected to each other. The input portion IN of the repeater is a node where the gates of the p-channel field-effect transistor PMOS and the n-channel field-effect transistor NMOS are connected together. The output portion OUT of the repeater is a node where the drains of the p-channel field-effect transistor PMOS and the n-channel field-effect transistor NMOS are connected together.

[0043] Address signal A is used to select a specific memory cell MC from among multiple memory cells MC included in the memory cell array ARY. Clock driver CLKD, in response to the input clock signal CLK and clock enable signal CEN, outputs internal clock signal ICLK to logic circuit LC. Clock signal CLK is used to determine the timing of the operation of memory circuit MCT; this signal is used to repeat a high level (e.g., power supply potential VDD) and a low level (e.g., ground potential VSS) at a predetermined period. Clock enable signal CEN is used to control whether the clock signal is enabled or disabled.

[0044] The logic circuit LC consists of an AND circuit. The logic circuit LC is connected to the first pre-decoder FPD, the clock driver CLKD, and the first pre-decoder line PDL1. Based on the product logic of the input internal address signal IA and the internal clock signal ICLK, the first pre-decoder signal PDS1 is output to the first pre-decoder line PDL1.

[0045] The row selection circuit RSEL includes a second pre-decoder SPD, a main decoder MD, and a word line driver WLD. The row selection circuit RSEL selects the corresponding memory cell row MR[n] based on the address signal A[n].

[0046] The second predecoder SPD consists of an AND circuit. The second predecoder SPD is provided to each of the multiple memory cell rows (MRs). The second predecoder SPD is connected to the first predecoder FPD via a second predecoder line PDL2 and a third predecoder line PDL3, and is connected to multiple master decoders (MDs) via multiple fourth predecoder lines PDL4. The second predecoder SPD receives a second predecoder signal PDS2 via the second predecoder line PDL2 and a third predecoder signal PD3 via the third predecoder line PDL3. Then, the second predecoder SPD selects one master decoder MD from the multiple master decoders MDs based on the product logic of the second predecoder signal PDS2 and the third predecoder signal PDS3. When the second predecoder SPD selects a master decoder MD, the fourth predecoder signal PDS4 is output to the selected master decoder MD via the fourth predecoder line PDL4. That is, the second predecoder SPD selects one master decoder MD from the multiple master decoders MDs based on the decoding result of the first predecoder FPD.

[0047] The master decoder (MD) consists of a NAND circuit system. The MD is connected to the logic circuit LC via the first pre-decoding line PDL1, to the second pre-decoding line SPD via the fourth pre-decoding line PDL4, and to the word line driver WLD via the fifth pre-decoding line PDL5. Based on the negative logic of the first pre-coding signal PDS1 and the fourth pre-coding signal PDS4, the MD outputs the fifth pre-coding signal PDS5 to the word line driver WLD and selects the word line driver WLD. In other words, the MD selects the word line driver WLD based on the decoding results of the first and second pre-decoding lines.

[0048] A word line driver (WLD) is provided corresponding to the word line (WL) of each row. A power supply potential (VDD, e.g., 0.8V) and a ground potential (VSS, e.g., 0V) lower than the power supply potential are supplied to the word line driver (WLD). The word line driver (WLD) supplies either the power supply potential or the ground potential to the word line (WL) in response to the signal PDS5 provided from the main decoder (MD). That is, the word line driver (WLD) changes the potential of the word line (WL) according to the signal PDS5, as a result of decoding the address signal A. The word line driver (WLD) supplies the power supply potential VDD to the word line (WL), which is also referred to as the "active word line".

[0049] The I / O circuitry includes a column select circuit, an optical amplifier, and a sense amplifier (not shown). The column select circuit selects a bit line pair (BLP) of a column based on the column select signal CSEL, connecting the selected bit line pair BLP to either the sense amplifier or the write amplifier. The write amplifier changes the potential of the bit line pair BLP based on the input signal data D, and inputs the input data D to the memory cell MC. That is, the write amplifier writes data to the memory cell MC. The sense amplifier detects and amplifies the potential difference between bit lines BT and BB included in each column's bit line pair BLP, and outputs output data Q. That is, the sense amplifier is used to read data from the memory cell MC.

[0050] Each memory block MB1, MB2 is defined as follows: a memory cell row MR having a predetermined number of rows in a plurality of memory cell rows MR, a word line driver WLD corresponding to that memory cell row MR, a master decoder MD, and a second pre-decoder SPD. For example, as described later, the memory block is partitioned for each well connector region WTR in which well power is supplied. In other words, the well connector regions WTR are arranged at the boundaries of memory blocks MB1, MB2. In this embodiment, k, m, and n are integers equal to or greater than 1, m is greater than k, and n is an integer greater than m. The memory cell row MR and the corresponding word line driver WLD and master decoder MD for rows 0 to k are included in memory block MB1. The memory cell row MR and the corresponding word line driver WLD and master decoder MD from rows m to n are included in memory block MB2.

[0051] Figure 5 This is a planar layout diagram of the memory circuit MCT in the first embodiment. The memory circuit MCT includes memory blocks MB1, memory blocks MB2, and a well junction region WTR.

[0052] Storage blocks MB1 and MB2 each have a memory cell array ARY and a peripheral region PER, respectively. In this figure, storage blocks MB1 and MB2 are rectangular regions with edges in the X and Y directions.

[0053] A memory cell array (ARY) comprises multiple rows of memory cells (MR) arranged consecutively in the Y direction. Each row of memory cells (MR) comprises multiple memory cells (MC) arranged in the X direction with respect to each other, either linearly or point-symmetrically. The multiple memory cells (MC) are arranged within a rectangular region of length L along the Y direction. In other words, the memory cell array (ARY) has multiple memory cells (MC) arranged in a matrix. Word lines (WL) are arranged to overlap with the rows of memory cells (MR) in a planar view.

[0054] The Peripheral Region (PER) is arranged in the X direction along the extension direction of the Memory Cell Array (ARY). The PER has a Driver Region (DR) and a Pre-decoder Region (PDR).

[0055] A driver region DR is provided for each memory cell row MR, and the driver region DR is formed in the X direction along the extension direction of the memory cell row MR. In other words, the driver region DR is adjacent to the memory cell row MR in the X direction. A word line driver WLD and a main decoder MD are arranged in each driver region DR. The word line driver WLD and the main decoder MD are arranged in a straight line in the X direction, and the word line driver WLD is positioned closer to the memory cell MC in the X direction than the main decoder MD.

[0056] The predecoder region (PDR) is the region that includes the second predecoder SPD. The predecoder region (PDR) is provided for each of the multiple memory cell rows (MRs), and the predecoder region (PDR) is arranged in the X-direction along the extension direction of the driver region (DR). In other words, the predecoder layer (PDR) is adjacent to the driver region (DR) in the X-direction. Figure 5 In this configuration, a pre-decoder region (PDR) is provided for each of the four memory cell rows (MR). Alternatively, the pre-decoder region (PDR) is arranged in the X-direction along the extension direction of the memory array (ARY). The pre-decoder region (PDR) is arranged such that the driver region (DR) is located in the X-direction between the pre-decoder region (PDR) and the memory cell array (ARY).

[0057] The well connector region (WTR) is located between memory blocks MB1 and MB2 in the Y direction. The well connector region (WTR) includes the memory well connector region (MWT) and the peripheral well connector region (PWT).

[0058] The memory well connector region (MWT) supplies power to the well of the memory cell array (MC). The memory well connector region (MWT) is arranged in the Y direction along the extension of the memory cell array (ARY).

[0059] The peripheral well connector region (PWT) performs well power feeding to the word line driver (WLD), the main decoder (MD), and the second pre-decoder (SPD). The peripheral well connector region (PWT) is positioned along the Y-direction of the driver region (DR) and the pre-decoder region (PDR). The memory well connector region (MWT) is arranged along the X-direction of the memory well connector region (MWT). In other words, the memory well connector region (MWT) is adjacent to the memory well connector region (MWT) in the X-direction.

[0060] The first predecoder FPD is arranged in the Y direction along the extension direction of storage block MB1. It can be said that the first predecoder FPD is adjacent to storage block MB1 in the Y direction. In the Y direction, the distance from the first predecoder FPD to storage block MB2 is longer than the distance from the first predecoder FPD to the second storage block MB1.

[0061] In the plan view, the first pre-decoding line PDL1 extends in the Y direction to overlap with the driver region DR. In the plan view, a first portion P1 of the first pre-decoding line PDL1 is arranged to overlap with multiple driver regions DR included in memory block MB1. In the plan view, a second portion P2 of the first pre-decoding line PDL1 is arranged to overlap with multiple driver regions DR included in memory block MB2.

[0062] The repeater RPT is positioned on the peripheral trap connector area PWT. Figure 5In the example shown, the repeater RPT is not set in the driver region DR or the memory sink connector region MWT.

[0063] In the plan view, the second pre-decoding line PDL2 and the third pre-decoding line PDL3 extend in the Y direction to overlap with the pre-decoding region PDR. In the X direction, the second pre-decoding line PDL2 is arranged between the first pre-decoding line PDL1 and the third pre-decoding line PDL3.

[0064] Figure 6A This is a diagram used to illustrate the problem, and Figure 6B This is a schematic diagram illustrating the effects of the first embodiment. In Figure 6A, six master decoders (MDs) are connected to the first pre-decoding line (PDL1). Considering the fan-out number, which indicates the number of logic gates connected to a single wiring, the fan-out number of the first pre-decoding line (PDL1) is 6. On the other hand, in the first embodiment, as in... Figure 6B As shown, the repeater RPT is set in the first pre-decoding line PDL1. Then, viewed from the control circuitry, the first pre-decoding line PDL1 includes a first section from the control circuitry to the repeater, and a second section P2 preceding the repeater. In this case, since the first section P1 is connected to the three master decoders MD and the repeater RPT, the fan-out is 4. Since the second section P2 is connected to the three master decoders MD, the fan-out is 3.

[0065] The fan-out number that is larger in either the first part P1 or the second part P2 of the first pre-decoding line PDL1 is called the maximum fan-out number. When the maximum fan-out is large, the load capacitance of the logic gate becomes larger, and the delay becomes longer.

[0066] Because in Figure 6B In the example, the maximum fan-out is 4, therefore, compared to Figure 6A Compared to the example where the maximum fan-out is 6, the maximum fan-out of the first pre-decoding line PDL1 can be reduced. Therefore, compared to the example where... Figure 6A Compared to the exemplary embodiments shown, the load capacitance of the logic gate relative to the first pre-decoding line PDL1 can be reduced, and the delay of the signal passing through the first pre-decoding line PDL can be reduced.

[0067] In the first embodiment, by inserting the repeater RPT into the first pre-decoding line PDL1, the fan-out of the first pre-decoding line PDL1 can be reduced, and the load capacitance can be reduced. The delay in the first pre-decoding signal PDS1 transmitted from the control circuit CTRL to the main decoder MD via the first pre-decoding line PDL can be suppressed, and the delay can be suppressed according to the internal clock signal ICLK until the potential of the word line WL is changed. Therefore, it has the effect of enhancing the operation of the memory circuit MCT.

[0068] Furthermore, by placing the repeater in the peripheral well junction region PWT, the repeater RPT can be configured without increasing the length L of the memory cell row MR in the Y direction. If the repeater is placed in the drive region DR, the length L of the memory cell row in the Y direction is longer than that of other memory cell rows for the row in which the repeater is located. Therefore, the symmetry of the memory cells MC is disrupted, leading to manufacturing deviations. On the other hand, by placing the repeater RPT in the peripheral well junction region PWT as in the first embodiment, the difference in the length L of the memory cell row MR in the Y direction for each memory cell row MR can be suppressed. Furthermore, by placing the repeater in the existing well junction region, the increase in area caused by the repeater can be suppressed, and an area-saving effect can be achieved.

[0069] (Example 2) Figure 7 This is a circuit diagram of the row selection circuit RSEL and the control circuit CTRL in the second embodiment. Figure 8 This is a plan view of the memory circuit MCT according to the second embodiment. In the second embodiment, as in... Figure 7 and Figure 8 As shown, the first pre-decoding line PDL1 branches at branch node BN. Furthermore, the master decoder MD is not connected to the first portion of the first pre-decoding line PDL1, which is closer to the control circuit CTRL than the repeater RPT. The remainder of this configuration is the same as in the first embodiment, and therefore its description is omitted.

[0070] When viewed from the control circuit CTRL, the first pre-decoding line PDL1 comprises a first section from the control circuit to the repeater RPT, and a second section P2 preceding the repeater. The main decoder MD is not connected to the first section P1.

[0071] The second part P2 includes a third part P3 extending from the repeater RPT to the main decoder MD included in storage block MB1, and a fourth part P4 extending from the repeater RPT to the main decoder MD included in storage block MB2. The third part P3 extends in the Y direction from the repeater RPT along a direction close to the control circuit CTRL. The third part P3 is connected to the main decoder MD of storage block MB1. Conversely, the fourth part P4 extends in the Y direction from the repeater RPT along a direction away from the control circuit CTRL. The fourth part P4 is connected to the main decoder MD of storage block MB2.

[0072] As in Figure 8 As shown, the repeater RPT is formed in the peripheral trap junction region PWT. Then, in the plan view, the branch node BN is positioned at a location overlapping the peripheral trap junction region PWT.

[0073] Figure 9 This is a schematic diagram illustrating the problem in Example 2. Figure 9 The diagram shows a row selection circuit RSEL, which simplifies the configuration of the first embodiment. Here, six word lines WL corresponding to six rows of memory cells are shown. To indicate direction, the right side of the paper surface is defined as the +X direction, the left side as the -X direction, the top side as the +Y direction, and the bottom side as the -Y direction. For the control circuit CTRL, the word line WL with the shortest distance in the Y direction is called the near-end word line NWL, and for the control circuit CTRL, the word line WL with the farthest distance in the Y direction is called the far-end word line FWL. When viewed from the control circuit, the first pre-decoding line PDL1 includes a first portion from the control circuit to the repeater, and a second portion P2 before the repeater.

[0074] exist Figure 9 In this context, R represents the parasitic resistance generated for each memory cell row MR relative to the first pre-decoding line PDL1. In this case, since four parasitic resistances R are connected in series from the control circuit CTRL to the main decoder MD connected to the far-end word line FWL, the combined resistance is 4R. On the other hand, in Figure 10 In the simplified example of the second embodiment shown, the output of the repeater RPT is connected via branch node BN to three word lines WL arranged in the +Y direction relative to branch node BN and three word lines WL arranged in the -Y direction relative to branch node BN. Therefore, the combined resistance received from the repeater to the far word line FWL becomes R'+2R. The relationship between R' and R varies depending on the design conditions, but when R' is less than 2R, R'+2R is less than 4R. Therefore, compared to... Figure 9 As shown, the combined resistance of the first pre-decoding line PDL1 can be reduced in the portion from the control circuit CTRL to the far word line FWL. Therefore, compared to the memory circuit MCT in the first embodiment, the time it takes for the signal to travel from the control circuit CTRL to the far word line FWL can be shortened, and the operation of the memory circuit MCT can be enhanced.

[0075] Furthermore, by making the distances from the repeater RPT to the far word line FWL and from the repeater RPT to the near word line NWL equal, the time difference between the time it takes for the signal to travel from the control circuit CTRL to the near word line NWL and the time it takes for the signal to travel from the control circuit CTRL to the far word line FWL can be essentially eliminated. Moreover, considering signal delays, the operating margin time can be set to be shorter. Therefore, this effectively enhances the operation of the memory circuit MCT.

[0076] exist Figure 7 In the example shown, word line WL[0] in row 0 is the near-end word line, and word line WL[n] in row n is the far-end word line. (See reference...) Figure 9 and 10 As described, in the memory circuit MCT according to the second exemplary embodiment, the wiring resistance from the control circuit CTRL to the far word line WL[n] can be reduced compared to the first exemplary embodiment. Therefore, the delay time until the signal reaches the far word line WL[n] from the control circuit CTRL can be shortened, and the operation speed of the memory circuit MCT is effectively improved. Furthermore, in the memory circuit MCT according to the second embodiment, since the distance from the repeater RPT to the far word line WL[n] and the distance from the repeater RPT to the near word line WL[0] are substantially equal, the time required for the signal to reach each of the near word line WL[0] and the far word line WL[n] from the control circuit CTRL is substantially equal, and considering the signal delay, the operating margin time can be set to be shorter. Therefore, it has the effect of enhancing the operation of the entire memory circuit MCT.

[0077] exist Figure 10 In the example, the fan-out of the first part P1 is 1, and the fan-out of the second part P2 is 6.

[0078] (Example 3) Figure 11 This is a circuit diagram of the row selection circuit RSEL in the third embodiment. Figure 12 This is a plan view of the memory circuit MCT in the third embodiment, and Figure 13 This is a detailed circuit diagram of the row selection circuit RSEL in the third embodiment, and in the planar layout diagram of the third embodiment, the repeater RPT is provided to each second pre-decoder SPD. The rest of this configuration is the same as in the first embodiment, and therefore its description is omitted.

[0079] exist Figure 11 In memory block MB1, a repeater RPT is provided to each of the (k+1) rows of memory cells connected to the second predecoder SPD. Further, in memory block MB2, a repeater RPT is provided to each of the (n-m+1) rows of memory cells.

[0080] Figure 12 This is a plan view of the memory circuit MCT in the third embodiment. In the X direction, the repeater RPT is disposed between the pre-decoder layer PDR and the driver region DR. Since the second pre-decoder SPD is arranged in the pre-decoder region PDR and the main decoder MD is arranged in the driver region DR, it can be said that the repeater RPT is disposed between the second pre-decoder SPD and the main decoder MD.

[0081] Figure 13 This is a detailed schematic plan view of the row selection circuit RSEL for N=8 in Embodiment 3. Here, each of the first pre-decoding line PDL1, the second pre-decoding line PDL2, and the third pre-decoding line PDL3 consists of eight wirings. The number of memory cell rows included in the memory circuit MCT is 8×8×8 = 512 rows. That is, the number of word lines WL included in the memory circuit MCT is 512. Figure 13 In the diagram, rows 0 to 63 are shown out of 512 memory cell rows. In the memory circuit MCT, the Y-direction is continuously repeated with... Figure 13 The same configuration as in [the previous context].

[0082] The first part P1 of the first pre-decoding line PDL1 includes wiring PDL1A[0:7] extending in the Y direction. Note that a is an integer of 0 or greater, and b is an integer greater than a, and the wiring symbol [a:b] indicates multiple (b-a+1) wirings from wiring [a] to wiring [b]. The second part P2 of the first pre-decoding line PDL1 includes wiring PDL1B[0:7] extending in the Y direction. Assuming k is an integer from 0 to 7, PDL1A[k] is connected to PDL1B[k] via repeater RPT[k]. For example, wiring PDL1A[0] is connected to wiring PDL1B[0] via repeater RPT[0]. Wiring PDL1A[1] is connected to wiring PDL1B[1] via repeater RPT[1]. Then, wiring PDL1A[7] is connected to wiring PDL1B[7] via repeater RPT[7].

[0083] The second pre-decoding line PDL2 comprises multiple wirings PDL2[0:7] extending in the Y direction. When p is an integer equal to or greater than 0, the second pre-decoding line PDL2[p] is connected to one input of the second pre-decoder SPD[p].

[0084] The third pre-decoder line PDL3 comprises multiple wirings PDL3[0:7] extending in the Y direction. Like the second pre-decoder line PDL2, the third pre-decoder line PDL3[p] is connected to another input terminal of the second pre-decoder SPD[p].

[0085] exist Figure 13In the embodiment shown, all input terminals of the second predecoder SPD connected to the third predecoder line PDL3 are connected to the third predecoder line PDL3[0]. Although not shown, the portion of the second predecoder SPD whose input terminals are continuously connected to the third predecoder line PDL[1] in the Y direction of the figure is PDL3[1], PDL3[2], ... PDL3[7], providing a circuit that is changed in this order.

[0086] The repeater RPT is arranged in the X direction along the extension direction of the second pre-decoder SPD. The repeater RPT[p] is set in the X direction along the extension direction of the second pre-decoder SPD[p].

[0087] Figure 14 This is a simplified example of Embodiment 3. The first portion P1 of the first pre-decoding line PDL1 is connected to two repeaters RPT. Therefore, the fan-out of the first portion P1 is 2. The second portion P2 of the first pre-decoding line PDL1 is connected to three master decoders MD. Therefore, the fan-out of the second portion P2 is 3.

[0088] In the first embodiment Figure 6B In the case shown, the maximum fan-out of the wiring PDL1 is 4. Further, in the second embodiment... Figure 10 In the case shown, the maximum fan-out of the wiring PDL1 is 6. On the other hand, in Figure 14 In Embodiment 3 shown, the maximum fan-out of the wiring PDL1 is 3. Therefore, in the third embodiment, compared with the first and second embodiments, the maximum fan-out can be reduced, which has the effect of suppressing signal delay.

[0089] It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0090] Furthermore, even when a specific numerical example is described, it can be a value exceeding the specific value, or it can be a value less than the specific value, except where theoretically the specific value is clearly limited to a numerical value.

Claims

1. A semiconductor memory device, comprising: Semiconductor substrate, having a main surface; A first memory cell row has a plurality of first memory cells arranged on the main surface parallel to a first direction in the plan view; The first word line is connected to the plurality of first memory cells; The first word line driver is configured to change the potential of the first word line; The control circuit is configured to output a first pre-decoding signal to the first word line driver via the first pre-decoding line in response to a clock signal and an address signal. as well as A repeater circuit is inserted into the first pre-decoding line between the control circuit and the first word line driver. The first row of memory cells is included in the memory cell array. The first word line driver is included in the peripheral region, which is positioned along the first direction in the plan view in the extension direction of the memory cell array. The semiconductor memory device further includes: The memory well junction region is arranged in a second direction along the extension direction of the memory cell array and supplies well power to the first memory cell, the second direction intersecting the first direction in the plan view; as well as The peripheral well connector region is arranged in the second direction along the extension direction of the memory well connector region, and supplies the well power to the first word line driver. The repeater is located in the peripheral trap junction area.

2. The semiconductor memory device of claim 1, wherein each of the plurality of first memory cells comprises a fin field-effect transistor.

3. The semiconductor memory device according to claim 1, further comprising: The second memory cell row has a plurality of second memory cells arranged in the extension direction of the first memory cell row, and the second memory cell row is arranged in a second direction parallel to the first direction, the second direction intersecting the first direction in the plan view; The second word line is connected to the plurality of second memory cells; as well as The second word line driver is configured to change the potential of the second word line. One of the first memory cell row or the second memory cell row is selected via the address signal. The first pre-decoding line transmits the first pre-decoding signal to either the first word line driver or the second word line driver. The repeater is inserted between the control circuit and the first word line driver, and The repeater is not inserted between the control circuit and the second word line driver.

4. The semiconductor memory device according to claim 1, wherein the first pre-decoding line comprises: From the repeater to the first part of the control circuit; From the repeater to the second part of the first word line driver The repeater responds to the first pre-decoding signal by providing the second part with a second potential corresponding to a high level of the first pre-decoding signal or a second potential corresponding to a low level of the first pre-decoding signal.

5. The semiconductor memory device of claim 1, wherein the repeater comprises an even number of CMOS inverters connected in series.

6. The semiconductor memory device of claim 1, wherein the control circuit, in response to the address signal, outputs a second pre-decoding signal to a second pre-decoding line different from the first pre-decoding line.

7. The semiconductor memory device of claim 6, wherein the repeater is not inserted into the first pre-decoding line.

8. The semiconductor memory device according to claim 6, The control circuit includes: First pre-decoder; The logic circuit is connected to the first pre-decoding line; as well as A clock driver is configured to output an internal clock signal in response to the input clock signal. The first pre-decoder, in response to the address signal, outputs an internal address signal to the logic circuit and outputs the second pre-decode signal to the second pre-decode line. The logic circuit, in response to the internal clock signal and the internal address signal, outputs the first pre-decoding signal to the first pre-decoding line.

9. The semiconductor memory device according to claim 8, The first predecoder, in response to the address signal, outputs a third predecoder signal to a third predecoder line that is different from the first and second predecoder lines. The semiconductor memory device further includes: The second predecoder is connected to the second predecoder line and the third predecoder line, and in response to the second predecoder signal and the third predecoder signal, outputs a fourth predecoder signal to the fourth predecoder line and the first predecoder line; as well as The master decoder is connected to the fourth pre-decoding line and the first pre-decoding line, and in response to the fourth pre-decoding signal and the first pre-decoding signal, outputs the fifth pre-decoding signal to the first word line driver.

10. The semiconductor memory device of claim 9, wherein the first pre-decode line comprises a first portion and a second portion, the first portion being closer to the first pre-decoder than the repeater, and the second portion being closer to the first word line driver than the repeater. The second part comprises a third part and a fourth part. The third part extends in a second direction, which intersects with the first direction in the plan view. The fourth part extends in the second direction and is different from the third part. The third part is connected to the main decoder. The first part is not connected to the main decoder.

11. The semiconductor memory device of claim 9, wherein the repeater is disposed between the second pre-decoder and the main decoder.

12. A semiconductor memory device, comprising: Main surface; A first memory cell row has a plurality of first memory cells arranged on the main surface parallel to a first direction in the plan view; The first word line is connected to the plurality of first memory cells; A first word line driver is arranged in the first direction along the extension direction of the first memory cell row and changes the potential of the first word line. The memory sink connector region is arranged in a second direction along the extension direction of the first memory cell row and supplies sink power to the first memory cell row, the second direction intersecting the first direction in the plan view; The peripheral well connector region is arranged in the second direction along the extension direction of the first word line driver, and well power is supplied to the memory well connector region arranged in the first direction along the extension direction of the first word line driver, and well power is supplied to the first word line driver in the first direction. The control circuit has a first pre-decoding signal, which is responsive to a clock signal and an address signal, and the first pre-decoding signal is output to the first word line driver via a first pre-decoding line; The first pre-decoding line includes a first part and a second part, the first part extending from the control circuit to a first repeater disposed in the peripheral well connector region, and the second part extending from the first repeater to the first word line driver.

13. The semiconductor memory device of claim 12, further comprising: A second memory cell row has a plurality of second memory cells arranged in the second direction along the extending direction of the first memory cell row, wherein a memory well connector region is inserted between the plurality of second memory cells. The second word line is connected to the plurality of second memory cells; as well as A second word line driver is arranged in the first direction along the extension direction of the second memory cell row and changes the potential of the second word line; The control circuit, in response to the clock signal and the address signal, outputs the first pre-decoding signal to the first word line driver via the first pre-decoding line. The second part of the first pre-decoding line includes: The second portion from the first repeater to the first word line driver, and The third part from the first repeater to the second word line driver.

14. The semiconductor memory device according to claim 12, The first repeater responds to the first pre-decoding signal by supplying the second part with a first potential corresponding to the high level of the first pre-decoding signal or a second potential corresponding to the low level of the first pre-decoding signal.

15. The semiconductor memory device according to claim 12, The control circuit, in response to the address signal, outputs a second pre-decoding signal to a second pre-decoding line that is different from the first pre-decoding line.

16. The semiconductor memory device according to claim 15, The control circuit includes: First pre-decoder; The logic circuit is connected to the first pre-decoding line; as well as A clock driver for outputting an internal clock signal in response to the input clock signal. The first pre-decoder, in response to the address signal, outputs an internal address signal to the logic circuit and outputs the second pre-decode signal to the second pre-decode line. The logic circuit, in response to the internal clock signal and the internal address signal, outputs the first pre-decoding signal to the first pre-decoding line.

17. The semiconductor memory device according to claim 16, The first predecoder, in response to the address signal, outputs a third predecoder signal to a third predecoder line that is different from the first and second predecoder lines. The semiconductor memory device further includes: The second pre-decoder is connected to the second pre-decoder line and the third pre-decoder line, and outputs the fourth pre-decoder signal to the fourth pre-decoder line; The first pre-decoding line responds to the second pre-decoding signal and the third pre-decoding signal; as well as The master decoder is connected to the fourth pre-decoding line and the first pre-decoding line, and in response to the fourth pre-decoding signal and the first pre-decoding signal, outputs the fifth pre-decoding signal to the first word line driver.

18. The semiconductor memory device of claim 17, wherein the second repeater is disposed between the second pre-decoder and the main decoder.

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