Semiconductor packaging and manufacturing methods

Abstract

This disclosure provides a semiconductor package comprising: a semiconductor die having a first surface and a second surface opposite to the first surface; a conductive wiring layer stacked on and adjacent to the semiconductor die and the first surface; a package body encapsulating the semiconductor die and stacked on and with the conductive wiring layer; and a replacement structure exposed from the package body and without filler. This disclosure also discloses a method for manufacturing the semiconductor package.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package, and more specifically to a fan-out package structure. Background Technology

[0002] To adapt to the development of mobile communication devices, smaller size (e.g., thinner), lower manufacturing costs, functional flexibility, and faster product cycles are essential for device packaging.

[0003] Grinding is a well-known method in semiconductor packaging for reducing package thickness. Generally, a semiconductor die is placed on a redistribution layer (RDL), encapsulated with molding compound, and the molding compound is ground to reduce the package thickness, followed by die sawing or single-cutting. However, this manufacturing sequence has several problems: First, ground packages are prone to warping due to insufficient structural stability. This warping can weaken the vacuum suction provided by the substrate during subsequent dicing, increasing the difficulty of the dicing operation. Second, because the roller blade can increase its rotational speed at the moment of complete cutting, cracks may occur near the molding compound. For partial cutting operations, the roller blade may also cause nearby molding compound to crack due to unavoidable vibrations during operation. Summary of the Invention

[0004] In some embodiments, this disclosure provides a semiconductor package comprising: a semiconductor die having a first surface and a second surface opposite to the first surface; a conductive wiring layer stacked with the semiconductor die and adjacent to the first surface; a package body encapsulating the semiconductor die and stacked with the conductive wiring layer; and a replacement structure exposed from the package body and without filler.

[0005] In some embodiments, this disclosure provides a semiconductor package comprising: a semiconductor die having a first surface and a second surface opposite to the first surface; a conductive wiring layer stacked with the semiconductor die and adjacent to the first surface; a package body encapsulating the semiconductor die and stacked with the conductive wiring layer, the package body having a first modulus; and a replacement structure exposed from the package body and having a second modulus. The second modulus is greater than the first modulus.

[0006] In some embodiments, this disclosure provides a method for manufacturing a semiconductor package, the method comprising: providing a first carrier having a first surface; disposing a replacement structure above the first surface; and engaging the replacement structure on the first carrier to a second carrier carrying a plurality of semiconductor dies, the replacement structure being aligned with regions that separate adjacent semiconductor dies. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that the features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0009] Figure 2 Description of some embodiments according to this disclosure Figure 1 A top view of a semiconductor package.

[0010] Figure 3 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0013] Figure 6 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0015] Figure 8 A cross-sectional view of a semiconductor package according to some embodiments of the present disclosure is shown.

[0016] Figures 9A to 9C This illustration shows cross-sectional views of intermediate products during various manufacturing operations of semiconductor packaging according to some embodiments of the present disclosure.

[0017] Figure 9C Description of some embodiments according to this disclosure Figure 9C A top view of the intermediate products in the process.

[0018] Figures 10A to 10L This illustration shows cross-sectional views of intermediate products during various manufacturing operations of semiconductor packaging according to some embodiments of the present disclosure. Detailed Implementation

[0019] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0020] Spatial descriptions, such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc., are specified relative to a particular component or group of components or a plane of a component or group of components to orient one or more components as shown in the associated figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged spatially in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangement.

[0021] This disclosure provides a fan-out thin package and a method for manufacturing the same. Compared to comparative embodiments, the package structure of this disclosure is slit before the application of a polishing operation. When in panel or substrate form, the semiconductor package structure is halved and then polished to reduce the package thickness to the desired level. This manufacturing sequence effectively solves the problems of lack of structural stability after polishing, reduced vacuum suction during dicing, and warping caused by peeling / cracking of adjacent molding material during roller blading.

[0022] The packaging structure described in this disclosure includes a replacement structure having a higher modulus than the molding material and the RDL. The replacement structure surrounds the semiconductor die and overlaps with the saw groove. The dimensions of the replacement structure are adjustable to achieve an optimal structural balance among the molding material, the replacement structure, the semiconductor die, and the RDL.

[0023] refer to Figure 1 , Figure 1 A cross-sectional view of a semiconductor package 10 according to some embodiments of the present disclosure is shown. The semiconductor package 10 includes a semiconductor die 100 having a first surface 100A and a second surface 100B opposite to the first surface 100A. In some embodiments, the first surface 100A is an active surface, wherein a plurality of conductive elements 101 are adjacent to, embedded below, and / or partially exposed from the active surface. The conductive elements 101 may include conductive pads, conductive pillars, solder bumps, C4 bumps, and equivalents thereof. The conductive elements 101 on the first surface are configured to form electrical connections with a conductive wiring layer 103 stacked with the semiconductor die 100. The conductive wiring layer 103 is closer to the first surface 100A than the second surface 100B of the semiconductor die 100. In some embodiments, the conductive wiring layer 103 is a redistribution layer (RDL) consisting of a dielectric layer and conductive lines embedded in the dielectric layer. In some embodiments, the conductive wiring layer 103 is a fan-out RDL that expands the area coverage of the conductive elements 101 on the first surface 100A of the semiconductor die 100.

[0024] Package 105 surrounds semiconductor die 100 and conductive element 101, and is disposed on conductive wiring layer 103. In some embodiments, package 105 is composed of epoxy compound and filler. In some embodiments, package 105 is an encapsulation molding material (EMC) commonly used to protect integrated circuit (IC) chips. Its composition always contains a large amount (about 70%) of filler and affects the properties of EMC. In some embodiments, the filler comprises various types of oxides, silicon oxide, or silicon. Replacement structure 107 is partially encapsulated by package 105, surrounds the side surface 100C of semiconductor die 100, and is exposed from package 105 on the top and side surfaces of package 105. Side surface 100C of semiconductor die 100 connects to the first surface 100A and the second surface 100B of semiconductor die 100. In some embodiments, unlike package 105, replacement structure 107 does not contain any of the fillers as described above in package 105. Refer to this disclosure Figures 10A to 10G The replacement structure 107 is integrated into the semiconductor package 10 through a molding operation that transfers the replacement structure 107 from another carrier to the space between adjacent semiconductor dies 100. The filler in the package 105, particularly those adjacent to the replacement structure 107, is intact and unbroken. In some comparative embodiments, broken filler is typically observed because a portion of the package 105 is removed after curing. Mechanical removal processes can produce broken filler at the removal boundary of the package 105. Non-homogeneous material can subsequently fill the empty spaces in the package created by the removal operation. In other words, in comparative embodiments, broken filler can be observed at the boundary between the cured package and the non-homogeneous material. In this disclosure, because the replacement structure 107 is integrated into the semiconductor die 100 before the cured package 105, the filler in the package 105, even at the boundary between the cured package 105 and the replacement structure 107, is intact and unbroken.

[0025] In some embodiments, the Young's modulus (hereinafter referred to as modulus) of the replacement structure 107 is greater than the modulus of the package 105. In some embodiments, the modulus of the replacement structure 107 is greater than the modulus of the conductive wiring layer 103. For example, the modulus of the package 105 may be in the range of about 20 GPa to 30 GPa, and the modulus of the conductive wiring layer 103 may be in the range of about 3 to 5 MPa or 1 to 3 GPa, depending on whether the ambient temperature is below or above the glass transition temperature (Tg). The modulus of the replacement structure 107 may be greater than 50 GPa. In some embodiments, the replacement structure 107 is made of a pre-impregnated composite optical fiber in the form of an epoxy matrix having a modulus of about 60 GPa to 70 GPa. In some embodiments, the replacement structure 107 may be made of glass having a modulus of about 70 GPa to 80 GPa. In some embodiments, the replacement structure 107 may be made of ceramic having a modulus greater than 300 GPa. In some embodiments, the replacement structure 107 may be pre-formed to a desired shape or size; for example, the replacement structure 107 may have a columnar cross-section with a uniform width, such as... Figure 1 As described herein, alternative structure 107 may have a wider bottom and a narrower top, such as Figure 5 As explained in the text.

[0026] like Figure 1 As described herein, the distance D1 between the side surface 100C of the semiconductor die 100 and the side surface of the replacement structure 107 is in the range of approximately 3 μm to approximately 10 μm. (Refer to this disclosure...) Figures 10A to 10G The replacement structure 107 is integrated into the semiconductor package 10 through a molding operation that transfers the replacement structure 107 from another carrier to the space between adjacent semiconductor dies 100. The distance D1 between the side surface 100C of the semiconductor die 100 and the side surface of the replacement structure 107 can be modified by applying a wider or narrower replacement structure 107. The determination of the distance D1 may include the modulus of the replacement structure 107, the modulus of the package body 105, the modulus of the conductive wiring layer 103, and the corresponding volume suitable for preventing package warpage after the package thinning operation. In this disclosure, the distance D1 is determined to be in the range of about 3 μm to about 10 μm because the processing window for aligning the replacement structure 107 and the semiconductor die 100 on the two corresponding carriers is about 3 μm, and a distance D1 greater than 10 μm may reduce production by reducing the total number of packages per operation.

[0027] like Figure 1 As shown, the second surface 100B, the package 105, and the replacement structure 107 form coplanar surfaces due to a back-side grinding operation, as will be described in this disclosure. Figure 10LAs described in the present disclosure. The package 105 is exposed from the package at two different locations, with a first portion 105A adjacent to the second surface 100B and the second portion 105B adjacent to the conductive wiring layer 103. In some embodiments, the surface roughness of the second portion 105B is greater than the surface roughness of the first portion 105A. Referring to the present disclosure... Figure 10J and Figure 10L The first part 105A is formed by a back-side grinding operation, and the second part 105B is formed by a bare-blade sawing operation. The sawing blade typically produces a rougher surface than the grinding machine.

[0028] like Figure 1 As shown, the thickness or height H2 of the semiconductor die 100 may be shorter than the height H1 of the replacement structure 107. The height H2 is measured from the first surface 100A to the second surface 100B of the semiconductor die 100. In some embodiments, a height difference dH may be observed in the semiconductor package 10 because when a saw blade cuts a panel configuration adjacent to the semiconductor package 10 from a strip or from the side of the conductive wiring layer 103, peeling or cracking may easily form at the interface between the package 105 and the replacement structure 107. Keeping this interface away from the first surface 100A of the semiconductor die 100 reduces the likelihood of cracks propagating toward the active surface of the semiconductor die 100. Therefore, one end of the replacement structure 107 may not be flush with the first surface 100A of the semiconductor die 100, but extends toward the conductive wiring layer 103 to keep the interface away from the active surface of the semiconductor die 100.

[0029] refer to Figure 2 , Figure 2 Description of some embodiments according to this disclosure Figure 1 The semiconductor package 10 is shown in a top view 10T. In some embodiments, when the semiconductor die 100 has a quadrilateral layout when viewed from a top view, the replacement structure 107 is configured as an adjacent element or ring surrounding the four sides of the semiconductor die 100, such that when the die is sawn from each of the orthogonal slits surrounding the quadrilateral semiconductor die 100, the saw blade will interact with the replacement structure 107, which has a modulus greater than that of the package body 105.

[0030] refer to Figure 3 , Figure 3 This illustration shows a cross-sectional view of a semiconductor package 30 according to some embodiments of the present disclosure. The semiconductor package 30 and... Figure 1The semiconductor package 30 is generally similar to the semiconductor package 10, except that it further provides a substrate 300 for electrical connection to a conductive wiring layer 103 or a fan-out RDL. In some embodiments, the conductive wiring layer 103 is connected to the upper surface of the substrate 300, such as a printed circuit board, via solder bumps 301. In some embodiments, the conductive wiring layer 103 or the fan-out RDL has a thickness of about 30 μm. In some embodiments, the semiconductor package 30 is a fan-out chip-on-substrate (FOCOS) package.

[0031] refer to Figure 4 , Figure 4 This illustration shows a cross-sectional view of a semiconductor package 40 according to some embodiments of the present disclosure. The semiconductor package 40 and... Figure 1 The semiconductor package 10 is substantially the same as that of the package 105, except that the replacement structure 107 has a height H1 that is substantially the same as the height H3 of the package 105. In some embodiments, the height H3 of the package 105 is approximately 100 μm. Furthermore, the distance D2 between the side surface 100C of the semiconductor die 100 and the side surface of the replacement structure 107 is greater than... Figure 1 The distance D1 is described earlier. The volume (i.e., height and width) of the replacement structure 107 is determined by considering the modulus of the replacement structure 107, the modulus of the package body 105, the modulus of the conductive wiring layer 103, and the corresponding volume suitable for preventing package warping after the package thinning operation. Once the foregoing criteria are met, the height and width of the replacement structure 107 can be modified accordingly. In some embodiments, the distance D2 is in the range of about 3 μm to about 10 μm. Even though the height H1 appears substantially the same as the height H3, an interface INT at least partially filled by the package body 105 can be observed between the end of the replacement structure 107 near the conductive wiring layer 103 and the upper surface of the conductive wiring layer 103 that houses this end of the replacement structure 107. This is because the replacement structure 107 is integrated into the semiconductor package 40 through a molding operation that transfers the replacement structure 107 from another carrier to the space between adjacent semiconductor dies 100.

[0032] Figure 5 This illustration shows a cross-sectional view of a semiconductor package 50 according to some embodiments of the present disclosure. The semiconductor package 50 and... Figure 1The semiconductor package 10 is generally similar to the semiconductor die 100, except that the replacement structure 107 has a wider end 107W near the first surface 100A of the semiconductor die 100 and a relatively narrower end 107N near the second surface 100B of the semiconductor die 100. In some comparative embodiments, the mold is designed to create a groove in the package body surrounding the semiconductor die. After demolding, solid paraffin can be detected at the sidewalls and bottom of the groove as it facilitates the demolding process. Furthermore, in comparative embodiments, the groove may have a wider top and a narrower bottom to facilitate easier removal of the mold from the package body. In the embodiments of the present invention, the replacement structure 107, which is partially encapsulated by the package body 105, has a wider end 107W at the top and a narrower end 107N at the bottom, and no paraffin is detected at the boundary between the replacement structure 107 and the package body 105. Referring to the present disclosure... Figures 10A to 10L The replacement structure 107 is integrated into the semiconductor package 50 by a molding operation that transfers the replacement structure 107 from another carrier to the space between adjacent semiconductor dies 100. This molding operation is a different approach compared to the aforementioned comparative embodiment, which uses a mold with a specific shape to create a groove in the package and then fills the groove with a non-homogeneous material.

[0033] Figure 6 This illustration shows a cross-sectional view of a semiconductor package 60 according to some embodiments of the present disclosure. The semiconductor package 60 and... Figure 4 The semiconductor package 40 is largely the same, the difference being that the semiconductor package 60 is manufactured through chip-first operations. For example, in... Figures 10A to 10L As described, the semiconductor package 10 is manufactured through a last-in-the-chip operation in which a conductive wiring layer 103 is formed prior to processing the semiconductor die 100. In a first-in-the-chip operation, the semiconductor die 100 is placed on a carrier, and then the conductive wiring layer 103 is constructed over the carrier and the placed semiconductor die 100. Figure 6 As shown, the semiconductor die 100, replacement structure 107, and package 105 are disposed on a carrier that will be subsequently removed. Figure 6 (Not shown in the image). A planarization operation can be performed to obtain a coplanar surface between the conductive element 101, the replacement structure 107, and the package 105 of the semiconductor die 100. A conductive wiring layer 103 or RDL is constructed above the coplanar surface. The interface INT between the end of the replacement structure 107 near the conductive wiring layer 103 and the surface of the conductive wiring layer 103 that houses this end of the replacement structure 107 is not filled by the package 105 because the conductive wiring layer 103 is constructed on the coplanar surface of the conductive element 101, the replacement structure 107, and the package 105.

[0034] Figure 7This illustration shows a cross-sectional view of a semiconductor package 70 according to some embodiments of the present disclosure. The semiconductor package 70 and... Figure 1 The semiconductor package 10 is largely the same as the semiconductor package 100, except that the semiconductor package 70 is manufactured using a chip-first, active side-up operation, and the replacement structure 107 is shorter than the height of the semiconductor die 100. The chip-first operation is described in... Figure 6 And can be used as a reference Figure 6 .like Figure 7 As shown, the second surface 100B of the semiconductor die 100, the replacement structure 107, and the package 105 are disposed on a carrier that will be subsequently removed. Figure 7 (Not shown in the image). A planarization operation can be performed to obtain a coplanar surface between the conductive elements 101, replacement structure 107, and package 105 of the semiconductor die 100. A conductive wiring layer 103 or RDL is constructed above the coplanar surface. The interface between the end of the replacement structure 107 and the package 105 is positioned away from the first surface 100A or active surface of the semiconductor die 100 to prevent crack propagation toward the active surface during die sawing operations, as previously described. Figure 1 As described in the text.

[0035] Figure 8 This illustration shows a cross-sectional view of a semiconductor package 80 according to some embodiments of the present disclosure. The semiconductor package 80 and... Figure 1 The semiconductor package 10 is largely the same as the semiconductor package 100, except that the semiconductor package 80 is manufactured using a chip-first, active side-down operation, and the replacement structure 107 is shorter than the height of the semiconductor die 100. Chip-first operation is described in... Figure 6 And can be used as a reference Figure 6 .like Figure 8 As shown, the conductive element 101, replacement structure 107, and package 105 on the first surface 100A of the semiconductor die 100 are disposed on a carrier that will be subsequently removed. Figure 8 (Not shown in the image). Detachment of the carrier exposes the coplanar surface between the conductive element 101, the replacement structure 107, and the package 105 of the semiconductor die 100. A conductive wiring layer 103, or RDL, is constructed above the coplanar surface. The interface INT between the end of the replacement structure 107 approaching the conductive wiring layer 103 and the surface of the conductive wiring layer 103 that houses this end of the replacement structure 107 is not filled by the package 105 because the conductive wiring layer 103 is constructed on the coplanar surface of the conductive element 101, the replacement structure 107, and the package 105.

[0036] Figures 9A to 9C This illustration shows cross-sectional views of intermediate products during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure. Figure 9AIn this context, a first virtual carrier 900 having a first surface 900A is provided. Figure 9B In this process, release film 901 is placed on the first surface 900A. Figure 9C In this configuration, the replacement structure 107 is positioned above the first surface 900A and in contact with the release film. From a cross-sectional view, the replacement structure 107 may have a column shape with a uniform width. Each of the replacement structures 107 may be equally spaced from adjacent replacement structures 107. However, from a top view, the replacement structure 107 may be an adjacent element. As per [reference to...] Figure 9C As illustrated in the top view of the image, the replacement structure 107 has a grid layout, each of which is configured to surround the semiconductor die to be placed therein.

[0037] refer to Figures 10A to 10L , Figures 10A to 10L This illustration shows cross-sectional views of intermediate products during various manufacturing operations of a semiconductor package according to some embodiments of the present disclosure. Figure 10A In this context, a second carrier 1000 having a first surface 1000A is provided. Figure 10B In this process, release film 1001 is placed on the first surface 1000A. Figure 10C In this configuration, a conductive wiring layer 103 or RDL is constructed above the first surface 1000A. As previously discussed, Figures 10A to 10L This describes the final manufacturing sequence of the chip, thus forming the conductive wiring layer 103 before processing the semiconductor die. Figure 10D In this configuration, a plurality of semiconductor dies 100 are positioned above a second carrier 1000 and electrically connected to a conductive wiring layer 103 via, for example, a flip-chip bonding configuration. Subsequently, an underfill material is applied to surround the conductive contacts of the semiconductor dies 100 engaged with the conductive wiring layer 103.

[0038] exist Figure 10E In this process, an encapsulation body 105 is applied above the first carrier 900 on which the replacement structure 107 is disposed. The encapsulation body 105 may be a molding material that fills the space between adjacent replacement structures 107. Figure 10F In this assembly, the first surface 900A of the first carrier 900 engages with the first surface 1000A of the second carrier 1000, bonded by a package 105 previously disposed on the first surface 900A. During the bonding operation, replacement structures 107 are aligned with regions that separate adjacent semiconductor dies 100, such that after the bonding operation, each of the replacement structures 107 separates two adjacent semiconductor dies 100. After the bonding operation, the package 105 fills the space between each of the replacement structures 107, the adjacent semiconductor dies 100, the conductive wiring layer 103, and the first surface 900A of the first carrier 900.

[0039] exist Figure 10H In this process, the first carrier 900 is detached from the encapsulation body 105 and the replacement structure 107 by removing the release film 901. Figure 10I In this process, the second carrier 1000 is detached from the conductive wiring layer 103 by removing the release film 1001. Figure 10J In this process, a single-cut operation is performed to separate adjacent semiconductor dies 100 by aligning the saw blade 1002 with saw marks on the conductive wiring layer 103. The saw marks ( Figure 10J (Not shown) Formed on the surface of the conductive wiring layer 103 and aligned with each of the replacement structures 107. In some embodiments, the single-cut operation is a half-cut operation in which the saw blade 102 passes through the conductive wiring layer 103, the package 105, and along the longitudinal direction of the replacement structure 107. A closed end is formed after the single-cut operation because the saw blade 1002 stops in the replacement structure 107. In other words, after the single-cut operation, a portion of the second surface 100B of the replacement structure 107 adjacent to the semiconductor die 100 is joined or not separated.

[0040] exist Figure 10K In, such as Figure 10J The intermediate semiconductor package described herein is taped onto the polishing tape 1003 attached to the conductive wiring layer 103. For example... Figure 10L The back-side grinding operation is performed as described. The package 105 adjacent to the second surface 100B of the semiconductor die 100 is ground until the second surface 100B is exposed. In some embodiments, the semiconductor die 100 is further removed from the second surface 100B to expose a new surface suitable for die thinning targets. Furthermore, the grinding operation removes the remaining interconnected replacement structures 107 that hold adjacent semiconductor dies 100 together in the intermediate semiconductor package. After the back-side grinding operation, the semiconductor die 100 is completely slit and can be picked up from the grinding tape 1003 for further processing or integration.

[0041] As used herein and unless otherwise defined, the terms “substantially,” “essentially,” “roughly,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may refer to two surfaces located within a few micrometers along the same plane, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane.

[0042] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0043] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between artistic representations in this disclosure and actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limiting unless specifically indicated herein.

Claims

1. A method for manufacturing a semiconductor package, comprising: Provide a first carrier having a first surface; The replacement structure is placed above the first surface; A conductive wiring layer is attached above the second surface of the second carrier; Multiple semiconductor dies are disposed above the conductive wiring layer, and the multiple semiconductor dies are separated from the second carrier by the conductive wiring layer; as well as The replacement structure on the first carrier is engaged with the second carrier carrying the plurality of semiconductor dies, such that the first surface of the first carrier faces the second surface of the second carrier, and the replacement structure is aligned with the region that separates adjacent semiconductor dies. Before engaging the first carrier with the second carrier, the molding material is placed on the first surface of the first carrier; as well as After engaging the first carrier with the second carrier, the plurality of semiconductor dies and the conductive wiring layer are individually cut by a half-cutting operation.

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