Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a substrate, an electronic component disposed on the substrate, a support structure disposed on the substrate and surrounding the electronic component, and a heat dissipation structure disposed on the support structure. A length of the support structure and a length of the heat dissipation structure are greater than a length of the substrate.

Description

Technical Field

[0001] This disclosure relates to semiconductor device packaging and methods of manufacturing thereof. Background Technology

[0002] Semiconductor device packages can contain several semiconductor devices stacked one on top of the other. However, as the functionality of semiconductor devices improves, more heat is generated. The entire device package needs to have a large heat dissipation area to achieve more efficient heat dissipation. While increasing the size of the device package can improve heat dissipation, this inevitably increases manufacturing costs and sacrifices PCB area utilization. Summary of the Invention

[0003] According to some exemplary embodiments of this disclosure, a semiconductor device package includes a substrate; an electronic component disposed on the substrate; a support structure disposed on the substrate and surrounding the electronic component; and a heat dissipation structure disposed on the support structure. The length of the support structure and the length of the heat dissipation structure are greater than the length of the substrate.

[0004] According to some exemplary embodiments of this disclosure, a semiconductor device package includes a substrate; a first electronic component disposed on the substrate; a support structure surrounding the first electronic component; and a heat dissipation structure covering the first electronic component and the support structure. The support structure has a first portion above the substrate and a second portion extending laterally beyond the sides of the substrate. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that different features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of various components may be arbitrarily increased or decreased.

[0006] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0007] Figure 1F This is a top view of a support structure for a semiconductor device package according to some embodiments of the present disclosure.

[0008] Figure 2A This is a cross-sectional view of another semiconductor device package according to some embodiments of the present disclosure.

[0009] Figure 2B This is a top view of a support structure for a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 3A and Figure 3B This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 3C This is a top view of a support structure for a semiconductor device package according to some embodiments of the present disclosure.

[0012] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In this disclosure, references in the following description to a first feature being formed above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides several applicable concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0015] Figure 1A This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a carrier 10, a substrate 11, a support structure 12, electronic components 14a and 14b, and a heat dissipation structure 16.

[0016] The carrier 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The carrier 10 has interconnect structures and / or grounding elements.

[0017] Substrate 11 is formed or disposed on carrier 10. Substrate 11 can be connected to carrier 10 via electrical contact 15b. Substrate 11 can be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. Substrate 11 may contain interconnect structures, such as redistribution layers (RDLs) or grounding elements.

[0018] Each of electronic components 14a and 14b includes multiple semiconductor devices, such as, but not limited to, transistors, capacitors, and resistors interconnected via die interconnect structures to form functional circuits and thus integrated circuits. As those skilled in the art will understand, the device side of the semiconductor die includes active portions that contain integrated circuits and interconnects. According to several different embodiments, electronic components 14a and 14b can be any suitable integrated circuit device, including, but not limited to, microprocessors (e.g., single-core or multi-core), memory devices, chipsets, graphics devices, high-bandwidth memory (HBM), or application-specific integrated circuits (ASICs).

[0019] Electronic component 14a is formed or disposed on substrate 11. A plurality of electrical contacts 15a are disposed on the active surface of electronic component 14a to provide electrical connection between electronic component 14a and substrate 11. Electronic component 14b is formed or disposed on carrier 10. Electronic component 14b is disposed adjacent to substrate 11. Some of electronic components 14b may be disposed below support structure 12. For example, some of electronic components 14b are disposed within protrusions of support structure 12 on carrier 10. For example, viewed from a top view of semiconductor device package 1, some of electronic components 14b are completely covered by support structure 12.

[0020] A support structure 12 is disposed on a substrate 11. The support structure 12 can be connected to the substrate 11 via an adhesion layer 13a. In some embodiments, the support structure 12 extends laterally beyond the sides of the substrate 11. In some embodiments, the support structure 12 extends laterally beyond some of the sides of the electronic components 14b. In some embodiments, a portion of the support structure 12 extends within and contacts the substrate 11. A portion of the support structure 12 is surrounded by or embedded within the substrate 11. A portion of the support structure 12 is spaced apart from the substrate 11 by the adhesion layer 13a.

[0021] The support structure 12 may be or contain aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or other suitable materials (e.g., metallic, alloy, or non-metallic conductive materials). The support structure 12 may also contain epoxy resin, polyimide, phenolic compounds, silicone dispersed therein, or combinations thereof.

[0022] An adhesive layer 13a is formed between the substrate 11 and the support structure 12. The support structure 12 can be connected to the substrate using the adhesive layer 13a. In some embodiments, the adhesive layer 13a may comprise a gel-type or film-type adhesive layer. The adhesive layer 13a may comprise a thermosetting resin. The adhesive layer 13a may comprise a thermoplastic resin. The adhesive layer 13a may comprise one or more of the following: resin, polyester resin, polyether resin, epoxy resin, and / or a polyolefin composition. In some embodiments, the adhesive layer 13a may comprise a thermal interface material (TIM) or a thermal paste layer.

[0023] A heat dissipation structure 16 is formed or disposed on the support structure 12 and the electronic component 14a. The heat dissipation structure 16 can be supported or held by the support structure 12. The heat dissipation structure 16 is thermally connected to the electronic component 14a (e.g., thermally connected to the back surface of the electronic component 14a). When the electronic component 14a generates heat, heat dissipation can be achieved through the heat dissipation structure 16.

[0024] The heat dissipation structure 16 may include a heat sink, a cold plate, or other suitable cooling components, a cover, a heat pipe, or another intermediate structure in contact with the electronic component 14a. It is envisioned that the heat dissipation structure 16 is constructed using a thermally conductive material comprising copper and / or aluminum. The heat dissipation structure 16 can dissipate heat generated by circuitry present, for example, on the electronic component 14a.

[0025] An adhesive layer 13c is disposed between the heat dissipation structure 16 and the support structure 12. The heat dissipation structure 16 can be fixed or connected to the support structure 12 using the adhesive layer 13c. Therefore, an efficient heat transfer path can be provided from the electronic component 14a to the heat dissipation structure 16 via the adhesive layer 13c.

[0026] In some embodiments, the adhesive layer 13c may comprise a gel-type or film-type adhesive layer, a thermosetting resin, or a thermoplastic resin. The adhesive layer 13c may also comprise one or more of the following: resins, polyester resins, polyether resins, epoxy resins, and / or polyolefin compositions. In some embodiments, the adhesive layer 13c may comprise a thermal interface material (TIM) or a thermal paste layer.

[0027] An adhesive layer 13b is formed between the heat dissipation structure 16 and the support structure 12. The heat dissipation structure 16 can be connected to the support structure 12 using the adhesive layer 13b. In some embodiments, the adhesive layer 13b may comprise one or more of the following: resin, polyester resin, polyether resin, epoxy resin, and / or a polyolefin composition. In some embodiments, the adhesive layer 13b may comprise a thermal interface material (TIM) or a thermal paste layer.

[0028] In some embodiments, the material of adhesive layer 13b is the same as the material of adhesive layer 13a. The material of adhesive layer 13c is the same as the materials of adhesive layers 13b and 13a. In other embodiments, the material of adhesive layer 13c is different from the materials of adhesive layers 13b and 13a.

[0029] Figure 1B This is a cross-sectional view of a portion of a semiconductor device package 1 according to some embodiments of the present disclosure. Figure 1B In this configuration, carrier 10 and electronic component 14b may be omitted. Support structure 12 includes pin portion 12p1. Pin portion 12p1 may have a rectangular or similar rectangular outline, a circular or similar circular outline, a pyramidal or similar pyramidal outline, or a conical or similar conical outline.

[0030] The lead portion 12p1 extends from the bottom surface S3 of the support structure 12 into the substrate 11. The lead portion 12p1 is surrounded by an adhesion layer 13a and covered by the substrate 11. The lead portion 12p1 is in contact with the substrate 11. Because the lead portion 12p1 extends into or is snapped into the substrate 11, the retention and connection between the substrate 11 and the support structure 12 are improved.

[0031] In some embodiments, the length L2 of the support structure 12 is greater than the length L1 of the substrate 11. In some embodiments, the length L3 of the heat dissipation structure 16 is greater than the length L1 of the substrate. The length L2 of the support structure 12 and the length L3 of the heat dissipation structure 16 are substantially the same. Therefore, thermal resistance can be reduced to achieve efficient heat dissipation by arranging a long heat dissipation structure 16 with a large heat transfer area.

[0032] In some embodiments, the length L3 of the heat dissipation structure 16 is less than three times the length L1 of the substrate 11. The length L2 of the support structure 12 is less than three times the length L1 of the substrate 11. These size constraints prevent the heat dissipation structure 16 from falling or detaching.

[0033] Figure 1C This is a cross-sectional view of a semiconductor device package 1A according to some embodiments of the present disclosure. Semiconductor device package 1A is similar to semiconductor device package 1, and the differences therebetween are described below.

[0034] In some embodiments, the support structure 12A extends laterally beyond the side surface of the substrate 11. In some embodiments, the support structure 12A extends laterally beyond some of the side surfaces of the electronic components 14b. In some embodiments, a portion of the support structure 12 extends within and contacts the substrate 11. The support structure 12A further includes a lead portion 12p2. The lead portion 12p2 may have a rectangular or similar rectangular outline, a circular or similar circular outline, a pyramidal or similar pyramidal outline, or a conical or similar conical outline.

[0035] The pin portion 12p2 extends from the top surface S4 of the support structure 12 into the heat dissipation structure 16. The pin portion 12p2 is surrounded by the adhesive layer 13b and covered by the heat dissipation structure 16. The pin portion 12p2 extends into or is snapped into the heat dissipation structure 16. Therefore, the retention and connection between the heat dissipation structure 16 and the support structure 12A can be improved by arranging the pin portion 12p2.

[0036] The width W4 of the lead portion 12p2 is less than the thickness W2 of the heat dissipation structure 16. The width W4 of the lead portion 12p2 is greater than half the thickness W2 of the heat dissipation structure 16. For example, the width W4 of the lead portion 12p2 is approximately 50% to 90% of the thickness W2 of the heat dissipation structure 16. The width W3 of the lead portion 12p1 is less than the thickness W1 of the substrate 11. The width W3 of the lead portion 12p1 is greater than half the thickness W1 of the substrate 11. For example, the width W3 of the lead portion 12p1 is approximately 50% to 90% of the thickness W1 of the substrate 11.

[0037] Figure 1D This is another cross-sectional view of a semiconductor device package 1B according to some embodiments of the present disclosure. Semiconductor device package 1B is similar to semiconductor device package 1, and the differences therebetween are described below.

[0038] The support structure 12B includes a lead portion 12p3. The lead portion 12p3 is disposed within a protrusion of the support structure 12B. For example, viewed from a top view of the semiconductor device package 1B, the lead portion 12p3 can be completely covered by the support structure 12B. The lead portion 12p3 may have a rectangular or similar rectangular outline, a circular or similar circular outline, a pyramidal or similar pyramidal outline, or a conical or similar conical outline.

[0039] The lead portion 12p3 extends from the bottom surface S3 of the support structure 12B. The lead portion 12p3 is adjacent to or in direct contact with the side surface S8 of the substrate 11. The width W5 of the lead portion 12p3 is less than the thickness W1 of the substrate 11. The width W5 of the lead portion 12p3 is greater than half the thickness W1 of the substrate 11. For example, the width W5 of the lead portion 12p3 is approximately 50% to 90% of the thickness W1 of the substrate 11. The lead portion 12p3 supports the substrate 11 to improve the continuity and connection between the substrate 11 and the support structure 12B.

[0040] Figure 1E This is another cross-sectional view of a semiconductor device package 1C according to some embodiments of the present disclosure. Semiconductor device package 1B is similar to semiconductor device package 1, and the differences therebetween are described below. Electronic component 14a is spaced apart from support structure 12C. An air gap is formed between electronic component 14a and support structure 12C to achieve heat dissipation.

[0041] An adhesion layer 13d is formed or disposed on the substrate 11. The adhesion layer 13d is formed between the electronic component 14a and the support structure 12C. The adhesion layer 13d can be in direct contact with the adhesion layer 13a and the electrical contact 15a. A heat transfer path from the electronic component 14a through the electrical contact 15a to the adhesion layer 13d can be provided accordingly.

[0042] Figure 1F This is a top view of a support structure 12 of a semiconductor device package 1 according to some embodiments of the present disclosure. The support structure 12 includes two portions 121 and 122. Portion 121 may have a rectangular or similar rectangular outline or a square ring. Electronic component 14a may be located in a central area surrounded by portion 121.

[0043] A pin portion 12p1 is formed within portion 121. The pin portion 12p1 is positioned in a rectangular or similar rectangular outline. The pin portion 12p1 surrounds or encloses the electronic component 14a. Portion 122 includes a plurality of extension portions 131. The extension portions 131 extend from the four corners of portion 121. The thickness of portion 121 is substantially the same as the thickness of portion 122. In other embodiments, the thickness of portion 121 is greater than the thickness of portion 122.

[0044] Figure 2A This is a cross-sectional view of another semiconductor device package 2 according to some embodiments of the present disclosure. Semiconductor device package 2 is similar to semiconductor device package 1, and the differences therebetween are described below.

[0045] The support structure 12D comprises two parts, 121D and 122D. Part 121D includes a pin portion 12p1. The thickness W6 of part 121D may differ from the thickness W7 of part 122D. The thickness W7 of part 122D may be less than the thickness W6 of part 121D. The length of the support structure 12D is greater than the length of the substrate 11. Therefore, a large space can be provided below part 122D to accommodate electronic components 14b on the carrier 10. Furthermore, the weight of the support structure 12D can be reduced.

[0046] The length L3 of the heat dissipation structure 16 is greater than the length L1 of the substrate 11 but less than three times the length L1 of the substrate 11. The length L2 of the support structure 12D is less than three times the length L1 of the substrate 11. The thickness W2 of the heat dissipation structure 16 can be arranged in the range of 0.5 mm to 3 mm. A distance D exists to illustrate the difference between the thickness W6 of portion 121D and the thickness W7 of portion 122D. The length L3 of the heat dissipation structure 16 can be less than 100 times the difference between the distance D and the thickness W2 of the heat dissipation structure 16.

[0047] Figure 2BThis is a top view of a support structure 12D of a semiconductor device package according to some embodiments of the present disclosure. The support structure 12D includes two portions 121D and 122D. Portion 121D is surrounded or enclosed by portion 122D. Portion 121D may have a rectangular or similar rectangular outline or a square ring. Portion 122D may have a rectangular or similar rectangular outline or a square ring.

[0048] Electronic component 14a may be located in the central area surrounded by portion 121D. Electronic component 14b may be located below portion 122D. Pin portion 12p1 is formed within portion 121D. Pin portion 12p1 is arranged in a rectangular or similar rectangular outline. Pin portion 12p1 surrounds or encircles electronic component 14a. The thickness of portion 121D is greater than the thickness of portion 122D.

[0049] Figure 3A This is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. Semiconductor device package 3 is similar to semiconductor device package 2, and the differences therebetween are described below. Part 121E is connected to substrate 11 via an adhesive layer 13a. Part 122E includes a lead portion 12p1. Without forming an adhesive layer, part 122E is connected to substrate 11 via the lead portion 12p1. Parts 121E and 122E are spaced apart. An air gap may be formed between parts 121E and 122E to achieve heat dissipation.

[0050] The thickness W6 of portion 121E differs from the thickness W7 of portion 122E. The thickness W7 of portion 122E can be less than the thickness W6 of portion 121E. Therefore, a large space can be provided below portion 122E to accommodate the electronic components 14b on the carrier 10. In addition, the weight of the support structure 12E can be reduced.

[0051] Figure 3B This is another cross-sectional view of a semiconductor device package 3A according to some embodiments of the present disclosure. The semiconductor device package 3A is similar to semiconductor device package 3, and the differences therebetween are described below.

[0052] The heat dissipation structure 16 further includes a vapor chamber 16C. It is envisioned that the heat dissipation structure 16 is constructed using a thermally conductive material, which may include, for example, a vapor chamber or heat pipe within the substrate. Therefore, the heat dissipation structure 16 can dissipate or eliminate the heat generated by the electronic components 14a and 14b.

[0053] Figure 3C This is a top view of a support structure 12E of a semiconductor device package 1 according to some embodiments of the present disclosure. The support structure 12E includes two portions 121E and 122E. Portion 121E may have a rectangular or similar rectangular outline or a square ring. Electronic component 14a may be located in a central area surrounded by portion 121E.

[0054] The lead portion 12p1 is formed within portion 122E, not within portion 121E. The lead portion 12p1 may have a strip-shaped or similar strip-shaped profile. The lead portion 12p1 surrounds or encircles the electronic component 14a. Portion 122E includes several auxiliary portions 132. The auxiliary portions 132 extend from the four sides of portion 121E. Portions 121E are spaced apart from portion 122E. The thickness of portion 121E is greater than the thickness of portion 122E.

[0055] The relationship between one element or feature and another element or feature illustrated in the figures may be described herein using spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” for ease of description. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative terms used herein may be interpreted similarly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0056] As used herein, the terms “approximately,” “substantially,” “a great deal,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may refer to examples of events or situations that occur precisely or very approximately. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. In this document, a range may be expressed as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” may mean that two surfaces are located along the same plane within a few micrometers (μm), for example, within 10 μm, 5 μm, 1 μm, or 0.5 μm. When referring to “substantially” identical numerical values ​​or characteristics, the term may refer to values ​​within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0057] The foregoing outlines several embodiments and detailed features of this disclosure. The embodiments described in this disclosure can be readily used as the basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and variations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device package comprising: Substrate; Electronic components, which are disposed on the substrate; A support structure disposed on the substrate and surrounding the electronic component, wherein the support structure includes a first pin portion extending from the bottom surface of the support structure into the substrate and embedded within the substrate; and A heat dissipation structure is disposed on the support structure, wherein the length of the support structure and the length of the heat dissipation structure are greater than the length of the substrate.

2. The semiconductor device package of claim 1, wherein the length of the heat dissipation structure is less than three times the length of the substrate.

3. The semiconductor device package of claim 1, wherein the first pin portion extending into the substrate is in contact with and covered by the substrate.

4. The semiconductor device package of claim 1, wherein the support structure further includes a second pin portion extending from the top surface of the support structure into the heat dissipation structure, the second pin portion being in contact with and covered by the heat dissipation structure.

5. The semiconductor device package of claim 1, wherein the depth of the first pin portion is greater than half the thickness of the substrate, the support structure is connected to the substrate via an adhesive layer, and the pin portion is surrounded by the adhesive layer.

6. The semiconductor device package of claim 1, wherein the heat dissipation structure is connected to the top surface of the support structure via a first adhesive layer; the substrate is connected to the bottom surface of the support structure via a second adhesive layer, and the material of the first adhesive layer is the same as the material of the second adhesive layer.

7. The semiconductor device package of claim 6, wherein the heat dissipation structure is connected to the back surface of the electronic component via a third adhesive layer, and the material of the third adhesive layer is the same as the material of the first adhesive layer and the second adhesive layer.

8. The semiconductor device package of claim 6, wherein the heat dissipation structure is connected to the back surface of the electronic component via a third adhesive layer, and the material of the third adhesive layer is different from the materials of the first adhesive layer and the second adhesive layer.

9. The semiconductor device package of claim 1, wherein the bottom surface of the support structure disposed on the substrate faces the substrate, the support structure further including a third pin portion extending from the bottom surface of the support structure and directly contacting a side surface of the substrate, the third pin portion being completely covered by the support structure when viewed from a top view of the semiconductor device package.

10. The semiconductor device package of claim 1, wherein the support structure has a rectangular outline surrounding the electronic component.

11. The semiconductor device package of claim 10, wherein the support structure has a first portion and a second portion surrounding the first portion, the first portion and the second portion having rectangular outlines, and the thickness of the second portion being less than the thickness of the first portion.

12. The semiconductor device package of claim 10, wherein the support structure has a first portion and a second portion surrounding the first portion; the first portion has a rectangular outline, and the second portion includes four extensions extending from four corners of the first portion.

13. The semiconductor device package of claim 10, wherein the support structure has a first portion and a second portion spaced apart from the first portion; the first portion has a rectangular outline, and the second portion includes four auxiliary portions spaced apart from each other and extending from four sides of the first portion.

14. The semiconductor device package of claim 1, wherein the support structure is connected to the heat dissipation structure via an adhesive layer, the support structure including a second pin portion extending from the top surface of the support structure into the heat dissipation structure, and the second pin portion being surrounded by the adhesive layer.

15. A semiconductor device package comprising: Substrate; A first electronic component is disposed on the substrate; A support structure surrounding the first electronic component, the support structure having a first portion above the substrate and a second portion extending laterally beyond the side of the substrate, wherein the support structure includes a first pin portion extending from the bottom surface of the first portion into the substrate and embedded within the substrate; and A heat dissipation structure that covers the first electronic component and the supporting structure.

16. The semiconductor device package of claim 15, wherein the length of the support structure and the length of the heat dissipation structure are greater than the length of the substrate.

17. The semiconductor device package of claim 15, wherein the thickness of the first portion of the support structure is greater than the thickness of the second portion of the support structure, and the surfaces of the first portion and the second portion facing the heat dissipation structure are connected to the heat dissipation structure via an adhesive layer.

18. The semiconductor device package of claim 15, further comprising a second electronic component disposed adjacent to the substrate and below the second portion of the support structure.

19. The semiconductor device package of claim 15, wherein the first portion of the support structure has a rectangular outline, and the second portion of the support structure includes four extensions extending from the four corners of the first portion.

20. The semiconductor device package of claim 15, wherein the first portion of the support structure is spaced apart from the second portion of the support structure.

21. The semiconductor device package of claim 15, further comprising a carrier, the substrate disposed on the carrier, wherein the distance between the bottom surface of the second portion of the support structure and the carrier is greater than the distance between the bottom surface of the first portion of the support structure and the carrier.

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