Substrate structure and method of manufacturing the same

Abstract

A substrate structure and a method of manufacturing the same are disclosed. The substrate structure includes a substrate, a first redistribution structure, a first adhesive layer, and a first connection assembly. The substrate includes a first conductor on a first surface thereof. The first redistribution structure is disposed over the substrate. The first adhesive layer is disposed between the substrate and the first redistribution structure. The first connection assembly is electrically connected with the first conductor, penetrates through the first adhesive layer into the first redistribution structure, and electrically connects the substrate to the first redistribution structure.

Description

Technical Field

[0001] This disclosure generally relates to a substrate structure, and more particularly to a substrate structure comprising a substrate and a redistribution structure, and a method for manufacturing the substrate structure. Background Technology

[0002] Semiconductor device packages may include a substrate and a redistribution structure attached to the substrate. The redistribution structure includes a dielectric layer and one or more conductive layers within the dielectric layer, and may be used to provide fan-out purposes. The substrate includes conductive pads for electrical connection to the conductive layers in the redistribution layer. The conductive pads or traces associated with the substrate are larger than the conductive pads or traces associated with the redistribution structure in terms of line width and line spacing (L / S). Summary of the Invention

[0003] Embodiments of this disclosure provide a substrate structure comprising: a substrate having a first conductor on a first surface of the substrate; a first re-woven structure disposed on the substrate; a first adhesive layer between the substrate and the first re-woven structure; and a first connection assembly electrically connected to the first conductor, penetrating through the first adhesive layer into the first re-woven structure, and electrically connecting the substrate to the first re-woven structure.

[0004] Some embodiments of this disclosure provide a method for manufacturing a substrate structure. The method includes: providing a substrate having a first surface; forming a first conductor on the first surface; forming a first connection assembly on the first conductor, wherein the first connection assembly includes a tip portion; providing a first re-woven structure; and combining the substrate and the first re-woven structure by pushing the first connection assembly at the tip portion into the first re-woven structure. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, aspects of some embodiments of this disclosure are best understood in light of the following detailed description. It should be noted that various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 This is a cross-sectional view of a substrate structure according to an embodiment of the present disclosure.

[0007] Figure 2A and 2B This is a cross-sectional view of a substrate structure according to some embodiments of the present disclosure.

[0008] Figure 3 This is a cross-sectional view of a substrate structure according to another embodiment of the present disclosure.

[0009] Figure 4This is a cross-sectional view of a substrate structure according to yet another embodiment of the present disclosure.

[0010] Figure 5A , 5B 5C is a cross-sectional view of a substrate structure according to some embodiments of the present disclosure.

[0011] Figure 6A and 6B This is a cross-sectional view of a substrate structure according to some embodiments of the present disclosure.

[0012] Figure 7A and 7B This is a cross-sectional view of a substrate structure according to some embodiments of the present disclosure.

[0013] Figure 8A and 8B This is a cross-sectional view of a substrate structure according to some embodiments of the present disclosure.

[0014] Figures 9A to 9I The manufacturing process according to embodiments of the present disclosure is shown as follows: Figure 1 The method for the substrate shown is one or more stages.

[0015] Figure 9J The formation of an embodiment according to this disclosure is shown as follows Figure 1 The method for connecting components shown may be one or more stages.

[0016] Figures 10A to 10I This illustrates one or more stages of a method for forming a connecting component according to another embodiment of the present disclosure.

[0017] Figures 11A to 11K The manufacturing process according to embodiments of the present disclosure is shown as follows: Figure 1 The method of redistributing the structure shown has one or more stages.

[0018] Figures 12A to 12C The manufacturing process according to embodiments of the present disclosure is shown as follows: Figure 1 One or more stages of the method for the substrate structure shown.

[0019] Figure 13 A schematic perspective view of a carrier according to an embodiment of the present disclosure is shown.

[0020] Figure 14 A schematic perspective view of a carrier according to another embodiment of the present disclosure is shown. Detailed Implementation

[0021] Common reference numerals are used throughout the accompanying drawings and specific embodiments to denote the same or similar components. Embodiments of this disclosure will be readily understood from the specific details described in conjunction with the accompanying drawings.

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0023] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips are being integrated with an increasing number of electronic components to achieve better electrical performance and more functions. The trend towards miniaturization and multifunctionality in electronic devices, along with the reduction in design rules and the increase in the number of layers, characterizes the progress of semiconductor devices. Therefore, semiconductor chips have more input / output (I / O) connections. Rearranged structures for fan-out purposes have thus become popular. Rearranged structures can be formed using more advanced manufacturing processes compared to substrates. As a result, rearranged structures have relatively fine linewidths and spacings, while substrates have relatively coarse linewidths and spacings. Furthermore, the surface uniformity (U%) of the rearranged structure can differ significantly from that of the substrate. Specifically, the rearranged structure has a relatively small thickness variation between electrodes and a relatively low U% in the dielectric layer. In contrast, the substrate has a relatively large thickness variation between electrodes and a relatively high U% in the dielectric layer. Therefore, when a rearranged structure is formed on a substrate, there is a high probability of disconnection between the electrodes of the rearranged structure and the substrate. Therefore, it may be necessary to provide a substrate structure to address the disconnection problem.

[0024] Figure 1 This is a cross-sectional view of a substrate structure 100 according to an embodiment of the present disclosure.

[0025] See Figure 1 The substrate structure 100 includes a substrate 101, a redistribution structure 201, an adhesive layer 80 between the substrate 101 and the redistribution structure 201, and one or more connection components 30 that electrically connect the substrate 101 and the redistribution structure 201.

[0026] The substrate 101 includes a substrate plate 10 having a first surface 10a and a second surface 10b opposite to the first surface 10a, and a via 10v extending between the first surface 10a and the second surface 10b. Furthermore, the substrate 101 includes a first conductive pad 10p1 and a first conductive trace 10t1 disposed on the first surface 10a of the substrate plate 10, and a second conductive pad 10p2 and a second conductive trace 10t2 disposed on the second surface 10b of the substrate plate 10. The conductive pad or trace is referred to as a conductor in this disclosure.

[0027] The substrate 10 includes a dielectric layer and wiring structures within the dielectric layer for electrical communication between contact pads or traces on a first surface 10a and a second surface 10b. The dielectric layer in the substrate 10 may comprise an organic material selected from polyamide (PA), polyimide (PI), polybenzoxazole (PBO), FR-4, or epoxy-based materials. In other embodiments, the dielectric layer in the substrate 10 may comprise an inorganic material selected from silicon (Si), glass, ceramics, or oxides or nitrides such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). The substrate 10 may have a thickness ranging from approximately twenty (20) micrometers (μm) to approximately one hundred (100) μm.

[0028] Each of the first conductive pad 10p1 or the first conductive trace 10t1 includes a patterned first metal foil 21 and a patterned first conductive layer 281 stacked thereon. The patterned first metal foil 21 may comprise titanium (Ti), tungsten (W), or an alloy thereof. In an embodiment, the patterned first metal foil 21 has a thickness ranging from approximately 1 μm to approximately 5 μm. Furthermore, the patterned first conductive layer 281 may comprise copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the patterned first conductive layer 281 has a thickness ranging from approximately 5 μm to approximately 25 μm. The linewidth and pitch (L / S) of the first conductive pad 10p1 or the first conductive trace 10t1 are not less than approximately 7 μm and 7 μm, respectively.

[0029] Each of the second conductive pad 10p2 or the second conductive trace 10t2 includes a patterned second metal foil 22 and a patterned second conductive layer 282 stacked thereon. The patterned second metal foil 22 may comprise titanium (Ti), tungsten (W), or an alloy thereof. In an embodiment, the patterned second metal foil 22 has a thickness ranging from approximately 1 μm to approximately 5 μm. Furthermore, the patterned second conductive layer 282 may comprise copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or an alloy thereof. In an embodiment, the patterned second conductive layer 282 has a thickness ranging from approximately 5 μm to approximately 25 μm. The linewidth and spacing (L / S) of the second conductive pad 10p2 or the second conductive trace 10t2 are not less than approximately 7 μm and 7 μm, respectively.

[0030] The via 10v includes an insulating portion 27 and a via liner 15 generally surrounding the insulating portion 27. The via liner 15 is electrically connected to a patterned first metal foil 21 and a patterned second metal foil 22 corresponding in position to a pair of conductive pads 10p1 and 10p2 of the via liner 15. Suitable materials for the via liner 15 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof. In an embodiment, the via 10v has a diameter in the range of approximately 60 μm to approximately 150 μm.

[0031] The redistribution structure 201 includes a first dielectric layer p71, a second dielectric layer p72, a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3. Therefore, the redistribution structure 201 has a "2P3M" configuration, which is merely exemplary and not limiting. The second dielectric layer p72 is disposed between the first dielectric layer p71 and the adhesive layer 80. Each of the first dielectric layer p71 and the second dielectric layer p72 may contain an organic material selected from polyamide (PA), polyimide (PI), polybenzoxazole (PBO), FR-4, or epoxy-based materials, or an inorganic material selected from silicon (Si), glass, ceramics, or oxidized or nitrided materials such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). In embodiments, each of the first dielectric layer p71 and the second dielectric layer p72 has a thickness ranging from approximately 2 μm to approximately 10 μm.

[0032] A first conductive layer M1 is disposed within a first dielectric layer p71. The first conductive layer M1 includes a first conductive pad m1p, a first conductive trace m1t, and a first via m1v. Each of the first conductive pad m1p and the first conductive trace m1t further includes a first seed layer p51, a first barrier layer 511, and a first solder layer 512 arranged sequentially in a stacked configuration. Suitable materials for the first seed layer p51 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), palladium (Pd), or alloys thereof. In an embodiment, the first seed layer 51 has a thickness ranging from approximately 1 μm to approximately 5 μm. Furthermore, suitable materials for the first barrier layer 511 may include Ti and W. In an embodiment, the first barrier layer 511 has a thickness ranging from approximately 0.1 μm to approximately 0.5 μm. Furthermore, suitable materials for the first solder layer 512 may include solder, anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). In addition, the first weld layer 512 has a thickness in the range of approximately 5 μm to approximately 20 μm.

[0033] A second conductive layer M2 is disposed within a second dielectric layer p72. The second conductive layer M2 includes a second conductive pad m2p, a second conductive trace m2t, and a second via m2v. Each of the second conductive pad m2p and the second conductive trace m2t further includes a second seed layer p52, a second barrier layer 521, and a second solder layer 522 arranged sequentially in a stacked configuration. Suitable materials and dimensions for the second seed layer p52, the second barrier layer 521, and the second solder layer 522 are similar to or the same as suitable materials and dimensions for the first seed layer p51, the first barrier layer 511, and the first solder layer 512, respectively.

[0034] A third conductive layer M3 is disposed on the second dielectric layer P72 and covers the adhesive layer 80. The third conductive layer M3 includes a third conductive pad m3p and a third conductive trace m3t. Each of the third conductive pad m3p and the third conductive trace m3t further includes a third seed layer p53 and a third barrier layer 531 arranged sequentially in a stacked manner. Suitable materials and dimensions for the third seed layer p53 and the third barrier layer 531 are similar to or the same as suitable materials and dimensions for the first seed layer p51 and the first barrier layer 511, respectively.

[0035] Furthermore, the first via m1v in the first conductive layer M1 includes a second barrier layer 521 and a second seed layer p52 disposed in the first dielectric layer p71. Additionally, the second via m2v in the second conductive layer M2 includes a third barrier layer 531 and a third seed layer p53 disposed in the second dielectric layer p72.

[0036] The linewidth and spacing (L / S) of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 are smaller than the linewidth and spacing (L / S) of the first conductive pad 10p1 or the first conductive trace 10t1, the second conductive pad 10p2, and the second conductive trace 10t2. In an embodiment, the linewidth and spacing (L / S) of the first conductive pad m1p and the first conductive trace m1t in the first conductive layer M1 are not greater than approximately 2 μm and 2 μm, respectively. Similarly, the linewidth and spacing (L / S) of the second conductive pad m2p and the second conductive trace m2t in the second conductive layer M2, and the linewidth and spacing (L / S) of the third conductive pad m3p and the third conductive trace m3t in the third conductive layer M3 are not greater than approximately 2 μm and 2 μm, respectively.

[0037] An adhesive layer 80 is disposed between the substrate 101 and the reel structure 201. The adhesive layer 80 serves to attach the reel structure 201 to the substrate 101 and acts as a buffer against thrust from the connecting assembly 30. Suitable materials for the adhesive layer 80 include ACP, ACF, non-conductive paste (NCP), non-conductive film (NCF), PI, epoxy resin, or resin. In embodiments, the adhesive layer 80 has a thickness ranging from approximately 20 μm to approximately 100 μm.

[0038] The connecting assembly 30 includes a base portion 30b and a tip portion 30t. The base portion 30b is disposed on a conductive pad 10p1 or conductive trace 10t1 on a first surface 10a of the substrate 10, while the tip portion 30t extends from the base portion 30b in a generally tapered manner. The tip portion 30t has a tapered end or a relatively pointed end that facilitates insertion into the re-laid structure 201 via the adhesive layer 80. In this embodiment, the connecting assembly 30 includes cylindrical bumps that can be referenced... Figure 9J The methods described and illustrated are formed. In another embodiment, the connecting component includes a support post, which can be referenced... Figures 10A to 10I The methods described and illustrated are used to form the connection. Suitable materials for the cylindrical bump type connector 30 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof. In embodiments, the connector 30 has a thickness and diameter each ranging from approximately 20 μm to approximately 50 μm.

[0039] When pushed into the reconstituted structure 201, the connecting component 30 penetrates the second dielectric layer p72 and then the first dielectric layer p71 to reach the first conductive layer M1 in the reconstituted structure 201. As a result, the substrate 101 and the reconstituted structure 201 are electrically connected to each other. In the first conductive pad m1p or the first conductive trace m1t in the first conductive layer M1 electrically connected to the connecting component 30, the first solder layer 512 and the first barrier layer 511 are pierced, while the first seed layer p51 may not be pierced. Furthermore, the connecting component 30 may penetrate one or more conductive layers in the reconstituted structure 201 toward the first conductive layer M1. For example, in this embodiment, the connecting component 30 penetrates the second conductive trace m2t and the second conductive pad m2p, thereby obtaining a deformed second conductive trace dm2t and a deformed second conductive pad dm2p, respectively. Thus, the connecting component 30 can electrically connect the substrate 101 to a desired conductive layer in the reconstituted structure 201, and vice versa. The deformed conductive pad or trace includes a raised portion surrounding the tip portion 30t of the connecting assembly 30.

[0040] In some existing methods, a redistribution structure can be fabricated on a substrate, which can easily lead to interconnection disconnection due to significant differences in L / S and U% between the redistribution structure and the substrate. In this disclosure, the substrate 101 and the redistribution structure 201 are combined by pushing a connecting component 30 into the redistribution structure 201. The connecting component 30 can pierce the conductive layer and create a protrusion. However, the protrusion of the pierced conductive layer remains electrically connected to the connecting component 30. As a result, although the substrate 101 and the redistribution structure 201 are fabricated in separate processes and may have significant differences in L / S and U% of the conductive and dielectric layers, respectively, the pushing in of the connecting component 30 ensures that the tip portion 30t of the connecting component 30 reaches the desired or predetermined location in the redistribution structure 201, and thus ensures a reliable electrical connection between the substrate 101 and the redistribution structure 201. This mitigates or solves the interconnection disconnection problem that would otherwise occur in existing methods.

[0041] Figure 2A and 2B These are cross-sectional views of substrate structures 211 and 212 according to some embodiments of the present disclosure.

[0042] See Figure 2A Substrate structure 211 and reference Figure 1The substrate structure 100 described and shown is similar, except that, for example, the redistribution structure 251 has a "1P2M" configuration different from the "2P3M" configuration of the redistribution structure 201. Specifically, the redistribution structure 251 includes a first dielectric layer p71, a first conductive layer M1 in the first dielectric layer p71, and a second conductive layer M2 disposed on the first dielectric layer p71 and covering the adhesive layer 80. In addition, the substrate structure 211 includes a connection component 35 having a tip portion 35t shorter than the tip portion 30t of the connection component 30.

[0043] See Figure 2B Substrate structure 212 and reference Figure 1 The substrate structure 100 described and shown is similar, except that, for example, the redistribution structure 271 has a "3P4M" configuration different from the "2P3M" configuration of the redistribution structure 201. Specifically, the redistribution structure 271 includes a third dielectric layer p73 in addition to the first dielectric layer p71 and the second dielectric layer p72, and a fourth conductive layer M4 in addition to the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. The third dielectric layer p73 is disposed between the second dielectric layer p72 and the adhesive layer 80. The suitable materials and dimensions for the third dielectric layer p73 are similar to or the same as those for the first dielectric layer p71. Furthermore, the fourth conductive layer M4 is disposed on the third dielectric layer p73 and covers the adhesive layer 80. The suitable materials and dimensions for the fourth conductive layer M4 are similar to or the same as those for the first conductive layer M1. Additionally, the substrate structure 212 includes a connection component 38 having a tip portion 37t that is longer than the tip portion 30t of the connection component 30.

[0044] Figure 3 This is a cross-sectional view of a substrate structure 300 according to another embodiment of the present disclosure.

[0045] See Figure 3 Substrate structure 300 and reference Figure 1 The substrate structure 100 described and shown is similar, except for, for example, the inclusion of additional wiring layers. Specifically, substrate structure 300 includes a first wiring structure 361 disposed on a first surface 10a of substrate 10 between substrate 101 and adhesive layer 80. The first wiring structure 361 electrically connects substrate 101 to connection assembly 30. Substrate structure 300 may also include a second wiring structure 362 disposed on a second surface 10b of substrate 10. Each of the first wiring structure 361 and the second wiring structure 362 may include one or more dielectric layers and wiring structures that wire toward redistribution structure 201 through the one or more dielectric layers.

[0046] Figure 4This is a cross-sectional view of a substrate structure 400 according to yet another embodiment of the present disclosure.

[0047] See Figure 4 Substrate structure 400 and reference Figure 1 The substrate structure 100 described and shown is similar, except that it includes, for example, a second rewoven structure 202 in addition to the rewoven structure 201 (in this case, the first rewoven structure 201). The second rewoven structure 202, disposed beneath the second surface 10b of the substrate 10, is attached to the substrate 101 by a second adhesive layer 480. The second adhesive layer 480, disposed on the second surface 10b of the substrate 10 between the substrate 101 and the second rewoven structure 202, comprises substantially the same material as the first adhesive layer 80. In this embodiment, the second rewoven structure 202 comprises substantially the same configuration as the first rewoven structure 201, i.e., a 2P3M configuration. However, in other embodiments, the second rewoven structure 202 may comprise different configurations, such as… Figure 2A The 1P2M configuration shown, or as... Figure 2B The 3P4M configuration is shown. The substrate structure 400 further includes a second connection component 430, which electrically connects the substrate 101 and the second re-laid structure 202. The second connection component 430 includes a tip portion 430t. In this embodiment, the tip portion 430t is substantially equal in length to the tip portion 30t of the first connection component 30. However, in other embodiments, the tip portion 430t may be shorter or longer than the tip portion 30t of the connection component 30 (in this case, the first connection component 30), as shown in... Figure 2A and 2B The illustrated embodiment.

[0048] In this embodiment, the deformed second conductive pad dm2p in the first re-fabricated structure 201 includes a protrusion r2p extending along the direction in which the first connecting assembly 30 is pushed in. The protrusion r2p surrounds the tip portion 30t of the first connecting assembly 30. Similarly, the deformed second conductive pad dm2p' in the second re-fabricated structure 202 includes a protrusion r2p' extending along the direction in which the second connecting assembly 430 is pushed in. The protrusion r2p' surrounds the tip portion 430t of the second connecting assembly 430.

[0049] Figure 5A , 5B 5C and 5C are cross-sectional views of substrate structures 501, 502 and 503 according to some embodiments of the present disclosure.

[0050] See Figure 5A Substrate structure 501 and reference Figure 1The substrate structures 100 described and shown are similar, except that, for example, conductive pads or traces are electrically connected by bonding wires. Specifically, in this embodiment, a first conductive pad 10p1 or a first conductive trace 10t1 is electrically connected to another first conductive pad 10p1 or another first conductive trace 10t1 by bonding wire 51w. Furthermore, a third conductive pad m3p or a third conductive trace m3t is electrically connected to another third conductive pad m3p or another third conductive trace m3t by bonding wire 52w. Bonding wires 51w and 52w facilitate electrical connections between conductive pads or traces disposed on the same conductive layer.

[0051] See Figure 5B Substrate structure 502 and reference Figure 1 The substrate structure 100 described and shown is similar, except that it further includes, for example, a pillar 57. In this embodiment, the pillar 57 connects between a first conductive pad 10p1 and a third conductive pad m3p, which are positioned corresponding to each other. The pillar 57 serves to mechanically reinforce the substrate structure 502 and may not provide electrical connections between the conductive pads or traces connected to the pillar 57.

[0052] See 5C, substrate structure 503 and reference. Figure 1 The substrate structure 100 described and shown is similar, except that it further includes, for example, device 58. In this embodiment, device 58 is electrically connected between the third conductive pads m3p. Device 58 may include a chip or a passive component.

[0053] Figure 6A and 6B These are cross-sectional views of substrate structures 601 and 602 according to some embodiments of the present disclosure.

[0054] See Figure 6A Substrate structure 601 and reference Figure 1The substrate structure 100 described and shown is similar, except that it includes, for example, a connecting component having a different length than the connecting component 30. Specifically, in this embodiment, the first connecting component 61 includes a tip portion 61t shorter than the tip portion 30t of the connecting component 30. The first connecting component 61 pierces the third conductive pad m3p, thereby extending the protrusion r3p of the third conductive pad m3p into the second dielectric layer p72. Furthermore, the second connecting component 62 includes a tip portion 62t shorter than the tip portion 30t of the connecting component 30 and longer than the tip portion 61t of the first connecting component 61. The second connecting component 62 pierces the second conductive pad m2p, thereby extending the protrusion r2p of the second conductive pad m2p into the first dielectric layer p71. Thus, these connecting components 30, 61, and 62 electrically connect the substrate 101 to the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3, and vice versa.

[0055] See Figure 6B Substrate structure 602 and reference Figure 1 The substrate structure 100 described and shown is similar, except for, for example, the inclusion of vias electrically connected to the connection components. Specifically, in this embodiment, via m2v in the second conductive layer M2 electrically connects the second conductive pad m2p and the third conductive pad m3p. The third connection component 63, located corresponding to via m2v, includes a tip portion 63t that physically contacts the third conductive pad m3p. As a result, the third connection component 63 electrically connects the substrate 101 to the third conductive layer M3 via the third conductive pad m3p, and additionally connects the substrate 101 to the second conductive layer M2 via via m2v and the second conductive pad m2p.

[0056] Furthermore, via m1v in the first conductive layer M1 electrically connects the first conductive pad m1p and the second conductive pad m2p. The fourth connection component 64, corresponding in position to via m1v, includes a tip portion 64t that physically contacts the second conductive pad m2p. As a result, the fourth connection component 64 electrically connects the substrate 101 to the second conductive layer M2 via the second conductive pad m2p, and additionally connects the substrate 101 to the first conductive layer M1 via via m1v and the first conductive pad m1p. Thus, by means of vias 63 and 64, connection components 63 and 64 electrically connect the substrate 101 to the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3, and vice versa.

[0057] Figure 7A and 7B These are cross-sectional views of substrate structures 701 and 702, respectively, according to some embodiments of the present disclosure.

[0058] See Figure 7A Substrate structure 701 and reference Figure 1The substrate structures 100 described and shown are similar, except that, for example, conductive pads or traces may lack a solder layer. Specifically, in this embodiment, while the first conductive pad m1p includes a first solder layer 512 in addition to the first seed layer p51 and the first buffer layer 511, another first conductive pad m1p' includes only the first seed layer p51 and the first buffer layer 511 and lacks a first solder layer 512. Similarly, while the second conductive pad m2p includes a second solder layer 522 in addition to the second seed layer p52 and the second buffer layer 521, another second conductive pad m2p' includes only the second seed layer p52 and the second buffer layer 521 and lacks a second solder layer 522.

[0059] See Figure 7B Substrate structure 702 and reference Figure 1 The substrate structure 100 described and shown is similar, except that, for example, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 have no bonding layers.

[0060] Figure 8A and 8B These are cross-sectional views of substrate structures 801 and 802, respectively, according to some embodiments of the present disclosure.

[0061] See Figure 8A Substrate structure 801 and reference Figure 1 The substrate structure 100 described and shown is similar, except for the filler 88 further included, for example, in the adhesive layer 80. The filler 88 is used to mechanically reinforce the substrate structure 801. Suitable materials for the filler 88 may comprise silica particles or glass fibers.

[0062] See Figure 8B Substrate structure 802 and reference Figure 8A The substrate structure 801 described and shown is similar, except that, for example, filler 88 is disposed in the substrate 10 instead of the adhesive layer 80. In other embodiments, filler 88 may be disposed in both the substrate 10 and the adhesive layer 80.

[0063] Figures 9A to 9I The manufacturing process according to embodiments of the present disclosure is shown as follows: Figure 1 One or more stages of the method for the substrate 101 shown.

[0064] See Figure 9AA substrate 10 is provided. The substrate 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a. Furthermore, the substrate 10 has a first metal foil 11 and a second metal foil 12 on the first surface 10a and the second surface 10b, respectively. The first metal foil 11 and the second metal foil 12 may each comprise titanium (Ti), tungsten (W), or alloys thereof. Additionally, the first metal foil 11 and the second metal foil 12 may each have a thickness ranging from about one (1) micrometer (μm) to about five (5) μm. The substrate 10 may include a dielectric layer and wiring structures in the dielectric layer for electrical communication between contact pads on the first surface 10a and the second surface 10b. The dielectric layer can be formed using processes such as lamination, printing, potting, or coating. In some embodiments, the dielectric layer in the substrate 10 may comprise an organic material selected from polyamide (PA), polyimide (PI), polybenzoxazole (PBO), FR-4, or epoxy-based materials. In other embodiments, the dielectric layer in the substrate 10 may comprise an inorganic material selected from silicon (Si), glass, ceramics, or oxides or nitrides such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). The substrate 10 may have a thickness in the range of approximately 20 μm to approximately 100 μm.

[0065] See Figure 9B Through-holes 10H are formed through the substrate 10 using a drilling process, such as a mechanical drilling machine 200. Each through-hole 10H exposes a wall 10w in the substrate 10 that defines the remaining portion of each through-hole 10H. The through-holes 10H can be vertical or tapered. In an embodiment, the through-holes 10H have a diameter in the range of approximately 60 μm to approximately 150 μm.

[0066] Next, see Figure 9C A via liner 15 is conformally formed along the wall of the remaining portion defining the via 10H in the substrate 10 using processes such as electroplating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable metal deposition processes. The via liner 15 is electrically connected to a first metal foil 11 and a second metal foil 12. Suitable materials for the via liner 15 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof.

[0067] See Figure 9D An electrically insulating layer 17 is formed using processes such as lamination, printing, potting, or coating. The insulating layer 17 covers the first metal foil 11, the second metal foil 12, and fills the through-hole 10H. Suitable materials for the insulating layer 17 may be similar to or the same as suitable materials for the dielectric layer in the substrate 10, as referenced. Figure 9A The discussion.

[0068] See Figure 9E The insulating layer 17 on the first metal foil 11 and the second metal foil 12 is removed by, for example, a brush coating process, thereby exposing the remaining portion 27 of the insulating layer 17 that fills the through-hole 10H. Each insulating portion 27 is substantially flush with the first metal foil 11 and the second metal foil 12.

[0069] See afterward. Figure 9F A first conductive layer 181 and a second conductive layer 182 are formed on a first metal foil 11 and a second metal foil 12, respectively, using processes such as sputtering, electroplating, electroless plating, printing, lamination, or potting. Suitable materials for the first conductive layer 181 and the second conductive layer 182 may each comprise copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof. In embodiments, the first conductive layer 181 and the second conductive layer 182 may each have a thickness in the range of approximately 5 μm to approximately 25 μm.

[0070] See Figure 9G In the coating process, a first photoresist layer 191 and a second photoresist layer 192 are formed on the first conductive layer 181 and the second conductive layer 182, respectively. Next, see... Figure 9H By patterning the first photoresist layer 191 and the second photoresist layer 192 in a photolithography process, a patterned first photoresist layer 291 and a patterned second photoresist layer 292 are formed on the first conductive layer 181 and the second conductive layer 182, respectively. The patterned first photoresist layer 291 and the patterned second photoresist layer 292 define conductive pads or traces to be formed on the first surface 10a and the second surface 10b of the substrate 10, respectively.

[0071] Subsequently, using patterned first photoresist layer 291 and patterned second photoresist layer 292 as masks, the first conductive layer 181 and the second conductive layer 182 are patterned in the etching process, thereby obtaining patterned first conductive layer 281 and patterned second conductive layer 282, respectively. Figure 9I As shown. Furthermore, a patterned first conductive layer 181 and a patterned second conductive layer 182 are used as masks during the etching process. Figure 9H The first metal foil 11 and the second metal foil 12 shown are patterned to obtain a patterned first metal foil 21 and a patterned second metal foil 22, respectively. Figure 9I As shown. Then, the patterned first photoresist layer 291 and the patterned second photoresist layer 292 are removed to obtain the result as shown in the reference. Figure 1The substrate structure 101 described and shown. A patterned first metal foil 21 and a patterned first conductive layer 281 thereon constitute conductive pads 10p1 or conductive traces 10t1 on the first surface 10a of the substrate 10. Additionally, a patterned second metal foil 22 and a patterned second conductive layer 282 thereon constitute conductive pads 10p2 or conductive traces 10t2 on the second surface 10b of the substrate 10. Furthermore, a pair of conductive pads 10p1, 10p2, along with a conductive liner 15 and a corresponding insulating portion 27 corresponding in position to the pair of conductive pads 10p1, 10p2, together constitute a via 10v, as shown. Figure 9I As shown. The linewidth and spacing (L / S) of the conductive pads 10p1 and 10p2 and the conductive traces 10t1 and 10t2 are not less than approximately 7 μm and 7 μm, respectively.

[0072] Figure 9J The formation of an embodiment according to this disclosure is shown as follows Figure 1 One or more stages of the method of connecting component 30 shown.

[0073] See Figure 9J A connection assembly 30 for interconnection is formed on a conductive pad 10p1 or conductive trace 10t1 on a first surface 10a of a substrate 10. The connection assembly 30 can be formed by a suitable process that produces tapered or relatively pointed ends to facilitate insertion into a re-lay structure. In this embodiment, the connection assembly 30 includes cylindrical bumps, which in turn include a base portion 30b and a tip portion 30t. The base portion 30b is disposed on the conductive pad 10p1 or conductive trace 10t1, while the tip portion 30t extends from the base portion 30b in a generally tapered manner. The connection assembly 30 is formed using a wire bonding process, such as that using a capillary 280. The size of the connection assembly 30, particularly the length of the tip portion 30t, can be predetermined by controlling the force and ultrasonic energy applied over time from the capillary 280 to the bonding wire 280w. Suitable materials for the cylindrical bumps used as the connection assembly 30 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof. In an embodiment, the connecting component 30 has a thickness and diameter in the range of approximately 20 μm to approximately 50 μm.

[0074] The connection components suitable for interconnection as connection components 30 can be formed by a method other than wire bonding. Figures 10A to 10I This illustrates one or more stages of a method for forming a connection component 83 according to an embodiment of the present disclosure.

[0075] See Figure 10A A carrier 81 is provided. Then, a first photoresist layer 91 is formed on the carrier 81 in, for example, a lamination process.

[0076] See Figure 10B In a photolithography process, a first photoresist layer 91 is patterned to obtain a patterned first photoresist layer p91. The patterned first photoresist layer p91 includes recesses 91H, each recess 91H defining a tip portion of the connecting assembly 83 to be formed later. Specifically, the recesses 91H are tapered from a first surface p91a toward an opposing second surface p91b of the patterned first photoresist layer p91. Subsequently, a barrier layer 82 is conformally formed on the patterned first photoresist layer p91 in, for example, a physical vapor deposition (PVD) process. Suitable materials for the barrier layer 82 may include titanium (Ti) and tungsten (W). In embodiments, the barrier layer 82 has a thickness in the range of approximately 0.1 μm to approximately 0.5 μm.

[0077] Next, see Figure 10C In the photolithography process, a patterned second photoresist layer p92 is formed on the barrier layer 82, exposing portions of the barrier layer 82 through the opening 92H, particularly the portion of the barrier layer 82 formed in the recess 91H. The patterned second photoresist layer p92 defines the substrate portion of the connection assembly 83.

[0078] See Figure 10D A first conductive layer 831 is formed on the exposed portion of the barrier layer 82 by, for example, an electroplating process, thereby filling the recess 91H. The first conductive layer 831 serves as both the base portion and the tip portion of the connecting assembly 83. Suitable materials for the first conductive layer 831 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), solder, or alloys thereof.

[0079] Then, a second conductive layer 832 is formed on the first conductive layer 831 by, for example, an electroplating process. The second conductive layer 832 serves as a barrier layer for the connection component 83. Suitable materials for the second conductive layer 832 may include titanium (Ti) and tungsten (W). In an embodiment, the second conductive layer 832 has a thickness in the range of about 0.1 μm to about 0.5 μm.

[0080] Subsequently, a third conductive layer 833 is formed on the second conductive layer 832 by, for example, an electroplating process. The third conductive layer 833 serves as a solder layer for connecting the assembly 83. Suitable materials for the third conductive layer 833 may include solder, anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). In an embodiment, the third conductive layer 833 has a thickness in the range of approximately 5 μm to approximately 20 μm. The patterned second photoresist layer p92 is then removed, thereby exposing the portion of the barrier layer 82 not masked by the third conductive layer 833.

[0081] Next, see Figure 10EThe exposed portion of the barrier layer 82 is removed by an etching process to obtain a patterned barrier layer p82. A portion of the patterned barrier layer p82 disposed on the surface p91a of the patterned first photoresist layer p91, and the stack of the first conductive layer 831, the second conductive layer 832, and the third conductive layer 833 on the aforementioned portion of the patterned barrier layer p82 constitute the base portion 83b of the connection assembly 83. Furthermore, the remaining portion of the patterned barrier layer p82 and the first conductive layer 831 in the patterned first photoresist layer p91 constitute the tip portion 83t of the connection assembly 83.

[0082] See Figure 10F A substrate structure 101 is provided, which can be based on a reference. Figures 9A to 9I The method described and shown is used for preparation. A second conductive layer 852 serving as a barrier layer and a third conductive layer 853 serving as a solder layer are sequentially formed on the conductive pad 10p1 (or conductive trace 10t1). A portion of the third conductive layer 853 may correspond in position to the third conductive layer 833 of the connecting assembly 83. Suitable processes and materials for forming the second conductive layer 852 and the third conductive layer 853 on the conductive pad 10p1 are similar to or the same as suitable processes and materials for the second conductive layer 832 and the third conductive layer 833 for the connecting assembly 83, as referenced. Figure 10D As described and shown.

[0083] Then, see Figure 10G The connecting assembly 83 is connected to the corresponding conductive pad 10t1 by, for example, connecting the connecting assembly 83 and the corresponding third conductive layers 833 and 853 of the corresponding conductive pad 10t1 in a reflow process, thereby obtaining a pillar-shaped connecting assembly having a connector 85 between the second conductive layers 832 and 852. Subsequently, the carrier 81 and the patterned first photoresist layer p91 are removed.

[0084] See Figure 10H A fourth conductive layer 834 is formed on the third conductive layer 833 of the connecting component 83 using, for example, an electroless plating process in an aqueous solution. The fourth conductive layer 834 serves as a solder layer. Suitable materials for the fourth conductive layer 834 may include titanium (Ti) and tungsten (W). Figure 10I The diagram shows a connection assembly 83 having a fourth conductive layer 834. In an embodiment, the connection assembly 83 has a thickness and diameter each ranging from approximately 20 μm to approximately 50 μm.

[0085] like Figure 9J The connecting component 30 shown is in the form of columnar protrusions and, as shown in the figure, is a connecting component 30 ... Figure 10I The connecting component 83 shown in the form of a pillar is used for assembling such as Figure 1 The exemplary connection assembly of the substrate 10 and the redistribution structure 201 shown. Figures 11A to 11KThe manufacturing process according to embodiments of the present disclosure is shown as follows: Figure 1 One or more stages of the method of the redistribution structure 201 shown.

[0086] Referring to 11A, a first carrier 41 is provided. The first carrier 41 is used to support a semiconductor component, device, or structure to be subsequently formed or disposed thereon. The first carrier 41 may comprise one of a metal carrier, a ceramic carrier, a glass carrier, a substrate, or a semiconductor wafer. Additionally, the first carrier 41 may have a rectangular or square shape, such as... Figure 13 As shown. Alternatively, the first carrier 10 may have a circular or elliptical shape, such as... Figure 14 As shown. Depending on the application, the thickness of the first carrier 41 can range from about 100 μm to about 500 μm, about 200 μm to about 800 μm, or about 500 μm to about 1500 μm.

[0087] A first release film 41r is then formed on the first carrier 41. The first release film 41r is used to facilitate the detachment of the first carrier 41 from the semiconductor structure temporarily held by the first carrier 41. In an embodiment, the first release film 202 comprises a polymer and has a thickness of approximately 0.5 μm.

[0088] Subsequently, a first seed layer 51 is formed on the first release film 41r using processes such as sputtering, electroplating, electroless plating, printing, lamination, or potting. Suitable materials for the first seed layer 51 may include copper (Cu), silver (Ag), gold (Au), nickel (Ni), palladium (Pd), or alloys thereof. In embodiments, the first seed layer 51 has a thickness in the range of approximately 1 μm to approximately 5 μm.

[0089] See Figure 11B A patterned first photoresist layer 61 is formed on the first seed layer 51, and a portion of the first seed layer 51 is exposed through an opening 61H. The patterned first photoresist layer 61 can be formed by forming the photoresist layer on the first seed layer 51 in a coating process and then in a photolithography process including exposure and development.

[0090] See Figure 11CA first barrier layer 511 and a first solder layer 512 are sequentially formed on the exposed portion of the first seed layer 51 using processes such as sputtering, electroplating, electroless plating, printing, lamination, or potting. Suitable materials for the first barrier layer 511 may include Ti and W. Suitable materials for the first solder layer 512 may include solder, ACF, or ACP. In an embodiment, the first barrier layer 511 has a thickness ranging from approximately 0.1 μm to approximately 0.5 μm. Additionally, the first solder layer 512 has a thickness ranging from approximately 5 μm to approximately 20 μm. The patterned first photoresist layer 61 is then removed, thereby exposing the portion of the first seed layer 51 not masked by the first barrier layer 511 and the first solder layer 512.

[0091] Next, see Figure 11D In the etching process, the exposed portion of the first seed layer 51 is patterned to obtain a patterned first seed layer p51. The patterned first seed layer p51, the first barrier layer 511, and the first solder layer 512, which are formed in a stacked manner, constitute the first conductive pad m1p or the first conductive trace m1t of the first conductive layer in the fabricated structure. The linewidth and spacing (L / S) of the first conductive pad m1p and the first conductive trace m1t are not greater than approximately 2 μm and 2 μm, respectively.

[0092] Subsequently, a first dielectric layer 71 is formed on the first release film 41 in processes such as printing, lamination, potting, or coating, thereby covering the first conductive pad m1p and the first conductive trace m1t. Suitable materials for the first dielectric layer 71 may comprise organic materials selected from polyamide (PA), polyimide (PI), polybenzoxazole (PBO), FR-4, or epoxy-based materials, or inorganic materials comprising oxides or nitrides selected from silicon (Si), glass, ceramics, or such as silicon oxide (SiOx), tantalum oxide (TaOx), or silicon nitride (SiNx). In embodiments, the first dielectric layer 71 has a thickness ranging from approximately 2 μm to approximately 10 μm.

[0093] See Figure 11E In the photolithography process, the first dielectric layer 71 is patterned to obtain the patterned first dielectric layer p71. The patterned first dielectric layer p71 exposes a portion of the first conductive pad m1p or the first conductive trace m1t through the opening p71H.

[0094] Then, see Figure 11F A second seed layer 52 is conformally formed on the patterned first dielectric layer p71. The suitable processes, materials, and dimensions used to form the second seed layer 52 are similar to or the same as those used to form the first seed layer 51, as shown in reference [reference needed]. Figure 11AAs described and shown. Subsequently, a patterned second photoresist layer 62 is formed on the second seed layer 52, exposing a portion of the second seed layer 52. Specifically, the patterned second photoresist layer 62 exposes the second seed layer 52 disposed in the opening p71H. A suitable process for forming the patterned second photoresist layer 62 is similar to or the same as a suitable process for forming the patterned first photoresist layer 61, as referenced. Figure 11B As described and shown.

[0095] See Figure 11G A second barrier layer 521 and a second weld layer 522 are sequentially formed on the exposed portion of the second seed layer 52. The second barrier layer 521 fills the exposed portion of the second seed layer 52 disposed in the opening p71H. The suitable processes, materials, and dimensions for forming the second barrier layer 521 and the second weld layer 522 are similar to or the same as the suitable processes, materials, and dimensions for forming the first barrier layer 511 and the first weld layer 512, respectively, as referenced. Figure 11C As described and shown. The patterned second photoresist layer 62 is then removed, thereby exposing the portion of the second seed layer 52 that is not masked by the second barrier layer 521 and the second solder layer 522.

[0096] Next, see Figure 11H In the etching process, the exposed portion of the second seed layer 52 is patterned to obtain a patterned second seed layer p52. The patterned second seed layer p52, the second barrier layer 521, and the second solder layer 522, which are formed in a stacked manner, constitute the second conductive pad m2p or the second conductive trace m2t of the second conductive layer in the constructed redistribution structure. The linewidth and spacing (L / S) of the second conductive pad m2p and the second conductive trace m2t are not greater than approximately 2 μm and 2 μm, respectively. In addition, the second barrier layer 521 filling the opening p71H and the patterned second seed layer p52 associated with the opening p71H constitute the via m1v of the first conductive layer M1 in the constructed redistribution structure. Specifically, see also Figure 11D The first conductive layer M1 includes a first conductive pad m1p, a first conductive trace m1t, and a first via m1v.

[0097] Then see Figure 11I A patterned second dielectric layer p72 is formed on the patterned first dielectric layer p71, exposing a portion of the second conductive pad m2p or the second conductive trace m2t through an opening p72H. Suitable processes, materials, and dimensions for forming the patterned second dielectric layer p72 are similar to or the same as suitable processes, materials, and dimensions for forming the patterned first dielectric layer p71, as referenced. Figure 11D As described and shown.

[0098] See Figure 11JA third seed layer 53 is conformally formed on the patterned second dielectric layer p72. The suitable processes, materials, and dimensions used to form the third seed layer 53 are similar to or the same as those used to form the first seed layer 51, as shown in reference [reference needed]. Figure 11A As described and shown. Subsequently, a patterned third photoresist layer 63 is formed on the third seed layer 53, exposing a portion of the third seed layer 53. Specifically, the patterned third photoresist layer 63 exposes the third seed layer 53 disposed in the opening p72H. A suitable process for forming the patterned third photoresist layer 63 is similar to or the same as a suitable process for forming the patterned first photoresist layer 61, as referenced. Figure 11B As described and shown.

[0099] Subsequently, a third barrier layer 531 is formed on the exposed portion of the third seed layer 53. The third barrier layer 531 fills the exposed portion of the third seed layer 53 disposed in the opening p72H. The suitable process, materials, and dimensions for forming the third barrier layer 531 are similar to or the same as the suitable process, materials, and dimensions for forming the first barrier layer 511, as referenced. Figure 11C As described and shown. The patterned third photoresist layer 63 is then removed, thereby exposing the portion of the third seed layer 53 that was not masked by the third blocking layer 531.

[0100] In addition, see Figure 11K In the etching process, the exposed portion of the third seed layer 53 is patterned to obtain a patterned third seed layer p53. The stacked patterned third seed layer p53 and the third barrier layer 531 constitute the third conductive pad m3p or the third conductive trace m3t of the third conductive layer M3 in the constructed redistribution structure. The linewidth and spacing (L / S) of the third conductive pad m3p and the third conductive trace m3t are not greater than approximately 2 μm and 2 μm, respectively. In addition, the third barrier layer 531 filling the opening p72H and the patterned third seed layer p53 associated with the opening p72H constitute the via m2v of the second conductive layer M2 in the constructed redistribution structure. Specifically, see also refer to Figure 11J The second conductive layer M2 includes a second conductive pad m2p, a second conductive trace m2t, and a second via m2v.

[0101] As a result, a redistribution structure 201 with a 2P3M configuration was realized, comprising a patterned first dielectric layer p71 and a second dielectric layer p72 as 2P, and a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 as 3M. ​​The 2P3M redistribution structure 201 is merely exemplary and not limiting. Further details can be found in the references. Figures 11A to 11K The methods described and illustrated prepare redistribution structures with different configurations without departing from the intended scope of this disclosure.

[0102] Figures 12A to 12C The manufacturing process according to embodiments of the present disclosure is shown as follows: Figure 1 One or more stages of the method for the substrate structure shown.

[0103] See Figure 12A An adhesive layer 80 is formed on the reel structure 201 using processes such as printing, lamination, potting, or coating, thereby covering the third conductive layer M3 and the patterned second dielectric layer p72. The adhesive layer 80 facilitates attachment of the reel structure 201 to the substrate 101 and acts as a buffer against thrust from the connection assembly. The adhesive layer 80 has a surface 80s facing away from the first carrier 41. Suitable materials for the adhesive layer 80 include ACP, ACF, non-conductive paste (NCP), non-conductive film (NCF), PI, epoxy, or resin. In embodiments, the adhesive layer 80 has a thickness ranging from approximately 20 μm to approximately 100 μm.

[0104] See Figure 12B A substrate 101 is provided on which one or more connecting components 30 are formed. Additionally, a rewoven structure 201 with an adhesive layer 80 attached is provided. The tip portion 30t of the connecting component 30 is oriented toward the surface 80s of the adhesive layer 80. A force f is then applied, for example, from a laminator to combine the substrate 101 and the rewoven structure 201 (arrows indicate movement). Thus, the connecting component 30 is pushed into the rewoven structure 201 through the adhesive layer 80. Specifically, see... Figure 12C The connecting component 30 penetrates not only the adhesive layer 80 but also the patterned second dielectric layer p72, and then the patterned first dielectric layer p71 to reach the first conductive layer M1 in the re-laid structure 201, thereby electrically connecting the substrate 101 and the re-laid structure 201. Furthermore, the connecting component 30 can be pushed towards the first conductive layer M1 through one or more conductive layers. In this example, the connecting component 30 penetrates the second conductive trace m2t and the second conductive pad m2p, thereby obtaining the deformed second conductive trace dm2t and the deformed second conductive pad dm2p, respectively. Therefore, the connecting component 30 can electrically connect the substrate 101 to the desired conductive layer in the re-laid structure 201.

[0105] The first release film 41r or the first carrier 41, or both, serve as a buffer against the insertion of the connecting assembly 30 for the first conductive layer M1, with the first conductive layer M1 positioned closest to the first release film 41r or the first carrier 41. As a result, in the first conductive pad m1p or the first conductive trace m1t of the first conductive layer M1 electrically connected to the connecting assembly 30, the first solder layer 512 and the first barrier layer 511 are punctured, while the patterned first seed layer p51 remains unpunctured. Therefore, significant deformation may not occur at the first conductive pad m1p or the first conductive trace m1t. The first carrier 41 and the first release film 41r are then removed, resulting in... Figure 1 The substrate structure 100 shown is shown.

[0106] Return to view Figure 12B Instead of the cylindrical protrusion type connecting component 30, a reference is adopted. Figure 10I The described and shown pillar-type connecting assembly 83. Therefore, a substrate 101 is provided on which one or more connecting assemblies 83 are formed. Additionally, a re-laid structure 201 with an adhesive layer 80 attached is provided. The tip portion 83t of the connecting assembly 83 is oriented toward the surface 80s of the adhesive layer 80. The substrate 101 and the re-laid structure 201 are then connected as referenced. Figure 12B and 12C The similar ways described and shown are electrically connected to each other.

[0107] For example, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” and “below” are relative to the orientation shown in the figures, unless otherwise specified. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure do not depart from such an arrangement.

[0108] As used herein, the terms “approximately,” “roughly,” “generally,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurred precisely or an instance where the event or situation occurred at a close approximation. For example, when used in conjunction with a numerical value, the term can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of these values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values ​​can be considered “roughly” the same or equal.

[0109] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or approximately coplanar.

[0110] As used herein, the singular terms “a” and “the” may include plural indicators unless the context clearly specifies otherwise.

[0111] As used herein, the terms "conductivity" and "electrical conductivity" refer to the ability to conduct electric current. Conductive materials are generally defined as those that exhibit little or no resistance to the flow of electric current. One measure of electrical conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than about 10⁴ S / m, for example, at least 10⁵ S / m or at least 10⁶ S / m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0112] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0113] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The drawings are not necessarily drawn to scale. Differences may exist between the process reproduction of this disclosure and the actual apparatus due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. This specification and the drawings are intended to be illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A substrate structure comprising: A substrate, which contains a first conductor on a first surface of the substrate; A first re-woven structure is disposed on the substrate, wherein the first re-woven structure includes a first dielectric layer, a first conductive layer in the first dielectric layer, a second dielectric layer between the substrate and the first dielectric layer, and a second conductive layer in the second dielectric layer, wherein the first conductive layer includes a first conductor, and the second conductive layer includes a second conductor. A first adhesive layer is placed between the substrate and the first rewoven structure; as well as A first connecting component, electrically connected to the first conductor of the substrate, penetrates through the first adhesive layer into the first rewoven structure and electrically connects the substrate to the first rewoven structure. The first connection component physically contacts the first conductor of the first conductive layer and electrically connects the substrate to the first conductive layer, wherein the first connection component passes through the second conductor of the second conductive layer, and wherein the second conductor of the second conductive layer includes a protrusion surrounding the first connection component.

2. The substrate structure of claim 1, wherein the first connection component comprises a base portion disposed on the first conductor of the substrate and a tip portion extending in a tapered manner from the base portion toward the first re-woven structure.

3. The substrate structure according to claim 1, wherein the protrusion extends into the first dielectric layer.

4. The substrate structure according to claim 1, wherein the first conductor of the first conductive layer comprises a first seed layer and a first barrier layer on the first seed layer.

5. The substrate structure according to claim 4, wherein the first conductor of the first conductive layer comprises a first bonding layer, and the first barrier layer is disposed between the first seed layer and the first bonding layer.

6. The substrate structure of claim 1, further comprising a second re-fabricated structure beneath a second surface of the substrate, the second surface being opposite to the first surface, and the substrate structure comprising a second adhesive layer between the substrate and the second re-fabricated layer.

7. The substrate structure of claim 6, wherein the substrate includes a second conductor on the second surface, the substrate structure further including a second connection component electrically connected to the second conductor, penetrating through the second adhesive layer into the second re-woven structure, and electrically connecting the substrate to the second re-woven structure.

8. The substrate structure of claim 1, wherein the first conductor of the first conductive layer of the first re-woven structure is covered in the first adhesive layer, and the substrate structure further includes a strut connecting the first conductor of the first re-woven structure and the first conductor of the substrate.

9. The substrate structure of claim 8, wherein the second conductor of the second conductive layer of the first re-laid structure is covered in the first adhesive layer, and the substrate structure further includes a device electrically connected between the first conductor and the second conductor of the first re-laid structure.

Images