Semiconductor device and method of forming thereof

Abstract

A semiconductor device and a method of forming the same are provided. The method may include forming a stacked structure, which may include stacked regions and stepped regions, and may include alternatingly stacked first and second layers. The second layer may have a stepped shape in the stepped regions, and the stepped regions may include at least one flat region and at least one inclined stepped region. The method may further include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a level lower than the first upper surface. The method may further include patterning the capping insulating layer to form a plurality of protrusions, and then planarizing the capping insulating layer, at least one of the protrusions overlapping a stepped region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0138719, filed with the Korean Intellectual Property Office on November 1, 2019, the full disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to a method for planarizing a capping insulating layer, a method for forming a semiconductor device using the same, and a semiconductor device formed therefrom. Background Technology

[0004] To increase the integration density of semiconductor devices, semiconductor devices have been developed that include gates stacked and spaced apart from each other in a direction perpendicular to the upper surface of the substrate. As the number of stacked gates increases, unintended process defects may occur and it may make it difficult to improve the productivity of semiconductor devices. Summary of the Invention

[0005] Embodiments of the present invention provide a method for forming a semiconductor device, wherein the flatness of the capping insulating layer surrounding the stacked structure can be improved.

[0006] Embodiments of the present invention provide a method for improving the integration density of semiconductor devices.

[0007] Embodiments of the present invention provide a method for improving the productivity of semiconductor devices.

[0008] According to an embodiment of the present invention, a method of forming a semiconductor device may include: forming a stacked structure and a planarization stop layer on a first region of a substrate, the stacked structure including a stacked region having a flat upper surface and a stepped region adjacent to the stacked region, the stacked structure including a plurality of first layers and a plurality of second layers repeatedly stacked in a vertical direction perpendicular to the upper surface of the substrate, the uppermost of the plurality of first layers and the plurality of second layers being a first layer at the highest level, and the planarization stop layer being formed on the uppermost layer; forming a capping insulating layer covering the planarization stop layer and the stacked structure and covering a second region of the substrate adjacent to the first region of the substrate, the capping insulating layer including a first capping region having a first upper surface, a second capping region having a second upper surface at a level lower than the first upper surface, and a layer between the first capping region and the second capping region. A third capping region between capping regions; patterning a capping insulating layer to form a plurality of horizontally spaced protrusions on a first region of a substrate, the horizontal direction being parallel to the upper surface of the substrate, at least one of the plurality of protrusions overlapping a stepped region; planarizing the capping insulating layer with the plurality of protrusions to form a planarized capping insulating layer; partially etching the planarized capping insulating layer to form a partially etched capping insulating layer; performing an annealing process to convert the partially etched capping insulating layer into a dense capping insulating layer; forming a first upper insulating layer covering the dense capping insulating layer and the uppermost layer of the stacked structure; forming a channel via penetrating the first upper insulating layer and the stacked region of the stacked structure; forming a vertical memory structure in the channel via; forming contact plugs on the vertical memory structure; and forming bit lines on the contact plugs.

[0009] According to an embodiment of the present invention, a method of forming a semiconductor device may include: forming a first stacked structure on a first region of a substrate, the first stacked structure including a first stacked region and a first stepped region adjacent to the first stacked region, the first stacked structure including a plurality of first layers and a plurality of second layers repeatedly stacked in a vertical direction perpendicular to the upper surface of the substrate, the plurality of second layers being arranged in a stepped shape in the first stepped region; forming a first capping insulating layer covering the first stacked structure on the first region of the substrate and covering a second region of the substrate adjacent to the first region of the substrate, the first capping insulating layer including a first capping region having a first upper surface, a second capping region having a second upper surface at a level lower than the first upper surface, and a third capping region between the first capping region and the second capping region; patterning the first capping insulating layer to form a plurality of first protrusions spaced apart in a horizontal direction on the first region of the substrate, the horizontal direction being a direction parallel to the upper surface of the substrate, and at least one of the plurality of first protrusions overlapping the first stepped region; and planarizing the capping insulating layer on which the plurality of first protrusions are formed.

[0010] According to an embodiment of the present invention, a method of forming a semiconductor device may include: forming a stacked structure on a first region of a substrate, the stacked structure including a stacked region and a stepped region adjacent to the stacked region, and including a plurality of first layers and a plurality of second layers repeatedly stacked in a vertical direction perpendicular to the upper surface of the substrate, the plurality of second layers being arranged in a stepped shape in the stepped region, the stepped region of the stacked structure including one or more flat regions and inclined stepped regions respectively adjacent to the one or more flat regions; forming a capping insulating layer covering the stacked structure on the first region of the substrate and covering a second region of the substrate adjacent to the first region of the substrate, the capping insulating layer including a first capping region having a first upper surface, a second capping region having a second upper surface horizontally lower than the first upper surface, and a third capping region between the first capping region and the second capping region; patterning the capping insulating layer to form a plurality of protrusions spaced apart in a horizontal direction on the first region of the substrate, the horizontal direction being a direction parallel to the upper surface of the substrate, and at least one of the plurality of protrusions overlapping the stepped region; and planarizing the capping insulating layer on which the plurality of protrusions are formed.

[0011] According to embodiments of the present invention, a semiconductor device may include: a stacked structure on a first region of a substrate, the stacked structure including a stacked region and a stepped region adjacent to the stacked region, the stacked structure including a plurality of first layers and a plurality of second layers repeatedly stacked in a vertical direction perpendicular to the upper surface of the substrate, the plurality of second layers being arranged in a stepped shape in the stepped region, the stepped region of the stacked structure including one or more flat regions and inclined stepped regions respectively adjacent to the one or more flat regions; a capping insulating layer covering the stepped region of the stacked structure and covering a second region of the substrate adjacent to the first region of the substrate, the capping insulating layer including an upper surface having a first surface and a second surface at a level lower than the first surface, the first surface overlapping the stepped region of the stacked structure, the first surface including inclined portions located at different height levels; an upper insulating layer on the stacked structure and the capping insulating layer; and a vertical memory structure penetrating the upper insulating layer and the stacked structure.

[0012] According to an embodiment of the present invention, a semiconductor device may include: a lower stacked structure on a first region of a substrate, the lower stacked structure including a lower stacked region and a lower stepped region adjacent to the lower stacked region; a lower capping insulating layer covering the lower stepped region of the lower stacked structure and covering a second region of the substrate adjacent to the first region of the substrate, the lower capping insulating layer including a first upper surface having a first portion and a second portion at a level lower than the first portion, the first portion overlapping the lower stepped region of the lower stacked structure, the first portion including first inclined portions located at different height levels; and the lower stacked structure... The structure comprises an upper stacked structure including an upper stacked region and an upper stepped region adjacent to the upper stacked region; an upper cover insulating layer covering the upper stepped region of the upper stacked structure and covering a lower cover insulating layer, the upper cover insulating layer including a second upper surface having a third portion and a fourth portion at a level lower than the third portion, the third portion overlapping the upper stepped region of the upper stacked structure and including second inclined portions located at different height levels; an upper insulating layer on the upper stacked structure and the upper cover insulating layer; and a vertical memory structure penetrating the upper insulating layer, the upper stacked structure, and the lower stacked structure. Attached Figure Description

[0013] The above and other aspects, features and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1A and Figure 1B This is a process flow diagram illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present invention;

[0015] Figures 2A to 12C These are diagrams illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present invention; and

[0016] Figures 13A to 15B This is a diagram illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present invention. Detailed Implementation

[0017] Throughout this specification, terms such as “upper,” “middle,” and “lower” are used to distinguish the relative positions of components, but the scope of the inventive concept is not limited by these terms. Therefore, terms such as “top,” “middle,” and “bottom” may be replaced by other terms such as “first,” “second,” and “third,” or by other terms, and may be used to describe the components of this specification.

[0018] The following will refer to Figures 1A to 15B Methods for forming semiconductor devices according to exemplary embodiments of the present invention are described, as well as various examples of semiconductor devices formed therefrom. Figure 1A and Figure 1B This is a process flow diagram illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present invention. Figures 2A to 12C This is a cross-sectional view illustrating an example of a method for forming a semiconductor device according to an exemplary embodiment of the present invention. Figures 13A to 15B This is a cross-sectional view illustrating a method for forming a semiconductor device according to an exemplary embodiment of the present invention.

[0019] exist Figures 2A to 12C middle, Figure 2A , Figures 4 to 9A , Figure 10A , Figure 11A and Figure 12A It is a cross-sectional view taken along a first horizontal direction to illustrate an example of a method for forming a semiconductor device according to an exemplary embodiment. Figure 2B It is shown Figure 2A An enlarged cross-sectional view of the portion indicated by "A". Figure 2C It is a section taken along a second horizontal direction perpendicular to the first horizontal direction. Figure 2A An enlarged cross-sectional view of the portion indicated by line B-B'. Figure 2D It is a cut along the second horizontal direction by Figure 2A An enlarged cross-sectional view of the portion indicated by line C-C'. Figure 9B yes Figure 9A A magnified view of part D. Figure 9C yes Figure 9A A magnified view of part D. Figure 10B and Figure 10C Each is Figure 10A A magnified cross-sectional view of a portion of the image. Figure 11B It shows the section cut along the second horizontal direction. Figure 11A An enlarged cross-sectional view of the portion indicated by line B1-B1'. Figure 12B It is shown Figure 12A An enlarged cross-sectional view of the portion indicated by line B1-B1'. Figure 12C It shows the section cut along the second horizontal direction. Figure 12A An enlarged cross-sectional view of the portion indicated by line C1-C1'.

[0020] First, refer to Figure 1A as well as Figures 2A to 12B The present invention will describe a method for forming a semiconductor device according to an example embodiment.

[0021] Reference Figure 1A and Figures 2A to 2C A substrate 3 can be prepared. The substrate 3 may include a semiconductor substrate. A stacked structure 15 and a planarization stop layer 21 can be formed (S5). The stacked structure 15 and the planarization stop layer 21 can be formed on a first region 3a of the substrate 3.

[0022] In substrate 3, the region forming the stacked structure 15 is defined as the first region 3a, and the region not forming the stacked structure 15 is defined as the second region 3b. In substrate 3, the first region 3a and the second region 3b may be adjacent to each other.

[0023] The stacked structure 15 may include a plurality of first layers 17 and a plurality of second layers 19 alternately stacked with the plurality of first layers 17 in the vertical direction Z. In the stacked structure 15, the uppermost layer may be the uppermost first layer 17U located on top of the plurality of first layers 17. The vertical direction Z may be a direction perpendicular to the upper surface 3s of the substrate 3.

[0024] In some embodiments, the plurality of first layers 17 may include a first insulating material (e.g., silicon oxide, etc.), and the plurality of second layers 19 may include a second insulating material (e.g., silicon nitride, etc.) that is different from the first insulating material. When the plurality of second layers 19 are formed of the second insulating material, the plurality of second layers 19 may be sacrificial gate layers.

[0025] In some embodiments, the plurality of first layers 17 may include an insulating material (e.g., silicon oxide, etc.), and the plurality of second layers 19 may include a conductive material (e.g., doped silicon, metal nitride, metal semiconductor compound, or metal). When the plurality of second layers 19 are formed of a conductive material, the second layers 19 may be gate layers.

[0026] The stacked structure 15 may include a stacked region 15A1 having a flat upper surface 15U on a first region 3a of the substrate 3 and a stepped region 15A2 adjacent to the stacked region 15A1.

[0027] The stepped region 15A2 of the stacked structure 15 may include one or more flat regions 15f1 and 15f2 and inclined stepped regions 15s1, 15s2 and 15s3 that are adjacent to the one or more flat regions 15f1 and 15f2 respectively.

[0028] In some embodiments, multiple flat regions 15f1 and 15f2 may be provided as the one or more flat regions 15f1 and 15f2. For example, the multiple flat regions 15f1 and 15f2 may include a first flat region 15f1 and a second flat region 15f2 located at different height levels. For example, the distance between the first flat region 15f1 and the upper surface 3s of the substrate 3 may be greater than the distance between the second flat region 15f2 and the upper surface 3s of the substrate 3.

[0029] Each of the multiple flat regions 15f1 and 15f2 may be substantially parallel to the upper surface 3s of the substrate 3.

[0030] In some embodiments, the stepped region 15A2 of the stacked structure 15 may include an upper stepped region 15s4, an upper inclined stepped region 15s3, a second flat region 15f2, an intermediate inclined stepped region 15s2, a first flat region 15f1, and a lower inclined stepped region 15s1 arranged in the first horizontal direction X.

[0031] The first flat region 15f1 can be set between the downward sloping stepped region 15s1 and the middle sloping stepped region 15s2, and the second flat region 15f2 can be set between the middle sloping stepped region 15s2 and the upward sloping stepped region 15s3.

[0032] In some embodiments, the upper stepped region 15s4 may have a stepped shape that gradually descends in the first horizontal direction X with a first step SHa and then rises again with a first step SHa. The first step SHa may be substantially equal to the distance between the upper surfaces of a pair of adjacent second layers 19 in the vertical direction Z. In some embodiments, such as Figure 2B As shown, the first step SHa can be equal to the thickness of a pair of first layers 17 and second layers 19 in the vertical direction Z.

[0033] In some embodiments, each of the upper inclined stepped region 15s3, the middle inclined stepped region 15s2, and the lower inclined stepped region 15s1 may have a stepped shape that gradually descends in the first horizontal direction X with a second step SHb greater than the first step SHa. The second step SH2 may be substantially equal to the distance between the upper surface of the uppermost second layer and the lower surface of the lowermost second layer in a plurality of second layers 19 (e.g., five second layers 19) arranged sequentially in the vertical direction Z. In some embodiments, such as Figure 2B As shown, the second step SHb can be equal to the thickness of four pairs of the first layer 17 and the second layer 19 in the vertical direction Z. In some embodiments, such as Figure 2B As shown, the upper stepped region 15s4 may have a first step SHa rising, and the upper inclined stepped region 15s3 may have a second step SHb rising, which is greater than the first step SHa.

[0034] Each of the upper stepped region 15s4, the upper inclined stepped region 15s3, the second flat region 15f2, the middle inclined stepped region 15s2, the first flat region 15f1, and the lower inclined stepped region 15s1 may have the following characteristics: Figure 2D The step shape shown is a step shape that gradually descends or rises with a first step SHa in a second horizontal direction Y perpendicular to the first horizontal direction X.

[0035] The length of at least one of the upwardly inclined stepped region 15s3, the intermediately inclined stepped region 15s2, and the downwardly inclined stepped region 15s1 in the first horizontal direction X may be less than the length of each of the plurality of flat regions 15f1 and 15f2 in the first horizontal direction X.

[0036] A planarization stop layer 21 may be formed on the stacked region 15A1 of the stacked structure 15. The planarization stop layer 21 may be self-aligned with the topmost first layer 17U of the stacked structure 15.

[0037] In some embodiments, the planarization stop layer 21 may be formed of silicon nitride or an alternative material.

[0038] A capping insulating layer 25 can be formed (S10). The capping insulating layer 25 covers the stacked structure 15 and the planarization stop layer 21 on the first region 3a of the substrate 3, and covers the second region 3b of the substrate 3. The capping insulating layer 25 can be formed of, for example, silicon oxide. The capping insulating layer 25 can be formed of silicon oxide or porous silicon oxide with a density lower than that of the silicon oxide of the plurality of first layers 17. For example, the capping insulating layer 25 can be formed of TEOS oxide with a deposition rate or formation rate faster than that of silicon oxide of the plurality of first layers 17 to improve the productivity of semiconductor devices. In some embodiments, the capping insulating layer 25 can be formed of oxide formed using flowable CVD or spin-on glass (SOG). “Element A covers element B” (or similar language) means that element A is on element B, but does not necessarily mean that element A completely covers element B.

[0039] Before forming the capping insulating layer 25, a buffer insulating layer 23 may be formed on the substrate 3 to conformally cover the surface of the planarization stop layer 21 and the stepped region 15A2 of the stacked structure 15. The buffer insulating layer 23 may be formed, for example, from silicon oxide.

[0040] The sealing insulation layer 25 may include a first sealing region 25U1 having a first upper surface, a second sealing region 25U2 having a second upper surface that is horizontally lower than the first upper surface, and a third sealing region 25s1, 25f1, 25s2, 25f2 and 25s3 between the first sealing region 25U1 and the second sealing region 25U2.

[0041] In the capping insulating layer 25, the first capping region 25U1 may overlap with the entire stacked region 15A1 and a portion of the stepped region 15A2. The second capping region 25U2 may overlap with the second region 3b of the substrate 3.

[0042] The upper surface of the first capping region 25U1 may include a first surface 25U1a parallel to the upper surface 3s of the substrate 3 and a second surface 25U1b extending from and bending the first surface 25U1a.

[0043] The third capping regions 25s1, 25f1, 25s2, 25f2 and 25s3 may overlap with the remaining stepped regions 15A2 that do not overlap with the first capping region 25U1, and may overlap with a part of the second region 3b.

[0044] The third capping region (25s1, 25f1, 25s2, 25f2, 25s3) may include one or more flat surfaces 25f1 and 25f2 spaced apart from the first capping region 25U1 and the second capping region 25U2, and inclined surfaces 25s1, 25s2 and 25s3 adjacent to the one or more flat surfaces 25f1 and 25f2.

[0045] In some embodiments, the one or more flat surfaces 25f1 and 25f2 may be formed as a plurality. For example, the plurality of flat surfaces 25f1 and 25f2 may include a first flat surface 25f1 and a second flat surface 25f2 located at different height levels. The inclined surfaces 25s1, 25s2 and 25s3 may include a lower inclined surface 25s1, an intermediate inclined surface 25s2 and a third inclined surface 25s3. Therefore, the third sealing region 25s1, 25f1, 25s2, 25f2 and 25s3 may include a third inclined surface 25s3, a second flat surface 25f2, an intermediate inclined surface 25s2, a first flat surface 25f1 and a lower inclined surface 25s1 sequentially disposed in the first horizontal direction X.

[0046] In some embodiments, substrate 3 may be a semiconductor substrate. However, the inventive concept is not limited thereto, and substrate 3 may be modified to include a structure comprising a plurality of substrates and a circuit region between the plurality of substrates. Reference will be made to... Figure 3 An example describing the deformability of substrate 3.

[0047] In some embodiments, refer to Figure 3 The substrate 3' may include a first substrate 5, circuit regions 7 and 9 on the first substrate 5, and a second substrate 11 on the circuit regions 7 and 9. Circuit regions 7 and 9 may include wiring 7 that can constitute an integrated circuit and a lower insulating layer 9 covering the wiring 7. The first substrate 5 may be a semiconductor substrate. The second substrate 11 may include at least one of silicon and conductive materials. For example, the second substrate 11 may be formed of doped silicon, metal nitrides (e.g., TiN or WN), metal semiconductor compounds (e.g., TiSi, WSi), or metals (e.g., W).

[0048] The following, even if not described, refers to the use of... Figure 2A In the semiconductor substrate formed by substrate 3, the substrate ( Figure 2A 3) can be made from a substrate ( Figure 3 Replace 3' in the middle.

[0049] Return to reference Figure 1A The sealing insulating layer 25 can be patterned to form multiple protrusions (S15). Hereinafter, reference will be made to... Figures 4 to 7 An example of a process (S15) is described by patterning the cover insulation layer 25 to form multiple protrusions.

[0050] Reference Figure 1A and Figure 4 , can Figure 2A A first mask pattern 28 is formed on the sealing insulating layer 25. The first mask pattern 28 may be, for example, a photoresist pattern.

[0051] The first mask pattern 28 can cover the sealing insulating layer 25 (see...) Figure 2A The second sealing area 25U2 and the first inclined surface 25s1.

[0052] In some embodiments, the first mask pattern 28 may cover the sealing insulating layer 25 (see...). Figure 2A The first inclined surface 25s1 and may be covered by a sealing insulation layer 25 (see Figure 2A The first flat surface 25f1 (see) Figure 2A Part of ).

[0053] In an etching process using the first mask pattern 28 as an etching mask, the capping insulating layer 25 can be partially etched to form a first protrusion 25P1 below the first mask pattern 28. Therefore, a capping insulating layer 25a with the first protrusion 25P1 can be formed.

[0054] The first protrusion 25P1 may have the ability to be retained Figure 2A The upper end portion 25f1a is formed by a portion of the first flat surface 25f1 and the first inclined surface 25s1. Figure 2A The remaining portion of the first flat surface 25f1 may be etched to form a first flat surface 25f1b that is horizontally lower than the upper end 25f1a of the first protrusion 25P1. Additionally, the capping insulation layer 25a may have a height lower than the capping insulation layer 25( Figure 2A The first capping region 25U1', the third inclined surface 25s3', the second flat surface 25f2', and the intermediate inclined surface 25s2' are defined in the middle. The first capping region 25U1' may include a first surface 25U1a' and a second surface 25U1b' with a lower height.

[0055] Reference Figure 1A and Figure 5 The first mask pattern 28 can be selectively removed (see...). Figure 4 ). Can be used in the form of a first protrusion 25P1 Figure 4A second mask pattern 31 is formed on the capping insulating layer 25a. The second mask pattern 31 may be, for example, a photoresist pattern. "Selective removal of element A" (or similar language) means that element A is removed much faster than other elements. For example, the removal rate of element A may be at least 5 times (e.g., about 10 times, 15 times, or 20 times) that of other elements.

[0056] The second mask pattern 31 can cover the sealing insulation layer 25a (see...) Figure 4 The second sealing area 25U2, the first protrusion 25P1, the first flat surface 25f1b and the intermediate inclined surface 25s2'.

[0057] In some embodiments, the second mask pattern 31 may cover Figure 4 The middle inclined surface 25s2' of the capping insulation layer 25a, and can cover the capping insulation layer 25a (see Figure 4 The second flat surface 25f2' (see) Figure 4 Part of ).

[0058] In the etching process using the second mask pattern 31 as the etching mask, Figure 4 The capping insulating layer 25a can be partially etched to form a second protrusion 25P2 below the second mask pattern 31. Thus, a capping insulating layer 25b having a first protrusion 25P1 and a second protrusion 25P2 can be formed.

[0059] The second protrusion 25P2 may have a centrally inclined surface 25s2' and by retaining Figure 4 The upper end portion 25f2a is formed as a part of the second flat surface 25f2'. Figure 4 The remaining portion of 25f2' can be etched to form a second flat surface 25f2b that is horizontally lower than the upper end 25f2a of the second protrusion 25P2.

[0060] Additionally, the sealing insulation layer 25b may include a height lower than Figure 4 The third inclined surface 25s3” of the sealing insulation layer 25a and the first sealing region 25U1”. The first sealing region 25U1” may include a first surface 25U1a” and a second surface 25U1b with a relatively lower height.

[0061] The first protrusion 25P1 and the second protrusion 25P2 may be spaced apart from each other in the first horizontal direction X.

[0062] The first protrusion 25P1 and the second protrusion 25P2 may be formed on the stepped region 15A2 of the laminated structure 15. The first protrusion 25P1 and the second protrusion 25P2 may overlap with the stepped region 15A2 of the laminated structure 15.

[0063] Reference Figure 1A and Figure 6 Selective removal Figure 5 The second mask pattern 31. It can be used in a design with a first protrusion 25P1 and a second protrusion 25P2. Figure 5 A third mask pattern 33 is formed on the sealing insulating layer 25b. The third mask pattern 33 can be, for example, a photoresist pattern.

[0064] The third mask pattern 33 can cover the sealing insulation layer 25b (see...) Figure 5 The second capping region 25U2, the first protrusion 25P1, the first flat surface 25f1b, the second protrusion 25P2, the third inclined surface 25s3”, and a portion of the first capping region 25U1”.

[0065] In the etching process using the third mask pattern 33 as the etching mask, Figure 5 The capping insulating layer 25b is partially etched to form a third protrusion 25P3 below the third mask pattern 33. Thus, a capping insulating layer 25c having the first to third protrusions 25P1, 25P2 and 25P3 can be formed.

[0066] At least one of the first to third protrusions 25P1, 25P2, and 25P3 includes sides that are opposite each other and have different angles, and the side closer to the stacked region 15A1 among the sides with different angles may be steeper than the side farther from the stacked region 15A1. In some embodiments, each of the first to third protrusions 25P1, 25P2, and 25P3 may include opposite sides, and one of the opposite sides that is closer to the stacked region 15A1 may be perpendicular to the upper surface 3s of the substrate 3, such as... Figure 6 As shown. In some embodiments, the first flat surface 25f1b between the first protrusion 25P1 and the second protrusion 25P2 and the second flat surface 25f2b between the second protrusion 25P2 and the third protrusion 25P3 may be at the same level, as shown. Figure 6 As shown.

[0067] The third protrusion 25P3 may have the characteristics of... Figure 5 The remaining portion of the first sealing region 25U1” forms the upper end and the third inclined surface 25s3”. In the third protrusion 25P3, when the first sealing region ( Figure 5 When a portion of 25U1” is retained, the upper end formed may include a portion of the first surface 25U1a” and the second surface 25U1b”.

[0068] Reference Figure 1A and Figure 7 Selective removal Figure 6The third mask pattern 33. Therefore, a capping insulating layer 25c with first to third protrusions 25P1, 25P2 and 25P3 can be formed.

[0069] The first to third protrusions 25P1, 25P2 and 25P3 may be spaced apart from each other in the first horizontal direction X.

[0070] At the same height level, the length of any one of the first to third protrusions 25P1, 25P2, and 25P3 in the first horizontal direction X may be greater than the length of the remaining protrusions in the first horizontal direction X. For example, at the same height level, the length of the third protrusion 25P3 in the first horizontal direction X may be greater than the length of each of the first protrusion 25P1 and the second protrusion 25P2 in the first horizontal direction X.

[0071] Although the formation of three protrusions (e.g., the first to third protrusions 25P1, 25P2, and 25P3) has been described, the inventive concept is not limited thereto. For example, according to embodiments thereof, only two of the first to third protrusions 25P1, 25P2, and 25P3 may be formed.

[0072] In some embodiments, four or more protrusions may be formed depending on the step shape of the stacked structure 15. For example, in reference Figure 2A When the number of flat regions 15f1 and 15f2 in the described laminated structure 15 is increased, the number of protrusions in the capping insulation layer 25c can be increased.

[0073] Reference Figure 1A and Figure 8 The capping insulation layer with multiple protrusions can be planarized using a chemical mechanical polishing process (S20). Therefore, a planarized capping insulation layer 25d can be formed. In this case, the multiple protrusions can be... Figure 7 The first to third protrusions 25P1, 25P2, and 25P3. When the planarized capping insulation layer 25d is formed, it can be removed. Figure 7 The first to third processes are 25P1, 25P2 and 25P3.

[0074] The planarized sealing insulation layer 25d can be formed to have an upper surface 25dU located at a higher level than the upper surface of the planarization stop layer 21.

[0075] Reference Figure 1A , Figure 9A and Figure 9B This can flatten the sealing insulation layer ( Figure 8Partial etching (S25) is performed on the 25d portion. Thus, a partially etched capping insulating layer 25e can be formed. The upper surface 25eU of the partially etched capping insulating layer 25e can be located at a lower level than the upper surface of the planarization stop layer 21, and can be located at a higher level than the lower surface of the planarization stop layer 21. As used herein, "surface A is lower than surface B" (or similar language) means that the distance from the upper surface 3s of the substrate 3 to surface A in the vertical direction Z is shorter than the distance from the upper surface 3s of the substrate 3 to surface B in the vertical direction Z.

[0076] In some embodiments, a partially etched planarized capping insulation layer ( Figure 8 At the same time as 25d), refer to the above. Figures 2B to 2D The described buffer insulation layer 23 can also be partially etched.

[0077] Planarized sealing insulation layer ( Figure 8 25d) and buffer insulation layer ( Figures 2B to 2D The etching rates of 23) can be substantially the same or similar. For example, Figure 8 The planarized sealing insulation layer 25d and Figures 2B to 2D The buffer insulating layer 23 can be partially etched in a dry etching process. The partially etched buffer insulating layer 23 and the partially etched capping insulating layer 25e can have continuously extending top surfaces, such as... Figure 9B As shown.

[0078] In some embodiments, etching processes (e.g., wet etching processes) with different etching rates can be used to partially etch the material. Figure 8 The planarized sealing insulation layer 25d and the buffer insulation layer 23. Therefore, refer to Figure 9C Describes the partial etching of a planarized capping insulation layer using etching processes with different etching rates (e.g., wet etching processes). Figure 8 Examples of 25d) and buffer insulation layer 23.

[0079] Reference Figure 9C It can be used for Figure 8 The planarized sealing insulation layer 25d and Figures 2B to 2D The buffer insulating layer 23 is partially etched using an etching process with different etching rates (e.g., using a wet etching process). Figure 8 The planarized sealing insulation layer 25d and Figures 2B to 2D The buffer insulating layer 23. Therefore, the upper surface of the partially etched buffer insulating layer 23' can be formed at a lower level than the upper surface of the partially etched capping insulating layer 25e.

[0080] The following, such as Figure 9B The description will primarily focus on the use of a planarized sealing insulation layer ( Figure 8 25d in the middle) and buffer insulation layer ( Figures 2B to 2D (23) Etching processes with substantially the same or similar etch rates partially etch the planarized capping insulation layer. Figure 8 25d) and buffer insulation layer ( Figures 2B to 2D The partially etched buffer insulation layer 23 and the partially etched capping insulation layer 25e are formed by 23).

[0081] Reference Figure 1A , Figure 10A and Figure 10B Selectively remove the planarization stop layer ( Figure 9A and Figure 9B 21). Annealing process 35 (S35) can be performed.

[0082] For example, the annealing process 35 can be performed at a temperature of about 500°C to about 850°C.

[0083] For example, an annealing process 35 can be performed for approximately 30 minutes to 2 hours.

[0084] Annealing process 35 can increase the partially etched sealing insulation layer. Figure 9A and Figure 9B The density of 25e) is increased to form a dense capping insulating layer 25f. Annealing process 35 can reduce the etched capping insulating layer (…). Figure 9A and Figure 9B The volume of 25e in the middle.

[0085] For ease of description, the term "capping insulation" will be used below to describe the dense capping insulation 25f.

[0086] Through annealing process 35, the upper surface 25fU of the sealing insulation layer 25f can be formed to have a first surface 25fU1 and a second surface 25fU2 at a level lower than the first surface 25fU1.

[0087] The uppermost 25fUa of the first surface 25fU1 is higher than the uppermost surface of the first layer 17U of the stacked structure 15 by a first height H1.

[0088] For example, the first height H1 can be less than Figure 2B The thickness of each of the multiple second layers 19.

[0089] The second surface 25fU2 of the upper surface 25fU of the sealing insulation layer 25f can be formed to have a height level that is substantially the same as the upper surface of the uppermost first layer 17U.

[0090] On the upper surface 25fU of the sealing insulation layer 25f, the first surface 25fU1 may include an upper portion 25fUa, an upper inclined portion 25fs3, an upper flat portion 25ff2, a middle inclined portion 25fs2, a lower flat portion 25ff1 and a lower inclined portion 25fs1 arranged sequentially in the first horizontal direction X.

[0091] In some embodiments, the lower flat portion 25ff1 may be formed at a lower level than the upper flat portion 25ff2.

[0092] In some embodiments, the buffer insulation layer 23 disposed between the laminated structure 15 and the capping insulation layer 25f may extend on the side of the capping insulation layer 25f disposed at a level higher than the laminated structure 15.

[0093] In some embodiments, refer to Figure 10C The upper surface of the buffer insulation layer 23' disposed between the laminated structure 15 and the capping insulation layer 25f can be formed at a level lower than the first uppermost layer 17U of the laminated structure 15.

[0094] Reference Figure 1B , Figure 11A and Figure 11B A first upper insulating layer 36 may be formed on the laminated structure 15 and the capping insulating layer 25f. The first upper insulating layer 36 may be formed of silicon oxide.

[0095] A channel hole 38 (S40) can be formed. The channel hole 38 can penetrate the first upper insulating layer 36 and the laminated structure 15.

[0096] The vertical memory structure 39 may include a core region 49, a pad pattern 51 on the upper surface of the core region 49, a channel semiconductor layer 47 covering the side and lower surfaces of the core region 49 and in contact with the pad pattern 51, and a dielectric structure 42 surrounding the outer surface of the channel semiconductor layer 47.

[0097] The dielectric structure 42 may include a first dielectric layer 44, a second dielectric layer 46, and a data storage layer 45 disposed between the first dielectric layer 44 and the second dielectric layer 46. The first dielectric layer 44 may be disposed between the data storage layer 45 and the stacked structure 15, and the second dielectric layer 46 may be disposed between the data storage layer 45 and the channel semiconductor layer 47. The data storage layer 45 may be a charge trapping layer formed of silicon nitride or the like. The data storage layer 45 may include regions capable of storing data in a semiconductor device such as a vertical NAND flash memory device.

[0098] Reference Figure 1B , Figure 12A , Figure 12B and Figure 12CA second upper insulating layer 53 may be formed on the first upper insulating layer 36. A separation trench 56 (S50) may be formed.

[0099] The stacked structure exposed through the separation trench 56 can be replaced by gate layer 59. Figure 11B The second layer of 15) Figure 11B (S55). Therefore, a stacked structure 15' including multiple first layers 17 and gate layers 59 can be formed.

[0100] Each gate layer 59 may include a first material layer 59a and a second material layer 59b. The first material layer 59a may cover the upper and lower surfaces of the second material layer 59b and may extend between the second material layer 59b and the vertical memory structure 39.

[0101] In some embodiments, the first material layer 59a may be formed of a first conductive type material (e.g., TiN, etc.), and the second material layer 59b may be formed of a second conductive type material (e.g., W, etc.) that is different from the first conductive type material.

[0102] In some embodiments, the first material layer 59a may be formed of an insulating material, and the second material layer 59b may be formed of a conductive material.

[0103] A separation structure 60 (S60) can be formed in the separation trench 56.

[0104] In some embodiments, the separation structure 60 may be formed of an insulating material.

[0105] In some embodiments, the separation structure 60 may be formed of multiple material layers (e.g., a conductive material layer and an insulating material layer surrounding the sides of the conductive material layer).

[0106] A third upper insulating layer 62 may be formed on the second upper insulating layer 53.

[0107] On the stacked region 15A1 of the stacked structure 15', a third upper insulating layer 62 and a bit line contact plug 67 that penetrates the second upper insulating layer 53 and is electrically connected to the vertical memory structure 39 can be formed.

[0108] On the stepped region 15A2 of the stacked structure 15', a third upper insulating layer 62, a second upper insulating layer 53, a first upper insulating layer 36, and a gate contact plug 65 that penetrates the capping insulating layer 25f and is electrically connected to the gate layer 59 (see [link]). Figure 12C Based on the location where the stacked structure 15' is cut, Figure 12C The gate contact plug 65 can be as follows Figure 12C As shown, it can be observed in cross-section, or as can be seen in cross-section. Figure 12A As shown in the cross-section, it is not displayed.

[0109] You can refer to the above. Figures 1A to 12C The described method forms a semiconductor device. The semiconductor device thus formed can be configured to have, for example, […]. Figures 12A to 12C The structure is shown. In some embodiments, the semiconductor device formed by the method of forming a semiconductor device according to an embodiment of the present invention may include a stacked structure 15' having a stacked region 15A1 and a stepped region 15A2, and as shown in reference... Figure 10A and Figure 10B The buffer insulating layer 23 and the capping insulating layer 25f are described. In some embodiments, the semiconductor device may include, as referenced... Figure 10C The described buffer insulation layer 23'. Therefore, as referenced above. Figures 1A to 12C The semiconductor device described above may include those referenced above. Figures 1A to 12C The components formed by the method described in this paper are semiconductor devices. Therefore, a detailed description of the structure of the semiconductor device will be omitted here.

[0110] Next, we will refer to Figures 13A to 15B Methods for forming semiconductor devices according to some embodiments of the present invention are described. Figure 13A , Figure 14A and Figure 15A It is a cross-sectional view taken along a first horizontal direction to show a method of forming a semiconductor device according to an example embodiment. Figure 13B It is shown Figure 13A An enlarged cross-sectional view of the upper surface of the lower sealing insulation layer. Figure 13C This is an enlarged cross-sectional view showing the lower stacked structure. Figure 14B yes Figure 14A A magnified cross-sectional view of a portion of the image. Figure 15B It is a cut along the second horizontal direction by Figure 15A An enlarged cross-sectional view of the portion indicated by line B2-B2'.

[0111] Reference Figure 13A , Figure 13B and Figure 13C A substrate 103 can be prepared. The substrate 103 can be a reference. Figure 2A Substrate 3 as described (see Figure 2A (or you can refer to the above.) Figure 3 The substrate 3' described (see Figure 3 ).

[0112] A lower stack structure 115 may be formed on a first region 103a of substrate 103. The lower stack structure 115 may include a plurality of first lower layers 117 and a plurality of second lower layers 119 alternately stacked. The plurality of first lower layers 117 and the plurality of second lower layers 119 may respectively correspond to references. Figures 2B to 2D The description of multiple first layers ( Figures 2B to 2D 17) and multiple second layers ( Figures 2B to 2D (19). Therefore, the topmost layer 117U among the plurality of first lower layers 117 and the plurality of second lower layers 119 can be the first lower layer 117.

[0113] The lower stack-up structure 115 may include stepped regions 115s1, 115f1, 115s2, 115f2, and 115s3. In the lower stack-up structure 115, the regions other than the stepped regions 115s1, 115f1, 115s2, 115f2, and 115s3 may be defined as stack-up regions. The stepped regions 115s1, 115f1, 115s2, 115f2, and 115s3 of the lower stack-up structure 115 may include a first downwardly inclined stepped region 115s3, a first downwardly flat region 115f2, a second downwardly inclined stepped region 115s2, a second downwardly flat region 115f1, and a third downwardly inclined stepped region 115s1, sequentially arranged in a first horizontal direction X parallel to the upper surface of the substrate 103.

[0114] The first downward-sloping step region 115s3 can be formed at a level higher than the second downward-sloping step region 115s2, and the second downward-sloping step region 115s2 can be formed at a level higher than the third downward-sloping step region 115s1. The first downward-flat region 115f2 can be formed at a level higher than the second downward-flat region 115f1.

[0115] Subsequently, executable and reference Figures 1A to 10B The described process is substantially the same as the process for forming the lower cap insulation layer 125f. For example, forming the lower cap insulation layer 125f may include processes such as... Figures 2A to 2D As shown, a planarization stop layer is formed on the lower stacked structure 115. Figures 2A to 2C The process of 21) to the reference Figure 10A The described annealing process ( Figure 10A The various processes of 35). Therefore, the lower cover insulation layer 125f may include an upper surface 125U having a first surface 125fU1 that is higher than the upper surface of the uppermost layer 117U and a second surface 125fU2 that is at a level lower than the first surface 125fU1.

[0116] The lower capping insulating layer 125f can cover the stepped regions 115s1, 115f1, 115s2, 115f2 and 115s3 of the lower stacked structure 115 and the second region 103b of the substrate 103 on which the lower stacked structure 115 is not formed.

[0117] In the upper surface 125U of the lower cover insulation layer 125f, the first surface 125fU1 may include a first upper inclined portion 125fs3, a first upper flat portion 125ff2, a first middle inclined portion 125fs2, a first lower flat portion 125ff1 and a first lower inclined portion 125fs1 arranged sequentially in the first horizontal direction X.

[0118] In some embodiments, the first lower flat portion 125ff1 may be formed at a lower level than the first upper flat portion 125ff2.

[0119] In some embodiments, the first upper inclined portion 125fs3 may be formed at a level higher than the first middle inclined portion 125fs2, and the first middle inclined portion 125fs2 may be formed at a level higher than the first lower inclined portion 125fs1.

[0120] In some embodiments, a buffer insulating layer 123 may be formed between the lower cap insulating layer 125f and the lower laminate structure 115. In some embodiments, such as Figure 13B As shown, the upper surface of the uppermost layer 117U is at a lower distance H1a than the uppermost end of the first surface 125fU1.

[0121] Reference Figure 14A and Figure 14B It can form a sacrificial vertical structure 139 that penetrates part of the lower stacked structure 115.

[0122] An upper stacked structure 215 can be formed on the lower stacked structure 115. A stacked structure 214 can be formed, which includes the sequentially stacked lower stacked structure 115 and the upper stacked structure 215.

[0123] The upper stacked structure 215 may be formed on the first surface 115U1 of the upper surface of the lower stacked structure 115, and the second surface 115U2 of the upper surface of the lower stacked structure 115 may be exposed.

[0124] The upper stacked structure 215 may include structures corresponding to... Figures 2B to 2D Multiple first-layer (described in) Figures 2B to 2D 17) and multiple second layers ( Figures 2B to 2D (19) Multiple first upper layers 217 and multiple second upper layers. The uppermost layer 217U of the upper stack structure 215 can be the first upper layer 217.

[0125] The stepped regions 215s4, 215s3, 215f2, 215s2, 215f1, and 215s1 of the upper stacked structure 215 may include a second upper stepped region 215s4, a second upper inclined stepped region 215s3, a second upper flat region 215f2, a second intermediate inclined stepped region 215s2, a second lower flat region 215f1, and a second lower inclined stepped region 215s1 arranged in the first horizontal direction X. In the upper stacked structure 215, the region other than the stepped regions 215s4, 215s3, 215f2, 215s2, 215f1, and 215s1 can be defined as a stacked region.

[0126] The stacked structure 214 may include a stacked region 214A1 and a stepped region 214A2 adjacent to the stacked region 214A1. The stepped regions of the lower stacked structure 115 and the upper stacked structure 215 may be formed on the stepped region 214A2 of the stacked structure 214.

[0127] Subsequently, executable and reference Figures 1A to 10B The described processes are substantially the same or similar to those used to form the upper capping insulation layer 225f. For example, forming the upper capping insulation layer 225f may include performing processes such as... Figures 2A to 2D As shown, a planarization stop layer is formed on the upper stacked structure 215. Figures 2A to 2C The process of 21) in the middle is referenced. Figure 10A The described annealing process ( Figure 10A (35 in the middle). Therefore, the upper cover insulation layer 225f may include an upper surface having a first surface 225fU1 that is higher than the upper surface of the uppermost layer 217U and a second surface 225fU2 that is at a level lower than the first surface 225fU1.

[0128] The upper cover insulation layer 225f can cover the stepped regions 215s4, 215s3, 215f2, 215s2, 215f1 and 215s1 of the upper stacked structure 215, and can also cover the upper surface of the lower stacked structure 115 on which the upper stacked structure 215 is not formed and the lower cover insulation layer 125f.

[0129] The upper surface of the upper sealing insulation layer 225f may have a first surface 225fU1 and a second surface 225fU2 below the first surface 225fU1.

[0130] In the upper surface 225U of the upper cover insulation layer 225f, the first surface 225fU1 may include an upper portion 225fUa, a second upper inclined portion 225fs3, a second upper flat portion 225ff2, a second middle inclined portion 225fs2, a second lower flat portion 225ff1 and a second lower inclined portion 225fs1 arranged sequentially in the first horizontal direction X.

[0131] In some embodiments, the second lower flat portion 225ff1 may be formed at a lower level than the second upper flat portion 225ff2.

[0132] In some embodiments, the second upper inclined portion 225fs3 may be formed at a level higher than the second middle inclined portion 225fs2, and the second middle inclined portion 225fs2 may be formed at a level higher than the second lower inclined portion 225fs1.

[0133] Reference Figure 15A and Figure 15B , can Figure 14A A first upper insulating layer 236 is formed on the upper stacked structure 215. The upper channel hole 238U can be formed as a through-hole. Figure 14A The first upper insulating layer 236 and the upper laminate structure 215 are exposed Figure 14A The sacrifice of the vertical structure 139. Exposed Figure 14A The sacrificial vertical structure 139 can be removed to form the lower channel hole 238L.

[0134] A vertical memory structure 239 may be formed in the upper channel hole 238U and the lower channel hole 238L. The vertical memory structure 239 may include an upper vertical memory structure 239U in the upper channel hole 238U and a lower vertical memory structure 239L in the lower channel hole 238L.

[0135] Vertical memory structure 239 may include references Figure 12B The vertical memory structure 239 described has the same or similar components, and for example, the vertical memory structure 239 may include a core region 49, a pad pattern 51, a dielectric structure 42, and a channel semiconductor layer 47.

[0136] A second upper insulating layer 253 may be formed on the first upper insulating layer 236. A structure penetrating the second upper insulating layer 253, the first upper insulating layer 236, and the laminated structure 214 (see [link to documentation]) may be formed. Figure 14A ) separation groove 256.

[0137] Figure 14A The stacked structure 214 may include reference to Figures 2B to 2D The description of multiple second layers ( Figures 2B to 2D The second layer corresponding to 19), and the separation trench 256 can be exposed to... Figures 2B to 2D The multiple second layers of the stacked structure 214 described in the text ( Figures 2B to 2D The second layer corresponding to 19). These exposed second layers can be replaced with gate layer 259. Gate layer 259 can be compared with reference to Figure 12B The gate layer described ( Figure 12B 59) are the same or similar.

[0138] A separation structure 260 can be formed to fill the separation trench 256. Subsequently, a third upper insulating layer 262 can be formed on the second upper insulating layer 253. A bit line contact plug 267 can be formed to penetrate the third upper insulating layer 262 and the second upper insulating layer 253. A bit line 270 can be formed on the bit line contact plug 267.

[0139] You can refer to the above. Figures 13A to 15B The described method forms a semiconductor device. The semiconductor device thus formed can be configured to have, for example, […]. Figure 15A and Figure 15B The structure is shown. For example, a semiconductor device formed by a method of forming a semiconductor device according to an exemplary embodiment of the present invention may include a stacked structure 215' and as shown in reference... Figure 13B and Figure 14B The lower cover insulation layer 125f and the upper cover insulation layer 225f are described. Therefore, as referred to above... Figures 13A to 15B In the described method, the semiconductor device may include those described above. Figures 13A to 15B The described method for forming a semiconductor device forms an assembly. Therefore, it can be described with reference to... Figures 13A to 15B The method for forming a semiconductor device is described, and therefore, a detailed description of the structure of the semiconductor device will be omitted herein.

[0140] According to the example embodiment, a stepped region is formed ( Figure 2A The 15A2) layered structure forms a capping insulation layer ( Figure 2A 25) to cover the stacked structure ( Figure 2A The stepped area of ​​(15) is covered with an insulating layer. Figure 2A 25) is patterned to form protrusions that overlap with the stepped areas and are spaced apart from each other in the horizontal direction. Figure 7 25P1, 25P2 and 25P3), with protrusions ( Figure 7 The sealing insulation layer of 25P1, 25P2 and 25P3) Figure 7 25c) is planarized, the planarized cover insulation layer ( Figure 8 The 25d section was partially etched and then subjected to an annealing process. Figure 10A 35) causes partial etching of the sealing insulation layer ( Figure 9A The 25e) is dense, thus forming a dense capping insulation layer ( Figure 10A 25f). This forms a dense sealing insulation layer ( Figure 10A The method of 25f) can be used to form Figure 13A The lower cover insulation layer 115f and Figure 14A The upper sealing insulation layer is 215f.

[0141] According to an example embodiment, a dense capping insulation layer is formed ( Figure 10AIn the method of 25f), due to the formation in the stacked structure 15 (see 25f), Figure 2A The dense capping insulation layer 25f on the stepped area 15A2 (see) Figure 10A The flatness of the semiconductor can be improved, thus improving the productivity of semiconductor devices.

[0142] As described above, according to the example embodiment, a method can be provided that improves the flatness of the capping insulating layer covering the stepped regions of a stacked structure. The integration density of a semiconductor device formed using this method can be improved, and the productivity of the semiconductor device can be improved.

[0143] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims. The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the true spirit and scope of the inventive concept.

Claims

1. A method for forming a semiconductor device, the method comprising: A stacked structure and a planarization stop layer are formed on a first region of a substrate. The stacked structure includes a stacked region and a stepped region. The stacked region includes a flat upper surface. The stepped region is adjacent to the stacked region and includes an upper surface having a stepped shape. The stacked structure includes a plurality of first layers and a plurality of second layers that are alternately stacked with the plurality of first layers in a vertical direction perpendicular to the upper surface of the substrate. The uppermost layer of the stacked structure is the uppermost of the plurality of first layers, and the stacked structure is located between the substrate and the planarization stop layer. A capping insulating layer is formed on the planarization stop layer and the stacked structure, and on a second region of the substrate adjacent to a first region of the substrate. The capping insulating layer includes a first capping region and a second capping region. The first capping region includes a first upper surface, and the second capping region includes a second upper surface at a level lower than the first upper surface. The sealing insulating layer is patterned to form a plurality of protrusions spaced apart from each other in a horizontal direction on a first region of the substrate, the horizontal direction being parallel to the upper surface of the substrate, and at least one of the plurality of protrusions overlapping the stepped region. The capping insulation layer, including the plurality of protrusions, is planarized to form a planarized capping insulation layer; The planarized capping insulation layer is partially etched to form a partially etched capping insulation layer; An annealing process is performed to convert the partially etched capping insulation layer into a dense capping insulation layer; A first upper insulating layer is formed on the dense capping insulating layer and the uppermost layer of the laminated structure; Forming a channel hole that extends through the stacked region of the first upper insulating layer and the stacked structure; A vertical memory structure is formed in the channel hole; Contact plugs are formed on the vertical memory structure; as well as Bit lines are formed on the contact plug. The patterning of the sealing insulation layer includes: A first etching process is performed using a first etch mask to form a first protrusion, and After performing the first etching process, a second etching process is performed using a second etching mask to form a second protrusion, wherein the edge of the first etching mask is spaced apart from the interface between the stacked region and the stepped region in the horizontal direction by a first distance, and the edge of the second etching mask is spaced apart from the interface between the stacked region and the stepped region in the horizontal direction by a second distance shorter than the first distance.

2. The method according to claim 1, further comprising: After forming the partially etched capping insulating layer, and before the annealing process, the planarization stop layer is removed to expose the top layer of the stacked structure.

3. The method according to claim 1, wherein, The stepped region of the stacked structure includes at least one flat region and at least one inclined stepped region adjacent to the at least one flat region.

4. The method according to claim 3, wherein, One of the plurality of protrusions overlaps with the at least one inclined stepped region.

5. The method according to claim 1, wherein, During the planarization of the sealing insulation layer, at least a portion of each of the plurality of protrusions is removed.

6. The method according to claim 1, wherein, The upper surface of the dense capping layer includes a first surface and a second surface at a level lower than the first surface, and The uppermost point of the first surface is a first height higher than the uppermost surface of the stacked structure.

7. The method according to claim 6, wherein, The first height is less than the thickness of each of the plurality of second layers.

8. The method according to claim 1, further comprising: A second upper insulating layer is formed on the vertical memory structure and the first upper insulating layer; Forming separation trenches that extend through the second upper insulating layer, the first upper insulating layer, and the laminated structure and expose the plurality of second layers of the laminated structure; The plurality of second layers exposed through the separation trench are replaced with a plurality of gate layers respectively; as well as A separation structure is formed in the separation trench. Each of the plurality of first layers is formed of an insulating material.

9. The method according to claim 1, wherein, The partially etched capping insulation layer includes the upper surface at a horizontal position between the lower surface of the planarization stop layer and the upper surface of the planarization stop layer.

10. The method according to claim 1, wherein, The volume of the partially etched capping insulation layer is reduced by performing the annealing process.

11. The method according to claim 1, wherein, The annealing process is carried out at a temperature of 500°C to 850°C for 30 minutes to 2 hours.

12. A method of forming a semiconductor device, the method comprising: A first stacked structure is formed on a first region of a substrate. The first stacked structure includes a first stacked region and a first stepped region adjacent to the first stacked region. The first stacked structure includes a plurality of first layers and a plurality of second layers that are alternately stacked with the plurality of first layers in a vertical direction perpendicular to the upper surface of the substrate. The plurality of second layers are arranged in a stepped shape in the first stepped region. A first capping insulating layer is formed on a first stacked structure on a first region of the substrate and on a second region of the substrate adjacent to the first region of the substrate. The first capping insulating layer includes a first capping region and a second capping region. The first capping region includes a first upper surface, and the second capping region includes a second upper surface at a level lower than the first upper surface. The first capping insulating layer is patterned to form a plurality of first protrusions spaced apart from each other in a horizontal direction on a first region of the substrate, the horizontal direction being parallel to the upper surface of the substrate, and at least one of the plurality of first protrusions overlapping the first stepped region. as well as The first capping insulation layer, including the plurality of first protrusions, is planarized. The patterning of the first sealing insulating layer includes: A first etching process is performed using a first etch mask to form one of the plurality of first protrusions, and After performing the first etching process, a second etching process is performed using a second etching mask to form another of the plurality of first protrusions, wherein the edge of the first etching mask is spaced apart from the interface between the first stacked region and the first stepped region in the horizontal direction by a first distance, and the edge of the second etching mask is spaced apart from the interface between the first stacked region and the first stepped region in the horizontal direction by a second distance shorter than the first distance.

13. The method of claim 12, further comprising: After planarizing the first capping insulation layer, a first annealing process is performed to increase the density of the first capping insulation layer by reducing its volume.

14. The method of claim 13, further comprising: After the first annealing process A second stacked structure is formed on the first stacked structure. The second stacked structure includes a second stacked region and a second stepped region adjacent to the second stacked region. The second stacked structure includes a plurality of first upper layers and a plurality of second upper layers that are alternately stacked with the plurality of first upper layers in the vertical direction. The plurality of second upper layers are arranged in a stepped shape in the second stepped region. A second capping insulation layer is formed on the second laminated structure and on the first capping insulation layer; The second capping insulating layer is patterned to form a plurality of second protrusions spaced apart from each other in the horizontal direction, at least one of the plurality of second protrusions overlapping the second stepped region; as well as The second capping insulation layer, including the plurality of second protrusions, is planarized.

15. The method of claim 14, further comprising: After planarizing the second capping insulation layer, a second annealing process is performed to increase the density of the second capping insulation layer by reducing its volume.

16. The method of claim 14, further comprising: After the second capping insulating layer is planarized, a vertical memory structure is formed that extends through the second stacked structure and the first stacked structure.

17. A method of forming a semiconductor device, the method comprising: A stacked structure is formed on a first region of a substrate. The stacked structure includes a stacked region and a stepped region adjacent to the stacked region, and includes a plurality of first layers and a plurality of second layers that are alternately stacked with the plurality of first layers in a vertical direction perpendicular to the upper surface of the substrate. The plurality of second layers are arranged in a stepped shape in the stepped region, and the stepped region of the stacked structure includes at least one flat region and at least one inclined stepped region adjacent to the at least one flat region. A capping insulating layer is formed on the laminated structure and on a second region of the substrate adjacent to a first region of the substrate. The capping insulating layer includes a first capping region and a second capping region. The first capping region includes a first upper surface, and the second capping region includes a second upper surface at a level lower than the first upper surface. The sealing insulating layer is patterned to form a plurality of protrusions spaced apart from each other in a horizontal direction on a first region of the substrate, the horizontal direction being parallel to the upper surface of the substrate, and at least one of the plurality of protrusions overlapping the stepped region. as well as The sealing insulation layer, including the plurality of protrusions, is planarized. The patterning of the sealing insulation layer includes: A first etching process is performed using a first etch mask to form a first protrusion, and After performing the first etching process, a second etching process is performed using a second etching mask to form a second protrusion, wherein the edge of the first etching mask is spaced apart from the interface between the stacked region and the stepped region in the horizontal direction by a first distance, and the edge of the second etching mask is spaced apart from the interface between the stacked region and the stepped region in the horizontal direction by a second distance shorter than the first distance.

18. The method according to claim 17, wherein, At least one of the plurality of protrusions includes opposing sides with different inclination angles, and the first side of the opposing sides that is closer to the stacked region is steeper than the second side that is opposite to the first side.

Images