Semiconductor device including vertical memory structure

Abstract

A semiconductor device is disclosed, comprising: a first stacked structure and a second stacked structure spaced apart from each other on a substrate; and a plurality of discrete structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure along a first direction parallel to the upper surface of the substrate. Each of the first stacked structure and the second stacked structure includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on a lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. The side surfaces of the first stacked structure and the second stacked structure facing the vertical memory structures are concave in a plan view.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0142089, filed with the Korean Intellectual Property Office on November 7, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor device, and more specifically, to a semiconductor device having a vertical storage structure and a method for forming the same. Background Technology

[0004] The need to improve the integration of semiconductor devices to increase product price competitiveness is growing. To improve the integration of semiconductor devices, a three-dimensional array of memory cells has been proposed instead of a two-dimensional array of memory cells. Summary of the Invention

[0005] Exemplary embodiments of the present invention provide semiconductor devices that can improve integration and methods for forming such semiconductor devices.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes a lower structure and a plurality of discrete structures disposed on the lower structure and spaced apart from each other in a first direction parallel to the upper surface of the lower structure. A vertical memory structure is disposed between adjacent discrete structures of the plurality of discrete structures. The vertical memory structure includes a core region, a channel semiconductor structure, and a data storage structure. A stacked structure is disposed on the lower structure. The stacked structure includes a first stacked structure and a second stacked structure, which are spaced apart from each other in a second direction by the plurality of discrete structures and the vertical memory structure. The second direction is parallel to the upper surface of the lower structure and perpendicular to the first direction. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the lower structure. The channel semiconductor structure includes a first channel semiconductor layer disposed along the second direction between the core region and the first stacked structure, and a second channel semiconductor layer disposed along the second direction between the core region and the second stacked structure. The data storage structure includes: a first data storage structure disposed along the second direction between the first stacked structure and the first channel semiconductor layer; and a second data storage structure disposed along the second direction between the second stacked structure and the second channel semiconductor layer. Each of the first data storage structure and the second data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer disposed between the first dielectric layer and the second dielectric layer; and the side surfaces of the first stacked structure and the second stacked structure facing the vertical storage structure are concave in a first plan view defined by the first direction and the second direction.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes a first stacked structure and a second stacked structure disposed on a substrate. The first stacked structure and the second stacked structure are spaced apart from each other in a first direction parallel to the upper surface of the substrate. A plurality of discrete structures and a plurality of vertical memory structures are alternately arranged between the first stacked structure and the second stacked structure in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction. Each of the first stacked structure and the second stacked structure includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the substrate. Each of the plurality of vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. The side surfaces of the first stacked structure and the second stacked structure facing the plurality of vertical memory structures are concave in a first planar view defined by the first direction and the second direction.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes a first stacked structure and a second stacked structure disposed on a substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the substrate. A plurality of vertical memory structures are disposed between the first and second stacked structures and arranged along a first direction parallel to the upper surface of the substrate. Each of the plurality of vertical memory structures includes a channel semiconductor structure and a data storage structure. Separating structures, together with the plurality of vertical memory structures, fill the gap between the first and second stacked structures and separate adjacent vertical memory structures. Conductors are disposed on the vertical memory structures to extend along the first direction. The channel semiconductor structure includes a first channel semiconductor layer and a second channel semiconductor layer having a mirror-symmetric structure with respect to each other. The first data storage structure and the second data storage structure have a mirror-symmetric structure relative to each other. The first data storage structure is disposed between the first channel semiconductor layer and the first stacked structure. The second data storage structure is disposed between the second channel semiconductor layer and the second stacked structure. The side surface of the first stacked structure facing the first data storage structure is concave. The side surface of the second stacked structure facing the second data storage structure is concave. The first channel semiconductor layer has a substantially uniform thickness and faces the first data storage structure in a planar view.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes a lower structure. A plurality of discrete structures and a plurality of vertical memory structures are disposed on the lower structure. The plurality of discrete structures and the plurality of vertical memory structures are alternately repeated in a first direction parallel to the upper surface of the lower structure. A stacked structure is disposed on the lower structure and is divided in a second direction by the plurality of discrete structures and the plurality of vertical memory structures. The second direction is parallel to the upper surface of the lower structure and perpendicular to the first direction. The stacked structure includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the lower structure. Each of the plurality of vertical memory structures includes a channel semiconductor structure and a data storage structure. The plurality of discrete structures includes a plurality of first discrete structures and a second discrete structure disposed between adjacent first discrete structures of the plurality of first discrete structures. The width of each of the plurality of first discrete structures in the first direction is smaller than the width of the second discrete structure in the first direction.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes a lower structure and a stacked structure disposed on the lower structure. The stacked structure includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the lower structure. A plurality of discrete structures are disposed on the lower structure to penetrate the stacked structure and are spaced apart from each other in a first direction parallel to the upper surface of the lower structure. A vertical memory structure is disposed between the plurality of discrete structures to penetrate the stacked structure. The vertical memory structure includes a core region, a channel semiconductor structure, and a data storage structure. The vertical memory structure has a side facing the stacked structure. The distance between the sides of the vertical memory structure facing the stacked structure gradually narrows or gradually widens from a first discrete structure of the plurality of discrete structures to an adjacent second discrete structure of the plurality of discrete structures.

[0011] According to an exemplary embodiment of the present invention, a semiconductor device includes a lower structure and a plurality of discrete structures disposed on the lower structure. The plurality of discrete structures are spaced apart from each other in a first direction parallel to the upper surface of the lower structure. A vertical memory structure is disposed between adjacent discrete structures of the plurality of discrete structures. A stacked structure is disposed on the lower structure. The stacked structure includes a first stacked structure and a second stacked structure, which are spaced apart from each other in a second direction via the plurality of discrete structures and the vertical memory structure. The second direction is parallel to the upper surface of the lower structure and perpendicular to the first direction. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the lower structure. At least a portion of the side of the first and second stacked structures facing the vertical memory structure is concave in a first planar direction defined by the first and second directions. Attached Figure Description

[0012] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood through the following detailed description of exemplary embodiments taken in conjunction with the accompanying drawings, wherein:

[0013] Figure 1 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0014] Figure 2A It is along the exemplary embodiment of the concept of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines Ia-Ia' and IIa-IIa';

[0015] Figure 2B It is along the exemplary embodiment of the concept of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines Ia-Ia' and IIa-IIa';

[0016] Figure 2C It is along the exemplary embodiment of the concept of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines Ia-Ia' and IIa-IIa';

[0017] Figure 2D It is along the exemplary embodiment of the concept of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines Ia-Ia' and IIa-IIa';

[0018] Figure 3A This is an enlarged plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0019] Figure 3B This is an enlarged plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0020] Figure 3C This is an enlarged plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0021] Figure 4A This is an enlarged plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0022] Figure 4B It is along the exemplary embodiment of the concept of the present invention. Figure 4A Cross-sectional views of semiconductor devices taken by lines IIIa-IIIa' and IVa-IVa';

[0023] Figure 5A This is an enlarged plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0024] Figure 5BIt is along the exemplary embodiment of the concept of the present invention. Figure 5A Cross-sectional views of the semiconductor device taken by lines IIIb-IIIb and IVb-IVb';

[0025] Figure 6A This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0026] Figure 6B It is along the exemplary embodiment of the concept of the present invention. Figure 6A Cross-sectional views of semiconductor devices taken by lines IIb-IIb and Ib-Ib';

[0027] Figure 7A This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0028] Figure 7B It is along the exemplary embodiment of the concept of the present invention. Figure 7A Cross-sectional views of the semiconductor device taken by lines Ic-Ic' and IIc-IIc';

[0029] Figure 8A This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0030] Figure 8B It is along the exemplary embodiment of the concept of the present invention. Figure 8A Cross-sectional views of the semiconductor device taken by lines Id-Id' and IId-IId';

[0031] Figure 9 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0032] Figure 10 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0033] Figure 11 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0034] Figure 12 It is along the exemplary embodiment of the concept of the present invention. Figure 11 Cross-sectional views of semiconductor devices taken by lines Ie-Ie' and IIe-IIe';

[0035] Figure 13 It is along the exemplary embodiment of the concept of the present invention. Figure 11 Cross-sectional views of semiconductor devices taken by lines Ie-Ie' and IIe-IIe';

[0036] Figure 14It is along the exemplary embodiment of the concept of the present invention. Figure 11 Cross-sectional views of semiconductor devices taken by lines Ie-Ie' and IIe-IIe';

[0037] Figure 15 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0038] Figure 16 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0039] Figure 17 This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0040] Figure 18A This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0041] Figure 18B It is along the exemplary embodiment of the concept of the present invention. Figure 18A A cross-sectional view of a semiconductor device taken by the line If-If';

[0042] Figure 19A This is a plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0043] Figure 19B It is along the exemplary embodiment of the concept of the present invention. Figure 19A Cross-sectional views of a semiconductor device taken by lines V-V' and VI-VI';

[0044] Figure 19C This is an enlarged plan view of a semiconductor device according to an exemplary embodiment of the present invention.

[0045] Figure 20A It is along the exemplary embodiment of the concept of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines Ia-Ia' and IIa-IIa';

[0046] Figure 20B It is along the exemplary embodiment of the concept of the present invention. Figure 1 Cross-sectional views of the semiconductor device taken by lines Ia-Ia' and IIa-IIa';

[0047] Figure 20C It is along the exemplary embodiment of the concept of the present invention. Figure 18A A cross-sectional view of a semiconductor device taken by the line If-If';

[0048] Figure 20D It is along the exemplary embodiment of the concept of the present invention. Figure 18AA cross-sectional view of a semiconductor device taken by the line If-If';

[0049] Figure 20E It is along the exemplary embodiment of the concept of the present invention. Figure 18A A cross-sectional view of a semiconductor device taken by the line If-If';

[0050] Figure 20F It is along the exemplary embodiment of the concept of the present invention. Figure 18A A cross-sectional view of a semiconductor device taken by the line If-If';

[0051] Figure 21 This is a flowchart illustrating an exemplary embodiment of a method for forming a semiconductor device according to a concept of the present invention;

[0052] Figure 22A This is a plan view illustrating a method for forming a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0053] Figure 22B This is an example illustrating an exemplary embodiment of the concept according to the present invention. Figure 22A A cross-sectional view of the method for forming a semiconductor device, taken from lines Ia-Ia' and IIa-IIa';

[0054] Figure 22C This is an example illustrating an exemplary embodiment of the concept according to the present invention. Figure 22A A cross-sectional view of the method for forming a semiconductor device, taken from lines Ia-Ia' and IIa-IIa';

[0055] Figure 23A This is a plan view illustrating a method for forming a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0056] Figure 23B This is an example illustrating an exemplary embodiment of the concept according to the present invention. Figure 23A A cross-sectional view of the method of forming a semiconductor device, taken from lines VII-VII' and VIII-VIII';

[0057] Figure 24 This is a plan view illustrating a method for forming a semiconductor device according to an exemplary embodiment of the concept of the present invention;

[0058] Figures 25A to 25C This is an example illustrating an exemplary embodiment of the concept according to the present invention. Figure 11 Cross-sectional views of the method for forming a semiconductor device, taken from lines Ie-Ie' and IIe-IIe'; and

[0059] Figure 26A and Figure 26B This is an example illustrating an exemplary embodiment of the concept according to the present invention. Figure 11 A cross-sectional view of the method of forming a semiconductor device, taken from lines Ie-Ie' and IIe-IIe'. Detailed Implementation

[0060] Reference Figure 1 and Figure 2A A semiconductor device is described according to an exemplary embodiment of the concept of the present invention. Figure 1 This is a plan view illustrating a semiconductor device according to an exemplary embodiment. Figure 2A It shows along Figure 1 A cross-sectional view of the region intercepted by lines Ia-Ia' and IIa-IIa'.

[0061] refer to Figure 1 and Figure 2A The stacked structure 6 (e.g., along the vertical Z-direction) can be disposed on the lower structure 2. The lower structure 2 may include a substrate 3 and an impurity region 5 disposed on the substrate 3 (e.g., along the Z-direction). In an exemplary embodiment, the impurity region 5 may have N-type conductivity. The substrate 3 may be a semiconductor substrate.

[0062] The stacked structure 6 may include (e.g., along the Z direction) alternately stacked interlayer insulating layers 9 and gate layers 12. The uppermost layer of the interlayer insulating layers 9 and gate layers 12 may be the uppermost interlayer insulating layer 9U. In an exemplary embodiment, the interlayer insulating layer 9 may be formed of an insulating material such as silicon oxide. However, exemplary embodiments of the inventive concept are not limited thereto.

[0063] The gate layer 12 may include a conductive material. For example, in an exemplary embodiment, the gate layer 12 may include at least one material selected from polysilicon, metal nitrides (e.g., TiN, TaN, etc.), metal silicides (e.g., TiSi, TaSi, CoSi, WSi, etc.), and metals (e.g., W, etc.). For example, the gate layer 12 may be formed of polysilicon having P-type conductivity.

[0064] Gate layer 12 may include gate electrodes. For example, in gate layer 12, one gate electrode or at least one of a plurality of lower gate layers may be a ground select gate electrode, and one gate electrode or at least one of a plurality of upper gate layers may be a string select gate electrode, and a plurality of intermediate gate layers between one or more lower gate layers and one or more upper gate layers may be word lines.

[0065] On the lower structure 2, vertical storage structures 18a and separation structures 35 can be provided to penetrate the stacking structure 6. The vertical storage structure 18a can extend in the vertical direction Z, perpendicular to the upper surface of the lower structure 2, to penetrate the stacking structure 6. The separation structures 35 can be spaced apart from each other. For example, the separation structures 35 can be spaced apart from each other in the X direction, parallel to the upper surface of the lower structure 2. The vertical storage structures 18a can also be spaced apart from each other (e.g., in the X direction).

[0066] In a plan view taken along the X direction and parallel to the upper surface of the lower structure 2 and perpendicular to the X direction in the Y direction, the vertical storage structure 18a and the separation structure 35 are arranged to contact each other along the X direction and can be arranged to be spaced apart from each other in the Y direction. Therefore, the vertical storage structure 18a and the separation structure 35 arranged in the X direction can be arranged alternately and repeatedly while in contact with each other, and the vertical storage structure 18a and the separation structure 35 arranged to be spaced apart from each other in the Y direction can be arranged in a zigzag pattern.

[0067] The vertical storage structure 18a and the separation structure 35 arranged in the X direction can divide the stacking structure 6 in the Y direction, which is vertical to the X direction. Therefore, as Figure 1 In the exemplary embodiment shown, the stacking structure 6 may include a first stacking structure 6a and a second stacking structure 6b, which are spaced apart from each other in the Y direction by a separation structure 35 arranged in the X direction and a vertical storage structure.

[0068] Each vertical memory structure 18a may include a data storage structure 20, a channel semiconductor structure 27, and a core region 29.

[0069] The core region 29 may be disposed (e.g., in the Y direction) between the first stacked structure 6a and the second stacked structure 6b. In an exemplary embodiment, the core region 29 may include an insulating material such as silicon oxide. Alternatively, the core region 29 may include an insulating material with voids. However, exemplary embodiments of the inventive concept are not limited thereto.

[0070] Between the first stacked structure 6a and the second stacked structure 6b, the channel semiconductor structure 27 can cover the bottom surface and side surface of the core region 29.

[0071] In the channel semiconductor structure 27, the first portion 27a disposed between the core region 29 and the first stacked structure 6a is described as 'first channel semiconductor layer 27a', and the second portion 27b disposed between the core region 29 and the second stacked structure 6b is described as 'second channel semiconductor layer 27b'. The first channel semiconductor layer 27a and the second channel semiconductor layer 27b can extend in the Z direction and can be spaced apart in the Y direction.

[0072] The channel semiconductor structure 27 can be electrically connected to the impurity region 5 of the lower structure 2. In an exemplary embodiment, the channel semiconductor structure 27 can be formed of polysilicon.

[0073] The data storage structure 20 includes (e.g., in the Y direction) a first data storage structure 20a and a second data storage structure 20b, wherein the first data storage structure 20a is located between a first stacked structure 6a and a first channel semiconductor layer 27a, and the second data storage structure 20b is located between a second stacked structure 6b and a second channel semiconductor layer 27b. The first data storage structure 20a and the second data storage structure 20b may be spaced apart from each other in the Y direction. The first channel semiconductor layer 27a and the second channel semiconductor layer 27b may also be spaced apart from each other in the Y direction.

[0074] Each of the first data storage structure 20a and the second data storage structure 20b may include a first dielectric layer 21, a data storage layer 23, and a second dielectric layer 25 arranged in the Y direction. The data storage layer 23 may (e.g., in the Y direction) be located between the first dielectric layer 21 and the second dielectric layer 25. The first dielectric layer 21 may be located between the stacked structure 6 and the data storage layer 23, and the second dielectric layer 25 may be located between the channel semiconductor structure 27 and the data storage layer 23. The first dielectric layer 21 may be in direct contact with the stacked structure 6, and the second dielectric layer 25 may be in direct contact with the channel semiconductor structure 27. In an exemplary embodiment, the second dielectric layer 25 may include silicon oxide or silicon oxide doped with impurities. The first dielectric layer 21 may include silicon oxide and / or a high-k dielectric. However, exemplary embodiments of the inventive concept are not limited thereto.

[0075] Data storage layer 23 may be a charge trapping layer capable of trapping electrical charges. Data storage layer 23 may include a charge trapping material, such as silicon nitride. Data storage layer 23 may be used as a data storage area of ​​NAND flash memory. Each of the first data storage structure 20a and the second data storage structure 20b may include a data storage layer 23 that can be used as a data storage area of ​​NAND flash memory. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, at least one of the first data storage structure 20a and the second data storage structure 20b may further include a data storage layer capable of storing information in a manner different from that of NAND flash memory.

[0076] exist Figure 1 In the plan view shown (e.g., in a plane defined by the X and Y directions), each separation structure 35 may be circular. In an exemplary embodiment, the separation structure 35 may be formed of an insulating material such as silicon oxide.

[0077] exist Figure 1 In the plan view shown, the side surface 29S1 of the core region 29 facing the channel semiconductor structure 27 may have a convex shape in the direction toward the channel semiconductor structure 27.

[0078] exist Figure 1 In the plan view shown, the side surface 29S2 of the core region 29 facing the separation structure 35 can have a concave shape in the direction toward the separation structure 35.

[0079] When in Figure 1 When viewed in the plan view, the first data storage structure 20a may have a predetermined thickness and face the first stacked structure 6a, and the second data storage structure 20b may have a predetermined thickness and face the second stacked structure 6b. When viewed in the plan view, the first data storage structure 20a may have a substantially uniform thickness and face the first stacked structure 6a, and the second data storage structure 20b may have a substantially uniform thickness and face the second stacked structure 6b. In the plan view, the first channel semiconductor layer 27a may have a predetermined thickness and face the first data storage structure 20a, and the second channel semiconductor layer 27b may have a predetermined thickness and face the second data storage structure 20b. In the plan view, the first channel semiconductor layer 27a may have a substantially uniform thickness, and the second channel semiconductor layer 27b may have a substantially uniform thickness.

[0080] exist Figure 1 In the plan view shown, the first channel semiconductor layer 27a and the first data storage structure 20a may have a strip shape that is convexly curved in the direction from the core region 29 toward the first stacked structure 6a, and the second channel semiconductor layer 27b and the second data storage structure 20b may have a strip shape that is convexly curved in the direction from the core region 29 toward the second stacked structure 6b.

[0081] exist Figure 1 In the plan view shown, the length of the interface surface between the data storage structure 20 and the channel semiconductor structure 27 can be greater than the length of the interface surface between the channel semiconductor structure 27 and the core region 29. For example, as Figure 1 As shown in the exemplary embodiment, the length of the interface surface 27S between the first data storage structure 20a and the first channel semiconductor layer 27a can be greater than the length of the interface surface 29S between the first channel semiconductor layer 27a and the core region 29. The length of the interface surface 27S1 between the second data storage structure 20b and the second channel semiconductor layer 27b can be greater than the length of the interface surface 29S3 between the second channel semiconductor layer 27b and the core region 29.

[0082] exist Figure 1In the plan view shown, the length of the interface surface 20S between the data storage structure 20 and the stacked structure 6 can be greater than the length of the interface surface 27S between the first data storage structure 20a and the first channel semiconductor structure 27a, and the length of the interface surface 27S1 between the second data storage structure 20b and the second channel semiconductor layer 27b. For example, the length of the interface surface 20S between the first data storage structure 20a and the first stacked structure 6a can be greater than the length of the interface surface 27S between the first data storage structure 20a and the first channel semiconductor layer 27a. The length of the interface surface 20S between the second data storage structure 20b and the second stacked structure 6b can be greater than the length of the interface surface 27S1 between the second data storage structure 20b and the second channel semiconductor layer 27b.

[0083] The interface surface 20S between the data storage structure 20 and the stacking structure 6 can be the side of the vertical storage structure 18a facing the stacking structure 6.

[0084] exist Figure 1 In the plan view shown, the side surface of the vertical storage structure 18a facing the separation structure 35 may be concave in the direction toward the separation structure 35.

[0085] exist Figure 1 In the plan view shown, the side surfaces of the first stacked structure 6a and the second stacked structure 6b facing the vertical storage structure 18a can be concave in the direction toward the vertical storage structure 18a. For example, when viewed in the plan view, the side surface 20S of the vertical storage structure 18a facing the first stacked structure 6a and the second stacked structure 6b can be convex in the direction toward the adjacent stacked structure. Since the side surface 20S of the vertical storage structure 18a is convex, the side surfaces of the gate layer (which may be a word line) in the gate layer 12 of the data storage structure 20 facing the stacked structure 6, as well as the side surfaces of the channel semiconductor structure 27, can also be convex. Therefore, when the data storage structure 20 is used as the data storage area of ​​NAND flash memory, the programming speed of the NAND flash memory can be increased through field-effect concentration because the channel semiconductor structure 27 is bent in the direction toward the adjacent stacked structure 6, and the reverse tunneling phenomenon during the erase operation can be reduced. Therefore, the performance of semiconductor devices such as NAND flash memory can be improved.

[0086] As described above, the separation structure 35 and the vertical memory structure 18a arranged in the X direction can divide the stacked structure 6 into a first stacked structure 6a and a second stacked structure 6b. Thus, each of the first stacked structure 6a and the second stacked structure 6b can include multiple gate layers 12. Therefore, each vertical memory structure 18a can include a first data storage structure 20a facing the first stacked structure 6a and a second data storage structure 20b facing the second stacked structure. As described above, the multiple gate layers 12 can include multiple word lines.

[0087] Therefore, in each vertical memory structure 18a, multiple data storage areas capable of storing information can be formed in the data storage layer 23 of the second data storage structure 20a facing multiple gate layers 12 (which may be word lines of the first stacked structure 6a), and multiple data storage areas capable of storing information can be formed in the data storage layer 23 of the second data storage structure 20b facing multiple gate layers 12 (which may be word lines of the second stacked structure 6b). Thus, multiple data storage areas can be formed in each of the first data storage structure 20a and the second data storage structure 20b, and such data storage areas can constitute memory cells. Therefore, since relatively more data storage areas can be formed in a single vertical memory structure 18a, the integration density of the semiconductor device can be improved.

[0088] The components of the above exemplary embodiments are not limited to those of the above exemplary embodiments and can be modified in various ways. In the following description of exemplary embodiments with various modifications to some of these components, descriptions of the remaining components that are not modified and are substantially the same as those in the foregoing embodiments will be omitted when describing the modified components. For example, in the above embodiments, when "Component A" and "Component B" are described, and only a variant example of "Component A" is described in the modified examples, it should be understood that the modified examples include both "Component B" and "the modified Component A" even if there is no description or mention of "Component B".

[0089] Next, we will refer to Figure 2B The above describes about Figure 1 and Figure 2A The exemplary embodiments described herein are modified examples of the vertical storage structure 18a and the stacking structure 6. Figure 2B It is along Figure 1 The cross-sectional view taken from lines Ia-Ia' and IIa-IIa'.

[0090] refer to Figure 2BIn an exemplary embodiment, the stacked structure 6' may include a lower stacked structure 7a and an upper stacked structure 7b disposed on the lower stacked structure 7a (e.g., in the Z direction). The lower stacked structure 7a may include a first interlayer insulating layer 9a and a first gate layer 12a stacked alternately and repeatedly. The uppermost layer of the first interlayer insulating layer 9a and the first gate layer 12a (e.g., in the Z direction) may be a first intermediate interlayer insulating layer 9M1. The upper stacked structure 7b may include a second interlayer insulating layer 9b and a second gate layer 12b stacked alternately and repeatedly. The uppermost layer of the second interlayer insulating layer 9b and the second gate layer 12b (e.g., in the Z direction) may be an uppermost interlayer insulating layer 9U, and its lowermost layer may be a second intermediate interlayer insulating layer 9M2. Figure 2B As shown in the exemplary embodiment, the lower surface of the second interlayer insulation layer 9M2 can directly contact the upper surface of the first interlayer insulation layer 9M1.

[0091] The vertical storage structure 18a' and the separation structure 35 can be configured (e.g., in the Z direction) to penetrate the stack structure 6'. The separation structure 35 can be related to the above... Figure 1 and Figure 2A The separation structure 35 described in the exemplary embodiment is substantially the same.

[0092] The planar shapes of the vertical storage structure 18a' and the separation structure 35 (e.g., in a plane defined by the X and Y directions) can be the same as those described above. Figure 1 and Figure 2A The vertical storage structure described in the exemplary embodiments (see Figure 1 The planar shapes of 18a) and the separation structure 35 are basically the same.

[0093] Each vertical storage structure 18a' may include a data storage structure (see the first data storage structure) respectively. Figure 1 and Figure 2A 20a), Second data storage structure (see 20a) Figure 1 and Figure 2A 20b), channel semiconductor structure (see 20b) Figure 1 and Figure 2A 27) and the core area (see Figure 1 and Figure 2A The first data storage structure 20a', the second data storage structure 20b', the channel semiconductor layer 27', and the core region 29' correspond to 29). The channel semiconductor structure 27' may include, respectively, the first data storage structure 20a', the second data storage structure 20b', the channel semiconductor layer 27', and the core region 29' mentioned above. Figure 1 and Figure 2A The exemplary embodiments described correspond to the first channel semiconductor layer 27a' and the second channel semiconductor layer 27b'.

[0094] Each vertical storage structure 18a' may include a lower vertical storage portion penetrating the lower stacking structure 7a and an upper vertical storage portion penetrating the upper stacking structure 7b. In the vertical storage structure 18a', the upper width (e.g., length in the Y direction) of the lower storage vertical portion penetrating the lower stacking structure 7a may be greater than the lower width of the upper storage vertical portion penetrating the upper stacking structure 7b. For example, the width of the lower storage vertical portion penetrating the first interlayer insulating layer 9M1 may be greater than the width of the upper storage vertical portion penetrating the second interlayer insulating layer 9M2. In an exemplary embodiment, the width of the lower storage vertical portion penetrating the lower stacking structure 7a may increase with increasing distance from the lower structure 2 (e.g., in the Z direction), and the width of the upper storage vertical portion penetrating the upper stacking structure 7b may increase with increasing distance from the lower structure 2 (e.g., in the Z direction).

[0095] Next, we will refer to Figure 2C The following exemplary embodiments are used to describe a modified example of the lower structure 2 described above. Figure 2C It shows along Figure 1 A cross-sectional view of the region intercepted by lines Ia-Ia' and IIa-IIa'.

[0096] In the modified embodiment, reference is made to Figure 2C In an exemplary embodiment, the lower structure 2a may include a lower substrate 3a, an upper substrate 5a disposed on the lower substrate 3a (e.g., along the Z direction), a peripheral circuit region 4 disposed between the lower substrate 3a and the upper substrate 5a (e.g., in the Z direction), and an impurity region 5b disposed on the upper substrate 5a (e.g., in the Z direction). In an exemplary embodiment, the lower substrate 3a may be a semiconductor substrate, which may be formed of a semiconductor material such as silicon. The peripheral circuit region 4 may include: peripheral wiring 4a, which may constitute a peripheral circuit; and a lower insulating layer 4b, which covers the peripheral wiring 4a and extends between the lower substrate 3a and the upper substrate 5a. In an exemplary embodiment, the upper substrate 5a may include a conductive material layer, which includes a metallic material. For example, the upper substrate 5a may include a metal and / or a metal silicide. For example, the upper substrate 5a may be formed of a conductive material layer including tungsten and tungsten silicide on tungsten. The impurity region 5b may be formed of polycrystalline silicon having N-type conductivity.

[0097] Next, we will refer to Figure 2D The following exemplary embodiments are used to describe a modified example of the vertical storage structure 18a described above. Figure 2D It shows along Figure 1 The cross-sectional view of the semiconductor device taken by lines Ia-Ia' and IIa-IIa' in the figure.

[0098] In one variation, reference Figure 2DThe vertical memory structure 18a” may include the first data storage structure 20a and the second data storage structure 20b described above, as well as the channel semiconductor structure 27. The vertical memory structure 18a” may also include a core region 29' and (e.g., in the Z direction) pad patterns 31 stacked on the core region 29'. For example, as Figure 2D In the exemplary embodiment, the lower surface of the pad pattern 31 can directly contact the upper surface of the core region 29'. In the exemplary embodiment, the pad pattern 31 can be formed of polysilicon. For example, the pad pattern 31 can be formed of polysilicon with N-type conductivity. The pad pattern 31 can contact the channel semiconductor structure 27. The channel semiconductor structure 27 may include the first channel semiconductor layer 27a and the second channel semiconductor layer 27b described above.

[0099] In an exemplary embodiment, the core region 29' may be referred to as the "bottom core region" and the pad pattern 31 may be referred to as the "upper core region". For example, the lower core region 29' and the upper core region 31 may (e.g., in the Z direction) penetrate the stack structure 6.

[0100] It can be used Figure 2D The insulating lower core region 29' and the upper core region 31 having N-type conductivity described in the exemplary embodiments are used to replace certain components described below using the term "core region".

[0101] Please refer to the following: Figure 3A , Figure 3B and Figure 3C The exemplary embodiments described above are used to illustrate a modified example of the vertical storage structure 18a and the separation structure 35. Figure 3A , Figure 3B and Figure 3C This is a partially enlarged planar view showing a pair of discrete structures adjacent to each other and a vertical memory structure located between the pair of discrete structures, to illustrate various modifications to the semiconductor device according to the example. Therefore, in the following reference... Figure 3A , Figure 3B and Figure 3C In the description of exemplary embodiments, the description will be from... Figure 1 The exemplary embodiments shown include a vertical storage structure and a pair of separate structures.

[0102] refer to Figure 3AIn an exemplary embodiment, a vertical storage structure 18a_1 may (e.g., in the X direction) be disposed between and in contact with a pair of separate structures 35a. As described above, the vertical storage structure 18a_1 includes a first data storage structure 20a_1 and a second data storage structure 20b_1 spaced apart from each other in the Y direction, a first channel semiconductor layer 27a_1 and a second channel semiconductor layer 27b_1 disposed between the first data storage structure 20a_1 and the second data storage structure 20b_1 and spaced apart from each other in the Y direction, and a core region 29 disposed between the first channel semiconductor layer 27a_1 and the second channel semiconductor layer 27b_1. Each of the first data storage structure 20a_1 and the second data storage structure 20b_1 may include the first dielectric layer 21, the data storage layer 23 and the second dielectric layer 25 described above.

[0103] Each discrete structure 35a may have a first side surface 36S1a that contacts the stacked structure 6 and a second side surface 36S2a that contacts the first data storage structure 20a_1 and the second data storage structure 20b_1. A third side surface 36S3a may contact the first channel semiconductor layer 27a_1 and the second channel semiconductor layer 27b_1, and a fourth side surface 36S4a may contact the core region 29.

[0104] The stacked structure 6 may have a first side surface 37S1a, which is concave in the direction facing the separation structure 35a and may form a first concave side surface. The second side surface 37S2a of each of the first data storage structure 20a_1 and the second data storage structure 20b_1 may be concave in the direction facing the separation structure 35a and may form a second concave side surface. The third side surface 37S3a of each of the first channel semiconductor layer 27a_1 and the second channel semiconductor layer 27b_1 may be concave in the direction facing the separation structure 35a and may form a third concave side surface. The fourth side surface 37S4a of the core region 29 may be concave in the direction facing the separation structure 35a and may form a fourth concave side surface. The first side surface 36S1a and the second side surface 36S2a may have protruding shapes, such as convex shapes. The second side surface 36S2a and the third side surface 36S3a may have protruding shapes, such as convex shapes. The third side surface 36S3a and the fourth side surface 36S4a may have a protruding shape, such as a convex shape.

[0105] refer to Figure 3BIn an exemplary embodiment, in a vertical memory structure 18a_2 between a pair of separate structures 35b, the vertical memory structure 18a_2 may include a first data storage structure 20a_2, a first channel semiconductor layer 27a_2, a core region 29, a second channel semiconductor layer 27b_2, and a second data storage structure 20b_2, such as Figure 3A As described in the exemplary embodiments.

[0106] The stacked structure 6 may have a first side surface 37S1b facing a first side surface 36S1b of the separation structure 35b, which is concave and can form a first concave side surface. Each of the first data storage structure 20a_2 and the second data storage structure 20b_2 may have a second side surface 37S2b facing a second side surface 36S2b of the separation structure 35b, which is concave and can form a second concave side surface. Each of the first channel semiconductor layer 27a_2 and the second channel semiconductor layer 27b_2 may have a third side surface 37S3b facing a third side surface 36S3b of the separation structure 35b, which is concave and can form a third concave side surface. The core region 29 may have a fourth side surface 37S4b facing a fourth side surface 36S4b of the separation structure 35b, which is concave and can form a fourth concave side surface. The first side surface 36S1b of the separation structure 35b may have a protruding shape, such as a convex shape. The second side surface 36S2b and the third side surface 36S3b of the separation structure 35b may have protruding shapes. The second side surface 36S2b and the third side surface 36S3b of the separation structure 35b may together form a convex shape. The fourth side surface 36S4b of the separation structure 35b may have a protruding shape.

[0107] refer to Figure 3C In the exemplary embodiment shown, in the case of a vertical memory structure 18a_3 between a pair of separate structures 35c, the vertical memory structure 18a_3 may include a first data storage structure 20a_3, a first channel semiconductor layer 27a_3, a core region 29, a second channel semiconductor layer 27b_3, and a second data storage structure 20b_3, similar to... Figure 3A Description of exemplary embodiments.

[0108] The stacked structure 6 may have a first side surface 37S1c facing a first side surface 36S1c of the separation structure 35c, which is concave and forms a first concave side surface. Each of the first data storage structure 20a_3 and the second data storage structure 20b_3 may have a second side surface 37S2c facing a second side surface 36S2c of the separation structure 35c, which is concave and forms a second concave surface. Each of the first channel semiconductor layer 27a_3 and the second channel semiconductor layer 27b_3 may have a third side surface 37S3c facing a third side surface 36S3c of the separation structure 35c, which is concave and forms a third concave surface. The core region 29 may have a fourth side surface 37S4c facing a fourth side surface 36S4c of the separation structure 35c, which is concave and forms a fourth concave surface. The second side surface 37S2c and the third side surface 37S3c can together form a concave shape. The second side surface 37S2c of the first data storage structure 20a_3 and the second data storage structure 20b_3, as well as the third side surface 37S3c of the first channel semiconductor layer 27a_3 and the second channel semiconductor layer 27b_3, can be formed into a concave shape that is more recessed than the first side surface 37S1c of the stacked structure 6 and the fourth side surface 37S4c of the core region 39.

[0109] Figure 4A and Figure 4B This is a modified example of a semiconductor device illustrating an exemplary embodiment of the concept according to the present invention. Figure 4A This is a plan view showing a pair of adjacent discrete structures and a vertical memory structure located between the pair of discrete structures, illustrating a modified example of a semiconductor device according to an exemplary embodiment. Figure 4A It is an enlarged plan view. Figure 4B It shows along Figure 4A A cross-sectional view of the region intercepted by lines IIIa-IIIa' and IVa-IVa'.

[0110] refer to Figure 4A and Figure 4B In an exemplary embodiment, in the case of a vertical storage structure 118 between a pair of separate structures 135, the vertical storage structure 118 may include a first data storage structure (see [link to previous embodiment]). Figure 1 and Figure 2A 20a), first channel semiconductor layer (see 20a) Figure 1 and Figure 2A 27a), core area (see 27a) Figure 1 and Figure 2A 29), second channel semiconductor layer (see Figure 1 and Figure 2A 27b) and the second data storage structure (see Figure 1 and Figure 2A The first data storage structure 120a, the first channel semiconductor layer 127a, the core region 129, the second channel semiconductor layer 127b, and the second data storage structure 120b correspond to 20b. The first channel semiconductor layer 127a and the second channel semiconductor layer 127b can constitute the channel semiconductor structure 127.

[0111] exist Figure 4A In an exemplary embodiment, reference numeral 120U indicates the outer surface of the upper end (e.g., in the Z direction) of the first data storage structure 120a, reference numeral 120L may indicate the outer surface of the lower end (e.g., in the Z direction) of the first data storage structure 120a, reference numeral 127U may indicate the outer surface of the upper end (e.g., in the Z direction) of the channel semiconductor structure 127, reference numeral 127L may indicate the outer surface of the lower end (e.g., in the Z direction) of the channel semiconductor structure 127, reference numeral 129U may indicate the outer surface of the upper end (e.g., in the Z direction) of the core region 129, and reference numeral 129L may indicate the outer surface of the lower end (e.g., in the Z direction) of the core region 129.

[0112] Therefore, in the vertical storage structure 118, the width of the upper surface of the vertical storage structure 118 in the Y direction can be greater than the width of the lower surface of the vertical storage structure 118 in the Y direction. The vertical storage structure 118 can have inclined side surfaces, such that the width in the Y direction increases towards the upper part of the vertical storage structure 118.

[0113] exist Figure 4A In the figures, reference numeral 135U may indicate the upper end (e.g., in the Z direction) side surface of each separation structure 135, and reference numeral 135L may indicate the lower end (e.g., in the Z direction) side surface of each separation structure 135. Therefore, in each separation structure 135, the width of the upper surface in the Y direction may be greater than the width of the lower surface. Each separation structure 135 may have an inclined side surface whose width increases towards the top.

[0114] Figure 5A and Figure 5B This is a modified example of a semiconductor device illustrating an exemplary embodiment of the concept according to the present invention. Figure 5A This is a partially enlarged plan view showing a pair of adjacent discrete structures and a vertical memory structure located between the pair of discrete structures, to illustrate a modification of the semiconductor device according to an exemplary embodiment. Figure 5B It shows along Figure 5A A cross-sectional view of the region intercepted by lines IIIb-IIIb' and IVb-IVb'.

[0115] refer to Figure 5Aand Figure 5B An exemplary embodiment, Figure 4A The vertical storage structure 118 shown can be positioned between a pair of separate structures 135'. Figure 5A In the figures, reference numeral 135U' may indicate one side of the upper end (e.g., in the Z direction) of each separation structure 135', and reference numeral 135L' may indicate one side of the lower end (e.g., in the Z direction) of each separation structure 135'. Each separation structure 135' may include a lower portion and an upper portion above the lower portion. The width of the lower portion of each separation structure 135' may be greater than the width of the upper portion of each separation structure 135'. Therefore, in each separation structure 135', the width of the upper surface may be less than the width of the lower surface. Each separation structure 135' may have sloping sides such that the width decreases towards the top.

[0116] Reference Figure 6A and Figure 6B An example of a semiconductor device according to an example embodiment. Figure 6A Is Figure 1 The plan view also includes plan views of contact plug 55 and wire 60. Figure 6B It is shown Figure 2A The cross-sectional view of the upper insulating layer 50, contact plug 55 and wire 60. Figure 6B It shows along Figure 6A A cross-sectional view of the region intercepted by lines Ib-Ib' and IIb-IIb'.

[0117] refer to Figure 6A and Figure 6B Exemplary embodiments and the above Figure 1 and Figure 2A The upper insulating layer 50 may (e.g., in the Z direction) be disposed on the stacked structure 6, the vertical storage structure 18a, and the separation structure 35. The contact plug 55 may (e.g., in the Z direction) penetrate the upper insulating layer 50 and may be electrically connected to the first channel semiconductor layer 27a and the second channel semiconductor layer 27b. A wire 60 may be disposed on the upper insulating layer 50 to be electrically connected to the contact plug 55. For example, the lower surface of the wire 60 may directly contact the upper insulating layer 50 and the upper surface of the contact plug 55. Therefore, the wire 60 can be electrically connected to the first channel semiconductor layer 27a and the second channel semiconductor layer 27b through the contact plug 55.

[0118] In an exemplary embodiment, the impurity region 5 of the lower structure 2 can be a common source line, and the conductor 60 can be a bit line. However, the exemplary embodiments of the present invention are not limited thereto.

[0119] Reference Figure 7A and Figure 7BModified examples of semiconductor devices according to exemplary embodiments of the present invention are described. Figure 7A This is a plan view illustrating a modified semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 7B This is an example illustrating an exemplary embodiment of the concept according to the present invention. Figure 7A A cross-sectional view of the region intercepted by lines Ic-Ic' and IIc-IIc'.

[0120] refer to Figure 7A and Figure 7B An exemplary embodiment, Figure 2A The stacked structure 6, which includes an interlayer insulating layer 9 and a gate layer 12, as described in the exemplary embodiments, may be disposed on the lower structure 2 (e.g., in the Z direction).

[0121] The vertical memory structure 118a can be configured to penetrate the stacked structure 6 (e.g., in the Z direction). Each vertical memory structure 118a may include a core region 129' that penetrates the gate layer 12, a data storage structure 120' covering the bottom surface and sides of the core region 129', and a channel semiconductor layer 127' disposed between the data storage structure 120' and the core region 129'. The data storage structure 120' may include the same first dielectric layer 21, data storage layer 23, and second dielectric layer 25 as described above.

[0122] When in Figure 7B When viewed in a cross section marked Ic-Ic', the channel semiconductor structure 127' can have a "U" shape. Therefore, the channel semiconductor structure 127' may include a first channel semiconductor layer 127a' and a second channel semiconductor layer 127b' facing each other, wherein a core region 129' is located between the first channel semiconductor layer 127a' and the second channel semiconductor layer 127b', and the lower surface of the channel semiconductor structure 127' is located below the lower surface of the core region 129'.

[0123] The data storage structure 120' may include a first data storage structure 120a' and a second data storage structure 120b' facing each other, wherein a core region 129' is between the first data storage structure 120a' and the second data storage structure 120b', and the lower surface of the data storage structure 120' is located below the lower surface of the channel semiconductor structure 127'. When in Figure 7B When viewed in a cross section marked Ic-Ic', the data storage structure 120' may have a "U" shape covering the outer and lower surfaces of the channel semiconductor structure 127'. Therefore, the data storage structure 120' may (e.g., in the Z direction) extend between the channel semiconductor structure 127' and the lower structure 2.

[0124] The separation structure 35 can be configured (e.g., in the Z direction) to penetrate the stacked structure 6. The separation structure 35 can be related to a reference... Figure 1 and Figure 2A The separation structure described in the exemplary embodiment is the same. The planar shape or arrangement of the vertical storage structure 118a and the separation structure 35 may be the same as that described in the reference. Figure 1 and Figure 2A The exemplary embodiments described herein have essentially the same planar shape or arrangement as the vertical storage structure and the separate structure.

[0125] The first pad 152a and the second pad 152b can be disposed on the stacked structure 6, the vertical storage structure 118a, and the separation structure 35. For example, the lower surfaces of the first pad 152a and the second pad 152b can directly contact the upper surfaces of the stacked structure 6 and the vertical storage structure 118a.

[0126] Each first pad 152a can be electrically connected to a first channel semiconductor layer 127a' of each vertical memory structure 118a, and the second pad 152b can be electrically connected to a second channel semiconductor layer 127b' of the vertical memory structure 118a. Therefore, one second pad 152b can be electrically connected to multiple second channel semiconductor layers 127b'.

[0127] The first upper insulating layer 155 covers the first pad 152a and the second pad 152b, and the second upper insulating layer 170 may be disposed on the first upper insulating layer 155 (e.g., in the Z direction).

[0128] A contact plug 175 that passes through the first upper insulating layer 155 and the second upper insulating layer 170 and is electrically connected to the first pad 152a may be disposed on the first pad 152a.

[0129] The wire 180 may be disposed on the second upper insulation layer 170 (e.g., the upper surface of the second upper insulation layer 170) to be electrically connected to the contact plug 175, and extends in the Y direction and is arranged in the X direction.

[0130] A contact pattern 160 may be formed on the second pad 152b (e.g., in the Z direction) that passes through the first upper insulating layer 155 and is electrically connected to the second pad 152b. The conductive pattern 165 may be formed on the first upper insulating layer to be electrically connected to the contact pattern 160.

[0131] In an exemplary embodiment, the conductor 180 may be a bit line, and the second pad 152b may be a common source line. Contact pattern 160 and conductive pattern 165 provide the electrical connection relationship for the second pad 152b, and the exemplary embodiment is not limited to... Figure 7A and Figure 7BThe shape disclosed herein. For example, contact pattern 160 and conductive pattern 165 may be disposed on a second pad 152b in an area that does not overlap with wire 180.

[0132] Reference Figure 8A and Figure 8B This describes modifications to a semiconductor device based on an example embodiment. Figure 8A Is Figure 1 The plan view also includes a first pad 252a, a second pad 252b, a first contact plug 255a, a second contact plug 255b, a first wire 180a, and a second wire 180b. Figure 8B It shows along Figure 8A A cross-sectional view of the region intercepted by lines Id-Id' and IId-IId'.

[0133] refer to Figure 8A and 8B In an exemplary embodiment, the semiconductor device may include a semiconductor device with Figure 1 and Figure 2A The stacked structure 6, vertical memory structure 18a, and separate structure 35 described in the exemplary embodiments are the same as those in the exemplary embodiments. A first pad 252a and a second pad 252b may be provided on the vertical memory structure 18a. The first pad 252a may be electrically connected to the first channel semiconductor layer 27a of the vertical memory structure 18a, and the second pad 252b may be electrically connected to the second channel semiconductor layer 27b of the vertical memory structure 18a. For example, the lower surface of the first pad 252a may directly contact the upper surface of the vertical memory structure 18a.

[0134] The upper insulating layer 250 covering the first pad 252a and the second pad 252b can be disposed on the stacked structure 6, the vertical storage structure 18a and the separation structure 35.

[0135] A first contact plug 255a, penetrating the upper insulating layer 250, may be disposed on the first pad 252a for electrical connection to the first pad 252a. A second contact plug 255b may be disposed on the second pad 252b for electrical connection to the second pad 252b.

[0136] The first conductor 180a and the second conductor 180b, which extend in the Y direction and are arranged in the X direction, can be disposed on the upper insulating layer 250.

[0137] The conductors 180a and 180b may include a first conductor 180a and a second conductor 180b arranged alternately in the X direction.

[0138] The first conductor 180a can be electrically connected to the first channel semiconductor layer 27a of the vertical memory structure 18a via the first contact plug 255a and the first pad 252a. The second conductor 180b can be electrically connected to the second channel semiconductor layer 27b of the vertical memory structure 18a via the second contact plug 255b and the second pad 252b.

[0139] Reference Figure 9 This describes a modification example of a semiconductor device according to an exemplary embodiment. Figure 9 It is shown Figure 1 A plan view showing the planar changes of the separation structure 35 and the vertical storage structure 18a.

[0140] refer to Figure 9 An exemplary embodiment, Figure 1 The circular separation structure 35 can be modified to have a separation structure 235 having vertical sides (e.g., extending substantially in the Y direction). For example, each separation structure 235 can have a shape with a predetermined width between core regions 29 adjacent to each other in the X direction. Each separation structure 235 can have a shape with a uniform width between core regions 29 adjacent to each other in the X direction and between channel semiconductor structures 27. When viewed in a plan view (e.g., in a plane defined by the X and Y directions), the side surfaces of the core regions 29 facing the separation structure 235 can have a line shape (e.g., extending substantially in the Y direction) that are parallel to each other, and the side surfaces of the core regions 29 facing the channel semiconductor structure 27 can have a convex shape.

[0141] Each partition structure 235 can be configured between first data storage structures 20a adjacent to each other in the X direction and between second data storage structures 20b adjacent to each other in the X direction, while having a width that decreases in the X direction toward the stacking structure 6. For example, the ends (e.g., in the Y direction) of a plurality of vertical storage structures 235 adjacent to data storage structures 20a (e.g., in the X direction) can have a convex shape in the direction toward the stacking structure 6.

[0142] Reference Figure 10 This describes a modification example of a semiconductor device according to an exemplary embodiment. Figure 10 It is shown Figure 1 A plan view showing the changes in the planar shape of the separation structure 35 and the vertical storage structure 18a.

[0143] refer to Figure 10 An exemplary embodiment thereof, and formed having the same size and shape. Figure 1 Compared to isolation structure 35, the semiconductor device includes isolation structures 235a and 235b with different sizes and shapes. For example, the semiconductor device may include isolation structures 235a and 235b with shapes similar to... Figure 9In an exemplary embodiment, the separation structures 235 include a first separation structure 235a with a similar shape and a second separation structure 235b with a basically square shape and rounded corners. The size of each first separation structure 235a may be smaller than the size of each second separation structure 235b. For example, the width of each first separation structure 235a in the X direction may be smaller than the width of each second separation structure 235b in the X direction to form different shapes. The placement density of the first separation structures 235a may be greater than the placement density of the second separation structures 235b. For example, the first separation structures 235a and the second separation structures 235b may be arranged sequentially in the X direction, and each of the second separation structures 235b may be arranged between a plurality of consecutive first separation structures 235a on each side of the second separation structure 235b.

[0144] First, refer to Figures 11 to 14 Various modifications to the semiconductor device according to the embodiments are described. Figure 11 This is a plan view illustrating a modified example of a semiconductor device according to an exemplary embodiment. Figure 12 A cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment is provided, and a cross-sectional view illustrating along... Figure 11 A cross-sectional view of the region intercepted by lines Ie-Ie' and IIe-IIe'. Figure 13 Provided along Figure 11 A cross-sectional view of the region intercepted by lines Ie-Ie' and IIe-IIe' is provided to illustrate another modification of the semiconductor device according to an exemplary embodiment. Figure 14 Provided along Figure 11 A cross-sectional view of the region intercepted by lines Ie-Ie' and IIe-IIe' is provided to illustrate another modification of the semiconductor device according to an exemplary embodiment.

[0145] Refer to the modification example Figure 11 and Figure 12 You can refer to Figure 2A The same stacked structure 6 described in the exemplary embodiment is disposed on the lower structure 2. Similar to Figure 10 In an exemplary embodiment, the semiconductor device may include a first partition structure 235a and a second partition structure 235b' having different shapes and sizes. For example, the shape and size of the first partition structure 235a may be different from those of the second partition structure 235b'. Figure 10In the exemplary embodiment, the first partition structures are substantially the same in shape and size. The second partition structure 235b' may have a rectangular shape with rounded corners and a relatively long side extending in the Y direction. The second partition structure 235b' is larger than the size of each first partition structure 235a. For example, each first partition structure 235a may have a width in the X direction that is smaller than the width of each second partition structure 235b' in the X direction. The first partition structures 235a and the second partition structures 235b' are arranged sequentially in the X direction, such that the first partition structures 235a have a greater placement density. For example, each second partition structure 235b' may be disposed between a plurality of consecutive first partition structures 235a on each side of the second partition structure 235b'.

[0146] The first separation structure 235a and the second separation structure 235b', as well as the vertical storage structures 18a and 218a, are arranged alternately along the X direction. The first separation structure 235a and the second separation structure 235b', as well as the first vertical storage structure 18a and the second vertical storage structure 218a, can penetrate the stacking structure 6 (e.g., in the Z direction) and can divide the stacking structure 6 in the Y direction.

[0147] The semiconductor device may include a first vertical memory structure 18a between two adjacent first separation structures 235a, and a second vertical memory structure 218a adjacent to and disposed on each side of the second separation structure 235b'. The second vertical memory structure 218a may be disposed between the adjacent second separation structures 235b' and the first separation structures 235a.

[0148] The width of the first vertical storage structure 18a in the X direction can be smaller than the width of the second vertical storage structure 218a in the X direction. The width of the first vertical storage structure 18a in the Y direction can be equal to the width of the second vertical storage structure 218a in the Y direction.

[0149] The first vertical storage structure 18a may include and Figure 1 and Figure 2A The first data storage structure 20a and the second data storage structure 20b, the channel semiconductor structure 27, and the core region 29 are substantially the same as those described in the exemplary embodiments. In the first vertical memory structure 18a, the channel semiconductor structure 27 may be referred to as the "first channel semiconductor structure," and the core region 29 may be referred to as the "first core region." As described above, the channel semiconductor structure 27 may include a first channel semiconductor layer 27a and a second channel semiconductor layer 27b.

[0150] The second vertical memory structure 218a may include a third data storage structure 220a and a fourth data storage structure 220b, a second channel semiconductor structure 227, and a second core region 229. The second core region 229 may extend in the Z direction perpendicular to the upper surface of the lower structure 2 to penetrate the stacked structure 6. Each of the first data storage structure 20a, the second data storage structure 20b, the third data storage structure 220a, and the fourth data storage structure 220b may include a first dielectric layer 21, a data storage layer 23, and a second dielectric layer 25, which are substantially the same as described above.

[0151] When viewed in a plan view (e.g., in a plane defined by the X and Y directions), the two side surfaces of the first core region 29 (e.g., in the X direction) can contact the first separation structure 235a.

[0152] In the plan view, in the second vertical storage structure 218a between the second separation structure 235b' and the first separation structure 235a that are adjacent to each other, one side surface of the second core region 229 can contact the first separation structure 235a, and the other side surface of the second core region 229 can be spaced apart from the second separation structure 235b' in the X direction.

[0153] The second channel semiconductor structure 227 may cover the side surface, bottom surface, and top surface of the second core region 229 between the spaced-apart portions of the stacked structure 6, the side surface of the second core region 229 contacting the first spacer 235a structure. A portion of the second channel semiconductor structure 227 may be located between the spaced-apart second core region 229 and the second separation structure 235b'. In a plan view, the second channel semiconductor structure 227 may have a "C" shape. For example, the second channel semiconductor structure 227 may extend from the first portion 227a and the second portion 227b between the second core region 229 and the stacked structure 6 to the second core region 229 and the second separation structure 235b', to have a "C" shape when viewed in a plan view. A third data storage structure 220a may be disposed between the first portion 227a of the second channel semiconductor structure 227 and the stacked structure 6, and a fourth data storage structure 220b may be disposed between the second portion 227b of the second channel semiconductor structure 227 and the stacked structure 6.

[0154] Reference Figure 13 In another exemplary embodiment, the semiconductor device may include a reference disposed on the lower structure 2. Figure 2B The stacking structure 6' described in the exemplary embodiment is the same as the stacking structure 6'. The planar shape of the stacking structure 6' can be the same as... Figure 11The regions indicated by the stacked structure 6 shown in the exemplary embodiment are substantially the same. Therefore, Figure 13 An exemplary embodiment can be combined with a stacked structure 6'. Figures 11 to 12 The exemplary embodiments are different.

[0155] Reference Figure 11 and Figure 12 The first partition structure 235a and the second partition structure 235b', which are substantially the same as the first partition structure and the second partition structure, can be set on the lower structure 2.

[0156] The semiconductor device may include a first vertical memory structure 18a' and a second vertical memory structure 218a' arranged alternately with a first discrete structure 235a and a second discrete structure 235b' in the X direction. The arrangement of the first vertical memory structure 18a' and the second vertical memory structure 218a' can be similar to that of a previously arranged... Figure 11 The arrangement of the first vertical storage structure 18a and the second vertical storage structure 218a described in the exemplary embodiments is substantially the same. The first partition structure 235a and the second partition structure 235b', as well as the first vertical storage structure 18a' and the second vertical storage structure 218a', can penetrate the stack structure 6' (e.g., in the Z direction) and can divide the stack structure 6' in the Y direction.

[0157] The semiconductor may include a first vertical memory structure 18a' between the first separation structures 235a and a second vertical memory structure 218a' adjacent to the second separation structure 235b'. The second vertical memory structure 218a' may be disposed between the second separation structure 235b' and the first separation structure 235a, which are adjacent to each other.

[0158] Figure 13 The first vertical storage structure 18a' in the exemplary embodiment may include Figure 2B The first data storage structure 20a' and the second data storage structure 20b', Figure 2B The channel semiconductor layer 27' and Figure 2B The core area 29', these are related to the above in Figure 2B The same as described in the exemplary embodiments.

[0159] The second vertical memory structure 218a' may include a third data storage structure 220a' and a fourth data storage structure 220b', a second channel semiconductor structure 227', and a second core region 229'. The second core region 229' may extend in the Z direction perpendicular to the upper surface of the lower structure 2 to penetrate the stacked structure 6'. Figure 2BEach of the first data storage structure 20a', the second data storage structure 20b', the third data storage structure 220a', and the fourth data storage structure 220b' may include a first dielectric layer 21, a data storage layer 23, and a second dielectric layer 25 that are substantially the same as those described above.

[0160] In the cross-sectional structure taken along line IIe-IIe', in the second vertical storage structure 218a' between the adjacent second separation structure 235b' and the first separation structure 235a, the entire side surface of the second core region 229' facing the first separation structure 235a can contact the first separation structure 235a, and the upper side of the second core region 229' facing the second separation structure 235b' (e.g., through the second channel semiconductor structure 227') is spaced apart from the second separation structure 235b', while the lower side of the second core region 229' facing the second separation structure 235b' can directly contact the second separation structure 235b'.

[0161] The second channel semiconductor structure 227' can cover the side and bottom surfaces of the second core region 229' between the spaced-apart portions of the stacked structure 6'. The planar shape of the second channel semiconductor structure 227' can have the same as described above. Figure 11 and Figure 12 The second channel semiconductor structure 227 of the exemplary embodiment has a planar shape that is substantially the same as that of the second channel semiconductor structure 227 (e.g., a "C" shape). The second channel semiconductor structure 227' can extend from the first portion 227a' and the second portion 227b' between the second core region 229' and the stacked structure 6' to the upper side of the second core region 229' and the second separation structure 235b', so as to have a "C" shape when viewed in a planar view (e.g., in a plane defined by the X and Y directions).

[0162] The third data storage structure 220a' may be disposed (e.g., in the Y direction) between the first portion 227a' of the second channel semiconductor structure 227' and the stacked structure 6'. The fourth data storage structure 220b' may be disposed (e.g., in the Y direction) between the second portion 227b' of the second channel semiconductor structure 227' and the stacked structure 6'.

[0163] Reference Figure 14 In a modified example of an exemplary embodiment, the semiconductor device may include a lower structure 2, a stacked structure 6', a first separation structure 235a, a second separation structure 235b, and a first vertical memory structure 18a, which are consistent with the reference... Figure 13 The exemplary embodiments described herein are identical.

[0164] Reference Figure 13Compared to the second vertical storage structure 218a' described in the exemplary embodiment, Figure 14 The semiconductor device includes a second vertical memory structure 218a.

[0165] The second vertical memory structure 218a” may include a third data storage structure 220” and a fourth data storage structure 220b”, a second channel semiconductor structure 227”, and a second core region 229”. The second core region 229” may extend in the Z direction perpendicular to the upper surface of the lower structure 2 to penetrate the stacked structure 6'. The third data storage structure 220a” and the fourth data storage structure 220b” may be connected with Figure 13 The third data storage structure 220a' and the fourth data storage structure 220b' of the exemplary embodiment are basically the same.

[0166] In the cross-sectional structure taken along line IIe-IIe', in the second vertical storage structure 218a” between the adjacent first separation structure 235a and second separation structure 235b’, the entire side surface of the second core region 229” facing the first separation structure 235a can contact the first separation structure 235a, the lower side surface of the second core region 229” facing the second separation structure 235b’ (e.g., through the second channel semiconductor structure 227”) is spaced apart from the second separation structure 235b’, and the upper side surface of the second core region 229” facing the second separation structure 235b’ can directly contact the second separation structure 235b’.

[0167] The second channel semiconductor structure 227” can cover the side and bottom surfaces of the second core region 229” between the spaced-apart portions of the stacked structure 6'. The planar shape of the second channel semiconductor structure 227” can have the same as... Figure 11 and Figure 12 The second channel semiconductor structure 227 of the exemplary embodiment has a planar shape that is substantially the same as the planar shape (e.g., a "C" shape). For example, the second channel semiconductor structure 227" can extend from the first portion 227a" and the second portion 227b" between the second core region 229" and the stacked structure 6', and the portion covering the lower surface of the second core region 229" to between the lower surface of the second core region 229" and the second separation structure 235b', so as to have a "C" shape when viewed in a plan view.

[0168] Reference Figure 15 This describes a modified example of a semiconductor device based on an example embodiment. Figure 15 It is shown Figure 11 A plan view of an example of a modification of the planar shape of the vertical storage structures 18a and 218a in an exemplary embodiment.

[0169] refer to Figure 15 An exemplary embodiment of the semiconductor device may include a stacked structure 6 and a first separation structure 235a and a second separation structure 235b' with reference to Figure 11 The exemplary embodiments described are substantially the same.

[0170] Separating structures 235a and 235b' and vertical memory structures 318a and 318a' are arranged alternately in the X direction. The semiconductor device includes first and second vertical memory structures 318a and 318a'. The first vertical memory structure 318a is disposed between the first separating structures 235a, and the second vertical memory structure 318' is adjacent to the second separating structure 235b' (e.g., disposed on each side of the second separating structure 235b'). The second vertical memory structure 318a' may be disposed between the second separating structure 235b' and the first separating structure 235a, which are adjacent to each other (e.g., in the X direction).

[0171] The first vertical storage structure 318a can be a structure that has access to... Figure 11 The exemplary embodiment of the first vertical storage structure 18a has a modified planar shape (e.g., in a plane defined by the X and Y directions) of the vertical storage structure, and the second vertical storage structure 318a' may be a vertical storage structure having Figure 11 The second vertical storage structure 218a of the exemplary embodiment is a vertical storage structure with a modified planar shape.

[0172] The X-direction width of the first vertical storage structure 318a can be smaller than the X-direction width of the second vertical storage structure 318a'. The Y-direction width of the first vertical storage structure 318a can be approximately equal to the Y-direction width of the second vertical storage structure 318a'.

[0173] In each of the first vertical storage structure 318a and the second vertical storage structure 318a', with Figure 11 Compared to the first vertical storage structure 18a and the second vertical storage structure 218a with curved sides facing the stacking structure in the exemplary embodiment, the sides facing the stacking structure 6 can have a linear shape that is parallel to each other (e.g., extending in the X direction).

[0174] Reference Figure 16 This describes a modified example of a semiconductor device based on an example embodiment. Figure 16 It is shown Figure 1 A plan view of a modified example of the planar shape of the vertical storage structure 18a.

[0175] refer to Figure 16 In an exemplary embodiment, the semiconductor device may include a semiconductor device with Figure 1The stacked structure 6 is the same as the stacked structure in the exemplary embodiment. The semiconductor device may also include a stacked structure similar to that in the reference embodiment. Figure 1 The exemplary embodiment describes separation structures 35 that are substantially the same as separation structures 435a and 435b. The first separation structure 435a and the second separation structure 435b may include the first separation structure 435a and the second separation structure 435b arranged alternately in the X direction.

[0176] The semiconductor device may include vertical memory structures 418a and 418b, which have a reference Figure 1 The exemplary embodiment describes a modification of the planar shape of the vertical storage structure 18a.

[0177] Each of the vertical memory structures 418a and 418b may include data storage structures 420a and 420b, a channel semiconductor structure 427, and a core region 429. Data storage structures 420a and 420b may have a reference... Figure 1 The exemplary embodiment describes a modified data storage structure 20 with a planar shape (e.g., in a plane defined by the X and Y directions), wherein the channel semiconductor structure 427 may have a reference... Figure 1 The exemplary embodiment described herein is a modified channel semiconductor structure with a planar shape of channel semiconductor structure 27. Core region 429 may be having a... Figure 1 The core region 29 described in the exemplary embodiment is a modified core region with a planar shape.

[0178] The semiconductor device includes a first vertical memory structure 418a and a second vertical memory structure 418b alternately arranged in the X direction. Each first vertical memory structure 418a may have a width that gradually decreases in the Y direction toward the X direction. Each second vertical memory structure 418b may have a width that gradually increases in the Y direction toward the X direction. However, exemplary embodiments of the inventive concept are not limited thereto.

[0179] Each vertical storage structure 418a and 418b may have a side facing the stacked structure 6, and the distance between the sides of each of the first vertical storage structure 418a and the second vertical storage structure 418b facing the stacked structure 6 may gradually narrow or gradually widen in the direction from one of the separation structures 435a and 435b toward the other separation structure.

[0180] The first separation structure 435a and the second separation structure 435b can be circular and can have the same width in the X and Y directions.

[0181] Figure 17 An example is shown in which the first separation structure 435a and the second separation structure 435b have different widths in the X direction. Figure 17 It is shown Figure 16 A plan view of an example of a modification of the planar shape of the separate structures 435a and 435b in an exemplary embodiment.

[0182] refer to Figure 17 An exemplary embodiment, with Figure 16 Compared to the second separation structure 435b in the exemplary embodiment, the semiconductor device may include a second separation structure 435b' with an increased width. For example, each first separation structure 435a may have a first width in the X direction, and each second separation structure 435b may have a second width in the X direction that is greater than the first width. Figure 17 The first separation structure 435a, the first vertical storage structure 418a, and the second vertical storage structure 418b of the exemplary embodiment can be combined with... Figure 16 Those exemplary embodiments are substantially the same.

[0183] refer to Figure 18A and Figure 18B This section will describe a modified example of a semiconductor device according to an exemplary embodiment. Figure 18A This is a plan view illustrating a modified example of a semiconductor device according to an example embodiment. Figure 18B It shows along Figure 18A A cross-sectional view of the area intercepted by the line If-If'.

[0184] refer to Figure 18A and Figure 18B In an exemplary embodiment, the semiconductor device includes a semiconductor device with Figure 1 and Figure 2A The exemplary embodiment uses the same stacking structure 6, vertical storage structure 18a, and separation structure 35.

[0185] A separation pattern 90 can be provided to penetrate the stacked structure 6. The separation pattern 90 can extend in the X direction. The side surface of the separation pattern 90 in the Y direction can be wavy. The separation pattern 90 can be provided in the Y direction between multiple vertical storage structures 18a arranged sequentially in the X direction and multiple vertical storage structures 18a arranged sequentially in the X direction.

[0186] The separation pattern 90 may include an isolation core pattern 90b that penetrates the stacked structure 6, and an isolation spacer 90a between the isolation core pattern 90b and the stacked structure 6 (e.g., in the Y direction).

[0187] In an exemplary embodiment, the isolation core pattern 90b and the isolation spacer 90a may be formed of an insulating material. However, exemplary embodiments of the present invention are not limited thereto.

[0188] For example, in another exemplary embodiment, the isolation core pattern 90b may be formed of a conductive material, and the isolation spacer 90a may be formed of an insulating material.

[0189] refer to Figure 19A and Figure 19B The exemplary embodiments will be described below, including examples of modifications to the semiconductor device according to the exemplary embodiments. Figure 19A This is a plan view illustrating a modified example of a semiconductor device according to an exemplary embodiment. Figure 19B It shows along Figure 19A A cross-sectional view of the region intercepted by lines V-V' and VI-VI'.

[0190] refer to Figure 19A and Figure 19B In an exemplary embodiment, the semiconductor device may include a semiconductor device with Figure 1 and Figure 2A The lower structure 2 and stacked structure 6 described in the exemplary embodiments are the same as those in the stacked structure.

[0191] On the lower structure 2, the first vertical storage structure 518a, the second vertical storage structure 518b, and the separation structure 535 can be arranged (e.g., in the Z direction) to penetrate the stacked structure 6. The separation structure 535 can have a line shape extending in the X direction.

[0192] The first vertical storage structure 518a and the second vertical storage structure 518b can be separated in the Y direction by the separation structure 535.

[0193] The first vertical storage structure 518a and the second vertical storage structure 518b can be mirror-symmetric structures, wherein the separating structure 535 (e.g., in the Y direction) is located between the first vertical storage structure 518a and the second vertical storage structure 518b. The first vertical storage structure 518a and the second vertical storage structure 518b can be hemispherical.

[0194] Each first vertical memory structure 518a may include a first data storage structure 520a, a first channel semiconductor layer 527a, and a first core region 529a. Each second vertical memory structure 518b may include a second data storage structure 520b, a second channel semiconductor layer 527b, and a second core region 529b.

[0195] Each of the first data storage structure 520a and the second data storage structure 520b may include references. Figure 1 and Figure 2A The same first dielectric layer 21, data storage layer 23 and second dielectric layer 25 are described in the exemplary embodiments.

[0196] In a plan view (e.g., in a plane defined by the X and Y directions), the side surfaces of the first core region 529a and the second core region 529b may be convex in the direction facing the first channel semiconductor layer 527a and the second channel semiconductor layer 527b. In a plan view, the side surfaces of the first vertical memory structure 518a and the second vertical memory structure 518b are convex in the direction facing the stacked structure 6.

[0197] Reference Figure 19C The exemplary embodiments described herein illustrate examples of modifications to the planar shape of the first vertical storage structure 518a and the second vertical storage structure 518b. Figure 19C This is an enlarged plan view showing a pair of first vertical storage structures 518a' and second vertical storage structures 518b'.

[0198] refer to Figure 19C In an exemplary embodiment, the semiconductor device includes a pair of first vertical memory structures 518a' and second vertical memory structures 518b', which are mirror-symmetric structures relative to a separate structure 535 separating the first vertical memory structures 518a' and second vertical memory structures 518b' in the Y direction. The first vertical memory structure 518a' may include a first data storage structure 520a', a first channel semiconductor layer 527a', and a first core region 529a'. Each second vertical memory structure 518b' may include a second data storage structure 520b', a second channel semiconductor layer 527b', and a second core region 529b'. Figure 19A Compared to the first vertical storage structure 518a and the second vertical storage structure 518b in the exemplary embodiment, each of the first vertical storage structure 518a' and the second vertical storage structure 518b' may have an elongated hemispherical shape in the Y direction.

[0199] Reference Figure 20A This describes a modified example of a semiconductor device based on an example embodiment. Figure 20A It shows along Figure 1 A modified cross-sectional view of the area intercepted by lines Ia-Ia' and IIa-IIa' in the diagram.

[0200] refer to Figure 1 and Figure 20A In an exemplary embodiment, the semiconductor device may include, according to Figure 1 and Figure 2A The vertical storage structure 18a in the exemplary embodiment is a modified vertical storage structure 618. Although referenced Figure 1 and Figure 2A An exemplary embodiment is described Figure 20AThe modified vertical storage structure 618, but the modified vertical storage structure 618 can be included as at least one of the vertical storage structures. Figures 2B to 19C In any exemplary embodiment described herein, the vertical storage structure 618 will be described primarily, and descriptions of other components will be omitted.

[0201] The vertical memory structure 618 may include a data storage structure 620, a channel semiconductor structure 627, and a core region 629.

[0202] The core region 629 may (e.g., in the Z direction) penetrate the stacked structure 6. In an exemplary embodiment, as referenced... Figure 2A As described in the exemplary embodiments, the core region 629 may be formed of an insulating material such as silicon oxide. In another exemplary embodiment, the core region 629 may include a lower core region, for example, in Figure 2D In an exemplary embodiment, the lower core region 29' is formed by an insulating material and an upper core region having N-type conductivity.

[0203] Between the first stacked structure and the second stacked structure (see Figure 1 (6a and 6b), the channel semiconductor structure 627 can cover the bottom and side surfaces of the core region 629. The channel semiconductor structure 627 may include a first channel semiconductor layer 627a disposed between the core region 629 and the first stacked structure. Figure 1 6a) and the second channel semiconductor layer 627b disposed between the core region 629 and the second stacked structure. Figure 1 (6b).

[0204] The data storage structure 620 may include a first data storage structure 620a between the first stacked structure 6a and the first channel semiconductor layer 627a, and a second data storage structure 620b between the second stacked structure 6b and the second channel semiconductor layer 627b.

[0205] Each of the first data storage structure 620a and the second data storage structure 620b may include a first dielectric layer 621, a plurality of data storage layers 623, and a second dielectric layer 625. The plurality of data storage layers 623 may be located between the first dielectric layer 621 and the second dielectric layer 625. The plurality of data storage layers 623 may be spaced apart from each other in the Z direction perpendicular to the upper surface of the lower structure 2.

[0206] The first dielectric layer 621 may be in direct contact with the stacked structure 6, and the second dielectric layer 625 may be in direct contact with the channel semiconductor structure 627. In an exemplary embodiment, the first dielectric layer 621 may include silicon oxide or silicon oxide doped with impurities. The second dielectric layer 625 may include silicon oxide and / or a high-k dielectric. However, exemplary embodiments of the present invention are not limited thereto.

[0207] Each of the first data storage structure 620a and the second data storage structure 620b may protrude in the Y direction toward the gate layer 12 of the stacked structure 6 in a region including multiple data storage layers 623.

[0208] In an exemplary embodiment, the plurality of data storage layers 623 may be charge trapping layers capable of trapping charge. For example, data storage layers 623 may include a material configured to trap charge, such as silicon nitride. Data storage layers 623 may be used as data storage areas of NAND flash memory.

[0209] Reference Figure 20B A cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment. Figure 20B It is along Figure 1 The cross-sectional views taken from lines Ia-Ia' and IIa-IIa' show an example of a modified semiconductor device.

[0210] Reference Figure 1 and Figure 20B In the modified example, the semiconductor device may include... Figures 1 to 20A The vertical storage structure 618 described in the exemplary embodiments is different from the vertical storage structure 718.

[0211] The vertical memory structure 718 may include a gate dielectric layer 719, a channel semiconductor structure 727, a data storage structure 720, and a core region 729.

[0212] The core region 729 can be positioned on the lower structure 2 to penetrate the stacked structure 6 (e.g., in the Z direction). Figure 1 Between the first stacked structure 6a and the second stacked structure 6b, a channel semiconductor structure 727 can be disposed on the bottom surface and side surface of the core region 729. The channel semiconductor structure 727 may include structures disposed in the Y direction between the core region 729 and the first stacked structure (…). Figure 1 The first channel semiconductor layer 727a between the 6a) and the second stacked structure disposed in the core region 729 and the second stacked structure in the Y direction. Figure 1 The second channel semiconductor layer 727b is located between 6b and 6b.

[0213] In contrast to the previously described vertical storage structure, Figure 20BThe data storage structure 720 of the exemplary embodiment may be disposed (e.g., in the Y direction) between the channel semiconductor structure 727 and the core region 729. The data storage structure 720 may directly contact the side and bottom surfaces of the core region 729. The data storage structure 720 may include a first data storage structure 720a between the core region 729 and the first channel semiconductor layer 727a, and a second data storage structure 720b between the core region 729 and the second channel semiconductor layer 727b. The gate dielectric layer 719 may be disposed between the channel semiconductor structure 727 and the stacked structure 6.

[0214] In an exemplary embodiment, the data storage structure 720 may include a variable resistance material.

[0215] In an exemplary embodiment, the variable resistance material of the data storage structure 720 may include a transition metal oxide. For example, the data storage structure 720 may include a metal oxide, such as at least one compound selected from hafnium oxide and aluminum oxide.

[0216] In an exemplary embodiment, the variable resistance material of the data storage structure 720 may include one of SiOx, AlOx, MgOx, ZrOx, HfOx, SiNx, WOx, and TiOx, or a composite material including at least two or more of them. For example, the variable resistance material of the data storage structure 720 may be formed from a composite material such as Zr-Hf-Ox. However, exemplary embodiments of the present invention are not limited thereto, and the variable resistance material of the data storage structure 720 may be replaced by other materials that can be used as data storage materials for ReRAM. In another exemplary embodiment, the data storage structure 720 may include a phase change material. For example, the data storage structure 720 may be a phase change memory material, such as a chalcogenide material including at least one compound selected from Ge, Sb, and Te. Alternatively, the data storage structure 720 may also be a phase change memory material including at least one compound selected from Te and Se, and at least one compound selected from Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N, and In.

[0217] The above is for reference only. Figures 1 to 20A The exemplary embodiments of the stacked structure and vertical storage structure described herein (e.g., refer to Figure 18A and Figure 18B The described stack structure 6 and vertical storage structure 18a) can be replaced by stack structures and vertical storage structures modified in other forms, respectively. See references for details. Figures 20C to 20F The exemplary embodiments described herein illustrate various examples of stacked and vertical storage structures that can be replaced as described above. In this case, the components that can be replaced will be described primarily, while the description of components that are not replaced will be omitted. Figures 20C to 20F Various modifications of the semiconductor device are shown, illustrating exemplary embodiments of the concept according to the present invention. Figures 20C to 20F It is along Figure 18A A cross-sectional view of the area intercepted by the line If-If'.

[0218] refer to Figure 1 and Figure 20C An exemplary embodiment, in accordance with the above reference Figures 1 to 20A Compared to the stacked structure and vertical memory structure described in the exemplary embodiments, the semiconductor device may include... Figure 20C The stacked structure 806a and the vertical storage structure 818a are shown.

[0219] The stacked structure 806a may include an interlayer insulating layer 9, a planar conductive layer 812a, and a switching layer 810a. The interlayer insulating layer 9 and the planar conductive layer 812a may be stacked alternately and repeatedly (e.g., in the Z direction). Each switching layer 810a may be located between one side of each planar conductive layer 812a and the vertical storage structure 818a, and may extend to cover the upper and lower surfaces of each planar conductive layer 812a.

[0220] In an exemplary embodiment, each planar conductive layer 812a may include at least one material selected from metallic materials (e.g., at least one compound selected from W, Ti, Ta, etc.), metal nitrides (e.g., at least one compound selected from WN, TiN, TaN, etc.), and doped silicon. However, the exemplary embodiments of the present invention are not limited thereto, and the planar conductive layer 812a may also be formed from another conductive material as well as the aforementioned materials.

[0221] In an exemplary embodiment, the planar conductive layer 812a may be a gate layer.

[0222] The vertical storage structure 818a may include (e.g., in the Z direction) a core region 829a that penetrates the stacked structure 806a, a data storage structure 820a that extends between the core region 829a and the lower structure 2 (e.g., in the Z direction) and is also (e.g., in the Y direction) between the core region 829a and the stacked structure 806a, and a vertical conductive layer 827a disposed between the data storage structure 820a and the core region 829a. For example, the vertical conductive layer 827a may directly contact the bottom and side surfaces of the core region 829a and the data storage structure 820a.

[0223] In an exemplary embodiment, the vertical conductive layer 827a may include at least one material selected from metallic materials such as W, Ti, Ta, metal nitrides such as WN, TiN, TaN, and doped silicon. However, the exemplary embodiments of the present invention are not limited thereto, and the vertical conductive layer 827a may be formed from other materials as well as the materials described above. In an exemplary embodiment, the vertical conductive layer 827a may be a string wiring.

[0224] In an exemplary embodiment, the data storage structure 820a may include a variable resistance material, such as any one of SiOx, AlOx, MgOx, ZrOx, HfOx, SiNx, WOx, and TiOx, or a composite material including at least two or more of them (e.g., Hf-Zr-Ox). However, exemplary embodiments of the present invention are not limited thereto. For example, the material of the data storage structure 820a may be replaced with another variable resistance material different from the materials described above.

[0225] In an exemplary embodiment, the switching layer S10a may be formed of a material having switching device characteristics. For example, the switching layer 810a may include an oxide containing any one of Zr, Hf, Al, Ni, Cu, Mo, Ta, Ti, Zn, V, Nb, and W, or an oxide including at least two or more of them. However, exemplary embodiments of the present invention are not limited thereto. For example, in addition to the materials described above, another switching material that can be used as a switching element may be used instead of the material of the switching layer 810a.

[0226] In an exemplary embodiment, the core region 829a may include an insulating material, such as silicon oxide. The core region 829a may also include voids in the insulating material.

[0227] Reference Figure 1 and Figure 20D In a modified example of an exemplary embodiment, with in Figure 20C Compared to the stacked structure 806a described in the exemplary embodiments, the semiconductor device may include Figure 20D The stacked structure 806b shown is illustrated. Figure 20D The semiconductor device in the exemplary embodiments may include a reference Figure 20C The vertical storage structure described is the same as the vertical storage structure 818a.

[0228] The stacked structure 806b may include an interlayer insulating layer 9, a planar conductive layer 812b, and a switching layer 810b. The interlayer insulating layer 9 and the planar conductive layer 812b may be stacked alternately and repeatedly (e.g., in the Z direction). Each switching layer 810b may be located (e.g., in the Y direction) between one side of each of the planar conductive layers 812b adjacent to the vertical storage structure 818a and the vertical storage structure 818a. One side surface of each switching layer 810b may directly contact one side of the planar conductive layer 812b, and the other side surface of each switching layer 810b may directly contact the data storage structure 820a. The interlayer insulating layer 9 and the planar conductive layer 812b may be stacked alternately to directly contact each other. The upper and lower surfaces of the switching layer 810b may directly contact the lower and upper surfaces of the interlayer insulating layer 9, respectively.

[0229] In an exemplary embodiment, the planar conductive layer 812b and the switching layer 810b may be derived from a reference. Figure 20C The planar conductive layer 812a and the switching layer 810a described in the exemplary embodiment are formed of substantially the same material.

[0230] Reference Figure 1 and Figure 20E In another exemplary embodiment, with Figure 20C Compared to the vertical storage structure 818a shown in the exemplary embodiments, the semiconductor device may include Figure 20E The vertical storage structure 818b is shown in the diagram. (Compared to...) Figure 18A Compared to the discrete structure 35, semiconductor devices may also include Figure 20E The separation structure 835 is shown. The separation structure 835 can be combined with... Figure 19A and Figure 19B The separation structure 535 shown in the exemplary embodiment is substantially the same. The planar shape of the vertical storage structure 818b can be similar to... Figure 19A In the exemplary embodiment, the first vertical storage structure 518a and the second vertical storage structure 518b have substantially the same planar shape and are separated by a separate structure 835 to... Figure 19A The separation structure 535 is separated in essentially the same way. Semiconductor devices may include... Figure 20C The stacking structure described in the exemplary embodiment is the same as the stacking structure 806a.

[0231] The vertical storage structure 818b may include: a core region 829b, which passes through at least the planar conductive layer 812a of the stacked structure 806a; a data storage structure 820b, disposed on both sides of the core region 829b and between one side of the core region 829b and the stacked structure 806a; and a vertical conductive layer 827b, which is located between the data storage structure 820b and the core region 829b. One side surface of the data storage structure 820b may directly contact the side surface of the stacked structure 806a, and the other side surface of the data storage structure 820b may directly contact the vertical conductive layer 827b.

[0232] The separation structure 835 can (e.g., in the Z direction) penetrate the vertical memory structure 818b and the stacked structure 806a, and can extend into the lower structure 2. The separation structure 835 can penetrate the core region 829b and extend downwards into the lower structure 2, while dividing the vertical conductive layer 827b. For example, the separation structure 835 can extend through the bottom surface of the vertical conductive layer 827b. Therefore, the separation structure 835 can divide the vertical memory structure 818b into two spaced-apart sections.

[0233] refer to Figure 1 and Figure 20F In an exemplary embodiment, the semiconductor device may be included in Figure 20D The stacked structure 806b is shown in the exemplary embodiment. Additionally, the semiconductor device may be included in... Figure 20E The exemplary embodiment shows a vertical storage structure 818b and a separate structure 835. Therefore, in Figure 20E In the exemplary embodiment, the vertical storage structure 818b and the separation structure 835 can be configured to penetrate the stacking structure 806b (e.g., in the Z direction), as shown below. Figure 20D As described in the exemplary embodiments.

[0234] In an exemplary embodiment, the switching layer 810b of the stacked structure 806b may include (e.g., in the Y direction) a switching layer between the planar conductive layer 812b and the vertical storage structure 818b, and (e.g., in the Y direction) a switching layer between the planar conductive layer 812b and the separation structure 835.

[0235] In another exemplary embodiment, the semiconductor device may not include a switching layer between the planar conductive layer 812b and the separation structure 835. For example, the switching layer 810b of the stacked structure 806b may be between the planar conductive layer 812b and the vertical memory structure 818b, but may not be between the planar conductive layer 812b and the separation structure 835.

[0236] Therefore, the above references Figures 1 to 20FEach vertical storage structure described in the exemplary embodiments may include a storage cell of any one of a NAND flash memory device, a phase-change memory device, and a variable resistance memory device.

[0237] Reference Figure 21 Examples of methods for forming a semiconductor device according to exemplary embodiments are described. Figure 21 This is a flowchart illustrating an exemplary embodiment of a method for forming a semiconductor device according to a concept conceived in this invention.

[0238] refer to Figure 21 In an exemplary embodiment, in block S10, a stacked structure including an interlayer insulating layer and a gate layer can be formed. In block S20, an opening can be formed to penetrate the stacked structure. In block S30, a vertical memory structure can be formed in the opening. In block S40, a discrete structure can be formed. In block S50, pad and wiring processes can be performed.

[0239] Reference Figure 1 and Figure 2A as well as Figures 22A to 22C An exemplary embodiment of a method for forming a semiconductor device is described. Figure 22A This is a plan view illustrating a method for forming a semiconductor device according to an exemplary embodiment. Figure 22B and Figure 22C It shows along Figure 22A A cross-sectional view of the region intercepted by lines Ia-Ia' and IIa-IIa'.

[0240] refer to Figure 22A and Figure 22B as well as Figure 21 Within frame Si0, a stacked structure 6, including an interlayer insulating layer 9 and a gate layer 12, can be formed. The stacked structure 6 can be formed in conjunction with... Figure 2A The lower structure 2 shown in the exemplary embodiment is substantially the same as the lower structure 2 shown in the example. In block S20, an opening 15 penetrating the stacked structure 6 can be formed (e.g., in the Z direction). In block S30, a vertical storage structure 18 can be formed in the opening 15. The formation of the vertical storage structure 18 may include forming a data storage structure 20 on a corresponding sidewall of the opening 15 and forming a channel semiconductor structure 27 conformally covering the bottom surface and sidewalls of the opening 15 where the data storage structure 20 is formed. For example, the channel semiconductor structure 27 may directly contact the inner surface of the data storage structure 20. A core region 29 may be formed on the channel semiconductor structure 27 to fill the opening 15. For example, the core region 29 may directly contact the inner surface and bottom surface of the channel semiconductor structure 27.

[0241] In an exemplary embodiment, each vertical storage structure 18 may be circular or elliptical in a plan view (e.g., in a plane defined by the X and Y directions).

[0242] refer to Figure 22C An exemplary embodiment may form an isolation hole 33 that penetrates the stacked structure 6 (e.g., in the Z direction).

[0243] refer to Figure 1 , Figure 2A and Figure 21 In an exemplary embodiment, a separation structure 35 may be formed in block S40. The separation structure 35 may be formed in... Figure 22C In the isolation hole 33. Therefore, a reference can be formed. Figure 1 and Figure 2A The exemplary embodiments described herein include a vertical storage structure 18a and a separate structure 35.

[0244] In box S50, as shown in the reference Figure 21 Perform pad and routing processes as described. Pad and routing processes can be processes such as: forming pads and routing... Figure 7A and Figure 7B The first pad 152a and the second pad 152b and / or shown in the exemplary embodiment Figure 8A and Figure 8B The exemplary embodiments of the first pad 252a and the second pad 252b, etc., pads, and the formation of such Figure 6A and Figure 6B The exemplary embodiment of the wire 60, Figure 7A and Figure 7B The exemplary embodiment of the wire 180 and Figure 8A and Figure 8B At least one of the first conductor 180a and the second conductor 180b in an exemplary embodiment.

[0245] Reference Figure 23A and Figure 23B An exemplary embodiment describing a modification of the method for forming a semiconductor device. Figure 23A This is a plan view illustrating a modified example of a method for forming a semiconductor device according to an exemplary embodiment. Figure 23B It shows along Figure 23A A cross-sectional view of the region intercepted by lines VII-VII' and VIII-VIII'.

[0246] refer to Figure 23A and Figure 23B An exemplary embodiment may be formed as a reference. Figure 22A and Figure 22B The stacked structure 6. Figure 22A and Figure 22BThe vertical memory structure 18 shown, having a circular or elliptical shape, can be formed as a linear preliminary vertical memory structure 18'. Therefore, each preliminary vertical memory structure 18' may include (e.g., in the Y direction) a data storage structure 20', a channel semiconductor structure 27', and a core region 29' formed sequentially. In an exemplary embodiment, the sides of the vertical memory structure 18' may be wavy. However, exemplary embodiments of the inventive concept are not limited thereto, and the sides of the vertical memory structure 18' may be formed in various other shapes, such as straight lines.

[0247] refer to Figure 9 or Figure 10 An exemplary embodiment, Figure 9 The separation structure 235 or Figure 10 The first separation structure 235a and the second separation structure 235b can be formed as a penetrating structure. Figure 23A The linear preliminary vertical storage structure 18' is shown. It can be constructed from separate structures (e.g., Figure 9 The separation structure 235 or Figure 10 The first separation structure 235a and the second separation structure 235b) are related to Figure 23A Each initial vertical storage structure 18' is divided to form a vertical storage structure 18a.

[0248] Reference Figure 24 To describe the formation Figure 10 or Figure 11 The vertical storage structure 18a and the separate structure (e.g., described in the text) Figure 10 First separation structure 235a and second separation structure 235b or Figure 11 The method of the first separation structure 235a and the second separation structure 235b'. Figure 24 This is a plan view illustrating a modified method for forming a semiconductor device according to an exemplary embodiment.

[0249] refer to Figure 24 An exemplary embodiment, Figure 23A The initial vertical memory structure 18' having a linear shape can be formed as an initial vertical memory structure 18" having a partially cut linear shape. Each initial vertical memory structure 18" may include a data storage structure 20", a channel semiconductor structure 27", and a core region 29". The region 6s between the ends of the initial vertical memory structure 18" arranged in the X direction may be filled by the stacked structure 6 and may be referred to as a "support". For example, the region between the ends of the initial vertical memory structure 18" arranged in the X direction (e.g., the support 6s) may be used to prevent the stacked structure 6 from deforming or collapsing during the process of forming an opening by etching the stacked structure 6 to form the initial vertical memory structure 18".

[0250] Return to reference Figure 10 In an exemplary embodiment, the separation structures 235a and 235b can be formed as (e.g., in the Z direction) penetrating. Figure 24 The initial vertical storage structure in 18". Figure 24 The initial vertical storage structure 18” can be divided by separate structures 235a and 235b to form vertical storage structure 18a. (Referring to the above...) Figure 10 In the exemplary embodiments described, the second separation structure 235h, having a relatively large width (e.g., in the X direction), can penetrate the separation structures 235a and 235b. Figure 24 The support members between the ends of the initial vertical storage structure 18” in the middle ( Figure 24 (6s), thereby removing Figure 24 The support member 6s shown in the figure.

[0251] Return to reference Figure 11 An exemplary embodiment may form (e.g., in the Z direction) penetration. Figure 24 The initial vertical storage structure 18” is divided into separate structures 235a and 235b'. Figure 24 The initial vertical storage structure 18” in the middle can be made by Figure 11 The separation structures 235a and 235b' shown are divided to form vertical storage structures 18a and 218a.

[0252] The above references Figure 11 Of the described separation structures 235a and 235b', the second separation structure 235b', having a relatively large width, can penetrate... Figure 24 The initial vertical storage structure 18” between the ends Figure 24 The support member 6s shown is removed, and Figure 24 A portion of the end of the preliminary vertical storage structure 18” shown can be retained. (Reference) Figure 11 The exemplary embodiment of the second vertical storage structure 218a described herein may include Figure 24 The remaining ends of the preliminary vertical storage structure 18” shown.

[0253] Next, we will refer to Figures 25A to 25C Exemplary embodiments are used to describe the formation of reference. Figure 13 Examples of methods for semiconductor devices described in exemplary embodiments. Figures 25A to 25C It is along Figure 11 Cross-sectional views of the semiconductor device taken by lines Ie-Ie' and IIe-IIe' to illustrate the formation of the reference. Figure 13 Examples of methods for describing semiconductor devices.

[0254] refer to Figure 11 and Figure 25AIn an exemplary embodiment, the lower stacked structure 7a may be formed on the lower structure 2. For example, the lower stacked structure 7a may be formed directly on the upper surface of the lower structure 2. The lower stacked structure 7a may include (e.g., in the Z direction) alternatingly and repeatedly stacked first interlayer insulating layer 9a and first gate layer 12a. The uppermost layer of the first interlayer insulating layer 9a and the first gate layer 12a may be a first intermediate interlayer insulating layer 9M1. The upper stacked structure 7b may include (e.g., in the Z direction) alternatingly and repeatedly stacked second interlayer insulating layer 9b and second gate layer 12b. The uppermost layer of the second interlayer insulating layer 9b and the second gate layer 12b may be an upper interlayer insulating layer 9U, and its lowermost layer may be a second intermediate interlayer insulating layer 9M2.

[0255] It can form a lower sacrificial pattern 10 that penetrates the lower stacked structure 7a.

[0256] In an exemplary embodiment, the planar shape of the lower sacrificial pattern 10 (e.g., in a plane defined by the X and Y directions) can be consistent with... Figure 23A The planar shapes of the initial vertical storage structures 18' shown in the exemplary embodiments are the same or similar. Therefore, each lower sacrificial pattern 10 may have a line shape extending in the X direction.

[0257] The upper stacked structure 7b may be formed (e.g., in the Z direction) on the lower stacked structure 7a and the lower sacrificial pattern 10. The upper stacked structure 7b may include (e.g., in the Z direction) alternately and repeatedly stacked second interlayer insulating layers 9b and second gate layers 12b. The uppermost layer of the second interlayer insulating layers 9b and the second gate layer 12b may be an upper interlayer insulating layer 9U, and its lowermost layer may be a second intermediate interlayer insulating layer 9M2. The lower stacked structure 7a and the upper stacked structure 7b may constitute a stacked structure 6'.

[0258] refer to Figure 11 and Figure 25B An exemplary embodiment may form an upper opening 33a penetrating the upper stacked structure 7b. The planar shape of the upper opening 33a may be a line shape in which a portion is disrupted, while overlapping with the lower sacrificial pattern 10. For example, the planar shape of the upper opening 33a may be a line shape having ends facing each other, such as... Figure 24 The initial vertical storage structure 18” is shown. Therefore, a portion of the upper stacking structure 7b can be retained between the ends of the upper openings 33a facing each other in a linear shape. As described above, the portion of the upper stacking structure 7b retained between the ends of the upper openings 33a facing each other can be referred to as the upper support 6s'.

[0259] refer to Figure 11 and Figure 25CAn exemplary embodiment removes the lower sacrificial pattern 10 exposed by the upper opening 33a, thereby forming an opening 33a', the opening 33a' including Figure 25B The upper opening 33a is shown, along with the empty space formed by removing the lower sacrificial pattern 10. The upper support 6s' prevents the stacked structure 6' from deforming or collapsing, which could occur when the opening 33a' is formed.

[0260] Refer again Figure 11 and Figure 13 An exemplary embodiment, in Figure 25C A preliminary vertical storage structure is formed in the opening 33a' shown, and can subsequently be formed in Figure 11 and Figure 13 The first discrete structure 235a and the second discrete structures 235a and 235b' are described in the reference. Each preliminary vertical memory structure may include a data storage structure 20', a channel semiconductor structure 27', and a core region 29', which are related to the above reference. Figure 23A and Figure 23B The exemplary embodiments described therein are substantially the same.

[0261] The initial vertical storage structure is divided into a first separation structure 235a and a second separation structure 235b', thereby forming a reference. Figure 11 and Figure 13 The first vertical storage structure 18a and the second vertical storage structure 218a' are described. The second separation structure 235b', having a relatively large width, penetrates within the separation structures 235a and 235b' (e.g., in the X direction). Figure 25C The upper support member 6s' in the middle is removed Figure 25C The upper support member 6s' in the middle, a portion of the end of the initial vertical storage structure can be retained. Therefore, refer to Figure 11 and Figure 13 The exemplary embodiment of the second vertical storage structure 218a' described herein may include the remaining ends of the initial vertical storage structure.

[0262] Reference Figure 26A and Figure 26B Exemplary embodiments are used to describe the formation of reference. Figure 14 The method for the described semiconductor device. Figure 26A and Figure 26B It is along Figure 11 Cross-sectional views of the semiconductor device taken by lines Ie-Ie' and IIe-IIe' to illustrate the formation of the reference. Figure 14 Examples of methods for describing semiconductor devices.

[0263] refer to Figure 11 and Figure 26A ,refer to Figure 25A The described lower stacked structure 7a can be formed on the lower structure 2.

[0264] A lower sacrificial pattern 10 can be formed that penetrates the lower stacked structure 7a. The planar shape of the lower sacrificial pattern 10' can be... Figure 25B The upper opening 33a is essentially the same. For example, the planar shape of the lower sacrificial pattern 10' can be a line shape with ends facing each other, such as... Figure 24 The initial vertical storage structure 18” is shown. Therefore, a portion of the lower stacking structure 7a can be retained between the mutually facing ends of the lower sacrificial pattern 10'. Thus, the lower stacking structure 7a retained between the mutually facing ends of the lower sacrificial pattern 10' can be referred to as the “lower support 6s”.

[0265] For reference Figure 25A The upper stacking structure 7b can be formed (e.g., in the Z direction) on the lower stacking structure 7a and the lower sacrificial pattern 10'. Therefore, a stacking structure 6' including the lower stacking structure 7a and the upper stacking structure 7b can be formed.

[0266] An upper opening can be formed to penetrate the upper stacked structure 7b. The upper opening can have a line shape that overlaps with the lower sacrificial pattern 10' and the lower support 6s". Subsequently, the lower sacrificial pattern 10' can be removed to form an opening 33b, which includes the empty space formed by removing the lower sacrificial pattern 10' and the upper opening.

[0267] The lower support 6s” can prevent the stacked structure 6' from deforming or collapsing, which may occur when the opening 33b is formed.

[0268] Refer again Figure 11 and Figure 14 , as referenced above Figure 11 and Figure 13 The methods described are similar, in Figure 26B A preliminary vertical storage structure is formed in opening 33b. Then, a structure can be formed with reference... Figure 11 and Figure 14 The exemplary embodiment described herein uses the same first separation structure 235a and second separation structure 235b'. Therefore, the initial vertical storage structure is divided by the first separation structure 235a and the second separation structure 235b', thereby forming a first vertical storage structure 18a and a second vertical storage structure 218a", as referenced. Figure 11 and Figure 14 As described in the exemplary embodiments. The second separation structure 235b', having a relatively large width (e.g., in the X direction) in the separation structures 235a and 235b', passes through... Figure 26B The lower support member 6s in the middle is removed Figure 26B The lower support member 6s” in the middle, part of the end of the initial vertical storage structure can be retained. Therefore, refer to Figure 11 and Figure 14 The described second vertical storage structure 218a” may include the remaining ends of the initial vertical storage structure.

[0269] As described above, according to an exemplary embodiment, the separation structure and the vertical memory structure can separate the stacked structure into a first stacked structure and a second stacked structure. The vertical memory structure may include a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Since multiple data storage regions can be formed in the first data storage structure facing multiple gate layers that may be word lines of the first stacked structure, and multiple data storage regions can be formed in the second data storage structure facing multiple gate layers that may be word lines of the second stacked structure, the semiconductor device can have a high degree of integration.

[0270] Although exemplary embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.

Claims

1. A semiconductor device, comprising: Substructure; Multiple separate structures are disposed on the lower structure and spaced apart from each other in a first direction parallel to the upper surface of the lower structure; A vertical memory structure is disposed between adjacent discrete structures of the plurality of discrete structures. The vertical memory structure includes a core region, a channel semiconductor structure, and a data storage structure, wherein the adjacent discrete structures are in direct contact with the core region, the channel semiconductor structure, and the data storage structure. A stacked structure is provided on the lower structure. The stacking structure includes a first stacking structure and a second stacking structure. The first stacking structure and the second stacking structure are spaced apart from each other in a second direction by the plurality of separating structures and the vertical storage structure. The second direction is parallel to the upper surface of the lower structure and perpendicular to the first direction. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers that are alternately and repeatedly stacked on the lower structure. The channel semiconductor structure includes: a first channel semiconductor layer disposed between the core region and the first stacked structure along the second direction; and a second channel semiconductor layer disposed between the core region and the second stacked structure along the second direction. The data storage structure includes: a first data storage structure disposed along the second direction between the first stacked structure and the first channel semiconductor layer; and a second data storage structure disposed along the second direction between the second stacked structure and the second channel semiconductor layer. Each of the first data storage structure and the second data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer disposed between the first dielectric layer and the second dielectric layer. The side surfaces of the first and second stacked structures facing the vertical storage structure are concave in a first plan view defined by the first and second directions. The core region has a first side surface and a second side surface facing the adjacent separated structure in the first direction. The channel semiconductor structure has a third side surface and a fourth side surface facing the adjacent discrete structure in the first direction. Each of the first data storage structure and the second data storage structure has a data storage layer having a fifth side surface and a sixth side surface facing the adjacent separated structures in the first direction. In the first plan view, the first minimum distance between the first side surface and the second side surface of the core region is less than the second minimum distance between the fifth side surface and the sixth side surface of the data storage layer, and In the first planar view, the first minimum distance between the first side surface and the second side surface of the core region is greater than the third minimum distance between the third side surface and the fourth side surface of the channel semiconductor structure.

2. The semiconductor device of claim 1, wherein, The side surface of the core region facing the channel semiconductor structure is convex in the first planar view.

3. The semiconductor device of claim 2, wherein, The first and second side surfaces of the core region are concave in the first plan view.

4. The semiconductor device according to claim 2, wherein, The first and second side surfaces of the core region have line shapes that are parallel to each other in the first plan view.

5. The semiconductor device according to claim 1, wherein, In the first planar view, the length of the interface surface between the first data storage structure and the first channel semiconductor layer is greater than the length of the interface surface between the first channel semiconductor layer and the core region.

6. The semiconductor device according to claim 1, wherein, In the first planar view, the length of the interface surface between the first data storage structure and the first stacked structure is greater than the length of the interface surface between the first data storage structure and the first channel semiconductor layer.

7. The semiconductor device according to claim 1, wherein, Each separation structure includes a lower part and an upper part disposed on the lower part, and The width of the lower part is greater than the width of the upper part.

8. The semiconductor device according to claim 1, further comprising: Contact plugs disposed on the vertical storage structure are configured to be electrically connected to the first channel semiconductor layer and the second channel semiconductor layer; as well as The wires on the contact plug are configured to be electrically connected to the contact plug.

9. The semiconductor device according to claim 1, further comprising: A first pad is disposed on the vertical memory structure, and the first pad is configured to be electrically connected to the first channel semiconductor layer; A second pad is disposed on the vertical memory structure, and the second pad is configured to be electrically connected to the second channel semiconductor layer; A contact plug is disposed on the first pad, the contact plug being configured to be electrically connected to the first pad; as well as A wire is disposed on the contact plug, and the wire is configured to be electrically connected to the contact plug.

10. The semiconductor device according to claim 9, wherein, The channel semiconductor structure extends from the first channel semiconductor layer and the second channel semiconductor layer between the core region and the lower structure, and The data storage structure extends from the first data storage structure and the second data storage structure between the channel semiconductor structure and the lower structure.

11. The semiconductor device according to claim 1, further comprising: A first pad is disposed on the vertical memory structure, and the first pad is configured to be electrically connected to the first channel semiconductor layer; A second pad is disposed on the vertical memory structure, and the second pad is configured to be electrically connected to the second channel semiconductor layer; A first contact plug is disposed on the first pad and is configured to be electrically connected to the first pad. A second contact plug is disposed on the second pad and is configured to be electrically connected to the second pad. A first wire is disposed on the first contact plug, and the first wire is configured to be electrically connected to the first contact plug; as well as A second wire is disposed on the second contact plug and is configured to be electrically connected to the second contact plug. The first wire and the second wire are parallel to each other.

12. The semiconductor device according to claim 1, further comprising: The separation pattern penetrates the stacked structure and extends along the first direction. The separation pattern is spaced apart from the separation structure and the vertical storage structure in the second direction.

13. A semiconductor device, comprising: A first stacked structure and a second stacked structure are disposed on a substrate, and the first stacked structure and the second stacked structure are spaced apart from each other in a first direction parallel to the upper surface of the substrate. as well as Multiple discrete structures and multiple vertical memory structures are alternately arranged between the first stacked structure and the second stacked structure along a second direction parallel to the upper surface of the substrate and perpendicular to the first direction. Each of the multiple vertical memory structures includes a core region and a channel semiconductor structure, and the core region and the channel semiconductor structure are in direct contact with the corresponding discrete structure among the multiple discrete structures. Each of the first stacked structure and the second stacked structure includes multiple interlayer insulating layers and multiple gate layers that are alternately and repeatedly stacked on the substrate. Each of the plurality of vertical storage structures further includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. The side surfaces of the first and second stacked structures facing the plurality of vertical storage structures are concave in a first plan view defined by the first and second directions. The core region has a first side surface and a second side surface facing the corresponding separation structure in the first direction. The channel semiconductor structure has a third side surface and a fourth side surface facing the corresponding discrete structure in the first direction. Each of the first data storage structure and the second data storage structure has a data storage layer with a fifth side surface and a sixth side surface facing the corresponding separate structure in the first direction. In the first plan view, the first minimum distance between the first side surface and the second side surface of the core region is less than the second minimum distance between the fifth side surface and the sixth side surface of the data storage layer, and In the first planar view, the first minimum distance between the first side surface and the second side surface of the core region is greater than the third minimum distance between the third side surface and the fourth side surface of the channel semiconductor structure.

14. The semiconductor device according to claim 13, wherein, The plurality of separation structures include a plurality of first separation structures and a second separation structure disposed between adjacent first separation structures in the plurality of first separation structures, and Wherein, the width of each of the plurality of first separation structures in the second direction is smaller than the width of the second separation structure in the second direction.

15. The semiconductor device according to claim 13, wherein, The channel semiconductor structure includes a first channel semiconductor layer adjacent to the first stacked structure and a second channel semiconductor layer adjacent to the second stacked structure. The core region is disposed between the first channel semiconductor layer and the second channel semiconductor layer. The first data storage structure is disposed between the first stacked structure and the first channel semiconductor layer. The second data storage structure is disposed between the second stacked structure and the second channel semiconductor layer, and In the first plan view, the first side surface of the core region is convex in the direction toward the first stacked structure, and the second side surface of the core region is convex in the direction toward the second stacked structure.

16. The semiconductor device according to claim 13, wherein, Each of the first stacking structure and the second stacking structure includes a lower stacking structure and an upper stacking structure disposed on the lower stacking structure. Each of the plurality of vertical storage structures includes a lower storage portion that penetrates the lower stacking structure and an upper storage portion that penetrates the upper stacking structure, and The width of the upper surface of the lower storage portion is greater than the width of the lower surface of the upper storage portion.

17. A semiconductor device, comprising: A first stacked structure and a second stacked structure are disposed on a substrate, each of the first stacked structure and the second stacked structure comprising a plurality of interlayer insulating layers and a plurality of gate layers alternately and repeatedly stacked on the substrate; Multiple vertical memory structures are disposed between the first stacked structure and the second stacked structure and arranged in a first direction parallel to the upper surface of the substrate. Each of the multiple vertical memory structures includes a core region, a channel semiconductor structure, and a data storage structure. A separation structure, together with the plurality of vertical memory structures, fills the gap between the first stacked structure and the second stacked structure, and separates adjacent vertical memory structures among the plurality of vertical memory structures, wherein the separation structure is in direct contact with the core region, channel semiconductor structure, and data storage structure of the adjacent vertical memory structure; and The wires are disposed on the plurality of vertical storage structures and extend along a second direction perpendicular to the first direction. The channel semiconductor structure includes a first channel semiconductor layer and a second channel semiconductor layer that have a mirror-symmetric structure with respect to each other, and the data storage structure includes a first data storage structure and a second data storage structure that have a mirror-symmetric structure with respect to each other. The first data storage structure is disposed between the first channel semiconductor layer and the first stacked structure. The second data storage structure is disposed between the second channel semiconductor layer and the second stacked structure. The side surface of the first stacked structure facing the first data storage structure is concave. The side surface of the second stacked structure facing the second data storage structure is concave. The first channel semiconductor layer has a substantially uniform thickness and faces the first data storage structure in a plan view. The core region has a first side surface and a second side surface that are opposite to each other in the first direction. The channel semiconductor structure has a third side surface and a fourth side surface that are opposite to each other in the first direction. Each of the first data storage structure and the second data storage structure has a fifth side surface and a sixth side surface that are opposite to each other in the first direction. In the first plan view, the first minimum distance between the first side surface and the second side surface of the core region is less than the second minimum distance between the fifth side surface and the sixth side surface of the data storage layer. The channel semiconductor structure of the adjacent vertical memory structure has a third side surface facing the discrete structure in the first direction. The core region of the adjacent vertical storage structure has a first side surface facing the separated structure in the first direction, and In the plan view, the third side surface of the channel semiconductor structure is formed as a concave shape that is more recessed than the first side surface of the core region.

18. The semiconductor device according to claim 17, wherein, The core region is disposed between the first channel semiconductor layer and the second channel semiconductor layer.

19. The semiconductor device according to claim 17, wherein, The conductors include a first conductor and a second conductor that are adjacent to each other. The first channel semiconductor layer is configured to be electrically connected to the first wire, and The second channel semiconductor layer is configured to be electrically connected to the second wire.

20. The semiconductor device according to claim 17, wherein, In each of the plurality of vertical memory structures, the first channel semiconductor layer and the second channel semiconductor layer are configured to be electrically connected to one of the wires.

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