An easy-to-solder flip-chip LED chip

Abstract

The present invention discloses a flip-chip LED chip that is easy to weld, comprising a substrate, a light-emitting structure arranged on the substrate, a first electrode arranged on the light-emitting structure, a passivation layer arranged on the light-emitting structure and the first electrode, and a second electrode arranged on the passivation layer, wherein the passivation layer is provided with at least one electrode hole, and the electrode hole is filled with a conductive material of a preset hardness; wherein the conductive material is flush with the surface of the passivation layer, and forms a conductive connection between the first electrode and the second electrode, and forms a seamless connection with the passivation layer, the first electrode and the second electrode; the hardness of the conductive material is ≥80HBS. The flip-chip LED chip of the present invention solves the problem of different metal hardnesses between the passivation layer and the first electrode and the second electrode, reduces the void rate between the second electrode and the package substrate during package welding, and improves the welding performance of the chip.

Description

Technical Field

[0001] The invention relates to the technical field of light emitting diodes, and in particular to a flip-chip LED chip which is easy to weld. Background Art

[0002] Flip-chip LED chips are widely used in automotive lighting, household lighting, backlight display and other fields due to their outstanding features such as good heat dissipation performance, uniform current distribution, high reliability and high light efficiency.

[0003] AuSn eutectic welding technology is commonly used in the packaging application of flip-chip LED chips. It does not require wire bonding to fix the die, which greatly reduces the packaging time and cost. However, it has high requirements for the eutectic welding process, and also has high requirements for the selection, flatness and manufacturing process of the packaging substrate.

[0004] Existing flip-chip LED chips are welded on the packaging substrate using AuSn eutectic welding technology, which will produce a high void rate (defective rate). The void rate refers to the welding adhesion effect between the chip pad electrode metal and the packaging substrate. The welding adhesion area is scanned by X-Ray. If it is all black, the welding adhesion effect is good, the void rate is small, and the yield is high; if a local area of ​​the welding adhesion area appears white, it corresponds to the occurrence of voids. The more white areas, the higher the void rate and the lower the yield; among them, the void rate is equal to the ratio of the white area to the total welding adhesion area.

[0005] During the preparation of flip-chip LED chips, the holes formed by etching the epitaxial layer and the insulating layer will be filled with other structures such as electrodes and pads in subsequent processes. However, these holes will cause abnormal adhesion between the flip-chip LED surface and the packaging substrate, produce a large number of voids, and poor welding when the flip-chip LED chip is packaged, resulting in abnormal photoelectric parameters and chip peeling. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a flip-chip LED chip which is easy to weld, has a low void rate and a high yield rate.

[0007] In order to solve the above technical problems, the present invention provides a flip-chip LED chip that is easy to weld, comprising a substrate, a light-emitting structure disposed on the substrate, a first electrode disposed on the light-emitting structure, a passivation layer disposed on the light-emitting structure and the first electrode, and a second electrode disposed on the passivation layer, wherein the passivation layer is provided with at least one electrode hole, and the electrode hole is filled with a conductive material with a preset hardness;

[0008] The conductive material is flush with the surface of the passivation layer, and forms a conductive connection between the first electrode and the second electrode, and forms a seamless connection with the passivation layer, the first electrode and the second electrode;

[0009] The hardness of the conductive material is ≥80 HBS.

[0010] As an improvement of the above solution, the conductive material is selected from one or more of nickel, chromium, titanium and tungsten;

[0011] The conductive material is filled in the electrode hole by electron beam evaporation or thermal evaporation to form a seamless connection with the passivation layer, the first electrode and the second electrode;

[0012] Wherein, the vacuum degree of the conductive material is ≤1.0*10 -4 Pa, and the plating rate is 0.8 to 2.0 angstroms / second.

[0013] As an improvement of the above solution, the side wall of the electrode hole and the surface of the passivation layer have a preset angle θ1, and the angle θ1 is 115-145°.

[0014] Correspondingly, the present invention also provides a flip-chip LED chip that is easy to weld, comprising a substrate, a light-emitting structure disposed on the substrate, a first electrode disposed on the light-emitting structure, a passivation layer disposed on the light-emitting structure and the first electrode, and a second electrode disposed on the passivation layer, wherein the passivation layer is provided with at least two electrode holes, the electrode holes are etched to the surface of the first electrode, the second electrode is filled in the electrode holes and forms a conductive connection with the first electrode, the second electrode is provided with at least two filling holes, the filling holes are correspondingly arranged above the electrode holes, and the filling holes are filled with a conductive material with a preset hardness;

[0015] Wherein, the conductive material is flush with the surface of the second electrode and forms a seamless connection with the second electrode;

[0016] The hardness of the conductive material is ≥80 HBS.

[0017] As an improvement of the above solution, the conductive material is selected from one or more of nickel, chromium, titanium and tungsten;

[0018] The conductive material is filled in the filling hole by electron beam evaporation or thermal evaporation to form a seamless connection with the second electrode;

[0019] Wherein, the vacuum degree of the conductive material is ≤1.0*10 -4 Pa, and the plating rate is 0.8 to 2.0 angstroms / second.

[0020] As an improvement of the above solution, a preset angle θ2 is formed between the sidewall of the filling hole and the surface of the second electrode, and the angle θ2 is 115-145°.

[0021] Accordingly, the present invention also provides a flip-chip LED chip that is easy to weld, comprising a substrate, a light-emitting structure disposed on the substrate, a first electrode disposed on the light-emitting structure, a passivation layer disposed on the light-emitting structure and the first electrode, and a second electrode disposed on the passivation layer, wherein the passivation layer is provided with at least one electrode hole, the second electrode is provided with at least one filling hole, the filling hole is correspondingly disposed above the electrode hole, and the electrode hole and the filling hole are both filled with a conductive material with a preset hardness;

[0022] The conductive material filled in the electrode hole is flush with the surface of the passivation layer, and forms a conductive connection between the first electrode and the second electrode, and forms a seamless connection with the passivation layer, the first electrode and the second electrode; the conductive material filled in the filling hole is flush with the surface of the second electrode, and forms a seamless connection with the second electrode;

[0023] The hardness of the conductive material is ≥80 HBS.

[0024] As an improvement of the above solution, the conductive material is selected from one or more of nickel, chromium, titanium and tungsten;

[0025] The conductive material is filled in the electrode hole by electron beam evaporation or thermal evaporation to form a seamless connection with the passivation layer, the first electrode and the second electrode;

[0026] The conductive material is filled in the filling hole by electron beam evaporation or thermal evaporation to form a seamless connection with the second electrode;

[0027] Wherein, the vacuum degree of the conductive material is ≤1.0*10 -4 Pa, and the plating rate is 0.8 to 2.0 angstroms / second.

[0028] As an improvement of the above solution, the side wall of the electrode hole and the surface of the passivation layer have a preset angle θ1, and the angle θ1 is 115-145°;

[0029] A preset angle θ2 is formed between the sidewall of the filling hole and the surface of the second electrode, and the angle θ2 is 115-145°.

[0030] As an improvement of the above solution, the thickness of the conductive material filled in the electrode holes and the filling holes is 0.6-1.2 μm.

[0031] The implementation of the present invention has the following beneficial effects:

[0032] The present invention provides an easily solderable flip-chip LED chip, in which a conductive material with a hardness of ≥80 HBS is filled in the electrode holes of the passivation layer, which not only fills the passivation layer, but also forms a conductive connection between the first electrode and the second electrode. More importantly, it plays a good supporting role for the first electrode and the second electrode, solves the problem of different metal hardnesses between the passivation layer and the first electrode and the second electrode, reduces the void rate between the second electrode and the packaging substrate during packaging welding, and improves the welding performance of the chip.

[0033] The present invention sets a preset angle θ1 between the side wall of the electrode hole and the surface of the passivation layer, and sets the range of the angle θ1 to 35 to 65 degrees, so as to avoid cracks between the conductive material and the passivation layer, further reduce the void ratio between the second electrode and the packaging substrate, and improve the welding performance of the chip.

[0034] The present invention provides an easily solderable flip-chip LED chip, wherein a filling hole corresponding to the position of the electrode hole is formed on the second electrode, and a conductive material with an available filling hardness ≥ 80 HBS is filled, so that the second electrode is not only filled, but also a conductive connection is formed between the second electrode and the packaging substrate. More importantly, a good supporting effect is provided for the second electrode, so that a gap between the second electrode and the packaging substrate is avoided when the second electrode is squeezed, thereby reducing the void rate between the second electrode and the packaging substrate during packaging welding, and improving the welding performance of the chip.

[0035] The present invention sets a preset angle θ2 between the side wall of the filling hole and the second electrode, and sets the range of the angle θ2 to 35 to 65 degrees, so as to avoid cracks between the conductive material and the second electrode, further reduce the void ratio between the second electrode and the packaging substrate, and improve the welding performance of the chip.

[0036] The present invention provides a flip-chip LED chip that is easy to weld. The electrode holes of the passivation layer are filled with a conductive material with a hardness of ≥80 HBS, and a filling hole corresponding to the position of the electrode hole is formed on the second electrode, and the conductive material with a hardness of ≥80 HBS is used to fill the hole. Not only the passivation layer and the second electrode are filled, but also the first electrode and the second electrode are conductively connected, and the second electrode and the packaging substrate are conductively connected. More importantly, the first electrode and the second electrode are well supported, the problem of different metal hardnesses between the passivation layer and the first electrode and the second electrode is solved, the void rate between the second electrode and the packaging substrate during packaging welding is reduced, and the welding performance of the chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural schematic diagram of a flip-chip LED chip according to the preferred embodiment 1 of the present invention;

[0038] Figure 2 It is a schematic diagram of the structure of the light-emitting structure of all schemes of the present invention;

[0039] Figure 3 is a schematic diagram of the first electrode of all solutions of the present invention after the light-emitting structure is formed;

[0040] Figure 4 It is a schematic diagram of the passivation layer of all solutions of the present invention after forming electrode holes;

[0041] Figure 5 is a schematic structural diagram of the second electrode of all solutions of the present invention;

[0042] Figure 6 It is a schematic structural diagram of a flip-chip LED chip according to the preferred embodiment 2 of the present invention;

[0043] Figure 7 is a schematic diagram of the second electrode of the preferred embodiment 2 of the present invention after forming a filling hole;

[0044] Figure 8 It is a schematic structural diagram of a flip-chip LED chip according to the preferred embodiment 3 of the present invention;

[0045] Fig. 9 It is a schematic diagram of the second electrode after forming the filling holes in the preferred embodiment 3 of the present invention. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0047] See also Figure 1 As a preferred solution 1 of the present invention, the present invention provides an easily solderable flip-chip LED chip, comprising a substrate 10, a light-emitting structure 20 arranged on the substrate 10, a first electrode 30 arranged on the light-emitting structure 20, a passivation layer 40 arranged on the light-emitting structure 20 and the first electrode 30, and a second electrode 50 arranged on the passivation layer 40, wherein the passivation layer 40 is provided with at least one electrode hole, and the electrode hole is filled with a conductive material 60 with a preset hardness; wherein the conductive material 60 is flush with the surface of the passivation layer 40, and forms a conductive connection between the first electrode 30 and the second electrode 50, and forms a seamless connection with the passivation layer 40, the first electrode 30 and the second electrode 50; the hardness of the conductive material 60 is ≥80HBS.

[0048] Specifically, the passivation layer 40 is a necessary structure of the flip-chip LED chip, which is used to protect the light-emitting structure 20, prevent water vapor, dust, etc. from entering the light-emitting structure 20, and prevent the chip from short-circuiting. In order to ensure that the first electrode 30 can form a conductive connection with the second electrode 50, the passivation layer 40 must be etched to form an electrode hole. The existing flip-chip LED chip directly deposits the metal of the second electrode 50 in the electrode hole of the passivation layer 40 so that the first electrode 30 can form a conductive connection with the second electrode 50. However, during the packaging welding, a downward pressure will be applied to the flip-chip LED chip. Since the metal hardness of the passivation layer 40 and the first electrode 30 and the second electrode 50 is different, a large number of voids will be generated on the second electrode 50 and the packaging substrate, affecting the packaging yield.

[0049] The passivation layer 40 of the present invention is made of an insulating layer material with good compactness. Preferably, the material of the passivation layer 40 is selected from one or more of SiO2, TiO5, SiNx, and SiON. More preferably, the passivation layer 40 is a DBR layer.

[0050] The present invention fills the electrode holes of the passivation layer 40 with a conductive material 60 having a preset hardness, not only to fill the passivation layer 40, but also to form a conductive connection between the first electrode 30 and the second electrode 50. More importantly, the conductive material 60 of the present invention can support the first electrode 30 and the second electrode 50, reduce the void ratio between the second electrode 50 and the packaging substrate during packaging welding, and improve the welding performance of the chip.

[0051] The conductive material 60 of the present invention with a preset hardness should have the following characteristics: (1) form good adhesion with the passivation layer 40, the first electrode 30 and the second electrode 50; (2) have good conductivity to form vertical conduction between the first electrode 30 and the second electrode 50; (3) have a hardness comparable to that of the surrounding structures. During chip packaging welding, only when the hardness of the conductive material 60 is ≥80HBS, the conductive material 60 will not produce gaps with the surrounding passivation layer 40, the first electrode 30 and the second electrode 50 due to extrusion, and no new voids will be formed.

[0052] In order to satisfy the above characteristics of the conductive material 60, the conductive material 60 of the present invention is selected from one or more of nickel, chromium, titanium, and tungsten. Specifically, the conductive material 60 of the present invention is filled in the electrode hole by evaporation to form a seamless connection with the passivation layer 40, the first electrode 30, and the second electrode 50.

[0053] In order to reduce the gap between the conductive material and other structures, the present invention uses electron beam evaporation or thermal evaporation to fill the conductive material into the electrode holes. Among them, the vacuum degree and plating rate have an important influence on the film density, porosity, conductivity and stability of the conductive material.

[0054] If the vacuum degree is low, that is, the air pressure value during evaporation is large, the oxygen content is high, the metal particles are easily oxidized, the size of the metal particles increases, the porosity in the film layer is large, the film layer has poor density, the conductivity is poor, the adhesion performance is reduced, and the conductive material will form larger pores when forming a film on each contact surface. If the plating rate is high, the metal particles are large and the deposition speed is fast, the metal particles form a film quickly, the adhesion with each contact surface is poor, the film layer has poor density, the porosity is high, the conductivity is poor, and the stability is poor. Preferably, the vacuum degree (air pressure during evaporation) of the conductive material is ≤1.0*10 -4 Pa, the plating rate is 0.8 to 2.0 angstroms per second. More preferably, the conductive material is made with a vacuum degree of 1.0*10 -6 ~1.0*10 -4 Pa, and the plating rate is 1.0 to 1.5 angstroms per second.

[0055] Preferably, the shape of the electrode hole is a trapezoid, that is, the side wall of the electrode hole and the surface of the passivation layer 40 have a preset angle θ1. The angle θ1 plays an important role in the effect of the conductive material 60; if the angle θ1 is too small, the conductive material 60 is prone to cracks with the passivation layer 40 during evaporation, and the second electrode 50 disposed on the conductive material 60 is also prone to disconnect from the conductive material 60; if the angle θ1 is too large, the opening of the electrode hole is very wide, that is, the area of ​​the electrode hole is too large, which will increase the void ratio of the chip and reduce the solderability of the chip.

[0056] Preferably, the angle θ1 is 115 to 145°. More preferably, the angle θ1 is 125 to 135°.

[0057] See also Figure 2 The light-emitting structure 20 of the present invention includes an epitaxial layer, a transparent conductive layer 24, a reflective layer 25 and a protective layer 26 arranged in sequence, and the epitaxial layer includes a first semiconductor layer 21, an active layer 22 and a second semiconductor layer 23 arranged in sequence, wherein the light-emitting structure 20 also includes a first concave hole 27 and a second concave hole 28, the first concave hole 27 is etched from the protective layer 26 to the first semiconductor layer 21, and the second concave hole 28 is etched from the protective layer 26 to the surface of the reflective layer 25.

[0058] See also Figure 3The first electrode 30 includes an N-type first electrode 31 and a P-type first electrode 32, wherein the N-type first electrode 31 is disposed on the protective layer 26 and the first semiconductor layer 21 of the first concave hole 27, and the P-type first electrode 32 is disposed on the reflective layer 25 of the second concave hole 28. The protective layer 26 is used to separate the N-type first electrode 31 and the P-type first electrode 32 to prevent the chip from short-circuiting. Preferably, the protective layer 26 is made of an insulating layer material with good compactness. Preferably, the material of the protective layer 26 is selected from one or more of SiO2, TiO5, SiNx, and SiON.

[0059] The portion of the N-type first electrode 31 located in the first concave hole 27 has a horizontal plane height slightly lower than the protective layer 26 , forming a third concave hole 33 . The protective layer 26 of the present invention covers the light emitting structure 20 outside the third concave hole 33 .

[0060] See also Figure 4 The passivation layer 40 is arranged on the first electrode 30, and fills the third concave hole 33 and the second concave hole 28; wherein, the electrode holes of the passivation layer 40 are correspondingly arranged above the third concave hole 33 and the second concave hole 28, so that the conductive material 60 filled in the electrode holes can play a good supporting role, reduce the void rate between the second electrode 50 and the packaging substrate during packaging welding, and improve the welding performance of the chip.

[0061] Specifically, the electrode holes include a first electrode hole 41 and a second electrode hole, the first electrode hole 41 is correspondingly arranged above the third concave hole 33, the second electrode holes include at least an N-type second electrode hole 42 and a P-type second electrode hole 43, the N-type second electrode hole 42 is etched to the surface of the N-type first electrode 31, and the P-type second electrode hole 43 is etched to the surface of the P-type first electrode 32. Specifically, the conductive material 60 filled in the N-type second electrode hole 42 is conductively connected to the N-type first electrode 31, the conductive material 60 filled in the P-type second electrode hole 43 is conductively connected to the P-type first electrode 32, and the conductive material 60 filled in the first electrode hole 41 may be conductively connected to the N-type first electrode 31, or may not be conductively connected to the N-type first electrode 31, which mainly depends on the depth of the first electrode hole 41. In order to reduce the void ratio, the first electrode hole 41 and the second electrode hole 42 have the same depth, so the conductive material 60 filled in the first electrode hole 41 generally does not form a conductive connection with the N-type first electrode 31 .

[0062] The second electrode 50 includes an N-type second electrode 51 and a P-type second electrode 52, wherein the N-type second electrode 51 is arranged on the first electrode hole 41 and the N-type second electrode hole 42, and the P-type second electrode 52 is arranged on the P-type second electrode hole 43, wherein the conductive material 60 filled in the N-type second electrode hole 42 forms a conductive connection between the N-type second electrode 51 and the N-type first electrode 31, and the conductive material 60 filled in the P-type second electrode hole 43 forms a conductive connection between the P-type second electrode 52 and the P-type first electrode 32.

[0063] It can be seen that the thickness of the conductive material 60 depends on the depth of the electrode hole, and the depth of the electrode hole depends on the thickness of the passivation layer 40. If the thickness of the passivation layer 40 is too thin, that is, the thickness of the conductive material 60 is too thin, the chip is prone to leakage, the conductivity of the conductive material 60 will be affected, thereby affecting the voltage of the chip, and the filling effect of the conductive material 60 is reduced, the void rate increases, and the weldability is reduced; if the thickness of the passivation layer 40 is too thick, that is, the thickness of the conductive material 60 is too thick, the cost increases, and the conductive material 60 and the passivation layer 40 are prone to cracks, the void rate increases, and the weldability is also reduced. Preferably, the thickness of the conductive material 60 is 0.6 to 1.2 μm. More preferably, the thickness of the conductive material 60 is 0.7 to 1.0 μm.

[0064] The second electrode 50 of the present invention is used for welding packaging, so its area is affected by the packaging substrate and the packaging process. In order to improve the welding efficiency and welding effect, the areas of the N-type second electrode 51 and the P-type second electrode 52 are equal, and the heights are on the same horizontal plane. The first electrode 30 of the present invention is used for current expansion of the chip, which plays a role in reducing voltage and increasing brightness. Preferably, the material of the first electrode 30 is selected from one or more of Cr, Ni, Al, Ti, Pt, and Au; the material of the second electrode 50 is selected from one or more of Cr, Ni, Al, Ti, Pt, Au, and Sn.

[0065] Since the bottom layer of the first electrode 30 needs to have a good adhesion with the protective layer 26 and the epitaxial layer, Cr or Ti is selected for the bottom layer of the first electrode 30; and the top layer of the first electrode 30 needs to have a function of protecting the metal underneath when the passivation layer 40 is etched, and the top layer of the first electrode 30 needs to have a good adhesion with the second electrode 50 and the passivation layer 40, so Pt, Au, and Ti are selected for the top layer of the first electrode 30. Preferably, the first electrode 30 is a Cr / Al / Ti / Pt / Au / Ti stacked structure, which has a certain reflectivity and can reflect the light emitted by the epitaxial layer to the side of the substrate 10.

[0066] See also Figure 5The second electrode 50 is a laminated structure, including a conductive layer 51 and a surface layer 52. The material of the conductive layer 51 is selected from one or more of Cr, Ni, Al, Ti, and Pt. The surface layer 52 is a laminated structure, including multiple layers of Sn / Au.

[0067] The surface layer is formed by compounding pure gold and pure tin to form a Sn / Au laminate, and the stress of the surface layer is eliminated by compounding Au and Sn in different proportions, thereby improving the wetting performance between the surface metal and the packaging substrate, thereby reducing the packaging void rate between the surface layer and the packaging substrate.

[0068] Specifically, when the package substrate is heated to a suitable eutectic temperature, gold or silver elements will penetrate into the surface layer to change the composition of the surface layer, thereby increasing the melting point of the surface layer, solidifying the surface layer and firmly soldering the flip-chip LED chip to the package substrate. The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold (Au) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the LED light efficiency is inversely proportional to the thermal resistance; (3) improving efficiency, as the LED eutectic is solidified in one step; and (4) the bonding strength is greater than that of silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0069] The thickness of Sn and the thickness of Au in the Sn / Au stack determine the ratio of Sn to Au in the Sn / Au stack. Since the surface layer of the present invention eliminates the stress of the surface layer by compounding AuSn in different ratios, the wetting performance between the surface metal and the packaging substrate is improved, thereby reducing the packaging void rate between the surface layer and the packaging substrate. The mass percentage of Au and Sn is within the range of (15% to 30%): (70% to 85%), and Au and Sn can form a stable eutectic compound. Therefore, the thickness of Sn and the thickness of Au in the Sn / Au stack cannot be too thick or too thin. Preferably, in the Sn / Au stack, the thickness of Sn is a1, and the thickness of Au is b1, wherein a1:b1=(15 to 30):(70 to 85). More preferably, a1:b1=(18 to 25):(75 to 82).

[0070] Preferably, in the Sn / Au stack, the thickness of Sn is 0.2-0.4 μm, and the thickness of Au is 1-1.5 μm.

[0071] Among them, the total thickness of the surface layer also plays an important role in reducing the packaging void rate between the surface layer and the packaging substrate; if the thickness of the surface layer is too thin, it will not play a role in reducing the packaging void rate; if the thickness of the surface layer is too thick, it will increase the preparation difficulty and production cost.

[0072] Preferably, the surface layer comprises 3 to 10 layers of Sn / Au stacked layers. More preferably, the surface layer comprises 3 to 5 layers of Sn / Au stacked layers.

[0073] The reflective layer 25 is a metal reflective layer, which reflects the light emitted by the epitaxial layer to the side of the substrate 10 to improve the light extraction efficiency of the flip-chip LED chip.

[0074] Preferably, the reflective layer 25 includes an Ag layer and an Ag layer protection layer, wherein the Ag layer protection layer covers the Ag layer to prevent the Ag layer from being oxidized when the protection layer 26 is deposited and to prevent the Ag layer from being etched when the protection layer 26 is etched.

[0075] Preferably, the material of the Ag layer protective layer is selected from one or more metals of Ti, W, Al, Ni, and Pt.

[0076] See also Figure 6 As a preferred solution 2 of the present invention, the present invention provides an easily solderable flip-chip LED chip, comprising a substrate 10, a light-emitting structure 20 arranged on the substrate 10, a first electrode 30 arranged on the light-emitting structure 20, a passivation layer 40 arranged on the light-emitting structure 20 and the first electrode 30, and a second electrode 50 arranged on the passivation layer 40, wherein the passivation layer 40 is provided with at least two electrode holes, the electrode holes are etched to the surface of the first electrode 30, the second electrode 50 is filled in the electrode holes and forms a conductive connection with the first electrode 30, the second electrode 50 is provided with at least two filling holes, the filling holes are correspondingly arranged above the electrode holes, and the filling holes are filled with a conductive material 60 of a preset hardness; wherein the conductive material 60 is flush with the surface of the second electrode 50 and forms a seamless connection with the second electrode 50; the hardness of the conductive material 60 is ≥80HBS.

[0077] Specifically, the passivation layer 40 is a necessary structure of the flip-chip LED chip, which is used to protect the light-emitting structure 20, prevent water vapor, dust, etc. from entering the light-emitting structure 20, and prevent the chip from short-circuiting. In order to ensure that the first electrode 30 can form a conductive connection with the second electrode 50, the passivation layer 40 must be etched to form an electrode hole. Since the flip-chip LED chip directly deposits the metal of the second electrode 50 in the electrode hole of the passivation layer 40, the first electrode 30 can form a conductive connection with the second electrode 50. However, during the packaging welding, a downward pressure will be applied to the flip-chip LED chip. Since the metal hardness of the passivation layer 40 and the first electrode 30 and the second electrode 50 is different, a large number of voids will be generated on the second electrode 50 and the packaging substrate, affecting the packaging yield.

[0078] The passivation layer 40 of the present invention is made of an insulating layer material with good compactness. Preferably, the material of the passivation layer 40 is selected from one or more of SiO2, TiO5, SiNx, and SiON. More preferably, the passivation layer 40 is a DBR layer.

[0079] The present invention forms a filling hole corresponding to the position of the electrode hole on the second electrode 50, and fills a conductive material 60 with a preset hardness in the filling hole, not only to fill the second electrode 50, but also to form a conductive connection between the second electrode 50 and the packaging substrate. More importantly, the conductive material 60 of the present invention can support the second electrode 50 to prevent the second electrode 50 from generating a gap with the packaging substrate due to squeezing, thereby reducing the void rate between the second electrode 50 and the packaging substrate during packaging welding, thereby improving the welding performance of the chip.

[0080] The conductive material 60 of the present invention with a preset hardness should have the following characteristics: (1) form good adhesion with the second electrode 50; (2) have good conductivity to form vertical conduction between the conductive substrate and the second electrode 50; (3) have a hardness comparable to that of the surrounding structure. During chip packaging welding, only when the hardness of the conductive material 60 is ≥80HBS, the conductive material 60 will not produce gaps with the second electrode 50 and the packaging substrate due to extrusion, and no new voids will be formed.

[0081] In order to satisfy the above characteristics of the conductive material 60, the conductive material of the present invention is selected from one or more of nickel, chromium, titanium, and tungsten. Specifically, the conductive material 60 of the present invention is filled in the filling hole by evaporation to form a seamless connection with the second electrode 50.

[0082] In order to reduce the gap between the conductive material and other structures, the present invention uses electron beam evaporation or thermal evaporation to fill the conductive material into the electrode holes. Among them, the vacuum degree and plating rate have an important influence on the film density, porosity, conductivity and stability of the conductive material.

[0083] If the vacuum degree is low, that is, the air pressure value during evaporation is large, the oxygen content is high, the metal particles are easily oxidized, the size of the metal particles increases, the porosity in the film layer is large, the film layer has poor density, the conductivity is poor, the adhesion performance is reduced, and the conductive material will form larger pores when forming a film on each contact surface. If the plating rate is high, the metal particles are large and the deposition speed is fast, the metal particles form a film quickly, the adhesion with each contact surface is poor, the film layer has poor density, the porosity is high, the conductivity is poor, and the stability is poor. Preferably, the vacuum degree (air pressure during evaporation) of the conductive material is ≤1.0*10 -4 Pa, the plating rate is 0.8 to 2.0 angstroms per second. More preferably, the conductive material is made with a vacuum degree of 1.0*10 -6 ~1.0*10 -4 Pa, and the plating rate is 1.0 to 1.5 angstroms per second.

[0084] Preferably, the shape of the filling hole is a trapezoid, that is, the side wall of the filling hole and the surface of the second electrode 50 have a preset angle θ2. The angle θ2 plays an important role in the effect of the conductive material 60; if the angle θ2 is too small, the conductive material 60 is prone to cracks in the second electrode 50 during evaporation; if the angle θ2 is too large, the opening of the filling hole is very wide, that is, the area of ​​the filling hole is too large, which not only affects the voltage of the chip, but also increases the void rate of the chip and reduces the solderability of the chip.

[0085] Preferably, the angle θ2 is 115 to 145°. More preferably, the angle θ2 is 125 to 135°.

[0086] See also Figure 2 The light-emitting structure 20 of the present invention includes an epitaxial layer, a transparent conductive layer 24, a reflective layer 25 and a protective layer 26 arranged in sequence, and the epitaxial layer includes a first semiconductor layer 21, an active layer 22 and a second semiconductor layer 23 arranged in sequence, wherein the light-emitting structure 20 also includes a first concave hole 27 and a second concave hole 28, the first concave hole 27 is etched from the protective layer 26 to the first semiconductor layer 21, and the second concave hole 28 is etched from the protective layer 26 to the surface of the reflective layer 25.

[0087] See also Figure 3 The first electrode 30 includes an N-type first electrode 31 and a P-type first electrode 32, wherein the N-type first electrode 31 is disposed on the protective layer 26 and the first semiconductor layer 21 of the first concave hole 27, and the P-type first electrode 32 is disposed on the reflective layer 25 of the second concave hole 28. The protective layer 26 is used to separate the N-type first electrode 31 and the P-type first electrode 32 to prevent the chip from short-circuiting. Preferably, the protective layer 26 is made of an insulating layer material with good compactness. Preferably, the material of the protective layer 26 is selected from one or more of SiO2, TiO5, SiNx, and SiON.

[0088] Among them, the horizontal plane height of the part of the N-type first electrode 31 located in the first concave hole 27 is slightly lower than the protective layer 26, forming a third concave hole 33; the area covered by the protective layer 26 of the present invention on the light-emitting structure 20 outside the third concave hole 33 should be as large as possible, which can reduce the proportion of the concave hole, reduce the void rate, and improve solderability.

[0089] See also Figure 4 The passivation layer 40 is arranged on the first electrode 30 and fills the third recessed hole 33 and the second recessed hole 28; wherein the electrode holes of the passivation layer 40 are correspondingly arranged above the third recessed hole 33 and the second recessed hole 28, so that the second electrode 50 filled in the electrode hole can form a conductive connection with the first electrode 30.

[0090] Specifically, the electrode holes include a first electrode hole 41 and a second electrode hole 42, the first electrode hole 41 is correspondingly arranged above the third recessed hole 33, the second electrode hole 42 includes at least an N-type second electrode hole 42 and a P-type second electrode hole 43, the N-type second electrode hole 42 is etched to the surface of the N-type first electrode 31, and the P-type second electrode hole 43 is etched to the surface of the P-type first electrode 32.

[0091] Among them, the second electrode 50 includes an N-type second electrode 51 and a P-type second electrode 52, the N-type second electrode 51 is arranged on the passivation layer 40 and filled into the first electrode hole 41 and the N-type second electrode hole 42, and forms a conductive connection with the N-type first electrode 31; the P-type second electrode 52 is arranged on the passivation layer 40 and filled into the P-type second electrode hole 43, and forms a conductive connection with the P-type first electrode 32.

[0092] See also Figure 7 , the filling holes include a first filling hole 53 and a second filling hole, the first filling hole 53 is correspondingly arranged above the first electrode hole 41, and the second filling hole 54 is correspondingly arranged above the second electrode hole. Specifically, the second filling through hole includes an N-type second filling through hole 54 and a P-type second filling through hole 55, the N-type second electrode 51 is provided with the first filling hole 53 and the N-type second filling hole 54, and the P-type second electrode 52 is provided with the P-type second filling hole 55; the filling material filled in the first filling hole 53 and the second filling hole can offset the influence of insufficient hardness and insufficient supporting force of the second electrode 50 in the first electrode hole 41 and the second electrode hole 42 on the passivation layer 40, reduce the void rate between the second electrode 50 and the package substrate during package welding, and improve the welding performance of the chip.

[0093] The thickness of the conductive material 60 depends on the depth of the filled hole, and the depth of the filled hole depends on the thickness of the second electrode 50. If the thickness of the conductive material 60 is too thin, the conductivity of the conductive material 60 will be affected, thereby affecting the voltage of the chip, and the filling effect of the conductive material 60 will decrease, the void rate will increase, and the weldability will decrease; if the thickness of the conductive material is too thick, the thickness of the second electrode 50 will also increase accordingly, thereby increasing the cost, and cracks are prone to appear between the conductive material 60 and the second electrode 50, the void rate will increase, and the weldability will also decrease. Preferably, the thickness of the conductive material 60 is 0.6 to 1.2 μm. More preferably, the thickness of the conductive material 60 is 0.7 to 1.0 μm.

[0094] The second electrode 50 of the present invention is used for welding packaging, so its area is affected by the packaging substrate and the packaging process. In order to improve the welding efficiency and welding effect, the areas of the N-type second electrode 51 and the P-type second electrode 52 are equal, and the heights are on the same horizontal plane. The first electrode 30 of the present invention is used for current expansion of the chip, which plays a role in reducing voltage and increasing brightness. Preferably, the material of the first electrode 30 is selected from one or more of Cr, Ni, Al, Ti, Pt, and Au; the material of the second electrode 50 is selected from one or more of Cr, Ni, Al, Ti, Pt, Au, and Sn.

[0095] Since the bottom layer of the first electrode 30 needs to have a good adhesion with the protective layer 26 and the epitaxial layer, Cr or Ti is selected for the bottom layer of the first electrode 30; and the top layer of the first electrode 30 needs to have a function of protecting the metal underneath when the passivation layer 40 is etched, and the top layer of the first electrode 30 needs to have a good adhesion with the second electrode 50 and the passivation layer 40, so Pt, Au, and Ti are selected for the top layer of the first electrode 30. Preferably, the first electrode 30 is a Cr / Al / Ti / Pt / Au / Ti stacked structure, which has a certain reflectivity and can reflect the light emitted by the epitaxial layer to the side of the substrate 10.

[0096] See also Figure 5 The second electrode 50 is a laminated structure, including a conductive layer 51 and a surface layer 52. The material of the conductive layer 51 is selected from one or more of Cr, Ni, Al, Ti, and Pt. The surface layer 52 is a laminated structure, including multiple layers of Sn / Au.

[0097] The surface layer is formed by compounding pure gold and pure tin to form a Sn / Au laminate, and the stress of the surface layer is eliminated by compounding Au and Sn in different proportions, thereby improving the wetting performance between the surface metal and the packaging substrate, thereby reducing the packaging void rate between the surface layer and the packaging substrate.

[0098] Specifically, when the package substrate is heated to a suitable eutectic temperature, gold or silver elements will penetrate into the surface layer to change the composition of the surface layer, thereby increasing the melting point of the surface layer, solidifying the surface layer and firmly soldering the flip-chip LED chip to the package substrate. The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold (Au) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the LED light efficiency is inversely proportional to the thermal resistance; (3) improving efficiency, as the LED eutectic is solidified in one step; and (4) the bonding strength is greater than that of silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0099] The thickness of Sn and the thickness of Au in the Sn / Au stack determine the ratio of Sn to Au in the Sn / Au stack. Since the surface layer of the present invention eliminates the stress of the surface layer by compounding AuSn in different ratios, the wetting performance between the surface metal and the packaging substrate is improved, thereby reducing the packaging void rate between the surface layer and the packaging substrate. The mass percentage of Au and Sn is within the range of (15% to 30%): (70% to 85%), and Au and Sn can form a stable eutectic compound. Therefore, the thickness of Sn and the thickness of Au in the Sn / Au stack cannot be too thick or too thin. Preferably, in the Sn / Au stack, the thickness of Sn is a1, and the thickness of Au is b1, wherein a1:b1=(15 to 30):(70 to 85). More preferably, a1:b1=(18 to 25):(75 to 82).

[0100] Preferably, in the Sn / Au stack, the thickness of Sn is 0.2-0.4 μm, and the thickness of Au is 1-1.5 μm.

[0101] Among them, the total thickness of the surface layer also plays an important role in reducing the packaging void rate between the surface layer and the packaging substrate; if the thickness of the surface layer is too thin, it will not play a role in reducing the packaging void rate; if the thickness of the surface layer is too thick, it will increase the preparation difficulty and production cost.

[0102] Preferably, the surface layer comprises 3 to 10 layers of Sn / Au stacked layers. More preferably, the surface layer comprises 3 to 5 layers of Sn / Au stacked layers.

[0103] The reflective layer 25 is a metal reflective layer 25, which reflects the light emitted by the epitaxial layer to the side of the substrate 10, so as to improve the light extraction efficiency of the flip-chip LED chip.

[0104] Preferably, the reflective layer 25 includes an Ag layer and an Ag layer protection layer, wherein the Ag layer protection layer covers the Ag layer to prevent the Ag layer from being oxidized when the protection layer 26 is deposited and to prevent the Ag layer from being etched when the protection layer 26 is etched.

[0105] Preferably, the material of the Ag layer protective layer is selected from one or more metals of Ti, W, Al, Ni, and Pt.

[0106] See also Figure 8As a preferred solution 3 of the present invention, the present invention provides an easily solderable flip-chip LED chip, comprising a substrate 10, a light-emitting structure 20 arranged on the substrate 10, a first electrode 30 arranged on the light-emitting structure 20, a passivation layer 40 arranged on the light-emitting structure 20 and the first electrode 30, and a second electrode 50 arranged on the passivation layer 40, wherein the passivation layer 40 is provided with at least one electrode hole, and the second electrode 50 is provided with at least one filling hole, and the filling holes are correspondingly arranged above the electrode holes, and the electrode holes and the filling holes are both filled with a conductive material 60 of a preset hardness; wherein the conductive material 60 filled in the electrode holes is flush with the surface of the passivation layer 40, and forms a conductive connection between the first electrode 30 and the second electrode 50, and forms a seamless connection with the passivation layer 40, the first electrode 30 and the second electrode 50; the conductive material 60 filled in the filling hole is flush with the surface of the second electrode 50, and forms a seamless connection with the second electrode 50; the hardness of the conductive material 60 is ≥80HBS.

[0107] Specifically, the passivation layer 40 is a necessary structure of the flip-chip LED chip, which is used to protect the light-emitting structure 20, prevent water vapor, dust, etc. from entering the light-emitting structure 20, and prevent the chip from short-circuiting. In order to ensure that the first electrode 30 can form a conductive connection with the second electrode 50, the passivation layer 40 must be etched to form an electrode hole. Since the flip-chip LED chip directly deposits the metal of the second electrode 50 in the electrode hole of the passivation layer 40, the first electrode 30 can form a conductive connection with the second electrode 50. However, during the packaging welding, a downward pressure will be applied to the flip-chip LED chip. Since the metal hardness of the passivation layer 40 and the first electrode 30 and the second electrode 50 is different, a large number of voids will be generated on the second electrode 50 and the packaging substrate, affecting the packaging yield.

[0108] The passivation layer 40 of the present invention is made of an insulating layer material with good compactness. Preferably, the material of the passivation layer 40 is selected from one or more of SiO2, TiO5, SiNx, and SiON. More preferably, the passivation layer 40 is a DBR layer.

[0109] The present invention fills the electrode holes of the passivation layer 40 with a conductive material 60 having a preset hardness, not only to fill the passivation layer 40, but also to form a conductive connection between the first electrode 30 and the second electrode 50. More importantly, the conductive material 60 of the present invention can support the first electrode 30 and the second electrode 50, reduce the void ratio between the second electrode 50 and the packaging substrate during packaging welding, and improve the welding performance of the chip.

[0110] Furthermore, the present invention forms a filling hole corresponding to the position of the electrode hole on the second electrode 50, and fills the conductive material 60 in the filling hole, not only to fill the second electrode 50, but also to form a conductive connection between the second electrode 50 and the packaging substrate. More importantly, the conductive material 60 of the present invention can support the second electrode 50 to prevent the second electrode 50 from generating a gap with the packaging substrate due to squeezing, thereby reducing the void ratio between the second electrode 50 and the packaging substrate during packaging welding, thereby improving the welding performance of the chip.

[0111] The conductive material 60 of the present invention with a preset hardness should have the following characteristics: (1) form good adhesion with the second electrode 50; (2) have good conductivity to form vertical conduction between the conductive substrate and the second electrode 50; (3) have a hardness comparable to that of the surrounding structure. During chip packaging welding, only when the hardness of the conductive material 60 is ≥80HBS, the conductive material 60 will not produce gaps with the second electrode 50 and the packaging substrate due to extrusion, and no new voids will be formed.

[0112] In order to satisfy the above-mentioned characteristics of the conductive material 60, the conductive material of the present invention is selected from one or more of nickel, chromium, titanium, and tungsten. Specifically, the conductive material 60 of the present invention is filled in the electrode hole by evaporation to form a seamless connection with the passivation layer 40, the first electrode 30, and the second electrode 50. Similarly, the conductive material 60 of the present invention is filled in the filling hole by evaporation to form a seamless connection with the second electrode 50.

[0113] In order to reduce the gap between the conductive material and other structures, the present invention uses electron beam evaporation or thermal evaporation to fill the conductive material into the electrode holes. Among them, the vacuum degree and plating rate have an important influence on the film density, porosity, conductivity and stability of the conductive material.

[0114] If the vacuum degree is low, that is, the air pressure value during evaporation is large, the oxygen content is high, the metal particles are easily oxidized, the size of the metal particles increases, the porosity in the film layer is large, the film layer has poor density, the conductivity is poor, the adhesion performance is reduced, and the conductive material will form larger pores when forming a film on each contact surface. If the plating rate is high, the metal particles are large and the deposition speed is fast, the metal particles form a film quickly, the adhesion with each contact surface is poor, the film layer has poor density, the porosity is high, the conductivity is poor, and the stability is poor. Preferably, the vacuum degree (air pressure during evaporation) of the conductive material is ≤1.0*10 -4 Pa, the plating rate is 0.8 to 2.0 angstroms per second. More preferably, the conductive material is made with a vacuum degree of 1.0*10 -6 ~1.0*10 -4 Pa, and the plating rate is 1.0 to 1.5 angstroms per second.

[0115] Preferably, the shape of the electrode hole is a trapezoid, that is, the side wall of the electrode hole and the surface of the passivation layer 40 have a preset angle θ1. The angle θ1 plays an important role in the effect of the conductive material 60; if the angle θ1 is too small, the conductive material 60 is prone to cracks with the passivation layer 40 during evaporation, and the second electrode 50 disposed on the conductive material 60 is also prone to disconnect from the conductive material 60; if the angle θ1 is too large, the opening of the electrode hole is very wide, that is, the area of ​​the electrode hole is too large, which will increase the void ratio of the chip and reduce the solderability of the chip.

[0116] Preferably, the angle θ1 is 115-145°. More preferably, the angle θ1 is 125-135°. Preferably, the shape of the filling hole is a trapezoid, that is, the side wall of the filling hole and the surface of the second electrode 50 have a preset angle θ2. Among them, the angle θ2 plays an important role in the effect of the conductive material 60; if the angle θ2 is too small, the conductive material 60 is prone to cracks in the second electrode 50 during evaporation; if the angle θ2 is too large, the opening of the filling hole is very wide, that is, the area of ​​the filling hole is too large, which not only affects the voltage of the chip, but also increases the void ratio of the chip and reduces the solderability of the chip.

[0117] Preferably, the angle θ2 is 115 to 145°. More preferably, the angle θ2 is 125 to 135°.

[0118] See also Figure 2 The light-emitting structure 20 of the present invention includes an epitaxial layer, a transparent conductive layer 24, a reflective layer 25 and a protective layer 26 arranged in sequence, and the epitaxial layer includes a first semiconductor layer 21, an active layer 22 and a second semiconductor layer 23 arranged in sequence, wherein the light-emitting structure 20 also includes a first concave hole 27 and a second concave hole 28, the first concave hole 27 is etched from the protective layer 26 to the first semiconductor layer 21, and the second concave hole 28 is etched from the protective layer 26 to the surface of the reflective layer 25.

[0119] See also Figure 3 The first electrode 30 includes an N-type first electrode 31 and a P-type first electrode 32, wherein the N-type first electrode 31 is disposed on the protective layer 26 and the first semiconductor layer 21 of the first concave hole 27, and the P-type first electrode 32 is disposed on the reflective layer 25 of the second concave hole 28. The protective layer 26 is used to separate the N-type first electrode 31 and the P-type first electrode 32 to prevent the chip from short-circuiting. Preferably, the protective layer 26 is made of an insulating layer material with good compactness. Preferably, the material of the protective layer 26 is selected from one or more of SiO2, TiO5, SiNx, and SiON.

[0120] See also Figure 4The horizontal plane height of the part of the N-type first electrode 31 located in the first concave hole 27 is slightly lower than that of the protective layer 26, forming a third concave hole 33; the area covered by the protective layer 26 of the present invention on the light-emitting structure 20 outside the third concave hole 33 should be as large as possible, which can reduce the proportion of the concave hole, reduce the void rate, and improve the solderability.

[0121] The passivation layer 40 is arranged on the first electrode 30, and fills the third recessed hole 33 and the second recessed hole 28; wherein, the electrode holes of the passivation layer 40 are correspondingly arranged above the third recessed hole 33 and the second recessed hole 28, so that the conductive material 60 filled in the electrode holes can play a good supporting role, reduce the void rate between the second electrode 50 and the packaging substrate during packaging welding, and improve the welding performance of the chip.

[0122] The electrode holes include a first electrode hole 41 and a second electrode hole 42, wherein the first electrode hole 41 is correspondingly arranged above the third concave hole 33, and the second electrode hole 42 includes at least an N-type second electrode hole 42 and a P-type second electrode hole 43, wherein the N-type second electrode hole 42 is etched to the surface of the N-type first electrode 31, and the P-type second electrode hole 43 is etched to the surface of the P-type first electrode 32. Specifically, the conductive material 60 filled in the N-type second electrode hole 42 is conductively connected to the N-type first electrode 31, the conductive material 60 filled in the P-type second electrode hole 43 is conductively connected to the P-type first electrode 32, and the conductive material 60 filled in the first electrode hole 41 may be conductively connected to the N-type first electrode 31, or may not be conductively connected to the N-type first electrode 31, which mainly depends on the depth of the first electrode hole 41. In order to reduce the void ratio, the first electrode hole 41 and the second electrode hole 42 have the same depth, so the conductive material 60 filled in the first electrode hole 41 generally does not form a conductive connection with the N-type first electrode 31 .

[0123] Specifically, the second electrode 50 includes an N-type second electrode 51 and a P-type second electrode 52, wherein the N-type second electrode 51 is arranged on the first electrode hole 41 and the N-type second electrode hole 42, and the P-type second electrode 52 is arranged on the P-type second electrode hole 43, wherein the conductive material 60 filled in the N-type second electrode hole 42 forms a conductive connection between the N-type second electrode 51 and the N-type first electrode 31, and the conductive material 60 filled in the P-type second hole forms a conductive connection between the P-type second electrode 52 and the P-type first electrode 32.

[0124] See also Fig. 9, the filling holes include a first filling hole 53 and a second filling hole, the first filling hole 53 is correspondingly arranged above the first electrode hole 41, and the second filling hole is correspondingly arranged above the second electrode hole 42. Specifically, the second filling through hole includes an N-type second filling through hole 54 and a P-type second filling through hole 55, the N-type second electrode 51 is provided with the first filling hole 53 and the N-type second filling hole 54, and the P-type second electrode 52 is provided with the P-type second filling hole 55; the filling material filled in the first filling hole 53 and the second filling hole can offset the influence of insufficient hardness and insufficient supporting force of the second electrode 50 in the first electrode hole 41 and the second electrode hole 42 on the passivation layer 40, reduce the void rate between the second electrode 50 and the package substrate during package welding, and improve the welding performance of the chip.

[0125] The thickness of the conductive material 60 filled in the electrode hole depends on the depth of the electrode hole, and the depth of the electrode hole depends on the thickness of the passivation layer 40. If the thickness of the passivation layer 40 is too thin, that is, the thickness of the conductive material 60 is too thin, the chip is prone to leakage, the conductivity of the conductive material 60 will be affected, thereby affecting the voltage of the chip, and the filling effect of the conductive material 60 is reduced, the void rate increases, and the weldability is reduced; if the thickness of the passivation layer 40 is too thick, that is, the thickness of the conductive material 60 is too thick, the cost increases, and the conductive material 60 and the passivation layer 40 are prone to cracks, the void rate increases, and the weldability is also reduced. Preferably, the thickness of the conductive material 60 is 0.6-1.2μm. More preferably, the thickness of the conductive material 60 is 0.7-1.0μm.

[0126] Similarly, the thickness of the conductive material 60 filled in the filling hole depends on the depth of the filling hole, and the depth of the filling hole depends on the thickness of the second electrode 50. If the thickness of the conductive material 60 is too thin, the conductivity of the conductive material 60 will be affected, thereby affecting the voltage of the chip, and the filling effect of the conductive material 60 will decrease, the void rate will increase, and the weldability will decrease; if the thickness of the conductive material is too thick, the thickness of the second electrode 50 will also increase accordingly, thereby increasing the cost, and the conductive material 60 and the second electrode 50 are prone to cracks, the void rate will increase, and the weldability will also decrease. Preferably, the thickness of the conductive material 60 is 0.6 to 1.2 μm. More preferably, the thickness of the conductive material 60 is 0.7 to 1.0 μm.

[0127] The second electrode 50 of the present invention is used for welding packaging, so its area is affected by the packaging substrate and the packaging process. In order to improve the welding efficiency and welding effect, the areas of the N-type second electrode 51 and the P-type second electrode 52 are equal, and the heights are on the same horizontal plane. The first electrode 30 of the present invention is used for current expansion of the chip, which plays a role in reducing voltage and increasing brightness. Preferably, the material of the first electrode 30 is selected from one or more of Cr, Ni, Al, Ti, Pt, and Au; the material of the second electrode 50 is selected from one or more of Cr, Ni, Al, Ti, Pt, Au, and Sn.

[0128] Since the bottom layer of the first electrode 30 needs to have a good adhesion with the protective layer 26 and the epitaxial layer, Cr or Ti is selected for the bottom layer of the first electrode 30; and the top layer of the first electrode 30 needs to have a function of protecting the metal underneath when the passivation layer 40 is etched, and the top layer of the first electrode 30 needs to have a good adhesion with the second electrode 50 and the passivation layer 40, so Pt, Au, and Ti are selected for the top layer of the first electrode 30. Preferably, the first electrode 30 is a Cr / Al / Ti / Pt / Au / Ti stacked structure, which has a certain reflectivity and can reflect the light emitted by the epitaxial layer to the side of the substrate 10.

[0129] See also Figure 5 The second electrode 50 is a laminated structure, including a conductive layer 51 and a surface layer 52. The material of the conductive layer 51 is selected from one or more of Cr, Ni, Al, Ti, and Pt. The surface layer 52 is a laminated structure, including multiple layers of Sn / Au.

[0130] The surface layer is formed by compounding pure gold and pure tin to form a Sn / Au laminate, and the stress of the surface layer is eliminated by compounding Au and Sn in different proportions, thereby improving the wetting performance between the surface metal and the packaging substrate, thereby reducing the packaging void rate between the surface layer and the packaging substrate.

[0131] Specifically, when the package substrate is heated to a suitable eutectic temperature, gold or silver elements will penetrate into the surface layer to change the composition of the surface layer, thereby increasing the melting point of the surface layer, solidifying the surface layer and firmly soldering the flip-chip LED chip to the package substrate. The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold (Au) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the LED light efficiency is inversely proportional to the thermal resistance; (3) improving efficiency, as the LED eutectic is solidified in one step; and (4) the bonding strength is greater than that of silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0132] The thickness of Sn and the thickness of Au in the Sn / Au stack determine the ratio of Sn to Au in the Sn / Au stack. Since the surface layer of the present invention eliminates the stress of the surface layer by compounding AuSn in different ratios, the wetting performance between the surface metal and the packaging substrate is improved, thereby reducing the packaging void rate between the surface layer and the packaging substrate. The mass percentage of Au and Sn is within the range of (15% to 30%): (70% to 85%), and Au and Sn can form a stable eutectic compound. Therefore, the thickness of Sn and the thickness of Au in the Sn / Au stack cannot be too thick or too thin. Preferably, in the Sn / Au stack, the thickness of Sn is a1, and the thickness of Au is b1, wherein a1:b1=(15 to 30):(70 to 85). More preferably, a1:b1=(18 to 25):(75 to 82).

[0133] Preferably, in the Sn / Au stack, the thickness of Sn is 0.2-0.4 μm, and the thickness of Au is 1-1.5 μm.

[0134] Among them, the total thickness of the surface layer also plays an important role in reducing the packaging void rate between the surface layer and the packaging substrate; if the thickness of the surface layer is too thin, it will not play a role in reducing the packaging void rate; if the thickness of the surface layer is too thick, it will increase the preparation difficulty and production cost.

[0135] Preferably, the surface layer comprises 3 to 10 layers of Sn / Au stacked layers. More preferably, the surface layer comprises 3 to 5 layers of Sn / Au stacked layers.

[0136] The reflective layer 25 is a metal reflective layer 25, which reflects the light emitted by the epitaxial layer to the side of the substrate 10, so as to improve the light extraction efficiency of the flip-chip LED chip.

[0137] Preferably, the reflective layer 25 includes an Ag layer and an Ag layer protection layer, wherein the Ag layer protection layer covers the Ag layer to prevent the Ag layer from being oxidized when the protection layer 26 is deposited and to prevent the Ag layer from being etched when the protection layer 26 is etched.

[0138] Preferably, the material of the Ag layer protective layer is selected from one or more metals of Ti, W, Al, Ni, and Pt.

[0139] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A flip-chip LED chip that is easy to solder, comprising a substrate, a light-emitting structure disposed on the substrate, a first electrode disposed on the light-emitting structure, a passivation layer disposed on the light-emitting structure and the first electrode, and a second electrode disposed on the passivation layer, characterized in that: The passivation layer is provided with at least one electrode hole, and the electrode hole is filled with a conductive material with a preset hardness; The conductive material is flush with the surface of the passivation layer, and forms a conductive connection between the first electrode and the second electrode, and forms a seamless connection with the passivation layer, the first electrode and the second electrode; The hardness of the conductive material is ≥80HBS; The thickness of the conductive material is 0.6-1.2 μm.

2. The flip-chip LED chip that is easy to solder as claimed in claim 1, characterized in that: The conductive material is selected from one or more of nickel, chromium, titanium and tungsten; The conductive material is filled in the electrode hole by electron beam evaporation or thermal evaporation to form a seamless connection with the passivation layer, the first electrode and the second electrode; Wherein, the vacuum degree of the conductive material is ≥1.0*10 -4 Pa, and the plating rate is 0.8 to 2.0 angstroms / second.

3. The flip-chip LED chip that is easy to solder as claimed in claim 1, characterized in that: The side wall of the electrode hole and the surface of the passivation layer have a preset angle θ1, and the angle θ1 is 115-145°.

4. A flip-chip LED chip that is easy to solder, comprising a substrate, a light-emitting structure disposed on the substrate, a first electrode disposed on the light-emitting structure, a passivation layer disposed on the light-emitting structure and the first electrode, and a second electrode disposed on the passivation layer, characterized in that: The passivation layer is provided with at least two electrode holes, the electrode holes are etched to the surface of the first electrode, the second electrode is filled in the electrode holes and forms a conductive connection with the first electrode, the second electrode is provided with at least two filling holes, the filling holes are correspondingly arranged above the electrode holes, and the filling holes are filled with a conductive material with a preset hardness; Wherein, the conductive material is flush with the surface of the second electrode and forms a seamless connection with the second electrode; The hardness of the conductive material is ≥80 HBS.

5. The flip-chip LED chip that is easy to solder as claimed in claim 4, characterized in that: The conductive material is selected from one or more of nickel, chromium, titanium and tungsten; The conductive material is filled in the filling hole by electron beam evaporation or thermal evaporation to form a seamless connection with the second electrode; Wherein, the vacuum degree of the conductive material is ≤1.0*10 -4 Pa, and the plating rate is 0.8 to 2.0 angstroms / second.

6. The flip-chip LED chip that is easy to solder as claimed in claim 4, characterized in that: A preset angle θ2 is formed between the sidewall of the filling hole and the surface of the second electrode, and the angle θ2 is 115-145°.

7. A flip-chip LED chip that is easy to solder, comprising a substrate, a light-emitting structure disposed on the substrate, a first electrode disposed on the light-emitting structure, a passivation layer disposed on the light-emitting structure and the first electrode, and a second electrode disposed on the passivation layer, characterized in that: The passivation layer is provided with at least one electrode hole, the second electrode is provided with at least one filling hole, the filling hole is correspondingly arranged above the electrode hole, and the electrode hole and the filling hole are both filled with a conductive material with a preset hardness; The conductive material filled in the electrode hole is flush with the surface of the passivation layer, and forms a conductive connection between the first electrode and the second electrode, and forms a seamless connection with the passivation layer, the first electrode and the second electrode; the conductive material filled in the filling hole is flush with the surface of the second electrode, and forms a seamless connection with the second electrode; The hardness of the conductive material is ≥80 HBS.

8. The flip-chip LED chip that is easy to solder as claimed in claim 7, characterized in that: The conductive material is selected from one or more of nickel, chromium, titanium and tungsten; The conductive material is filled in the electrode hole by electron beam evaporation or thermal evaporation to form a seamless connection with the passivation layer, the first electrode and the second electrode; The conductive material is filled in the filling hole by electron beam evaporation or thermal evaporation to form a seamless connection with the second electrode; Wherein, the vacuum degree of the conductive material is ≤1.0*10 -4 Pa, and the plating rate is 0.8 to 2.0 angstroms / second.

9. The flip-chip LED chip that is easy to solder as claimed in claim 7, characterized in that: The side wall of the electrode hole and the surface of the passivation layer have a preset angle θ1, and the angle θ1 is 115-145°; A preset angle θ2 is formed between the sidewall of the filling hole and the surface of the second electrode, and the angle θ2 is 115-145°.

10. The flip-chip LED chip that is easy to solder as claimed in claim 7, characterized in that: The thickness of the conductive material filled in the electrode holes and the filled holes is 0.6 to 1.2 μm.

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