Method and apparatus for regulating output voltage of a power converter during load transients

Abstract

Embodiments of the present disclosure relate to methods and apparatus for regulating an output voltage of a power converter during a load transient. A controller for a power converter is provided, the controller comprising an estimator configured to estimate or calculate a slew rate of an output voltage of the power converter or a slew rate of an error voltage during a load transient, the error voltage corresponding to a difference between the output voltage and a target voltage, and a modulator configured to modify regulation of the output voltage based on the estimated or calculated slew rate. A corresponding voltage regulation method and an electronic system comprising the power converter are also described.

Description

Background Technology

[0001] Power converters are widely used to regulate the supply voltage of electronic loads. Voltage regulation is achieved by tracking the output voltage of the power converter to a target voltage. During load transients when the load current changes rapidly, the output voltage deviates from the target voltage. For a positive load current step where the load current rises rapidly, the error voltage corresponding to the difference between the output voltage and the target voltage may exceed a threshold, depending on the magnitude of the load current step. If the threshold is exceeded, some form of nonlinear compensation, such as activating an additional phase, is typically implemented to increase the total current delivered to the load. Similarly, for a negative load current step where the load current falls rapidly, the error voltage may fall below the threshold, depending on the magnitude of the load current step. In response, one or more phases can be deactivated to reduce the total current delivered to the load.

[0002] If the output voltage or target voltage is unstable during load transients, the error voltage used as part of the voltage regulation process may have a delay. This can cause the high-side pulses of the PWM (Pulse Width Modulation) to add together, or the PWM to enter a tri-state after a load step or load release, potentially leading to voltage undershoot or overshoot conditions that exceed permissible limits.

[0003] Some power converter controllers achieve voltage regulation at higher switching frequencies, allowing the use of smaller output inductors and resulting in less output voltage overshoot. Higher switching frequencies with smaller inductors are less efficient compared to lower switching frequencies with higher inductors. However, efficiency is a critical parameter when selecting a power converter. Another solution involves adding more output capacitors, which can reduce undershoot or overshoot of the output voltage during load transients. However, more output capacitors increase the overall system cost and require additional area.

[0004] Therefore, there is a need for improved methods and apparatus for regulating the output voltage of a power converter during load transients. Summary of the Invention

[0005] According to an embodiment of a method for regulating the output voltage of a power converter during a load transient, the method includes: estimating or calculating, during the load transient, a slew rate of the output voltage or a slew rate of an error voltage corresponding to the difference between the output voltage and a target voltage; and modifying the regulation of the output voltage based on the estimated slew rate or the calculated slew rate.

[0006] According to an embodiment of a controller for a power converter, the controller includes: an estimator configured to estimate or calculate, during load transients, a slew rate of the output voltage of the power converter or a slew rate of an error voltage corresponding to the difference between the output voltage and a target voltage; and a modulator configured to modify the regulation of the output voltage based on the estimated or calculated slew rate.

[0007] According to an embodiment of the electronic system, the electronic system includes: an electrical load; and a power converter configured to regulate the output voltage supplied to the electrical load, the power converter including a controller configured to: estimate or calculate a slew rate or an error voltage slew rate of the output voltage during load transients, the error voltage corresponding to the difference between the output voltage and a target voltage, and modify the regulation of the output voltage based on the estimated slew rate or the calculated slew rate.

[0008] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0009] The elements in the accompanying drawings are not necessarily drawn to scale relative to each other. The same reference numerals designate corresponding similar parts. Features of various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the accompanying drawings and described in detail below.

[0010] Figure 1 The diagram illustrates a block diagram of an embodiment of an electronic system, which includes a load and a power converter configured to regulate the output voltage supplied to the load.

[0011] Figure 2 The illustration shows an example where a positive load current transient occurs at time t1, when the load current increases rapidly, followed shortly by a negative load current transient occurs at time t2, when the load current decreases rapidly.

[0012] Figure 3 The diagram illustrates the relationship with Figure 2 The same example, but used for non-zero load lines.

[0013] Figure 4 The diagram illustrates a block diagram of an embodiment of a slew rate estimator included in a power regulator controller, which is used to estimate or calculate the slew rate of the output voltage or the slew rate of the error voltage during load transients.

[0014] Figure 5 The diagram illustrates a waveform example of a comparison window where the slew rate of the output voltage or the slew rate of the error voltage is estimated or calculated using a slew rate estimator.

[0015] Figure 6A The illustration shows three conversion rate detection windows that are implemented by the conversion rate estimator and appear sequentially without overlap.

[0016] Figure 6B The diagram illustrates the relationship with Figure 6A The three conversion rate detection windows are identical but implemented by overlapping conversion rate estimators.

[0017] Figure 6C It is Figure 6A The illustrated non-pipeline / non-overlapping window path and Figure 6B The illustration shows a comparison of pipeline / overlapping window approaches.

[0018] Figure 7 The diagram illustrates a waveform that may cause jitter in the output voltage due to the flattening of the slope of the slew rate estimated or calculated by the slew rate estimator.

[0019] Figure 8 The diagram illustrates a block diagram of another embodiment of a slew rate estimator included in a power regulator controller, which is used to estimate or calculate the slew rate of the output voltage or the slew rate of the error voltage during load transients. Detailed Implementation

[0020] The described embodiments illustrate an apparatus and method for regulating the output voltage of a power converter during load transients without the need for an additional output capacitor and without operating at higher switching frequencies with lower inductance. The voltage regulation techniques described herein provide a faster response to load transients by estimating or calculating the slew rate of the output voltage or the slew rate of the error voltage during load transients, and modifying the output voltage regulation based on the estimated or calculated slew rate. The slew rate of the output voltage or the slew rate of the error voltage can be estimated or calculated much faster than waiting for the error voltage to exceed a threshold indicating that corrective action should be taken. Compared to threshold detection schemes based on voltage error, modifying the output voltage regulation based on the estimated or calculated slew rate of the output voltage or the error voltage reduces output voltage overshoot and / or undershoot, especially when the output voltage or target voltage is unstable during load transients.

[0021] As used herein, the term "power converter" broadly refers to any type of power converter or voltage regulator (VR) that provides one or more regulated voltages to one or more electronic loads, such as Ethernet switches, ASICs (Application-Specific Integrated Circuits), memory devices, processors such as central processing units (CPUs), microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), artificial intelligence (AI) accelerators, image processors, network or packet processors, coprocessors, multi-core processors, front-end processors, baseband processors, etc. For example, a power converter can be a buck converter, a boost converter, a buck-boost converter, a switched-capacitor voltage regulator, a step-down converter, etc. Power converters can be implemented as power device modules.

[0022] As used herein, the term "power device module" refers to a packaged functional component that includes at least one power switch of a power stage for converting voltage from one level to another, for example, as performed in power conversion and voltage regulation. The power device module may also include driver circuitry for driving the at least one power switch. Additionally, the power device module may include a controller for controlling the driver circuitry to implement the power converter. Alternatively, the controller and / or driver functions may be implemented outside the power device module. The driver circuitry for the at least one power switch included in the power device module may also be outside the power device module. Various passive components constituting the power converter, such as capacitors and / or inductors, may be included in the power device module, surface-mounted to the power device module, located on a separate board, etc. The following describes in more detail various embodiments of the power converter, methods for regulating the output voltage of the power converter during load transients, and electronic systems including the power converter.

[0023] Figure 1 An embodiment of an electronic system 100 is illustrated, which includes a load 102 and a power converter 104 configured to regulate the output voltage (Vout) supplied to the load 102. The load 102 can be any type of electronic load requiring a regulated supply voltage. For example, the load 102 can be an Ethernet switch, ASIC, memory device, processor such as a CPU, microprocessor, GPU, DSP, AI accelerator, image processor, network or packet processor, coprocessor, multi-core processor, front-end processor, baseband processor, etc. The power converter 104... Figure 1The example shown is a buck converter only. In this example, the power converter 104 includes multiple power stages 106, each configured to provide a phase current (iph) to a load 102 through a corresponding inductor (Lout), and an output capacitor (Cout) to reduce output voltage ripple.

[0024] The controller 108 for the power converter 104 is configured to generate a modulated signal (mod) for controlling the phase current iph of each power stage 106 to regulate the output voltage Vout supplied to the load 102. Alternatively, the power converter 104 may comprise a single phase / power stage 106. Generally, the power converter 104 can be any type of power converter or voltage regulator that provides one or more regulated voltages (Vout) to the load 102. For example, the power converter 104 may be such as... Figure 1 The buck converter, boost converter, buck-boost converter, switched capacitor voltage regulator, and step-down converter shown can be implemented as a power device module, as previously described herein.

[0025] The power converter controller 108 includes control circuitry 110 for regulating the output voltage Vout. Control circuitry 110 includes a modulator 112 for generating a modulation signal “mod” that controls the phase current iph of each power stage 106 to regulate the output voltage Vout supplied to the load 102. In one embodiment, modulator 110 implements pulse width modulation (PWM).

[0026] The controller 108 also includes a slew rate estimator 114, which estimates or calculates the slew rate of the output voltage Vout or the slew rate of an error voltage (Verr) during load transients, the error voltage corresponding to the difference between the output voltage Vout and the target voltage (Vtgt). During load transients, the load current (i_load) changes rapidly. A load transient can take the form of a positive load current step in which the load current i_load rises rapidly or a negative load current step in which the load current i_load falls rapidly.

[0027] Modulator 112 modifies the regulation of output voltage Vout based on the slew rate estimated or calculated by slew rate estimator 114. For example, in the case of a positive load current step, modulator 112 may activate one or more additional phase / power stages 106 to increase the total load current i_load. In the case of a negative load current step, modulator 112 may deactivate one or more phase / power stages 106 to decrease the total load current i_load.

[0028] The load 102 and the power converter controller 108 can communicate directly or indirectly, such as Figure 1 The communication can be unidirectional, from the load 102 to the controller 108, for example, to provide voltage identification (VID) information related to the voltage target setpoint, or it can be bidirectional, so that the controller 108 can also transmit telemetry information such as temperature and current to the load 102.

[0029] The power converter controller 108 also has a first voltage sensing terminal Vsenp and a second voltage sensing terminal Vsenn for sensing the output voltage Vout of the power converter 104. The voltage sensing terminals Vsenp and Vsenn of the controller 108 provide interfaces to which the corresponding voltage sensing line 116 is connected. The first voltage sensing terminal Vsenp of the controller 108 can be a positive sensing terminal, and the second voltage sensing terminal Vsenn of the controller 108 can be a negative sensing terminal or a reference (ground) sensing terminal.

[0030] Although the regulated output voltage Vout is shown as being sensed across the output capacitor Cout, this is for illustrative purposes only. The sensing lines 116 connected to the voltage sensing terminals Vsenp and Vsenn of controller 108 may not necessarily be directly connected to the output capacitor Cout as shown. For example, one end of the voltage sensing line 116 may be connected to the corresponding voltage sensing terminals Vsenp and Vsenn of controller 108, and the opposite end may be connected to the I / O (input / output) circuitry of one or more power stages in power stage 106.

[0031] Generally, the voltage sensing lines 116 connected to the voltage sensing terminals Vsenp and Vsenn of the power converter controller 108 carry a voltage corresponding to the output voltage Vout of the power converter 104, so that the voltage sensing circuit 118 included in the controller 108 can directly measure / sensor the regulated output voltage Vout at the first voltage sensing terminal Vsenp and the second voltage sensing terminal Vsenn of the controller 108. The voltage sensing terminals Vsenp and Vsenn of the controller 108 can be physically implemented as pins, connectors, terminal blocks, etc.

[0032] The power converter controller 108 may also include a current sensing and balancing circuit 120 for sensing the phase current (Iph) delivered by each power stage 106 at the corresponding current sensing terminal Isen of the controller 108 and converting the sensed current information into phase current information. The current sensing and balancing circuit 120 also converts the phase current information into adjustments to the duty cycle generated by the modulator 112 for each individual power stage 106 to adjust the phase current iph, thereby keeping the phase current iph balanced in multiphase operation.

[0033] Figure 2 The diagram illustrates an example of a positive load current transient at time t1, where the load current i_load increases rapidly, followed by a negative load current transient at time t2, where the load current i_load decreases rapidly. When the transient occurs at time t1, the load current i_load increases, and the output voltage Vout correspondingly decreases and then recovers. At the end of the short load transient at time t2, the output voltage Vout jumps back up. Furthermore, Figure 2 The diagram also shows the overshoot limit (Verr_over), undershoot limit (Verr_under), and target voltage (Vtgt), with the power converter's output voltage Vout adjusted to this target voltage (Vtgt).

[0034] The error voltage (Verr) can be calculated as Verr = Vout - Vtgt. An undershoot condition occurs when the error voltage Verr drops below the undershoot limit Verr_under. An overshoot condition occurs when the error voltage Verr exceeds the overshoot limit Verr_over. The slew rate of the output voltage Vout is ΔVout / Δt. If the output voltage Vout and / or the target voltage Vtgt have not stabilized before the short load transient at time t2 ends, adjusting the output voltage Vout based on the slew rate of Vout is faster than conventional Verr-based threshold detection. Verr-based threshold detection involves modifying the output voltage regulation in response to the error voltage Verr passing the overshoot limit Verr_over (overshoot condition) or the undershoot limit Verr_under (undershoot condition).

[0035] In contrast, at the beginning of a load transient (e.g., Figure 2 At time t1 or t2, the slew rate of the output voltage Vout changes almost instantly, thus allowing the modulator 112 to modify the output voltage regulation more quickly compared to conventional Verr-based threshold detection. Instead, the slew rate of the error voltage Verr can be used to determine when to modify the regulation of the output voltage Vout.

[0036] By using Vout or Verr slew rate detection instead of the conventional Verr-based threshold detection, controller 108 can modify the regulation of the output voltage Vout more quickly, resulting in less Vout overshoot for negative load current steps and less undershoot for positive load current steps. This is in Figure 2 This is self-evident. By examining the slope of the Vout (or Verr) curve, the slew rate estimator 114 can determine more quickly when a load transient occurs without waiting for the error voltage Verr to exceed the upper limit Verr_over or the lower limit Verr_under before the action is triggered by the modulator 112.

[0037] For example, modulator 112 may assert additional PWM pulses and / or add additional phase / power stage 106 more quickly in response to positive load current transients to reduce Vout undershoot, or may blank the PWM high-side pulse or put the PWM into tri-state more quickly in response to negative load current transients to reduce Vout overshoot. Generally, slew rate estimator 114 estimates or calculates the slew rate of output voltage Vout or the slew rate of error voltage Verr to determine when modulator 112 should modify the regulation of output voltage Vout.

[0038] Figure 2 The zero-load line scenario is illustrated. Generally, the upper and lower load line boundaries (Verr_over, Verr_under) should be set to provide an acceptable range for the output voltage Vout of load 102, for example, when the processor is the load 102. The output voltage Vout should not exceed these load line boundaries under non-transient load conditions to ensure proper operation of load 102. In the case of a 'zero' load line, this means that the load line (Vtgt) has zero slope and therefore does not change according to the load current i_load. Otherwise, the target voltage Vtgt changes according to the load current i_load. The load line can be linear or non-linear.

[0039] Figure 3 The diagram illustrates the relationship between... Figure 2 The same example, but for a non-zero load line (Vtgt). According to this embodiment, the target voltage Vtgt changes based on the load current i_load. For example, the target voltage Vtgt can be a function of the sensed inductor current iL. The error thresholds Verr_over and Verr_under shift accordingly. As... Figure 2As in the example, adjusting the output voltage Vout based on the slew rate of Vout or based on the slew rate of Verr is faster than conventional threshold detection based on Verr, especially if the output voltage Vout and / or the target voltage Vgt have not yet stabilized before the short load transient at time t2 ends. Therefore, the slew rate estimator 114 determines when the load transient at time t2 occurs more quickly and does not need to wait for the error voltage Verr to exceed the upper limit Verr_over before triggering the action via the modulator 112.

[0040] Figure 4 An embodiment of a slew rate estimator 114 included in a power regulator controller 108 is illustrated. This slew rate estimator 114 is used to estimate or calculate the slew rate of the output voltage Vout or the slew rate of the error voltage Verr during load transients. According to this embodiment, the slew rate estimator 114 includes an analog-to-digital converter (ADC) 200 configured to digitize an analog measurement of the output voltage Vout at a frequency F1. The ADC 200 may or may not be part of the controller voltage sensing circuitry 118.

[0041] The conversion rate estimator 114 also includes a delay unit 202 configured to delay the digitized measurement of the output voltage V_dig by a certain amount T_delay at frequency F1. The delay amount T_delay, which can be programmable or fixed, determines how much time is provided for the comparison, i.e., the window size.

[0042] The slew rate estimator 114 also includes a subtractor or adder 204 configured to subtract or add the digitally measured delay V_dig' of the output voltage Vout and the digitally measured output voltage Vout V_dig, respectively, to obtain the slew rate value SR. The adder / subtractor 204 estimates or measures the change (ΔV) in the output voltage Vout by adding V_dig' to V_dig or subtracting V_dig' from V_dig. Since Δt is known, this change (ΔV) can be used to estimate or calculate the slew rate value SR, where Δt corresponds to the delay T_delay implemented by the delay unit 202, thus defining the size of the comparison window. Alternatively, the slew rate value SR can be based on the error voltage Verr.

[0043] Figure 5An example comparison window is illustrated, on which the slew rate of the output voltage Vout or the slew rate of the error voltage Verr is estimated or calculated by the slew rate estimator 114. With a wide comparison window (larger Δt), the voltage difference (ΔV) should be large, thus allowing for more accurate detection of slope changes (slew rate = ΔV / Δt), but this also results in a larger delay due to the larger Δt. With a narrow comparison window (smaller Δt), slew rate detection is more susceptible to changes in Vout, potentially leading to false tripping, but with a smaller introduced delay. A sufficiently small comparison window can be selected to avoid unnecessary delay, but it cannot be too small to induce false tripping. In one embodiment, the delay T_delay implemented by the slew rate estimator 114, and thus the window size (Δt), is based on the system noise characteristics. The slew rate estimator 114 can execute the comparison window periodically, where the periodicity of the comparison window corresponds to the amount of time (T_delay) by which the digital measurement result V_dig of the output voltage Vout or the error voltage Verr is delayed. Furthermore, the delay T_delay can be programmable or fixed.

[0044] Figure 6A The diagram illustrates a scenario where three slew rate detection windows, A, B, and C, appear consecutively without overlap. As explained above, if the slew rate detection windows A, B, and C are too wide (Δt is large), the detection time will fluctuate even if the detection occurs earlier. This causes the timing to vary based on the window size, resulting in fluctuations (deviations) in the slew rate value SR.

[0045] Figure 6B The diagram illustrates the relationship between... Figure 6A The ADC 200 has three identical but overlapping slew rate detection windows A, B, and C. That is, the next consecutive slew rate detection window in the series begins before the end of the immediately preceding consecutive slew rate detection window. According to this embodiment, for each slew rate detection window A, B, and C in a series of overlapping windows, the ADC 200 digitizes the analog measurement result of the output voltage Vout or error voltage Verr at the beginning of each window A, B, and C. The delay unit 202 delays the digitized voltage measurement result V_dig to define the end of each window A, B, and C. The adder / subtractor 204 subtracts or adds the delayed digitized voltage measurement result V_dig' to the digitized voltage measurement result V_dig to obtain the slew rate value SR at the end of each window A, B, and C.

[0046] For each of the series of overlapping slew rate detection windows A, B, C, the detector 206 of the slew rate estimator 114 compares the slew rate value SR at the end of each window A, B, C with at least one threshold Thr1 (e.g., overshoot) and / or Thr2 (e.g., undershoot), and sets the corresponding latch 216, 218 in response to the slew rate value SR at the end of any window A, B, C exceeding the corresponding threshold Thr1, Thr2. As explained above, if the output of one of the latches 216, 218 is set, the detector 206 indicates that the regulation of the output voltage Vout should be modified.

[0047] according to Figure 6B The illustrated embodiment, and Figure 6A Compared to the non-overlapping steps n, n+1, n+2, n+3 in the previous method, the slew rate detection windows A, B, and C overlap with finer steps (smaller intervals). Therefore, the slew rate estimator 114 does not need to wait for the window where the load transient occurs to end before taking corrective action. Instead, multiple slew rate detection windows are pipelined in an overlapping manner, effectively reducing the window size to allow for corrective action in response to load transients. As a result, the change in Vout or Verr from the load transient detection point to the time of taking corrective action is smaller, thus reducing jitter.

[0048] Figure 6B The overlapping window approach shown can be implemented only for the first threshold detection circuit 208 for early detection of overshoot, only for early detection of undershoot, or for both the first and second threshold detection circuits 208 and 210 for early detection of both overshoot and undershoot. The overlapping window approach can be implemented by replicating the delay unit 202 and adder / subtractor 204 of the slew rate estimator 114 to derive an overlapping instance of the slew rate estimate / calculation.

[0049] Figure 6C Will Figure 6A The illustrated non-pipeline / non-overlapping window path and Figure 6B The illustrated pipeline / overlapping window path is compared. Two load transients are shown. The first load transient occurs at time t1, and the second load transient occurs at time t2. Figure 6AThe illustrated non-pipeline / non-overlapping window path does not detect load transients until the end of the second slew rate detection window, which occurs at time t3, because that is when the ΔV value of the second slew rate detection window is calculated. This results in a delay t3-t1 for taking corrective action in response to the first load transient and a delay t3-t2 for taking corrective action in response to the second load transient.

[0050] Because the windows overlap, and thus provide a smaller time interval for decision points, even if the size of the conversion rate detection window is the same as the size of the non-pipelined / non-overlapping window path, the conversion rate can still be achieved through... Figure 6B The illustrated pipeline / overlapping window path raises the question of whether the voltage regulation decision point should be modified to be more precise / shorter. (This is in contrast to...) Figure 6A Compared to the non-pipeline / non-overlapping window path illustrated, by Figure 6B The illustrated pipeline / overlapping window approach detects both load transients earlier because the corresponding ΔV values ​​are obtained significantly earlier due to the overlapping of the slew rate detection windows. This results in a significant reduction in the delay required to take corrective action in either load transient case.

[0051] Detector 206 may be included in the conversion rate estimator 114, or as... Figure 4 The modulator 112 is associated with a slew rate estimator 114 to determine whether the estimated or calculated slew rate value SR exceeds an overshoot threshold and / or an undershoot threshold. In response to the estimated or calculated slew rate SR exceeding either threshold, the modulator 112 modifies the regulation of the output voltage Vout. According to this embodiment, a latch reset is used to signal that the voltage regulation should be modified, and the latch reset is based on a threshold comparison. Ideally, the detection of load transients will not subside until the error voltage Verr is sufficiently small, because the slope of Vout or Verr, and therefore the slew rate, can decrease rapidly, but the error voltage Verr will still exist. Therefore, an error voltage threshold comparison of Verr = Vout - Vtgt can be used to determine when to reset the latch. The threshold can be variable and depends on, for example, the error voltage Verr. Alternatively, the threshold can be fixed. In either case, detector 206 can perform threshold comparison only for positive load current steps (undershoot), only for negative load current steps (overshoot), or for both positive and negative load current steps (undershoot and overshoot).

[0052] For example, detector 206 may include: a first threshold detection circuit 208 for determining when the slew rate value SR exceeds a first threshold (undershoot); and / or a second threshold detection circuit 210 for determining when the slew rate value SR drops below a second threshold (overshoot). Each threshold detection circuit 208, 210 includes: corresponding comparators 212, 214 configured to compare the slew rate value SR with corresponding thresholds Thr1, Thr2; and corresponding latches 216, 218, such as SR (set-reset) latches, configured to set in response to the slew rate value SR exceeding the corresponding thresholds Thr1, Thr2. The outputs (ATRL_fast, ATRH_fast) of the corresponding latches 216, 218 indicate whether the latches 216, 218 are set and whether the regulation of the output voltage Vout needs to be modified. In response to the target voltage Vtgt, the corresponding latch outputs ATRL_fast and ATRH_fast indicate a predetermined range within which latches 216 and 218 are reset, with each latch 216 and 218 being reset based on the error voltage Verr.

[0053] More specifically, the first threshold detection circuit 208 includes: a first comparator 212 for comparing a slew rate value SR with a first threshold Thr1; and a first latch 216 configured to be set in response to the slew rate value SR falling below the first threshold Thr1 (undershoot condition / negative slew rate slope). Similarly, the second threshold detection circuit 210 includes: a second comparator 214 for comparing a slew rate value SR with a second threshold Thr2; and a second latch 218 configured to be set in response to the slew rate value SR exceeding the second threshold Thr2 (overshoot condition / positive slew rate slope). In one embodiment, in response to the output ATRL_fast of the first latch 216 indicating that the first latch 216 is set, the modulator 112 adds one or more additional PWM pulses used in regulating the output voltage Vout. In response to the output ATRH_fast indication of the second latch 218 being set, the modulator 112 either blanks one or more PWM pulses or tri-states the PWM used in regulating the output voltage Vout.

[0054] The second threshold detection circuit 210 may further include a logic OR gate or similar logic 220, which is used to modify the regulation of Vout in response to the output ATRH_fast of the second latch 218 indicating that the second latch 218 is set, or in response to a legacy overshoot signal ('legacy ATRH') that can be generated by a conventional Verr-based threshold detection method. Similarly, the first threshold detection circuit 208 may include a logic OR gate or similar logic 222, which is used to modify the regulation of Vout in response to the output ATRL_fast of the first latch 216 indicating that the first latch 216 is set, or in response to a legacy undershoot signal ('legacy ATRL') that can be generated by a conventional Verr-based threshold detection method.

[0055] Figure 7 The illustration depicts a scenario where jitter in the output voltage Vout can occur due to the flattening of the slope of the slew rate estimated or calculated by the slew rate estimator 114. The output voltage Vout and the PWM control signals PWM1 and PWM2 for the high-side and low-side power switches of the power stage 106 of the power converter 104 are plotted around the time of the negative load current step transient, during which the load current i_load drops rapidly, and in response, the output voltage Vout rises. In response to this load transient, the modulator 112 can reduce one or more phases / power stages 106 to decrease the total load current i_load. As described herein, the slew rate estimator 114 determines when the modulator 114 should take corrective action based on the slew rate of the output voltage Vout or the slew rate of the error voltage during the load transient. The Vout transient waveform may change slowly due to the rise time of the output capacitance and the load current i_load. This produces an RC-type response when the load current i_load stops rising. This means that even before the load transient event has fully subsided, the slope of the output voltage Vout begins to flatten, which may cause the voltage regulation modification flag (ATRH_fast in this case) to disappear. This will result in output voltage waveforms with different slopes / slew rates (SR1, SR2, SR3) depending on when the slew rate value SR is estimated / calculated by the slew rate estimator 114.

[0056] To mitigate this effect, hysteresis can be added based on whether the corresponding latches 216, 218 of detector 206 are set to override the reset operation. According to this embodiment, to reset the corresponding latches 216, 218, the slew rate value SR estimated / calculated by slew rate estimator 114 must be lower than the corresponding thresholds Thr1, Thr2. Because load transients can be detected so quickly using the slew rate-based detection techniques described herein, the estimated / calculated slew rate value SR may not have exceeded the corresponding thresholds Thr1, Thr2 before the slope decreases. Because the slew rate value SR is lower than the corresponding thresholds Thr1, Thr2, the corresponding voltage regulation modification flag (ATRH_fast or ATRL_fast) disappears, thus avoiding glitches. If latched, a flatter slope is desired to maintain the correction action achieved by modulator 112. Different delays and slope thresholds with hysteresis can be used to mitigate this problem. Even if the Vout slope decreases, the power converter 104 may still have overshoot or undershoot issues; therefore, the correction action implemented by the modulator 112 should be allowed to continue. Adding hysteresis allows this to happen.

[0057] Figure 8 Another embodiment of a slew rate estimator 114 included in a power regulator controller 108 is illustrated. The slew rate estimator 114 is used to estimate or calculate the slew rate of the output voltage Vout or the slew rate of the error voltage Verr during load transients. Figure 8 The illustrated embodiments and Figure 4 The illustrated embodiment is similar. However, the difference is that if the conversion rate value SR exceeds a threshold, at least one of the delay implemented by the delay unit 202 and the threshold Thr1 and Th2 implemented by the corresponding threshold detection circuit 208 is increased.

[0058] Delay unit 202 outputs a first delayed digital measurement result V_L' to detect undershoot caused by a load transient with a positive load current step; and outputs a second delayed digital measurement result V_H' to detect overshoot caused by a load transient with a negative load current step. If the corresponding slew rate value SR_L is lower than the relevant threshold indicated by the signal Fast_setL, the first multiplexer of similar circuit 300 selects a smaller delay (T_delayH) to generate the first delayed digital measurement result V_L', and if the slew rate value SR_L exceeds the relevant threshold, the first multiplexer of similar circuit 300 selects a larger delay (T_delayH_hyst) to generate the first delayed digital measurement result V_L'. Similarly, if the corresponding conversion rate value SR_H is lower than the relevant threshold indicated by the signal Fast_setH, the second multiplexer similar to circuit 302 selects a smaller delay (T_delayL) to generate the second delay digitized measurement result V_H', and if the conversion rate value SR_H exceeds the relevant threshold, the second multiplexer similar to circuit 302 selects a larger delay (T_delayL_hyst) to generate the second delay digitized measurement result V_H'.

[0059] Additionally or separately, detector 206 may introduce hysteresis to mitigate slope flattening. In one embodiment, detector 206 includes a third multiplexer similar to circuit 304 that selects a smaller threshold (Thr1) for comparison with the first slew rate value SR_L generated by slew rate estimator 114 if the slew rate value SR_L is lower than the relevant threshold indicated by signal Fast_setL, and selects a larger threshold (Thr1_hyst) for comparison with the first slew rate value SR_L if the slew rate value SR_L exceeds the relevant threshold. Detector 206 also includes a fourth multiplexer similar to circuit 306. If the slew rate value SR_H is lower than the relevant threshold indicated by the signal Fast_setH, the fourth multiplexer similar to circuit 306 selects a smaller threshold (Thr2) for comparison with the second slew rate value SR_H generated by slew rate estimator 114. If the slew rate value SR_H exceeds the relevant threshold, the fourth multiplexer similar to circuit 306 selects a larger threshold (Thr2_hyst) for comparison with the second slew rate value SR_H. As previously described herein, the thresholds Thr1, Thr1_hyst, Thr2, and Thr2_hyst input to latches 216 and 218 of detector 206 can be programmable or fixed.

[0060] As used herein, the term 'ATR' refers to Active Transient Response, which is a form of nonlinear control implemented by the power converter controller 108. 'ATRL' refers to Active Transient Response for undershoot conditions, and 'ATRH' refers to Active Transient Response for overshoot conditions.

[0061] The power converter controller 108 may include a PID (Proportional-Integral-Derivative) controller for linear control and an ATR circuit for nonlinear control. The ATR circuit included in the power converter controller 108 can detect the voltage level and / or current level and / or slew rate of the output voltage at the load 102, and provide a corresponding signal to the modulator 112, for example, based on the magnitude of the deviation between the load voltage or the slew rate of the load voltage and a target voltage. For example, the ATR circuit included in the power converter controller 108 can compare the load voltage or the slew rate of the load voltage with one or more thresholds. If the transient voltage or corresponding slew rate at the load 102 deviates from the target voltage by one or more preset thresholds, the ATR circuit can provide the modulator 112 with a signal as a function of the magnitude of the detected voltage deviation from the target voltage. For example, the ATR output may be as previously described herein. Figure 4 and Figure 8 One of the following described: 'ATRL_fast', 'ATRH_fast', 'traditional ATRL', or 'traditional ATRH'.

[0062] Additionally or separately, the ATR circuitry included in the power converter controller 108 can provide such ATR event signals to the AVP (Adaptive Voltage Positioning) circuitry of the controller 108 to provide early predictive changes, since the sensed load current change is delayed through the output inductor L, so that the early predictive change can occur before the time when the sensed current change is received from the ADC of the current sensing and balancing circuit 120.

[0063] As long as the voltage at load 102 is maintained within a predetermined limit, the ATR circuit included in the power converter controller 108 will not be activated, and none of the corresponding signals 'ATRL_fast', 'ATRH_fast', 'traditional ATRL', and 'traditional ATRH' will be activated. However, when a change in the power demand of load 102 causes the voltage at load 102 to deviate beyond the predetermined limit, the ATR implemented by the power converter controller 108 provides the corresponding signal 'ATRL_fast', 'ATRH_fast', 'traditional ATRL', or 'traditional ATRH' to the modulator 112 to quickly correct the voltage deviation with minimal noise generation. Therefore, the power converter controller 108 can identify transient events in the output signal corresponding to the slew rate of the load voltage deviation and / or the load voltage Vout at load 102, or identify transient events in the output signal corresponding to the slew rate of the voltage deviation and / or the error voltage Verr at load 102.

[0064] When the load current changes, the power converter controller 108 can automatically and / or autonomously adapt the operating mode to maximize efficiency. For example, the controller 108 can control the number of phases / power stages 106 that supply power to the load 102. Specifically, the controller 108 can optimize the power efficiency of the power converter 104 by increasing and / or decreasing the number of active phases / power stages 106.

[0065] The power converter controller 108 can implement adaptive fall / rise timing and adaptive non-overlap timing for phase / power stage 106 to optimize efficiency, such as across the entire load current range of the relevant application. Furthermore, for each phase / power stage 106 setting, the controller 108 can vary the non-overlapping delay between the turn-off of the synchronous FET and the turn-on of the control FET to further optimize efficiency. Additionally, the ATR implemented by the power converter controller 108 can implement multi-level sensing technology to detect not only voltage shifts requiring active transient response but also the magnitude of the shift. When the transient magnitude, for example, crosses multiple thresholds in the negative direction, all previously disabled phase / power stages 106 can be immediately activated.

[0066] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0067] Example 1. A method for regulating the output voltage of a power converter during a load transient, the method comprising: estimating or calculating, during the load transient, a slew rate of the output voltage or a slew rate of an error voltage corresponding to the difference between the output voltage and a target voltage; and modifying the regulation of the output voltage based on the estimated or calculated slew rate.

[0068] Example 2. The method of Example 1, wherein modifying the regulation of the output voltage based on the estimated slew rate or the calculated slew rate includes: modifying the regulation of the output voltage in response to the estimated slew rate or the calculated slew rate exceeding a threshold.

[0069] Example 3. The method of Example 2, where the threshold is variable and depends on the error voltage.

[0070] Example 4. The method of any one of Examples 1 to 3, wherein estimating or calculating the slew rate of the output voltage or the slew rate of the error voltage comprises: digitizing an analog measurement of the output voltage; delaying the digitized measurement of the output voltage; and subtracting or adding the delayed digitized measurement of the output voltage to the digitized measurement of the output voltage to obtain a slew rate value.

[0071] Example 5. The method of Example 4, wherein modifying the regulation of the output voltage based on the estimated slew rate or the calculated slew rate includes: comparing the slew rate value with a threshold; and, in response to the slew rate value exceeding the threshold, setting a latch, wherein the output of the latch indicates that the latch is set and the regulation of the output voltage is to be modified.

[0072] Example 6. The method of Example 5, wherein the comparison is performed periodically, and wherein the periodicity of the comparison corresponds to the amount by which the digital measurement of the output voltage is delayed.

[0073] Example 7. The method of Example 6, where the delay is programmable.

[0074] Example 8. The method of any one of Examples 5 to 7 further includes: resetting the latch based on the error voltage and in response to the target voltage returning to a predetermined range, wherein the output of the latch indicates that the latch has been reset.

[0075] Example 9. A method of any one of Examples 4 and 6 to 8, wherein modifying the regulation of the output voltage based on the estimated slew rate or the calculated slew rate comprises: comparing a slew rate value with a first threshold; setting a first latch in response to a slew rate value being greater than the first threshold; blanking one or more PWM (pulse width modulation) pulses or tri-stating the PWM used in the regulation of the output voltage in response to an output indication of the first latch being set; comparing a slew rate value with a second threshold; setting a second latch in response to a slew rate value being less than the second threshold; and summing one or more additional PWM pulses used in the regulation of the output voltage in response to an output indication of the second latch being set.

[0076] Example 10. The method of any one of Examples 4 to 9 further includes: for each window in a series of overlapping windows, digitizing an analog measurement of the output voltage at the beginning of the window, delaying the digitized measurement of the output voltage to define the end of the window, and subtracting or adding the delayed digitized measurement of the output voltage to obtain a conversion rate value at the end of the window.

[0077] Example 11. The method of Example 10, wherein modifying the regulation of the output voltage based on the estimated slew rate or the calculated slew rate comprises: for each window in a series of overlapping windows, comparing the slew rate value at the end of the window with a threshold; and in response to the slew rate at the end of any window in the window exceeding the threshold, setting a latch, wherein the output of the latch indicates that the latch is set and the regulation of the output voltage is to be modified.

[0078] Example 12. The method of any one of Examples 4 to 11 further includes: increasing the delay and at least one of the threshold if the conversion rate value exceeds the threshold.

[0079] Example 13. The method of any one of Examples 1 to 12 further includes: identifying transient events in the signal corresponding to the slew rate of the load voltage offset and / or the output voltage; or identifying transient events in the signal corresponding to the slew rate of the voltage offset and / or the error voltage.

[0080] Example 14. A controller for a power converter, the controller comprising: an estimator configured to estimate or calculate, during a load transient, a slew rate of an output voltage or a slew rate of an error voltage corresponding to the difference between the output voltage and a target voltage; and a modulator configured to modify the regulation of the output voltage based on the estimated or calculated slew rate.

[0081] Example 15. The controller of Example 14 further includes: a detector configured to determine whether the estimated slew rate or the calculated slew rate exceeds a threshold, wherein the modulator is configured to modify the regulation of the output voltage in response to the estimated slew rate or the calculated slew rate exceeding the threshold.

[0082] Example 16. The controller of Example 15, where the threshold is variable and depends on the error voltage.

[0083] Example 17. A controller of Example 15 or 16, wherein the estimator includes: an analog-to-digital converter configured to digitize an analog measurement of the output voltage; a delay unit configured to delay the digitized measurement of the output voltage; and a subtractor or adder configured to subtract or add the delayed digitized measurement of the output voltage and the digitized measurement of the output voltage, respectively, to obtain a conversion rate value.

[0084] Example 18. The controller of Example 17, wherein the detector includes: a comparator configured to compare a slew rate value with a threshold; and a latch configured to set in response to a slew rate value exceeding the threshold, wherein the output of the latch indicates that the latch is set and the regulation of the output voltage is to be modified.

[0085] Example 19. The controller of Example 18, wherein the latch is further configured to: reset based on the error voltage in response to the target voltage returning to a predetermined range, and wherein the output of the latch indicates that the latch has been reset.

[0086] Example 20. A controller of any one of Examples 15 and 17 through 19, wherein the detector comprises: a first comparator configured to compare a slew rate value with a first threshold; a first latch configured to be set in response to a slew rate value being greater than the first threshold; a second comparator configured to compare a slew rate value with a second threshold; and a second latch configured to be set in response to a slew rate value being less than the second threshold, wherein a modulator is configured to blank one or more PWM (Pulse Width Modulation) pulses or tri-state the PWM used in regulating the output voltage in response to an output indication of the first latch being set, wherein the modulator is configured to add one or more additional PWM pulses used in regulating the output voltage in response to an output indication of the second latch being set.

[0087] Example 21. The controller of Example 17, wherein for each window in a series of overlapping windows, the estimator is configured to: digitize the analog measurement of the output voltage at the beginning of the window, delay the digitized measurement of the output voltage to define the end of the window, and subtract or add the delayed digitized measurement of the output voltage to the digitized measurement of the output voltage to obtain a slew rate value at the end of the window.

[0088] Example 22. The controller of Example 21, wherein for each window in a series of overlapping windows, the detector is configured to: compare the slew rate value at the end of the window with a threshold, and set a latch in response to any window at the end of the window having a slew rate value exceeding the threshold, the output of the latch indicating that the latch is set, and the regulation of the output voltage to be modified.

[0089] Example 23. The controller of Example 17, wherein if the conversion rate value exceeds a threshold, the estimator is configured to increase the delay and / or the detector is configured to increase the threshold.

[0090] Example 24. The controller of any one of Examples 14 to 23 further includes control circuitry configured to: identify transient events in a signal corresponding to the slew rate of load voltage offset and / or output voltage, or identify transient events in a signal corresponding to the slew rate of voltage offset and / or error voltage.

[0091] Example 25. An electronic system comprising: an electrical load; and a power converter configured to regulate an output voltage supplied to the electrical load, the power converter including a controller configured to: estimate or calculate a slew rate of the output voltage or a slew rate of an error voltage during load transients, the error voltage corresponding to the difference between the output voltage and a target voltage; and modify the regulation of the output voltage based on the estimated slew rate or the calculated slew rate.

[0092] Example 26. An electronic system of Example 25, wherein the controller of the power converter includes: an estimator configured to estimate or calculate a slew rate of the output voltage or a slew rate of an error voltage during a load transient; a detector configured to determine whether the estimated slew rate or the calculated slew rate exceeds a threshold; and a modulator configured to modify the regulation of the output voltage in response to the estimated slew rate or the calculated slew rate exceeding the threshold.

[0093] Example 27. An electronic system of Example 25 or 26, wherein the controller of the power converter is configured to: identify in a signal a transient event corresponding to the slew rate of voltage deviation at the electrical load and / or the output voltage, or identify in a signal a transient event corresponding to the slew rate of voltage deviation and / or error voltage.

[0094] Terms such as "first" and "second" are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the specification, similar terms refer to similar elements.

[0095] As used herein, the terms “having,” “comprising,” “including,” “containing,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude other elements or features. Unless the context clearly indicates otherwise, the articles “a,” “an,” and “the” are intended to include both plural and singular forms.

[0096] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0097] Although specific embodiments have been described and illustrated herein, those skilled in the art will recognize that various alternative implementations and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A method for regulating the output voltage of a power converter during load transients, the method comprising: During the load transient, the conversion rate of the error voltage is estimated or calculated, the error voltage corresponding to the difference between the output voltage and the target voltage, wherein the target voltage varies as a function of the load current provided by the power converter; as well as The output voltage is adjusted based on the estimated or calculated slew rate.

2. The method of claim 1, wherein modifying the adjustment of the output voltage based on the estimated slew rate or the calculated slew rate comprises: The regulation of the output voltage is modified in response to the estimated or calculated slew rate exceeding a threshold.

3. The method of claim 2, wherein the threshold is variable and depends on the error voltage.

4. The method of claim 1, wherein estimating or calculating the conversion rate of the error voltage comprises: The analog measurement results of the output voltage are digitized; The digital measurement result of the output voltage is delayed; as well as The conversion rate is obtained by subtracting or adding the delayed digital measurement result of the output voltage to the digital measurement result of the output voltage.

5. The method of claim 4, wherein modifying the adjustment of the output voltage based on the estimated slew rate or the calculated slew rate comprises: The conversion rate is compared with a threshold. as well as In response to the conversion rate exceeding the threshold, a latch is set, wherein the output of the latch indicates that the latch is set and the regulation of the output voltage is to be modified.

6. The method of claim 5, wherein the comparison is performed periodically, and wherein the periodicity of the comparison corresponds to an amount by which the digital measurement result of the output voltage is delayed.

7. The method of claim 6, wherein the delay is programmable.

8. The method according to claim 5, further comprising: Based on the error voltage and in response to the target voltage returning to a predetermined range, the latch is reset, wherein the output of the latch indicates that the latch has been reset.

9. The method of claim 4, wherein modifying the adjustment of the output voltage based on the estimated slew rate or the calculated slew rate comprises: The conversion rate is compared with a first threshold. In response to the conversion rate being greater than the first threshold, a first latch is set; In response to the output indication of the first latch being set, one or more PWM (pulse width modulation) pulses are blanked or the PWM used in the regulation of the output voltage is tri-stated; The conversion rate is compared with a second threshold. In response to the conversion rate being less than the second threshold, a second latch is set; as well as In response to the output indication of the second latch being set, one or more additional PWM pulses used in the regulation of the output voltage are added together.

10. The method of claim 4, further comprising: For each window in a series of overlapping windows, the analog measurement result of the output voltage is digitized at the beginning of the window, the digitized measurement result of the output voltage is delayed to define the end of the window, and the delayed digitized measurement result of the output voltage is subtracted or added to the digitized measurement result of the output voltage to obtain the conversion rate at the end of the window.

11. The method of claim 10, wherein modifying the adjustment of the output voltage based on the estimated slew rate or the calculated slew rate comprises: For each window in the series of overlapping windows, the conversion rate at the end of the window is compared with a threshold; as well as In response to the conversion rate at the end of any window in the window exceeding the threshold, a latch is set, wherein the output of the latch indicates that the latch is set and the regulation of the output voltage is to be modified.

12. The method according to claim 4, further comprising: If the conversion rate exceeds a threshold, then increase the delay and at least one of the threshold.

13. The method of claim 1, further comprising: Identify transient events in the signal that correspond to the load voltage offset and / or the slew rate of the output voltage; or Identify transient events in the signal that correspond to the switching rate of the voltage offset and / or the error voltage.

14. A controller for a power converter, the controller comprising: An estimator is configured to estimate or calculate the conversion rate of an error voltage during load transients, the error voltage corresponding to the difference between the output voltage of the power converter and a target voltage, wherein the target voltage varies as a function of the load current supplied by the power converter; as well as The modulator is configured to modify the regulation of the output voltage based on the estimated slew rate or the calculated slew rate.

15. The controller of claim 14, further comprising: The detector is configured to determine whether the estimated or calculated conversion rate exceeds a threshold. The modulator is configured to modify the regulation of the output voltage in response to an estimated or calculated slew rate exceeding the threshold.

16. The controller of claim 15, wherein the threshold is variable and depends on the error voltage.

17. The controller of claim 15, wherein the estimator comprises: An analog-to-digital converter is configured to digitize the analog measurement result of the output voltage; A delay unit is configured to delay the digital measurement result of the output voltage; as well as A subtractor or adder is configured to subtract or add the delayed digital measurement result of the output voltage and the digital measurement result of the output voltage, respectively, to obtain the conversion rate.

18. The controller of claim 17, wherein the detector comprises: A comparator is configured to compare the conversion rate with the threshold. as well as A latch is configured to be set in response to the conversion rate exceeding the threshold, wherein the output of the latch indicates that the latch is set and the regulation of the output voltage is to be modified.

19. The controller of claim 18, wherein the latch is further configured to reset based on the error voltage in response to the target voltage returning to a predetermined range, and wherein the output of the latch indicates that the latch has been reset.

20. The controller of claim 15, wherein the detector comprises: A first comparator is configured to compare the conversion rate with a first threshold. A first latch is configured to be set in response to the conversion rate being greater than the first threshold; A second comparator is configured to compare the conversion rate with a second threshold. as well as The second latch is configured to set in response to the conversion rate being less than the second threshold. The modulator is configured to, in response to an output indication that the first latch is set, either blank one or more PWM (pulse width modulation) pulses or tri-state the PWM used in the regulation of the output voltage. The modulator is configured to sum one or more additional PWM pulses used in the regulation of the output voltage in response to an output indication that the second latch is set.

21. The controller of claim 17, wherein for each window in a series of overlapping windows, the estimator is configured to: digitize the analog measurement of the output voltage at the beginning of the window, delay the digitized measurement of the output voltage to define the end of the window, and subtract or add the delayed digitized measurement of the output voltage to the digitized measurement of the output voltage to obtain the conversion rate at the end of the window.

22. The controller of claim 21, wherein for each of the series of overlapping windows, the detector is configured to: compare the transition rate at the end of the window with the threshold, and set a latch in response to the transition rate at the end of any window in the window exceeding the threshold, the output of the latch indicating that the latch is set and the regulation of the output voltage is to be modified.

23. The controller of claim 17, wherein if the conversion rate exceeds a threshold, the estimator is configured to increase the delay and / or the detector is configured to increase the threshold.

24. The controller of claim 14, further comprising control circuitry configured to: identify in a signal a transient event corresponding to the slew rate of the load voltage offset and / or the output voltage, or identify in a signal a transient event corresponding to the slew rate of the voltage offset and / or the error voltage.

25. An electronic system comprising: Electrical load; as well as A power converter configured to regulate the output voltage supplied to the electrical load, the power converter including a controller configured to estimate or calculate the conversion rate of an error voltage during load transients, the error voltage corresponding to the difference between the output voltage and a target voltage; And the regulation of the output voltage based on the estimated or calculated conversion rate, wherein the target voltage varies as a function of the load current provided by the power converter.

26. The electronic system of claim 25, wherein the controller of the power converter comprises: An estimator is configured to estimate or calculate the slew rate of the output voltage or the slew rate of the error voltage during the load transient. The detector is configured to determine whether the estimated or calculated conversion rate exceeds a threshold. And a modulator, configured to modify the regulation of the output voltage in response to an estimated or calculated slew rate exceeding the threshold.

27. The electronic system of claim 25, wherein the controller of the power converter is configured to: identify in a signal a transient event corresponding to the voltage offset at the electrical load and / or the conversion rate of the output voltage, or identify in a signal a transient event corresponding to the voltage offset and / or the conversion rate of the error voltage.

Images