Transparent display panel and transparent display device including the same

Abstract

A transparent display panel and a transparent display device including the same. The transparent display panel has an auxiliary electrode region including a partition wall, the width of the top surface of the partition wall being greater than the width of the bottom surface thereof. The auxiliary electrode region is arranged on a line region within a display region. The second electrode of the organic light emitting element and the VSS voltage connection line are electrically connected to each other via the auxiliary electrode, so that the resistance of the second electrode as a transparent electrode is reduced. In addition, the auxiliary electrode region is formed on each of a plurality of line regions including VSS voltage connection lines extending across the display region, respectively. Therefore, current is fed to each pixel in the display region in a smooth manner, so that the brightness distribution over the entire panel is uniform.

Description

Technical Field

[0001] The present disclosure relates to a transparent display panel in which occurrence of brightness non-uniformity is minimized and a transparent display device including the same. Background Art

[0002] Display devices that display various information using images include liquid crystal display devices (LCDs) and organic light emitting diode-based display devices (OLEDs).

[0003] With the advancement of image realization technology, in recent years, the demand for transparent display devices has increased, in which at least a partial area on which information is displayed is transparent to transmit light, thereby making objects or background behind the display device visible to users in front of the device.

[0004] The transparent display device transmits light in the front-to-back direction. Therefore, the device can display information in the front-to-back direction of the display device, so that the front user and the rear user in front of and behind the display device can respectively see the object or background opposite thereto.

[0005] For example, a transparent display device implemented as an organic light emitting display device may include a transparent region that transmits incident light as it is and a light emitting region that emits light. Summary of the invention

[0006] In a transparent display device, a transparent electrode having a high sheet resistance is used to improve transparency. In addition, when the thickness of the transparent electrode is small in order to improve the transmittance, the resistance of the transparent electrode is further increased.

[0007] When a transparent electrode having a high surface resistance is used, the difference between the rising values ​​of the low-level voltage (VSS) at the positions of the display panel becomes larger. Therefore, the uneven brightness phenomenon occurs in the display panel. This may lead to the degradation of display quality, especially in a transparent display device having a large-area display panel.

[0008] Therefore, the inventors of the present application invented a transparent display panel which minimizes the occurrence of brightness unevenness in a display panel by introducing an auxiliary electrode region capable of reducing the resistance of a transparent electrode, and a transparent display device including the same.

[0009] An object of the present disclosure is to provide a transparent display panel including an auxiliary electrode region capable of reducing the resistance of a transparent electrode, and a transparent display device including the same.

[0010] Furthermore, an object of the present disclosure is to provide a transparent display panel including a partition wall structure that can maximize an electrode contact area to further reduce resistance of a transparent electrode while helping to improve transmittance, and a transparent display device including the same.

[0011] Furthermore, an object of the present disclosure is to provide a transparent display panel in which brightness is distributed in a uniform manner via electrical connection between a transparent electrode arranged in a display area and a line area, and a transparent display device including the same.

[0012] Furthermore, an object according to the present disclosure is to provide a transparent display panel in which a partition wall is used as a spacer, thereby removing a process of forming a separate spacer, and a transparent display device including the same.

[0013] The purpose of the present disclosure is not limited to the above purpose. Other purposes and advantages of the present disclosure not mentioned above can be understood from the following description, and other purposes and advantages of the present disclosure not mentioned above can be more clearly understood from the embodiments of the present disclosure. In addition, it will be easily understood that the purposes and advantages of the present disclosure can be achieved by the features disclosed in the claims and their combinations.

[0014] According to an embodiment of the present disclosure, a transparent display panel includes a display area and a non-display area, wherein the display area includes: a plurality of light-emitting areas; a plurality of transmission areas; a plurality of line areas separated from each other, each line area extending in one direction; and a plurality of auxiliary electrode areas arranged above the corresponding line areas.

[0015] In this case, the light-emitting area includes an organic light-emitting element including a first electrode, an organic light-emitting layer and a second electrode, wherein at least one of the line areas includes a VSS voltage connection line, wherein the auxiliary electrode area is disposed above the line area including the VSS voltage connection line.

[0016] Specifically, the auxiliary electrode region includes: an auxiliary electrode, which is electrically connected to a VSS voltage connection line; a partition wall, which is arranged on the auxiliary electrode, wherein the width of the top surface of the partition wall is greater than the width of the bottom surface thereof; and an electrode contact, which is composed of a portion of the auxiliary electrode and a portion of the second electrode that are in contact with and electrically connected to each other, wherein the electrode contact is arranged inwardly than the end of the partition wall.

[0017] The light-emitting area includes a first color light-emitting area, a second color light-emitting area and a third color light-emitting area, wherein each of the second color light-emitting area and the third color light-emitting area is arranged above a corresponding line area, wherein the first color light-emitting area is arranged between the second color light-emitting area and the third color light-emitting area respectively arranged above different line areas, and wherein the auxiliary electrode area is arranged between the second color light-emitting area and the third color light-emitting area arranged on the same line area.

[0018] In addition, the second electrode may include IZO which is a material having a high diffraction property.

[0019] In addition, the partition wall may include a first partition wall structure and a second partition wall structure stacked on the first partition wall structure. The first partition wall structure contacts the auxiliary electrode, but the second partition wall structure may be spaced apart from the auxiliary electrode.

[0020] According to the present disclosure, introducing an auxiliary electrode region including a partition wall whose top surface width is greater than the bottom surface width on a line region within a display area can allow the second electrode of the organic light-emitting element and the VSS voltage connection line to be electrically connected to each other via the auxiliary electrode, thereby reducing the resistance of the second electrode as a transparent electrode.

[0021] In addition, according to the present disclosure, a partition wall structure including a first partition wall structure as a portion of a bank layer and a second partition wall structure stacked on the first partition wall structure and spaced apart from the auxiliary electrode can allow an increase in the area of ​​electrode contact. Therefore, the resistance of the second electrode as a transparent electrode can be further reduced. The size of the partition wall can be reduced, thereby improving the transmittance.

[0022] Furthermore, according to the present disclosure, forming an auxiliary electrode region on each of a plurality of line regions respectively including VSS voltage connection lines extending across a display region may allow current to be supplied to each pixel in the display region in a smooth manner, so that brightness in the panel may become more uniform.

[0023] In addition, according to the present disclosure, the partition wall of the auxiliary electrode region can be used as a spacer. Therefore, a process of forming a separate spacer and a separate region for forming the spacer are not required, thereby achieving high processing efficiency and panel space utilization.

[0024] Other specific effects of the present disclosure as well as the effects described above will be described in conjunction with descriptions of specific details for carrying out the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a block diagram schematically illustrating a system of a transparent display device.

[0026] Figure 2is a plan view for schematically illustrating the connection and arrangement relationship of components constituting the transparent display device.

[0027] Figure 3 is a schematic cross-sectional view of a light emitting region and a transmissive region of a pixel in an organic light emitting display panel.

[0028] Figure 4 is a more detailed cross-sectional view of a light emitting region of a pixel in an organic light emitting display panel.

[0029] Figure 5 The connection relationship of the wire connection pads provided on the first substrate in the transparent display panel according to the embodiment of the present disclosure is shown.

[0030] Figures 6 to 10 The present invention is based on the interlayer stacking structure to illustrate the transparent display panel according to the embodiment of the present invention. Figure 5 A plane diagram of the connection relationship between the lines.

[0031] Fig.11 yes Figure 8 An enlarged plan view of the A-A' region in FIG.

[0032] Fig.12 yes Fig.11 Enlarged plan view of the B-B' area.

[0033] Fig.13 yes Fig.11 Enlarged plan view of the C-C' region.

[0034] Fig.14 yes Fig. 9 Enlarged plan view of the D-D' region.

[0035] Fig.15 yes Fig.10 Enlarged plan view of the E-E' region.

[0036] Fig.16 yes Fig.10 Enlarged cross-sectional view of the F-F' region.

[0037] Fig.17 yes Fig.10 Enlarged plan view of the G-G' region.

[0038] Fig.18 yes Fig.17 Enlarged cross-sectional view of the H-H' region.

[0039] Fig.19 This is an embodiment of a transparent display device used as a head-up display.

[0040] Fig. 20(a) shows the long-range diffraction pattern through a single slit, and Fig. 20 (b) is an illustration of the diffraction effect in a single slit.

[0041] Fig.21 (a) to Fig.21 (d) shows the results of double-slit tests for particles, waves, light and electrons respectively.

[0042] Fig. 22 A typical arrangement of quadrilateral transmission areas in a transparent display device is shown.

[0043] Fig.23 It shows that when light is incident on a Fig. 22 The diffraction phenomenon of light occurs when the transmissive area shape is on the central area of ​​the transparent display device.

[0044] Figure 24 to Figure 26 An embodiment of the present disclosure is shown in which a transmissive area in a transparent display device has a curved shape.

[0045] Fig. 27 It shows that when light is incident on a Fig.26 The diffraction phenomenon of light occurs when the circular transmission area shape is on the central area of ​​the transparent display device.

[0046] Fig.28 and Fig.29 An embodiment of the present disclosure is shown in which a transmissive region in a transparent display device has a polygonal shape in which all internal angles are obtuse angles.

[0047] Fig.30 A configuration in which a transmission area and a light emitting area of ​​a transparent display device according to an embodiment of the present disclosure are arranged is shown.

[0048] Fig.31 (a) to Fig.31 (c) shows the haze value measurement based on the shape of the transmission area.

[0049] Fig.32 Haze value measurements based on the shape of the transmission area and based on different ppi are shown.

[0050] Fig.33 A configuration in which a transmission area and a light emitting area of ​​a transparent display device according to another embodiment of the present disclosure are arranged is shown.

[0051] Fig.34 and Fig.35 They are shown respectively Fig.30 Cross-sections of the I-I' and J-J' regions.

[0052] Fig.36and Fig.37 An outermost virtual pixel pattern region surrounding the display area is shown.

[0053] Fig.38 The arrangement relationship between the line area and the pixel circuit area in the display area according to the embodiment of the present disclosure is specifically shown.

[0054] Fig.39 The circuitry of the pixel circuit area connected to the line area of ​​the K-K' area is shown.

[0055] Fig.40 The circuitry of one pixel circuit area is shown.

[0056] Figure 41 to Figure 43 They are shown respectively Fig.38 Cross-sectional view of the L-L' region, M-M' region and N-N' region in FIG.

[0057] Fig.44 A specific arrangement relationship between the line region and the auxiliary electrode region in the display region according to an embodiment of the present disclosure is shown.

[0058] Fig.45 yes Fig.44 Cross-sectional view of the Q-Q' region and R-R' region in FIG.

[0059] Fig.46A and Fig.46B In the first embodiment and the second embodiment respectively Fig.45 Enlarged cross-sectional view of the S-S' region.

[0060] Fig.47A A region of electrode contact that can be formed when forming a partition wall having a single layer of an inverse tapered shape is shown.

[0061] Fig.47B The region of electrode contact that can be formed when the partition wall includes a stack of a first partition wall structure and a second partition wall structure having an inverse tapered shape is shown.

[0062] Fig.48A and Fig.48B The ΔVSS values ​​in the case where the partition wall exists and in the case where the partition wall does not exist are respectively shown.

[0063] Fig.49A The changes in the area and resistance of the electrode contact according to the width of the partition wall are shown.

[0064] Fig.49B The changes in the area and resistance of the electrode contact depending on the size of the opening region of the bank layer are shown. DETAILED DESCRIPTION

[0065] For the sake of simplicity and clarity of explanation, the elements in the figures need not be drawn to scale. The same reference numerals in different figures represent the same or similar elements, and therefore perform similar functions. In addition, in order to simplify the description, the description and details of the known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other examples, known methods, steps, components and circuits are not described in detail to avoid unnecessary ambiguity of various aspects of the present disclosure.

[0066] Examples of various embodiments are further illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0067] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular "one" and "an" are also intended to include plural forms. It will be further understood that, when used in this specification, the terms "include", "included in", "comprising" and "contained in" specify the existence of the described features, integers, operations, elements and / or components, but do not exclude the existence or increase of one or more other features, integers, operations, elements, components and / or a part thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When before the list of elements, expressions such as "at least one" can modify the entire list of elements, and the individual elements of the list may not be modified.

[0068] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or section described below may be referred to as a second element, component, region, layer or section.

[0069] In addition, it will also be understood that when a first element or layer is referred to as being “on” or “under” a second element or layer, the first element can be directly disposed on or under the second element, or can be indirectly disposed on or under the second element with a third element or layer disposed between the first element or layer and the second element or layer.

[0070] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0071] In addition, as used herein, when a layer, film, region, or plate, etc. is disposed "on" or "on top" of another layer, film, region, or plate, etc., the former may directly contact the latter, or another layer, film, region, or plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, or plate, etc. is disposed directly "on" or "on top" of another layer, film, region, or plate, etc., the former directly contacts the latter, and no further layer, film, region, or plate, etc. is disposed between the former and the latter. In addition, as used herein, when a layer, film, region, or plate, etc. is disposed "under" or "below" another layer, film, region, or plate, etc., the former may directly contact the latter, or another layer, film, region, or plate, etc. may also be disposed between the former and the latter. As used herein, when a layer, film, region, or plate, etc. is disposed directly "under" or "below" another layer, film, region, or plate, etc., the former directly contacts the latter, and no further layer, film, region, or plate, etc. is disposed between the former and the latter.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and unless expressly defined as such herein, should not be interpreted in an idealized or overly formal sense.

[0073] Hereinafter, a transparent display panel and a transparent display device including the same according to some embodiments of the present disclosure will be exemplified.

[0074] Figure 1 is a block diagram for schematically illustrating a transparent display device according to an embodiment of the present disclosure. Figure 2 is a plan view for schematically illustrating the connection and arrangement relationship of components constituting the transparent display device.

[0075] However, Figure 1 and Figure 2 Each of them is one embodiment according to the present disclosure. Therefore, the connection and arrangement relationship of the components of the transparent display device 100 according to the present disclosure is not limited thereto.

[0076] The transparent display device 100 may include a transparent display panel 110 , a timing controller 140 , a data driver 120 , and a gate driver 130 .

[0077] The transparent display panel 300 may include a display area DA including at least one pixel P to display an image, and a non-display area NDA in which no image is displayed.

[0078] The non-display area NDA may be provided to surround the display area DA.

[0079] In the non-display area NDA, the gate driver 130, the data driving IC pad 310, and various lines may be disposed. The non-display area NDA may correspond to a bezel.

[0080] The transparent area of ​​the transparent display panel 300 may be included in both the display area DA and the non-display area NDA.

[0081] The transparent display panel 300 may include a plurality of pixel regions defined by a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction orthogonal to the gate lines GL.

[0082] The pixel regions may be arranged in a matrix form. Each pixel region may include a pixel P composed of at least one sub-pixel SP.

[0083] The gate driver 130 is directly stacked on the transparent display panel 110 in the form of a GIP (Gate In Panel).

[0084] A plurality of GIP circuit areas may be arranged in a GIP form and may be disposed in left and right portions of the non-display area NDA respectively adjacent to left and right peripheral portions of the display area DA, with the display area DA interposed therebetween.

[0085] The data driver 120 may include at least one source driver integrated circuit 121 (source driver IC) to drive the plurality of data lines DL.

[0086] For example, a source driver chip corresponding to each source driver integrated circuit 121 may be mounted on the flexible film 123. One end of the flexible film 123 may be bonded to at least one control printed circuit board 150, and the other end thereof may be bonded to a data driver IC pad (DPA) of the transparent display panel 110.

[0087] The timing controller 140 may be disposed on the control printed circuit board 150. In addition, a power controller may also be disposed on the control printed circuit board 150.

[0088] In addition, the source printed circuit board may be disposed between the flexible film 123 and the control printed circuit board 150 while being connected thereto via a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

[0089] In one example, the transparent display device 100 may be implemented as a liquid crystal display device, an organic light emitting display device, etc. However, the present disclosure is not limited thereto. Figure 3 and Figure 4 An example in which the transparent display device 100 may be implemented as an organic light emitting display device is described.

[0090] The transparent display panel may include a first substrate 200 and a second substrate 270 .

[0091] The first substrate 200 may serve as a base substrate including a display area DA and a non-display area NDA in which pixels are disposed.

[0092] The second substrate 270 may be opposite to the first substrate 200 and may be used as a package substrate.

[0093] Each of the first substrate 200 and the second substrate 270 may be implemented as a plastic substrate or a glass substrate.

[0094] The display area DA of the first substrate 200 includes a light emitting area EA and a transmissive area TA.

[0095] A plurality of sub-pixels may be arranged in the emission area EA.

[0096] Each subpixel may be a red subpixel emitting red light, or may be a green subpixel emitting green light, or may be a blue subpixel emitting blue light, or may be a subpixel emitting light (eg, white light other than red, green, or blue light).

[0097] Each sub-pixel may include a light emitting area EA for emitting light of a corresponding color, and a circuit area electrically connected to the light emitting area EA to control light emission from the light emitting area EA.

[0098] The emission area EA of the subpixel may refer to a region in which light of a color corresponding to each subpixel is emitted, or may refer to a pixel electrode such as an anode electrode present in each subpixel, or may refer to a region where a pixel electrode is disposed.

[0099] The emission area EA includes an organic light emitting element 220 including an anode electrode as a first electrode 221, an organic light emitting layer 223, and a cathode electrode as a second electrode 225. The organic light emitting element 220 emits light at a predetermined brightness using a voltage supplied to the first electrode 221 and a voltage supplied to the second electrode 225.

[0100] In this case, the second electrode 225 as a transparent electrode may extend across both the emission area EA and the transmission area TA.

[0101] The circuit region of the sub-pixel refers to a circuit region including the driving thin film transistor 210 that supplies voltage or current to the pixel electrode of each sub-pixel to control light emission from the light emitting area EA, or refers to a region where the circuit region is provided.

[0102] The driving thin film transistor 210 includes a gate electrode 214 , a source electrode 217 a , a drain electrode 217 b , and an active layer 212 .

[0103] When the circuit area receives a gate signal from the gate line GL using the thin film transistor, the circuit area may provide a predetermined voltage to the first electrode 221 of the organic light emitting element 220 of the emission area EA based on the data voltage of the data line DL.

[0104] The circuit area may at least partially overlap the light emitting area EA in a vertical direction, but may also be disposed on a side opposite to a side where light is emitted so as not to interfere with light emission.

[0105] The encapsulation layer 250 is formed on the organic light emitting element 220, specifically, on the second electrode 225 of the organic light emitting element 220. A color filter 260 corresponding to the organic light emitting element 220 may be formed on the encapsulation layer 250.

[0106] The color filter 260 may have a color that is the same as or different from a color of a corresponding sub-pixel.

[0107] The transmission area TA refers to an area through which incident light is transmitted, and may be an area other than a circuit area. The transmittance of the transparent display device depends on the area of ​​the transmission area TA.

[0108] Figure 3 An embodiment of the present disclosure is shown in which the emission area EA and the transmission area TA correspond to one sub-pixel. However, the present disclosure is not limited thereto. The arrangement form of the emission area EA and the transmission area TA of the transparent display device according to the present disclosure is not limited thereto. Figure 4 is a more detailed cross-sectional view of the light emitting area EA corresponding to one sub-pixel in the organic light emitting display device according to an embodiment of the present disclosure.

[0109] A driving thin film transistor 210 and an organic light emitting element 220 are disposed above the first substrate 200 .

[0110] More specifically, if Figure 4 As shown, a buffer layer 201 is formed on the first substrate 200 , a gate insulating layer 213 is formed on the buffer layer 201 to cover the active layer 212 of the driving thin film transistor 210 , and an interlayer insulating layer 216 is formed on the gate insulating layer 213 to cover the gate electrode 214 of the driving thin film transistor 210 .

[0111] A passivation layer 218 may be formed on the driving thin film transistor 210 to cover the driving thin film transistor 210. A contact hole exposing the drain electrode 217b may be formed in the passivation layer 218.

[0112] The passivation layer 218 may serve as a planarization layer made of an organic insulating material.

[0113] A first electrode 221 constituting the organic light emitting element 220 is formed on the passivation layer 218. The first electrode 221 is electrically connected to the drain electrode 217b via a contact hole defined in the passivation layer 218. Thus, the driving thin film transistor 210 and the first electrode 221 may be electrically connected to each other.

[0114] The first electrode 221 may be used as an anode electrode for injecting holes. In this case, the first electrode may be implemented as a transparent electrode made of at least one transparent conductive material such as indium tin oxide (ITO), antimony tin oxide (ATO), and indium zinc oxide (IZO).

[0115] Bank layer 231 is formed on and over passivation layer 218. Sub-pixels may be separated from each other via bank layer 231 to form boundaries between adjacent emission areas EA to respectively present corresponding colors. Bank layer 231 may define bank holes therein corresponding to the sub-pixel areas to partially expose first electrode 221.

[0116] The organic light emitting layer 223 may be formed on the top surface of the bank layer 231 and a portion of the first electrode 221 exposed through the bank hole. A region where the organic light emitting layer 223 contacts the first electrode 221 may correspond to a sub-pixel region, more specifically, the emission area EA.

[0117] The organic light emitting layer 223 may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0118] The light emitting layer (EML) may emit red R, green G, or blue B light, and may be made of a phosphorescent material or a fluorescent material emitting the corresponding color.

[0119] In this case, each of the hole injection layer (HIL), the hole transport layer (HTL), the electron transport layer (ETL), and the electron injection layer (EIL) may occupy the entire display area. The light emitting layer EML may be patterned to correspond to each color region, specifically, to the first electrode 221. In addition, each of the hole injection layer (HIL), the hole transport layer (HTL), the electron transport layer (ETL), and the electron injection layer (EIL) may be patterned to correspond to each color region, specifically, to the first electrode 221.

[0120] The second electrode 225 is formed on the organic light emitting layer 223 and over the entire first substrate 200. The second electrode 225 is disposed over the entire display area DA of the first substrate 200. In this case, the second electrode 225 may be disposed over the entire display area DA except the transmission area TA.

[0121] The second electrode 225 may be used as a cathode electrode for injecting electrons. In this case, the second electrode 225 may include at least one of materials such as Ca, Al:Li, Ma:Ag, and Ag. In addition, the second electrode 225 may be implemented as a transparent electrode made of at least one of transparent conductive materials such as indium tin oxide (ITO), antimony tin oxide (ATO), and indium zinc oxide (IZO).

[0122] On the organic light emitting element 220 , an encapsulation layer 250 is formed to prevent external moisture from penetrating into the organic light emitting element 220 .

[0123] On the encapsulation layer 250 , a second substrate 270 as an encapsulation substrate opposite to the first substrate 200 may be formed.

[0124] In this case, a barrier layer may be formed between the encapsulation layer 250 and the second substrate 270 to more effectively prevent external moisture or oxygen from penetrating into the organic light emitting element 220 .

[0125] Figure 5 1 and 2 show the connection relationship of the wire connection pads disposed on the first substrate 301 in the transparent display panel 300 according to the embodiment of the present disclosure.

[0126] The first substrate 301 includes a display area DA and a non-display area NDA disposed to surround the display area DA. The non-display area NDA may surround the top, bottom, left, and right sides of the display area DA. The vertical direction or up-down direction of the display area DA refers to the Y-axis direction, and the horizontal direction or left-right direction of the display area DA refers to the X-axis direction.

[0127] The display area DA may have a rectangular shape including long sides and short sides.

[0128] In this case, the long side is relatively longer than the short side.

[0129] In addition, the long side refers to a side parallel to the X-axis direction which is the left-right direction of the display area DA.

[0130] The short side refers to a side parallel to the Y-axis direction which is the vertical direction or the up-down direction of the display area DA.

[0131] The gate driver 130 may be provided in the form of a GIP (Gate In Panel) and disposed on at least one side of the display area DA.

[0132] That is, a pair of GIP circuit areas 360 are provided in portions of the non-display area NDA located at the left and right sides of the display area DA, respectively.

[0133] For example, the GIP circuit area 360 is disposed along a short side of the display area DA. The first VSS voltage line 321 and the second VSS voltage line 322 may be disposed along a long side of the display area DA.

[0134] On a portion of the non-display area NDA where the GIP circuit area 360 is disposed, a GIP ESD (electrostatic discharge) protection circuit area 365 operating to minimize the inflow of static electricity when static electricity is introduced into the GIP circuit area 360 may be disposed.

[0135] At least one data driving IC pad 310 may be disposed at one side of the display area DA where the GIP circuit area 360 is not disposed, for example, at a portion of the non-display area NDA on a top long side of the display area DA.

[0136] The data driving IC pad 310 is connected to various lines required for driving the transparent display panel 300 , such as a power line and a data line.

[0137] Between the data driving IC pad 310 and the display area DA, a data line connection pad 311 , a reference voltage line connection pad 340 , a VSS voltage line connection pad 320 , and a VDD voltage line connection pad 330 are provided to be connected to each other via the data driving IC pad 310 and various lines.

[0138] Specifically, each of the left and right reference voltage line connection pads 340, each of the left and right VDD voltage line connection pads 330, and each of the left and right VSS voltage line connection pads 320 may be disposed adjacent to each of the left and right portions of the data driver IC pad 310. The interval between each of the left and right reference voltage line connection pads 340 and the center in the length direction of the data driver IC pad 310 is smaller than the interval between each of the left and right VDD voltage line connection pads 330 and the center in the length direction of the data driver IC pad 310. The interval between each of the left and right VDD voltage line connection pads 330 and the center in the length direction of the data driver IC pad 310 is smaller than the interval between each of the left and right VSS voltage line connection pads 320 and the center in the length direction of the data driver IC pad 310.

[0139] That is, the two reference voltage line connection pads 340 , the two VDD voltage line connection pads 330 , and the two VSS voltage line connection pads 320 may be arranged symmetrically to each other about the center of the data line connection pad 311 .

[0140] The reference voltage line connection pad 340 , the VDD voltage line connection pad 330 , and the VSS voltage line connection pad 320 are arranged to be spaced apart from each other.

[0141] The VDD voltage line connection pad 330 can be used as a high level voltage power line connection pad for providing high level voltage power to the pixel to drive the pixel, and the VSS voltage line connection pad 320 can be used as a low level voltage power line connection pad for applying low level voltage power to the pixel to drive the pixel.

[0142] The reference voltage line connection pad 340 may provide a reference voltage Vref to the pixel.

[0143] A reference voltage line 341 electrically connected to the reference voltage line connecting pad 340, a first VDD voltage line 331 electrically connected to the VDD voltage line connecting pad 330, and a first VSS voltage line 321 electrically connected to the VSS voltage line connecting pad 320 may be respectively arranged between the reference voltage line connecting pad 340 and the display area DA, between the VDD voltage line connecting pad 330 and the display area DA, and between the VSS voltage line connecting pad 320 and the display area DA.

[0144] In one embodiment of the present disclosure, the VDD voltage line connection pad 330 and the first VDD voltage line 331 are formed integrally with each other, the reference voltage line connection pad 340 and the reference voltage line 341 are formed to be spaced apart from each other and electrically connected to each other via a separate connection electrode, and the VSS voltage line connection pad 320 and the first VSS voltage line 321 are formed to be spaced apart from each other and electrically connected to each other via a separate connection electrode. However, the present disclosure is not limited thereto.

[0145] The first VDD voltage line 331 may be formed to have a bar shape and may extend parallel to one side of the display area DA (specifically, along a long side of the display area DA), and may be integrally formed with the VDD voltage line connection pad 330 .

[0146] In addition, the first VDD voltage line 331 may be integrally formed with the plurality of VDD voltage line connection pads 330 corresponding to each data drive IC pad 310 to electrically connect the plurality of VDD voltage line connection pads 330 to one another.

[0147] The reference voltage line 341 may be disposed between the first VDD voltage line 331 and the display area DA. In one embodiment of the present disclosure, an example in which the reference voltage line can be used as an initial voltage line will be described. However, the present disclosure is not limited thereto. Depending on the compensation circuit area, the reference voltage line 341 may be used as a line separated from the initial voltage line.

[0148] Therefore, the reference voltage line connection pad 340 may be disposed to be spaced apart from the reference voltage line 341 in the Y direction, while an interval between the former and the display area DA is greater than an interval between the latter and the display area DA.

[0149] The reference voltage line 341 may be formed to have a bar shape, and may extend parallel to the first VDD voltage line 331 .

[0150] In order to apply a reference voltage to the reference voltage line 341 , the reference voltage line connection pad 340 and the reference voltage line 341 may be electrically connected to each other via a second connection electrode 352 as a separate connection electrode.

[0151] The first VSS voltage line 321 may be disposed between the reference voltage line 341 and the display area DA.

[0152] Therefore, the VSS voltage line connection pad 320 may be disposed to be spaced apart from the first VSS voltage line 321 in the Y direction, while an interval between the former and the display area DA is greater than an interval between the latter and the display area DA.

[0153] The first VSS voltage line 321 may be formed to have a bar shape, and may extend in parallel with the first VDD voltage line 331 and the reference voltage line 341 .

[0154] In order to apply a VSS voltage to the first VSS voltage line 321 , the VSS voltage line connection pad 320 and the first VSS voltage line 321 may be electrically connected to each other via a first connection electrode 351 as a separate connection electrode.

[0155] Furthermore, a VSS voltage auxiliary line connection pad 326 , which is a portion separated from the VSS voltage line connection pad 320 , may be disposed between the left and right reference voltage line connection pads 340 .

[0156] Specifically, the VSS voltage auxiliary line connection pad 326 may have the form of an island spaced apart from and disposed between the left and right reference voltage line connection pads 340 and spaced apart from and disposed between the data line connection pad 311 and the VDD voltage line.

[0157] The VSS voltage auxiliary line connection pad 326 may be electrically connected to the first VSS voltage line 321 via the first connection electrode 351 .

[0158] In this way, when the VSS voltage auxiliary line connection pad 326 is electrically connected to the first VSS voltage line 321 via the first connection electrode 351, the entire contact area of ​​the first VSS voltage line 321 is increased, thereby reducing the total resistance of the first VSS voltage line 321 while keeping the resistance distribution of the first VSS voltage line 321 uniform.

[0159] The ESD protection circuit area 371 may be disposed between the reference voltage line 341 and the display area DA. The multiplexer (MUX) circuit area 373 may be disposed between the first VSS voltage line 321 and the display area DA. However, the present disclosure is not limited thereto. The positions of the area 371 and the area 373 may vary based on the design scheme of the transparent display panel 300.

[0160] The ESD protection circuit region 371 may include a plurality of thin film transistors constituting an ESD protection circuit. When static electricity is generated from the transparent display panel 300, the ESD protection circuit region operates to take the static electricity to the outside.

[0161] The MUX circuit region 373 may be configured to include a plurality of thin film transistors constituting a MUX circuit.

[0162] When the MUX circuit area 373 is used, one channel of the driver IC output can provide signals to two or more data lines 313. This has the advantage of reducing the number of driver ICs used.

[0163] Each of the ESD protection circuit region 371 and the MUX circuit region 373 may be formed in a stripe shape extending parallel to the reference voltage line 341 , etc. However, the present disclosure is not limited thereto.

[0164] The first VDD voltage line 331 and the first VSS voltage line 321 may be disposed at an upper portion of the non-display area NDA adjacent to an upper side of the display area DA, and the second VDD voltage line 332 and the second VSS voltage line 322 may be disposed at a lower portion of the non-display area NDA adjacent to a lower side of the display area DA.

[0165] The second VDD voltage line 332 and the second VSS voltage line 322 may be spaced apart from each other, with an interval between the former and the display area DA being smaller than an interval between the latter and the display area DA.

[0166] The second VDD voltage line 332 may be formed to have a bar shape, and may extend in parallel along one side of the display area DA (specifically, along a long side of the display area DA).

[0167] In order to apply the VDD voltage to the second VDD voltage line 332 , the first VDD voltage line 331 and the second VDD voltage line 332 may be electrically connected to each other via a separate connection electrode as a VDD voltage connection line 333 .

[0168] Therefore, using the connection structure as described above, the VDD voltage provided via the VDD voltage line connection pad 330 may be applied to the second VDD voltage line 332 via the first VDD voltage line 331 and the VDD voltage connection line 333 .

[0169] In this case, at least one VDD voltage connection line 333 is disposed in the display area DA to extend across the display area DA, thereby electrically connecting the first VDD voltage line 331 and the second VDD voltage line 332 to each other.

[0170] In one example, the second VSS voltage line 322 may be formed to have a bar shape, and may extend in parallel along one side of the display area DA (specifically, along a long side of the display area DA).

[0171] The width of the second VSS voltage line 322 may be smaller than the width of the first VSS voltage line 321 , such that the second VSS voltage line 322 is thinner than the first VSS voltage line 321 .

[0172] In order to apply the VSS voltage to the second VSS voltage line 322 , the first VSS voltage line 321 and the second VSS voltage line 322 may be electrically connected to each other via a separate connection electrode as a VSS voltage connection line 323 .

[0173] Therefore, using the connection structure as described above, the VSS voltage supplied through the VSS voltage line connection pad 320 may be applied to the second VSS voltage line 322 through the first VSS voltage line 321 and the VSS voltage connection line 323 .

[0174] In this case, at least one VSS voltage connection line 323 may be provided in the display area DA to extend across the display area DA, thus electrically connecting the first VSS voltage line 321 and the second VSS voltage line 322 to each other.

[0175] As in one embodiment of the present disclosure, the first VSS voltage line 321 and the second VSS voltage line 322 disposed above and below the display area DA may be electrically connected to each other via at least one VSS voltage connection line 323 extending across the display area DA. Therefore, the following effects may be achieved.

[0176] First, the opaque VSS voltage lines at the left and right portions of the non-display area located at the left and right sides of the display area DA may be omitted. Therefore, the transparent area of ​​the frame may be enlarged so that the transparent area in the frame may be maximized.

[0177] In addition, the opaque VSS voltage lines on the left and right portions of the non-display area on the left and right sides of the display area DA can be omitted. Therefore, there is no need to place the VSS voltage lines on the VSS voltage line connection area required on the frame portions on the left and right sides of the display area DA. Therefore, the frame can be thinner.

[0178] For example, when the VSS voltage connection line 323 is provided in each of the left and right portions of the non-display area NDA to the left and right of the display area DA, the VSS voltage line is provided to surround the display area DA and extend along the periphery of the display area DA. In this case, since an opaque VSS voltage line is formed in the non-display area NDA outside the periphery of the display area DA, the size of the transparent area of ​​the frame is reduced, thereby not allowing reduction of the frame area.

[0179] However, in the VSS voltage line arrangement structure according to the embodiment of the present disclosure, the VSS voltage line is not arranged on the top, bottom, left and right sides of the display area DA, that is, not arranged on the four sides of the frame. Instead, it is sufficient to arrange the VSS voltage line only on the top and bottom sides of the frame above and below the display area DA.

[0180] Therefore, according to the embodiment of the present disclosure, the maximum value of the transparent area of ​​the frame where the opaque VSS voltage line is not set can be ensured. If necessary, the size of the frame can be reduced so that the frame can be thinner.

[0181] In addition, when the VSS voltage line surrounds the periphery of the display area DA, the VSS voltage flows around the periphery of the display area DA and flows into the display area DA, and is then provided to the pixels in the display area DA. Therefore, the VSS voltage line used as a current path must be thick in order to be used as a current path in a reliable manner in terms of resistance.

[0182] However, in one embodiment of the present disclosure, when the VSS voltage connection line 323 passes through the display area DA, the VSS voltage connection line may directly provide the VSS voltage to the pixel. Therefore, the second VSS voltage line 322 may not be used as a current path.

[0183] In this way, when the second VSS voltage line 322 is not used as a current path, the second VSS voltage line 322 does not need to be formed thick in consideration of resistance and is thus as thin as possible.

[0184] Therefore, according to an embodiment of the present disclosure, the second VSS voltage line 322 may have a width smaller than that of the first VSS voltage line 321. Therefore, as the width of the second VSS voltage line 322 decreases, the size of the transparent area in the lower frame portion under the display area DA may be increased. If necessary, the frame may be made thinner.

[0185] The light emitting tester 375 may be disposed in the non-display area NDA and spaced apart from the second VSS voltage line 322 , while an interval between the former and the display area DA is greater than an interval between the latter and the display area DA.

[0186] The light emitting tester 375 may be formed in a bar shape extending in parallel to the second VSS voltage line 322 , and may also extend along both left and right sides of the display area DA, thereby surrounding three sides of the display area DA.

[0187] The light emitting tester 375 may provide a light emitting test signal to the plurality of data lines 313 before a module process after manufacturing the transparent display panel 300 , and may inspect defects of the transparent display panel 300 .

[0188] The light emission tester 375 includes a plurality of inspection switching elements respectively connected to the plurality of data lines 313 .

[0189] Therefore, a plurality of data lines 313 branched from the data line connection pads 311 extend across the display area DA and are then electrically connected to the light emitting tester 375 .

[0190] The light emitting test signal applier 376 may be formed on a partial area of ​​each of the reference voltage line connection pad 340 , the VDD voltage line connection pad 330 , and the VSS voltage line connection pad 320 to provide a light emitting test signal to the light emitting tester 375 .

[0191] Figures 6 to 10 The transparent display panel 300 according to the embodiment of the present disclosure is shown based on the interlayer stacking structure. Figure 5 A plane diagram of the connection relationship between the lines.

[0192] like Figure 6 As shown, the reference voltage line connection pad 340, the VDD voltage line connection pad 330, the VSS voltage line connection pad 320, the VSS voltage auxiliary line connection pad 326, the reference voltage line 341, the first VDD voltage line 331, the second VDD voltage line 332, the first VSS voltage line 321, and the second VSS voltage line 322 of the transparent display panel 300 according to the embodiment of the present disclosure may constitute the same layer and may be spaced apart from each other. The reference voltage line connection pad 340, the VDD voltage line connection pad 330, the VSS voltage line connection pad 320, the VSS voltage auxiliary line connection pad 326, the reference voltage line 341, the first VDD voltage line 331, the second VDD voltage line 332, the first VSS voltage line 321, the second VSS voltage line 322, the source electrode 217a and the drain electrode 217b of the driving thin film transistor 210 of the pixel may be made of the same material and may constitute the same layer.

[0193] However, as described above, the VDD voltage line connection pad 330 and the first VDD voltage line 331 may be integrally formed with each other without being separated from each other.

[0194] Therefore, the wire connection pad and the wire constitute the same layer. Therefore, the connection electrode that electrically connects the wire connection pad and the wire to each other should not form a short circuit with other wires between the wire connection pad and the wire to be connected to each other or between the wires.

[0195] For example, in order to connect the data line 313 branched from the data line connection pad 311 to the light emitting tester 375 , the data line 313 may be composed of a first data line 314 and a second data line 315 constituting different layers and electrically connected to each other.

[0196] In this case, the first data line 314, the source electrode 217a and the drain electrode 217b of the pixel driving thin film transistor 210 can constitute the same layer and can be made of the same material. The second data line 315 and the gate electrode 214 of the pixel driving thin film transistor 210 can constitute the same layer and can be made of the same material.

[0197] The data line 313 applies a data signal to the pixels in the display area DA. Therefore, the first data line 314 and the second data line 315 of the data line 313 branched from the data line connection pad 311 may constitute different layers so as not to form a short circuit with various wire connection pads and wires disposed in the area between the display area DA and the data line connection pad 311.

[0198] Therefore, the second data line 315 may be used as the data line 313 in the area between the display area DA and the data line connection pad 311. The first data line 314 constituting a layer different from that of the second data line 315 may be used as the data line 313 in the display area.

[0199] Then, the second data line 315 may be used as the data line 313 in the area between the display area DA and the light emitting tester 375. Then, the first data line 314 as the data line 313 may be connected to the light emitting tester 375.

[0200] However, the first data line 314 and the second data line 315 can be used as the data line 313 in a repeated alternating manner so that the data line 313 does not form a short circuit with the second VDD voltage line 332 and the second VSS voltage line 322 in an area where the data line 313 overlaps with the second VDD voltage line 332 and the second VSS voltage line 322 in an area between the display area DA and the light-emitting tester 375.

[0201] The data line 313 may be changed from the first data line 314 to the second data line 315 in an area where the data line 313 does not overlap with the second VDD voltage line 332, so that the data line 313 does not form a short circuit with the second VDD voltage line 332 while extending across the second VDD voltage line 332. In this way, the second data line 315 and the second VDD voltage line 332 do not constitute the same layer, thereby preventing a short circuit therebetween.

[0202] In this case, the data line 313 changes from the first data line 314 to the second data line 315 may refer to, for example Fig.12 As shown, the first data line 314 is connected to the second data line 315 via at least one contact hole so that the electrical connection between them is maintained, but the first data line 314 and the second data line 315 constitute different layers and are made of different materials. This principle can be equally applied to other lines in the following examples.

[0203] After the second data line 315 extends across the second VDD voltage line 332 , the second data line 315 may be changed back to the first data line 314 in a region where the data line 313 does not overlap the second VDD voltage line 332 .

[0204] That is, the first data line 314 and the second data line 315 may constitute different layers and be electrically connected to each other via at least one second data line contact hole 315h.

[0205] In the same manner, the reference voltage connection line 343 may be composed of a first reference voltage connection line 344 and a second reference voltage connection line 345 which constitute different layers and are electrically connected to each other.

[0206] In this case, the first reference voltage connection line 344, the source electrode 217a, and the drain electrode 217b may constitute the same layer and may be made of the same material. The second reference voltage connection line 345 and the gate electrode 214 may constitute the same layer and may be made of the same material.

[0207] For example, the reference voltage connection line 343 extends to the lower end of the display area DA. The reference voltage connection line 343 may be composed of a first reference voltage connection line 344 and a second reference voltage connection line 345 that constitute different layers and are electrically connected to each other. The reference voltage connection line 343 extends across the display area DA. The distal end of the reference voltage connection line 343 does not need to contact a separate line.

[0208] Because the reference voltage connection line 343 applies the reference voltage to the pixels in the display area DA, the reference voltage connection line 343 is composed of different reference voltage connection lines constituting different layers, so that the reference voltage connection line 343 will not form a short circuit with various wire connection pads and wires in the area between the display area DA and the reference voltage line 341.

[0209] Therefore, the reference voltage connection line 343 is implemented as the second reference voltage connection line 345 in the area between the display area DA and the reference voltage line 341. The reference voltage connection line 343 is implemented as the first reference voltage connection line 344 constituting a different layer from the second reference voltage connection line 345 in the display area DA.

[0210] The first reference voltage connection line 344 and the second reference voltage connection line 345 may constitute different layers and may be electrically connected to each other via at least one contact hole. In addition, the VSS voltage connection line 323 may be composed of the first VSS voltage connection line 324 and the second VSS voltage connection line 325 constituting different layers and electrically connected to each other.

[0211] In this case, the first VSS voltage connection line 324, the source electrode 217a, and the drain electrode 217b may constitute the same layer and may be made of the same material. The second VSS voltage connection line 325 and the gate electrode 214 may constitute the same layer and may be made of the same material.

[0212] For example, in order to connect the VSS voltage connection line 323 to the second VSS voltage connection line 322 , the first VSS voltage connection line 324 and the second VSS voltage connection line 325 constituting different layers are electrically connected to each other.

[0213] Since the VSS voltage connection line 323 electrically connects the first VSS voltage line 321 and the second VSS voltage line 322 sandwiched between the display area DA, the first VSS voltage connection line 324 and the second VSS voltage connection line 325 of the VSS voltage connection line can constitute different layers so that the VSS voltage connection line does not form a short circuit with various line connection pads and lines in the area between the first VSS voltage line 321 and the second VSS voltage line 322.

[0214] In one embodiment of the present disclosure, no other line is provided between the display area DA and the first VSS voltage line 321. Therefore, the VSS voltage connection line 323 extending from the first VSS voltage line 321 may be implemented as a first VSS voltage connection line 324 integrally formed with the first VSS voltage line 321 and made of the same material as the first VSS voltage line 321 and constituting the same layer as the first VSS voltage line 321.

[0215] The first VSS voltage connection line 324 branched from the first VSS voltage line 321 may extend across the display area DA. Then, when the VSS voltage connection line 323 extends across the second VDD voltage line 332, the first VSS voltage connection line 324 and the second VSS voltage connection line 325 may be used as the VSS voltage connection line 323 in a repeated alternating manner so that the VSS voltage connection line 323 does not form a short circuit with the second VDD voltage line 332 in an area where the VSS voltage connection line 323 overlaps the second VDD voltage line 332.

[0216] When the VSS voltage connection line 323 extends across the second VDD voltage line 332, the VSS voltage connection line 323 may be changed from the first VSS voltage connection line 324 to the second VSS voltage connection line 325 in an area where the VSS voltage connection line 323 does not overlap with the second VDD voltage line 332. Therefore, when the VSS voltage connection line 323 extends across the second VDD voltage line 332, the VSS voltage connection line 323 does not form a short circuit with the second VDD voltage line 332.

[0217] That is, the first VSS voltage link line 324 and the second VSS voltage link line 325 constitute different layers and are electrically connected to each other via at least one second VSS voltage link line contact hole 325h.

[0218] After the VSS voltage connection line 323 extends across the second VDD voltage line 332, the first VSS voltage connection line 324 may be connected to the second VSS voltage line 322, such as Fig.13 shown.

[0219] In this case, the first VSS voltage link line 324 and the second VSS voltage link line 322 may be electrically connected to each other via a second VSS voltage link line 325 connected to the first VSS voltage link line 324 via at least one second VSS voltage link line contact hole 325h.

[0220] In addition, in a region where the second VSS voltage line 322 does not overlap the data line 313 , an auxiliary line 327 connected to the second VSS voltage line 322 via at least one auxiliary line contact hole 327 h is disposed under the second VSS voltage line 322 .

[0221] The auxiliary line 327 and the gate electrode 214 may be made of the same material and may constitute the same layer.

[0222] The auxiliary line 327 may be connected to the back side of the second VSS voltage line 322 , thereby reducing the total resistance of the second VSS voltage line 322 .

[0223] In addition, the VDD voltage connection line 333 may be composed of a first VDD voltage connection line 334 and a second VDD voltage connection line 335 constituting different layers and being electrically connected to each other.

[0224] In this case, the first VDD voltage connection line 334, the source electrode 217a and the drain electrode 217b of the driving thin film transistor 210 of the pixel can be made of the same material and can constitute the same layer. The second VDD voltage connection line 335 and the gate electrode 214 of the driving thin film transistor 210 of the pixel can be made of the same material and can constitute the same layer.

[0225] For example, in order to connect the VDD voltage link line 333 to the second VDD voltage link line 332 , the first VDD voltage link line 334 and the second VDD voltage link line 335 constitute different layers and are electrically connected to each other.

[0226] The VDD voltage connection line 333 electrically connects the first VDD voltage line 331 and the second VDD voltage line 332 with the display area DA sandwiched therebetween. Therefore, the first VDD voltage connection line 334 and the second VDD voltage connection line 335 constitute different layers, so that the VDD voltage connection line 333 does not form a short circuit with various wire connection pads and wires in the area between the first VDD voltage line 331 and the second VDD voltage line 332.

[0227] Therefore, in the area between the first VDD voltage line 331 and the display area DA, the VDD voltage connection line 333 may be implemented as the first VDD voltage connection line 334. When the VDD voltage connection line 333 extends across the display area DA, the VDD voltage connection line 333 may be implemented as the second VDD voltage connection line 335. That is, the VDD voltage connection line 333 is changed from the first VDD voltage connection line 334 to the second VDD voltage connection line 335.

[0228] That is, the first VDD voltage connection line 334 and the second VDD voltage connection line 335 constitute different layers and are electrically connected to each other via at least one contact hole.

[0229] Then, if Fig.12 As shown, in the area between the display area DA and the second VDD voltage line 332 , the VDD voltage connection line 333 may be implemented as a first VDD voltage connection line 334 that may be connected to the second VDD voltage line 332 .

[0230] In this case, the first VDD voltage link line 334 and the second VDD voltage link line 332 may be electrically connected to each other via a second VDD voltage link line 335 connected to the first VDD voltage link line 334 via at least one second VDD voltage link line contact hole 335h.

[0231] In addition, the auxiliary line 327 connected to the second VDD voltage line 332 via at least one contact hole may be disposed in a region where the second VDD voltage line 332 does not overlap with the data line 313 and the VSS voltage connection line 323 .

[0232] The auxiliary line 327 and the gate electrode 214 may be made of the same material and may constitute the same layer.

[0233] The VDD voltage auxiliary line 327 may be connected to the back side of the second VDD voltage line 332 to reduce the total resistance of the second VDD voltage line 332 .

[0234] Figure 7 Also shown are passivation holes formed in the passivation layer 218 . Figure 8 Also shown are a first connection electrode 351 connecting the VSS voltage line connection pad 320 and the first VSS voltage line 321 to each other, and a second connection electrode 352 connecting the reference voltage line connection pad 340 and the reference voltage line 341 to each other.

[0235] A passivation layer 218 may be formed on the reference voltage line connection pad 340, the VDD voltage line connection pad 330, the VSS voltage line connection pad 320, the reference voltage line 341, the first VSS voltage line 321, the second VSS voltage line 322, the first VDD voltage line 331, and the second VDD voltage line 332. The passivation layer 218 may serve as a planarization layer made of an organic material layer such as PAC.

[0236] In addition, the passivation layer 218 serves as an insulating layer. Therefore, in order to make electrical connections between the wire connection pads and the wires, a passivation hole (ie, a planarization hole) may be formed in each wire connection pad and a portion of each wire.

[0237] The passivation hole refers to not only a contact hole but also an open hole formed by partially removing the passivation layer 218 to ensure a contact area as much as possible. Each wire connection pad and each wire may be electrically connected to each other via connection electrodes connected to each other through the passivation hole.

[0238] exist Figure 7 In order to make the distinction between the layers clear, the passivation layer 218 is not shown separately, and only the region where the passivation hole is formed is shown in an emphasized manner.

[0239] The first passivation hole 218a is formed on the VSS voltage line connection pad 320 and the first VSS voltage line 321. The first connection electrode 351 electrically connects the VSS voltage line connection pad 320 and the first VSS voltage line 321 to each other via the first passivation hole 218a. Figure 8 and Fig.14 shown.

[0240] In other words, in order to prevent a short circuit from occurring between the VSS voltage line connecting pad 320 and the first VSS voltage line 321 and the first VDD voltage line 331 and the reference voltage line 341 arranged between the VSS voltage line connecting pad 320 and the first VSS voltage line 331, a jump connection structure of the electrodes connecting the VSS voltage line connecting pad 320 and the first VSS voltage line 321 to each other may be required.

[0241] Therefore, according to an embodiment of the present disclosure, the passivation layer 218 is formed on the first VDD voltage line 331 and the reference voltage line 341. The first passivation hole 218a is formed on the VSS voltage line connection pad 320 and the first VSS voltage line 321.

[0242] Therefore, a skip connection structure of an electrode can be formed using a first connection electrode 351 formed on the passivation layer 218 and having a portion connected to the VSS voltage line connection pad 320 through a first passivation hole 218a and an opposite portion connected to the first VSS voltage line 321 via an opposite first passivation hole 218a.

[0243] The first connection electrode 351 and the anode electrode as the first electrode 221 constituting the organic light emitting element 220 may be made of the same material and may constitute the same layer.

[0244] The first connection electrode 351 electrically connects the VSS voltage line connection pad 320 and the first VSS voltage line 321 to each other, and to this end, is preferably formed to have as large an area as possible to minimize resistance and maximize uniformity of resistance distribution.

[0245] Therefore, the first connection electrode 351 may be formed to extend over the first VDD voltage line 331 , the reference voltage line 341 , and the first VSS voltage line 321 , and thus may be formed to have a maximized area.

[0246] However, the first connection electrode 351 does not extend over all regions of the first VDD voltage line 331 and the reference voltage line 341 and the first VSS voltage line 321. The first connection electrode 351 does not extend over a local region such as a region of a second connection electrode 352 described later or a spacing region between the first connection electrode 351 and the second connection electrode 352.

[0247] Furthermore, in order to maximize the contact area of ​​the first passivation hole 218 a with the VSS voltage line connection pad 320 and the first VSS voltage line 321 , the first passivation hole 218 a may have a shape corresponding to the first VSS voltage line 321 , ie, a long strip shape.

[0248] In addition, if Fig.14 As shown, at least one exhaust hole 355 may be formed in at least a partial region of the first connection electrode 351 .

[0249] The exhaust hole 355 serves to exhaust unnecessary gas that may be generated during a process of forming the transparent display panel 300. Therefore, when the exhaust hole 355 is formed in the first connection electrode 351 having a large area, the reliability of the transparent display panel 300 may be further enhanced.

[0250] The bank layer 231 formed on the first connection electrode 351 has an opening area defined therein corresponding to the exhaust hole 355 to ensure a passage of the exhaust hole 355. Each bank layer 231 may define a boundary between adjacent exhaust holes 355.

[0251] In addition, a VSS voltage auxiliary line connection pad 326 may be additionally provided, and the VSS voltage auxiliary line connection pad 326 may be electrically connected to the first VSS voltage line 321 via the first connection electrode 351 .

[0252] The VSS voltage auxiliary line connection pad 326 and the VSS voltage line connection pad 320 may be made of the same material and constitute the same layer. However, the VSS voltage auxiliary line connection pad 326 has an island shape that is separated from the VSS voltage line connection pad 320 and is not connected to a separate line.

[0253] The first passivation hole 218a is formed on the VSS voltage auxiliary line connection pad 326, so that the VSS voltage auxiliary line connection pad 326 is connected to the first connection electrode 351 via the first passivation hole 218a, thereby increasing the total area of ​​the first connection electrode 351, thereby reducing the total resistance and making the resistance distribution more uniform.

[0254] In one example, the passivation layer 218 is formed on the reference voltage line connection pad 340 and the reference voltage line 341. The second connection electrode 352 electrically connects the reference voltage line connection pad 340 and the reference voltage line 341 to each other via the second passivation hole 218b. Figure 8 and Fig.14 shown.

[0255] In order to prevent a short circuit between the reference voltage line connection pad 340 and the reference voltage line 341 and the first VDD voltage line 331 therebetween, a skip structure of an electrode for connecting the reference voltage line connection pad 340 and the reference voltage line 341 to each other is required.

[0256] Therefore, according to an embodiment of the present disclosure, the passivation layer 218 is formed on the first VDD voltage line 331, and the second passivation hole 218b is formed on each of the reference voltage line connection pad 340 and the reference voltage line 341, as shown in FIG. Figure 7 shown.

[0257] Therefore, a skip connection structure of the electrode can be formed using a second connection electrode 352 formed on the passivation layer 218 and having a portion connected to the reference voltage line connection pad 340 through a second passivation hole 218b and an opposite portion connected to the reference voltage line 341 through an opposite second passivation hole 218b.

[0258] The second connection electrode 352 and the first connection electrode 351 may be made of the same material and may constitute the same layer, but may be spaced apart from each other. Therefore, the second connection electrode 352 may have an island shape.

[0259] Therefore, the second connection electrode 352 and the anode electrode which is the first electrode 221 of the organic light emitting element 220 constituting the pixel may be made of the same material and may constitute the same layer.

[0260] The second connection electrode 352 electrically connects the reference voltage line connection pad 340 and the reference voltage line 341 to each other, and for this purpose, preferably, the second connection electrode 352 is formed to have as large an area as possible to minimize its resistance and maximize the uniformity of its resistance distribution. In addition, the second passivation hole 218b is formed to have as large an area as possible to maximize its contact area with the reference voltage line connection pad 340 and the reference voltage line 341.

[0261] In addition, as in the first connection electrode 351 , at least one exhaust hole 355 may be formed in a partial region of the second connection electrode 352 .

[0262] In one example, the third passivation hole 218c may be formed on the second VSS voltage line 322. Figure 7 As shown. Figure 8 As shown, the third connection electrode 353 may be formed on the third passivation hole 218 c.

[0263] The third passivation hole 218c formed on the second VSS voltage line 322 is intended to connect the second VSS voltage line 322 and the third connection electrode 353 to each other. The third connection electrode 353 is electrically connected to the second VSS voltage line 322 via the third passivation hole 218c.

[0264] In order to reduce resistance by maximizing the contact area between the second VSS voltage line 322 and the third connection electrode 353 , the third passivation hole 218 c may have a bar shape corresponding to the second VSS voltage line 322 .

[0265] In addition, when the third connection electrode 353 is formed at the lower end of the transparent display panel 300, the following effect occurs: the difference in vertical height between the upper end of the transparent display panel 300 and the lower end of the transparent display panel 300 of the first connection electrode 351 and the second connection electrode 352 can be removed.

[0266] The third connection electrode 353 , the first connection electrode 351 , and the second connection electrode may be made of the same material and may constitute the same layer, but may be spaced apart from each other. Therefore, the third connection electrode 353 is formed to have an island shape.

[0267] Therefore, the third connection electrode 353 and the anode electrode which is the first electrode 221 of the organic light emitting element 220 constituting the pixel may be made of the same material and may constitute the same layer.

[0268] A bank layer 231 may be formed on the first connection electrode 351, the second connection electrode 352, and the third connection electrode 353. Fig. 9As shown, the bank layer 231 may form a dam 380 disposed in the non-display area NDA to surround the display area DA. The dam 380 may include at least one patterned dam 380. When the dam 380 is formed on the first substrate 200, the dam 380 may be used to prevent the encapsulation material used to form the encapsulation layer 250 from flowing to the outside.

[0269] The dam 380 may be disposed in the non-display area NDA, and may be disposed to surround the light emitting tester 375 and the first VDD voltage line 331 disposed in the non-display area NDA.

[0270] In one example, the fourth connection electrode 354 is formed on the bank layer 231 and is connected to the cathode electrode of the second electrode 225 as the pixel. The fourth connection electrode 354 is electrically connected to the VSS voltage line to apply the VSS voltage to the cathode electrode of the pixel. In this case, the cathode electrode and the fourth connection electrode 354 can be formed integrally with each other.

[0271] One end of the fourth connection electrode 354 is electrically connected to the first connection electrode 351 to which the VSS voltage is applied, and the other end of the fourth connection electrode 354 is electrically connected to the third connection electrode 353 , thereby applying the VSS voltage to the cathode electrode.

[0272] like Fig. 9 , Fig.10 and Fig.16 As shown, the bank layer 231 is formed on the first connection electrode 351. The first bank hole 231a is formed on the first connection electrode 351 and is formed by removing a partial area of ​​the bank layer 231, thereby exposing the first connection electrode 351 to the outside. Therefore, the first connection electrode 351 can be electrically connected to one end of the fourth connection electrode 354 via the first bank hole 231a.

[0273] When a VSS voltage is applied to the fourth connection electrode 354, the fourth connection electrode 354 is not directly connected to the first VSS voltage line 321, but is connected thereto via the first connection electrode 351 made of the same material as the anode electrode, thereby reducing resistance.

[0274] In order to maximize the contact area between the first connection electrode 351 and the fourth connection electrode 354 , the first bank hole 231 a of the bank layer 231 on the first connection electrode 351 may be formed in the same stripe shape as the reference voltage line 341 .

[0275] In addition, the first bank hole 231 a may be formed in such a manner as to correspond to the reference voltage line 341 or the first VSS voltage line 321 .

[0276] For example, when the first bank hole 231 a is formed on a separate circuit region such as the ESD protection circuit region 371 , there may be a problem in that the bank hole is formed in a region with poor flatness.

[0277] Furthermore, when the first bank hole 231a is formed on a line such as the first VDD voltage line 331 away from the first VSS voltage line 321, a current path of the fourth connection electrode 354 electrically connected to the first VSS voltage line 321 via the first bank hole 231a becomes longer. Therefore, resistance increases accordingly.

[0278] For example, when the connection length to the fourth connection electrode 354 which is a cathode electrode of high resistance rather than an anode electrode of low resistance is larger, the total resistance may be larger.

[0279] Therefore, according to an embodiment of the present disclosure, it is preferable to form the first bank hole 231 a on the reference voltage line 341 or the first VSS voltage line 321 .

[0280] When the first bank hole 231 a is formed on the reference voltage line 341 , the inclined surface of the hole may be removed to obtain high flatness, thereby reducing resistance variation compared to when the bank hole is formed in a line-unformed portion of the bank layer 231 .

[0281] Furthermore, when the first bank hole 231 a is formed on the first VSS voltage line 321 , the length of the connection between the fourth connection electrode 354 and the first VSS voltage line 321 becomes smaller, thereby reducing the resistance.

[0282] like Fig. 9 and Fig.10 As shown, a second bank hole 231b formed by removing a local area of ​​the bank layer 231 is formed in a portion of the bank layer 231 on the third connection electrode 353 electrically connected to the second VSS voltage line 322, thereby electrically connecting the opposite portion of the fourth connection electrode 354 to the third connection electrode 353.

[0283] In this case, the second bank hole 231b is formed to correspond to the third passivation hole 218c on the second VSS voltage line 322. Therefore, when the second VSS voltage line 322, the third connection electrode 353 and the fourth connection electrode 354 are in a stacked state, they electrically contact each other at the same position.

[0284] In addition, the second VSS voltage line 322 is not directly connected to the cathode electrode but is connected thereto via the third connection electrode 353 which is a low-resistance anode electrode, thereby reducing resistance.

[0285] Due to the connection structure of the fourth connection electrode 354, the VSS voltage may be applied to the fourth connection electrode 354. Therefore, the VSS voltage may be applied to the cathode electrode of the organic light emitting element 220. That is, the VSS voltage applied from the VSS voltage line connection pad 320 may be applied to the fourth connection electrode 354 via the first VSS voltage line 321 and the first connection electrode 351.

[0286] The fourth connection electrode 354 may extend across the entire display area DA including the first VDD voltage line 331 , the reference voltage line 341 , the first VSS voltage line 321 , the second VDD voltage line 332 , and the second VSS voltage line 322 .

[0287] For example, Fig.15 As shown, the cathode electrode may extend across the entire display area DA including the second VDD voltage line 332 and the second VSS voltage line 322 , and may be surrounded by the dam 380 .

[0288] In one example, if Fig.17 As shown, the GIP circuit area 360 includes a GIP partition block 361 and a clock signal line area 363 .

[0289] The GIP partition block 361 includes at least one GIP partition block that divides the gate line GL into a plurality of blocks and drives each of the plurality of blocks in each of a plurality of display driving periods. The clock signal line region 363 may include at least one clock signal line to control the nodes of the GIP circuit region 360 .

[0290] The GIP partition blocks 361 and the clock signal line regions 363 may be alternately arranged in a direction away from the display area DA.

[0291] Specifically, the opaque and thick VSS voltage line may be omitted in the left and right portions of the non-display area NDA to the left and right of the display area DA. Therefore, the GIP circuit area 360 may occupy an area increased by the omitted area.

[0292] Therefore, the GIP partition block 361 and the clock signal line region 363 constituting the GIP circuit region 360 can be arranged in a non-compact manner. Therefore, a transparent region can be ensured even in the GIP circuit region 360.

[0293] For example, in the case where the space of the GIP circuit area 360 is narrow, the GIP partition block 361 and the clock signal line area 363 must be arranged in a very dense manner to maximize space utilization. Therefore, it is difficult to ensure a separate transparent area in the GIP circuit area 360.

[0294] On the contrary, as in one embodiment of the present disclosure, when the space of the GIP circuit area 360 increases, the GIP partition blocks 361 having a larger amount of opaque areas and the clock signal line areas 363 having a larger amount of transparent areas may be alternately arranged in a differentiated manner in the GIP circuit area 360. Therefore, even in the GIP circuit area 360, it is possible to ensure that the transparent area is maximized.

[0295] In other words, according to one embodiment of the present disclosure, the VSS voltage line is omitted in a side area of ​​the non-display area NDA outside the display area DA where the GIP circuit area 360 is disposed. Fig.17 and Fig.18 Therefore, the reduction of the transparent area due to the opaque VSS voltage line can be minimized.

[0296] Therefore, the light emitting tester 375 may be disposed between the dam 380 and the GIP circuit region 360 , but the VSS voltage line may not be disposed between the dam 380 and the GIP circuit region 360 .

[0297] The transparent display device should be able to display the image information to be displayed while having the same characteristics as those of the transparent glass substrate. The transparent display device having such characteristics can be configured as a composite transparent display device in which the display information and the spatial scene behind the transparent display device overlap each other. Representative examples thereof include head-up displays (HUDs) used in airplanes and cars.

[0298] like Fig.19 As shown, a head-up display used in a vehicle is mounted on a windshield of the vehicle to display various driving information to the driver while allowing the driver's forward vision to be ensured.

[0299] Therefore, in the head-up display, high visibility of the displayed information is required. When the haze value is high, the visibility of the displayed information is not good. Therefore, it is important to make the haze value as low as possible.

[0300] Haze is related to the clarity of an object seen through a transparent display device. Therefore, in a transparent display device having a high transmittance but a high haze value, there is a problem that the driver sees the object in a blurry manner, and thus the visibility of the displayed information is deteriorated. The occurrence of haze in a transparent display device can be attributed to the following light characteristics.

[0301] Fig. 20 (a) shows the long-distance diffraction pattern through a single slit. Fig. 20 (b) is an example of the diffraction effect in a single slit.

[0302] Diffraction of waves refers to the phenomenon that the wave front bends when the wave encounters an obstacle or a slit. In diffraction using a single slit, a surface wave of a certain wavelength leaving the slit forms a large number of spherical waves.

[0303] In this regard, light can be considered as a wave because diffraction occurs in slit experiments using light, e.g. Fig. 20 As shown in (a), when light passes through the slit, diffraction occurs in the same way as surface waves. However, a large number of new spherical waves interfere with each other, resulting in the occurrence of contrasting diffraction patterns.

[0304] Fig. 20 (b) shows Fraunhofer diffraction in which a diffraction pattern is observed at a greater distance from the diffraction object. Fraunhofer diffraction occurs when all rays are regarded as parallel rays, and the diffraction pattern is the same regardless of the distance.

[0305] The conditions for Fraunhofer diffraction to occur in a single slit can be calculated as follows.

[0306] When the difference between the paths of the two beams propagating at the edge and center of the slit is r1-r2, In this case, the mth offset interference condition for offset interference to occur is Since θ is usually much smaller than 1, the darkened points correspond to points farther from the center. or point.

[0307] Fig.21 (a) to Fig.21 (d) shows the results of double-slit experiments for particles, waves, light and electrons respectively.

[0308] When a particle passes through the double slits, Fig.21 As shown in (a), the distribution of particles hitting the screen appears as a simple sum of the individual distributions of particles passing through a single slit.

[0309] That is, in this case, the bright band appears on a portion of the screen that does not correspond to the center of the screen but to the slit position. When the wave passes through the double slit, the brightest band appears in the center of the screen, as Fig.21 This is shown in (b). This allows you to see if interference occurs. Since the particles do not interfere with each other, the particle distribution is stronger at the position where the particles can pass through the slit in the best way.

[0310] In one example, if Fig.21 As shown in (c), when light passes through the double slits, an interference pattern appears due to the fact that its particle properties disappear and waves pass through it. Electrons are usually considered particles. However, as Fig.21As shown in (d), when highly accelerated electrons pass through the double slits, the same results as those of the double slit experiment on waves appear.

[0311] That is, it can be seen that even when particles pass through the double slits at a sufficiently high speed, the same interference that occurs in waves occurs. As a result, it can also be seen that light has wave-particle duality because light is a wave generated by sufficiently fast particles as photons.

[0312] In this way, light has the characteristics of both waves and particles. Therefore, when light encounters a slit with a periodic pattern, overlap and deviation occur, resulting in periodic diffraction. Therefore, the diffraction phenomenon caused by the wave-particle duality of light can vary depending on the shape of the transmission area used as a slit in the transparent display device.

[0313] For example, Fig. 22 An arrangement of transmissive regions having a typical quadrilateral shape in a transparent display device is shown.

[0314] A plurality of transmission areas TAij are arranged in a matrix type, where i is a row number and j is a column number (i and j are natural numbers). Therefore, the transmission areas in the first row include TA11, TA12, TA13..., the transmission areas in the second row include TA21, TA22, TA23..., and the transmission areas in the third row include TA31, TA32, TA33... Similarly, the transmission areas in the first column are TA11, TA21, TA31..., the transmission areas in the second column are TA12, TA22, TA32..., and the transmission areas in the third column are TA13, TA23, TA33...

[0315] In this case, each transmission area has a rectangular shape with all inner angles of 90 degrees. As a result, each of the transmission areas TA21 and TA23 adjacent to the transmission area TA22 of the same row has a vertical side facing and parallel to the vertical side of the transmission area TA22.

[0316] In addition, each of the transmission areas TA12 and TA32 adjacent to the transmission area TA22 of the same column has a horizontal side facing and parallel to the horizontal side of the transmission area TA22. That is, each of all the sides of the transmission area TA22 faces and is parallel to the corresponding side of each adjacent transmission area. The same principle can be equally applied to other transmission areas.

[0317] Since light passes through the transmission areas, they can play the same role as the slits shown in the double slit experiment above. Therefore, depending on the shape and arrangement structure of the transmission area, the occurrence or non-occurrence of diffraction of light and the intensity may vary.

[0318] The diffraction of light is caused by the periodic repetition of lines constituting the slits, and when adjacent lines constituting the slits have periodicity in a manner parallel to each other or when the slits are periodically arranged, the diffraction of light can be more clearly produced.

[0319] Therefore, in a transparent display device, Fig. 22 As shown, when each transmission area having a rectangular shape is arranged in parallel in a matrix type having regularity and periodicity, the diffraction phenomenon of light can be clearly observed.

[0320] Fig.23 It shows that when light is incident on a Fig. 22 The shape of the transmission area and the arrangement structure of the transmission area shown in the figure are the diffraction phenomenon of light generated in the central area of ​​the transparent display device.

[0321] As in Fig.23 As can be seen in the figure, it can be seen that the diffraction phenomenon of light appears very clearly around the central area where the light is incident. As the diffraction phenomenon of light becomes more obvious in the transparent display device, the haze also increases. As a result, the clarity or visibility of the transparent display device is reduced.

[0322] Therefore, a new pixel structure having a shape of a transmission area is needed, which can minimize the diffraction of light caused by the periodic repetition of lines in the transmission area. Therefore, the present disclosure provides a new pixel structure, which includes a transmission area having a new transmission area shape as follows.

[0323] A transparent display panel according to another embodiment of the present disclosure includes: a substrate having a display area including a plurality of light-emitting areas and a plurality of transmission areas; and a plurality of line areas disposed above the substrate and extending across the display area, wherein an outer contour of each transmission area is at least partially curved.

[0324] For example, in Fig.24 In the embodiment of the present disclosure shown, the outer contour of each transmission area can be partially curved. Specifically, the transmission area TA22 has four sides protruding outward, which correspond to the four sides of the virtual rectangle drawn in the shape of dotted dots inside the transmission area. The same feature can be applied to other transmission areas.

[0325] Therefore, the sides of the transmission area TA22 and each of the transmission areas TA21 and TA23 adjacent to the transmission area TA22 facing each other may not be parallel to each other. In addition, the sides of the transmission area TA22 and each of the transmission areas TA12 and TA32 adjacent to the transmission area TA22 in the same column facing each other may not be parallel to each other.

[0326] exist Fig.25In another embodiment of the present disclosure, the outer contour of each transmission area can be partially curved. Specifically, the transmission area TA22 has six sides protruding outward, which correspond to the six sides of the virtual hexagon drawn in the form of dotted dots inside the transmission area. The same feature can be applied to other transmission areas.

[0327] Therefore, the sides of the transmission area TA22 and each of the transmission areas TA21 and TA23 adjacent to the transmission area TA22 facing each other may not be parallel to each other. In addition, the sides of the transmission area TA22 and each of the transmission areas TA12 and TA32 adjacent to the transmission area TA22 in the same column facing each other may not be parallel to each other.

[0328] exist Fig.26 In another embodiment of the present disclosure, the outer contour of each transmission area has a circular shape. Specifically, the transmission area TA22 is formed to have a circular shape. The same features can be applied to other transmission areas.

[0329] Therefore, the sides of the transmission area TA22 and each of the transmission areas TA21 and TA23 adjacent to the transmission area TA22 facing each other may not be parallel to each other. In addition, the sides of the transmission area TA22 and each of the transmission areas TA12 and TA32 adjacent to the transmission area TA22 in the same column facing each other may not be parallel to each other.

[0330] in other words, Figure 24 to Figure 26 All sides of the transmission area TA22 in FIG. 2 may not be parallel to all sides of each transmission area adjacent thereto. The same feature may be applied to other transmission areas.

[0331] Therefore, even when each has Figure 24 to Figure 26 When the transmission areas of the shown shape are arranged in a matrix type, it is also possible to avoid parallel regularity and periodicity of the transmission areas serving as slits, thereby minimizing the diffraction of light.

[0332] In addition, in another embodiment according to the present disclosure, each transmission area may be formed in an elliptical shape. Due to the elliptical shape, the parallel regularity and periodicity of the transmission area used as the slit as described above may be avoided, thereby minimizing the diffraction of light.

[0333] although Figure 24 to Figure 26 It is shown by way of example that the entire outer contour of each transmission area is curved, but the present disclosure is not limited thereto. Even when only a portion of the contour of the transmission area is curved, parallel regularity and periodicity of the transmission area can be avoided, thereby minimizing diffraction of light.

[0334] Therefore, in a transparent display panel including transmissive areas each having an outer contour that is at least partially curved, diffraction of light can be minimized, thereby reducing haze. As a result, clarity or visibility of the transparent display device can be improved.

[0335] Fig. 27 It shows that when light is incident on a Fig.26 The circular shape of the transmission area and the arrangement structure of the transmission area in the transparent display device shown in the figure generate a diffraction phenomenon of light in the central area. Fig. 27 It can be seen that there is basically no diffraction of light around the central area of ​​the incident light.

[0336] Therefore, in a Fig.26 FIG. 1 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 2 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 3 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 4 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 5 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 6 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 7 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 8 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 9 is a transparent display device having a circular-shaped transmission area and an arrangement structure of the transmission area, and FIG. 10 is a transparent display device having a circular-shaped transmission area and an arrangement structure Fig.23 In comparison, the non-occurrence of diffraction of light is much clearer.

[0337] The diffraction of light is minimized, especially when the transmission area has a circular shape. Therefore, in order to minimize the diffraction interference of light, it is desirable to form the transmission area to have a shape as close to a circle as possible. However, when the outer contour of the transmission area is at least partially curved, as in a circular transmission area, the area of ​​the transmission area may be reduced. Therefore, it may be difficult to design a pixel including a light emitting area and a line area.

[0338] Therefore, hereinafter, another embodiment according to the present disclosure is illustrated, which is capable of designing an optimized transmission area and an optimized light emitting area while minimizing the diffraction interference of light.

[0339] A transparent display panel according to another embodiment of the present disclosure includes: a substrate, which includes: a display area including multiple light-emitting areas and multiple transmission areas; and multiple line areas, which are arranged above the substrate and extend across the display area, wherein each transmission area has a polygonal shape and all internal angles of the polygon are obtuse angles.

[0340] For example, Fig.28 As shown, each transmission area has a polygonal shape with all internal angles being obtuse. That is, the polygon with all internal angles being obtuse includes all polygons with at least 5 sides. The polygon may include all sides with equal lengths.

[0341] Specifically, in Fig.28 In the embodiment, the transmission area has a hexagonal shape, more specifically, a regular hexagonal shape. This is an example. Fig.28As shown, the sides facing each other of the transmission area TA22 and each of the transmission area TA21 and the transmission area TA23 adjacent to the transmission area TA22 may not be parallel to each other. However, the sides facing each other of the transmission area TA22 and each of the transmission area TA12 and the transmission area TA32 adjacent to the transmission area TA22 in the same column may be parallel to each other.

[0342] Therefore, if Fig.28 As shown, when the transmission areas having a hexagonal shape are arranged, the sides of the transmission areas adjacent to each other in the same row facing each other may not be parallel to each other. Therefore, the parallel regularity and periodicity of the transmission areas are avoided, so that the diffraction of light can be minimized as much as possible.

[0343] In other words, when the mutually facing sides of transmission regions adjacent to each other in the same row and / or column are not parallel to each other, the diffraction of light can be minimized compared to when the mutually facing sides of transmission regions adjacent to each other in the same row and / or column are parallel to each other.

[0344] In such Fig.28 In the hexagonal transmission area shape shown, the length of each of the mutually facing sides of the transmission areas adjacent to each other in the same column is small. Therefore, even when the mutually facing sides of the transmission areas adjacent to each other in the same column are parallel to each other, the diffraction phenomenon of light can be reduced.

[0345] Therefore, even if the transparent display device is arranged in a matrix type with Fig.28 When the transmission regions are of the shape shown, the parallel regularity and periodicity of the transmission regions used as slits are also avoided, so that the diffraction of light can be minimized as much as possible.

[0346] In another embodiment according to the present invention, Fig.29 As shown, each transmission area has an octagonal shape, in particular, a regular octagonal shape with all internal angles being obtuse angles. This is an example. Fig.29 The octagon shown is closer to a circle than a hexagon, so that Fig.29 The shape of obtains an effect similar to minimizing the diffraction of light achieved by having a circular transmissive area.

[0347] exist Fig.29 In the octagonal transmission area shown, each of the mutually facing sides of the transmission areas adjacent to each other in the same column has a smaller length. Therefore, even when the mutually facing sides of the transmission areas adjacent to each other in the same column are parallel to each other, the diffraction phenomenon of light can be reduced.

[0348] Therefore, even when the transparent display device has a matrix type arrangement Fig.29When the transmission area is of the shape shown, the parallel regularity and periodicity of the transmission area as a slit are also avoided, so that the diffraction of light can be minimized as much as possible.

[0349] That is, the transmission area in the shape of a polygon in which all inner angles are obtuse angles, particularly the transmission area in the shape of a regular polygon in which all inner angles are obtuse angles, has a shape closer to a circle, thereby minimizing the diffraction of light.

[0350] In addition, the area of ​​the polygonal-shaped transmissive area in which all inner angles are obtuse angles can be larger than the area of ​​the curved or circular transmissive area. Therefore, when the polygonal-shaped transmissive area in which all inner angles are obtuse angles is used, pixel design and line area design can be easier than when the curved or circular transmissive area is used.

[0351] Therefore, a transparent display panel including a transmissive area having a polygonal shape in which all inner angles are obtuse angles may ensure a maximized transmissive area with a reduced haze level and may facilitate design of pixel and line areas.

[0352] Hereinafter, the arrangement shapes of the light emitting area and the transmission area according to the embodiment of the present disclosure will be described in more detail based on an embodiment in which the transmission area has an octagon among the various embodiments of the transmission area shape exemplified above.

[0353] like Fig.30 As shown, a transparent display panel according to an embodiment of the present disclosure includes: a substrate having a display area including a plurality of light-emitting areas and a plurality of transmission areas; and a line area, which is arranged on the substrate and extends across the display area. In this case, the transmission area has a polygonal shape in which all its internal angles are obtuse angles.

[0354] The transparent display panel may include a plurality of transmission areas TA through which light is transmitted and non-transmission areas NTA through which light is not transmitted. Among the transmission areas, the plurality of transmission areas are arranged in a matrix consisting of a plurality of rows and columns of transmission areas.

[0355] In this case, a plurality of transmission areas arranged in the same row is referred to as a transmission area row. A plurality of transmission areas arranged in the same column is referred to as a transmission area column. In this case, the row direction refers to the horizontal direction of the substrate and is consistent with the X-axis direction. The column direction is defined as the vertical direction of the substrate consistent with the Y-axis direction.

[0356] The non-transmission area NTA may include a light emitting area in which light is emitted and a non-light emitting area in which no light is emitted. The light emitting area refers to an area in which the light emitting area EA of the sub-pixel is arranged. The non-light emitting area may include a plurality of line areas CLA, each line area extending in a vertical direction of the substrate.

[0357] In this case, the plurality of line areas are column line areas CLA1, CLA2, CLA3, CLA4, ... each extending in the column direction. The plurality of line areas include data lines and various voltage lines extending in the column direction. In addition, the pixel circuit area PCA connected to the light emitting area of ​​each sub-pixel can be set in the non-light emitting area.

[0358] The pixel circuit area PCA may be disposed under the emission area EA and may be aligned with the emission area EA. The PCA partially overlaps the emission area EA, and a non-overlapping area of ​​the PCA area may be included in the non-emission area.

[0359] In addition, the line area CLA is placed in the non-luminous area. However, when the luminous area EA partially overlaps the line area CLA, the portion of the area CLA overlapping the luminous area EA can be used as the luminous area. A plurality of transmissive areas (TAij, where i is the row number, j is the column number, and i and j are natural numbers) can be arranged in a matrix type.

[0360] Fig.30 The transparent display panel of is an example of a sub-pixel arrangement structure having an RG-BG, but the present disclosure is not limited thereto. For example, the first color sub-pixel may be a red sub-pixel including a first color light-emitting area emitting red light. The second color sub-pixel may be a green sub-pixel including a second color light-emitting area emitting green light. The third color sub-pixel may be a blue sub-pixel including a third color light-emitting area emitting blue light. However, the present disclosure is not limited thereto.

[0361] The first color sub-pixel Rij_SP includes a first color light-emitting region Rij and a first color pixel circuit region Rij_CA electrically connected to the first color light-emitting region Rij to control light emission from the first color light-emitting region Rij. The first color pixel circuit region Rij_CA may be disposed below the first color light-emitting region Rij while partially overlapping therewith. Therefore, at least a partial region of the first color pixel circuit region Rij_CA does not overlap with the first color light-emitting region Rij and may be exposed to the outside.

[0362] In this case, the portion of the first color pixel circuit region Rij_CA exposed to the outside can be offset relative to the first color light-emitting region Rij, for example, can be offset to the right of the first color light-emitting region Rij. Therefore, the light-emitting region and the pixel circuit region can be arranged more efficiently in the entire pixel arrangement structure.

[0363] In a partial region of the first color pixel circuit region Rij_CA exposed to the outside, a first color sub-pixel contact hole Rij_H electrically connecting the first color light emitting region Rij and the first color pixel circuit region Rij_CA to each other may be formed.

[0364] Furthermore, each of the second and third color subpixels Gij_SP and Bij_SP may be configured in the same manner as the first color subpixel Rij_SP exemplified above in terms of emission region, pixel circuit region, subpixel contact hole, etc. Therefore, additional repeated descriptions thereof will be omitted.

[0365] The first color sub-pixels are placed between adjacent rows of transmission areas. For example, the first color sub-pixels R11_SP, R12_SP, and R13_SP are respectively disposed between the transmission areas TA11, TA12, and TA13 in the first row and the transmission areas TA21, TA22, and TA23 in the second row. Therefore, the first color light-emitting areas R11, R12, and R13 may be respectively disposed between the transmission areas TA11, TA12, and TA13 in the first row and the transmission areas TA21, TA22, and TA23 in the second row.

[0366] The first color sub-pixel is disposed between the second color sub-pixel and the third color sub-pixel. Therefore, the first color light emitting region is disposed between the second color light emitting region and the third color light emitting region.

[0367] Furthermore, the first color subpixel is disposed between adjacent line areas CLA among a plurality of line areas CLA arranged in the vertical direction of the substrate and does not overlap the line area CLA. The second color subpixel and the third color subpixel are disposed on the line area CLA and partially overlap the line area CLA.

[0368] For example, the second color sub-pixels G12_SP and G14_SP in the same row as the first color sub-pixels R11_SP, R12_SP and R13_SP among the second color sub-pixels at least partially overlap the second column line area CLA2 and the fourth column line area CLA4, respectively. The second color sub-pixels G21_SP and G23_SP in the same row as the first color sub-pixels R21_SP, R22_SP and R23_SP at least partially overlap the first column line area CLA1 and the third column line area CLA3, respectively.

[0369] The third color sub-pixels B11_SP and B13_SP in the same row as the first color sub-pixels R11_SP, R12_SP and R13_SP among the third color sub-pixels at least partially overlap the first column line area CLA1 and the third column line area CLA3, respectively. The third color sub-pixels B22_SP and B24_SP in the same row as the first color sub-pixels R22_SP, R22_SP and R23_SP at least partially overlap the second column line area CLA2 and the fourth column line area CLA4, respectively.

[0370] In other words, like the configuration in which the third color subpixel B11_SP and the second color subpixel G21_SP are spaced apart in the column direction and disposed in the first column line area CLA1, the second color subpixel and the third color subpixel are disposed in one column line area and are alternately arranged in the column direction.

[0371] In addition, as in the configuration in which the third color subpixel B11_SP and the second color subpixel G12_SP of the same row are respectively arranged in the first column line area CLA1 and the second column line area CLA2 adjacent thereto, the second color subpixels and the third color subpixels are alternately arranged in the row direction and are respectively arranged in column line areas adjacent to each other in the row direction.

[0372] Therefore, the first color subpixel R11_SP, the second color subpixel G12_SP, the first color subpixel R12_SP, and the third color subpixel B13_SP are sequentially arranged in the first row. In the second row adjacent to the first row, the first color subpixel R21_SP, the third color subpixel B22_SP, the first color subpixel R22_SP, and the second color subpixel G23_SP are sequentially arranged to correspond to the above pattern.

[0373] Therefore, the second color subpixel G12_SP, the first color subpixel R12_SP, and the third color subpixel B13_SP arranged in the first row and the third color subpixel B22_SP, the first color subpixel R22_SP, and the second color subpixel G23_SP arranged in the second row surround the transmission area TA22. When this arrangement shape is used as a basic unit, a plurality of units are arranged in a matrix manner in the display area.

[0374] That is, in the transmission area according to the embodiment of the present disclosure, when the above basic unit is defined as one pixel, a single transmission area is not divided into two or more in a single pixel, thereby effectively suppressing an increase in haze.

[0375] In this regard, the change in haze value based on the shape of the transmission area and based on the division or non-division of the transmission area can be based on Fig.31 and Fig.32 Specifically, Fig.31 (a) shows a configuration in which the transmission area has a quadrilateral shape and three transmission areas correspond to one pixel. Fig.31 (b) shows a configuration in which the transmission area has a quadrilateral shape and two transmission areas correspond to one pixel. Fig.31 (c) shows a configuration in which one transmission area corresponds to one pixel and the transmission area has a circular shape as in one embodiment of the present disclosure.

[0376] Fig.31 (a) to Fig.31 All of (c) are based on experimental results of 145ppi (pixels per inch). Fig.31 In (a), the haze value was measured to be 2.76%. Fig.31 In (b), the haze value was measured to be 2.03%. Therefore, it can be seen that as the number of transmission areas corresponding to one pixel decreases from three to two, the haze value decreases by 26.4%.

[0377] exist Fig.31 In (c), the haze value was measured to be 1.33%. Figure 3 In (c), Fig.31 Compared with the haze value in (b), the haze value is reduced by 34.5%. Therefore, it can be clearly seen that as the number of transmission areas decreases from 2 to 1 and the transmission area has a circular shape, the haze value is further reduced.

[0378] Fig.32 Graphs of haze values ​​are shown when the ppi is 200ppi, 100ppi, and 145ppi, respectively, and when the transmission area has a quadrilateral shape and the number of transmission areas corresponding to one pixel is 3 (A), when the transmission area has a quadrilateral shape and the number of transmission areas corresponding to one pixel is 2 (B), and when a circular transmission area is set and the number of transmission areas corresponding to one pixel is 1 (C).

[0379] from Fig.32 It can be seen from the graph result values ​​in that, in configuration C in which a circular transmission area is provided but the number of transmission areas corresponding to one pixel is 1, the haze value is minimized for all ppi.

[0380] The first color light emitting area, the second color light emitting area and the third color light emitting area are arranged to correspond to the first color sub-pixel, the second color sub-pixel and the third color sub-pixel respectively. Therefore, the light emitting areas are arranged in the same manner as the arrangement structure of the sub-pixels as described above.

[0381] like Fig.30As shown, the transmission area has an octagonal shape. The first color light emitting area has a rectangular shape. In this case, the shape of the first color light emitting area is formed to be surrounded by the bank layer 231, such as Fig.34 Specifically, in the first color light emitting region, the bank layer 231 may be removed to be open.

[0382] In addition, each of the second color light emitting region and the third color light emitting region may have a polygonal shape, such as a hexagon. The shape of each of the second color light emitting region and the third color light emitting region is formed to be surrounded by the bank layer 231. Specifically, in each of the second color light emitting region and the third color light emitting region, the bank layer 231 may be removed to be open.

[0383] The area of ​​a first color light-emitting region may be smaller than the area of ​​each of a second color light-emitting region and a third color light-emitting region. Specifically, since the life of the red light-emitting region is longer than the life of each of the green light-emitting region and the blue light-emitting region, the former has better life reliability and luminous efficiency. Therefore, it is desirable to form a red light-emitting region having an area smaller than the area of ​​each of the green light-emitting region and the blue light-emitting region. For example, the first color light-emitting region, the second color light-emitting region, and the third color light-emitting region may be formed with an area ratio of approximately 1:1.8:1.8.

[0384] Each of the second color light emitting area and the third color light emitting area can be arranged in a corresponding line area and can at least partially overlap with it. In this case, each of the second color light emitting area and the third color light emitting area can be arranged to be symmetrical around each corresponding line area. Due to this arrangement structure, the transparent display panel according to an embodiment of the present disclosure can have a pixel arrangement structure that can efficiently utilize most of the light emitting area.

[0385] In another embodiment of the present disclosure, Fig.33 As shown, each of the second color sub-pixel and the third color sub-pixel may include a light emitting region that further extends along the line region in a column direction of the line region.

[0386] In order to ensure the luminous area as much as possible, Fig.33 As shown, for example, the third color sub-pixel B11_SP and the second color sub-pixel G21_SP arranged in the column direction of the first line area CLA1 are enlarged so that the interval therebetween is larger.

[0387] Preferably, the third color subpixel B11_SP and the second color subpixel G21_SP arranged in the column direction of the first line area CLA1 may also extend to such an extent that the distal ends of the two subpixels abut each other. However, considering the process margin, the distal ends thereof may have a predetermined separation space therebetween.

[0388] In particular, when the second electrode of the organic light emitting diode, for example, the cathode electrode, is made of a metal such as Ag having a low surface resistance, a separate contact structure is not required to reduce the resistance of the cathode electrode. Fig.33 As shown, the area of ​​each color sub-pixel can be expanded as much as possible in the line area.

[0389] Fig.34 and Fig.35 They are shown respectively Fig.30 Cross-sections of the I-I' and J-J' regions. Fig.34 is a cross-sectional view of a first color sub-pixel region.

[0390] Specifically, a passivation layer 218 as a planarization layer is disposed on the first color pixel circuit area R_PCA. A first electrode 221 of the organic light emitting diode 220, for example, an anode electrode, is formed on the passivation layer 218.

[0391] The bank layer 231 is formed on the first electrode 221. In order to expose the portion of the first electrode 221 corresponding to the light emitting region to the outside, the portion of the bank layer 231 corresponding to the light emitting region is removed, and thus the bank layer is patterned. That is, the bank layer 231 can serve as a boundary defining the light emitting region, thereby determining the shape of the light emitting region, and can also serve as a boundary between the sub-pixel and the transmission region.

[0392] The shape of the first electrode 221 is determined based on the patterned shape of the bank layer 231. In order to maximize transmittance and a light emitting area, it is desirable to form the bank layer to have a minimum width allowed during a mask process for forming the bank layer 231.

[0393] On and over first electrode 221, organic light emitting layer 223 is formed to cover bank layer 231. Second electrode 225, for example, a cathode electrode, is formed on organic light emitting layer 223. Since organic light emitting layer 223 and second electrode 225 are stacked on first electrode 221 in an overlapping manner to form organic light emitting diode 220, a region of first electrode 221 exposed to the outside through an opening region in bank layer 231 can be used as a light emitting region.

[0394] The encapsulation layer 250 may be formed on the second electrode 225. The color filter CF may be formed on the encapsulation layer 250. The color filter CF may have the same color as the corresponding light emitting region. The first color filter R_CF corresponding to the first color sub-pixel R_SP may have the same color as the first color.

[0395] When the color filter CF is used, the reflectivity can be reduced and the color purity of the RGB colors can be improved. The color filter CF can extend to the boundary between the transmission area TA and the emission area EA, and thus can be formed in the non-transmission area NTA. Therefore, the area where the color filter CF is formed can be defined as the emission area.

[0396] The top substrate as the second substrate 270 may be adhered to the color filter CF. In addition, in order to prevent damage to the organic film layer susceptible to high temperature, the top substrate may be disposed on the color filter CF using a COE (color filter on package) method in which a low temperature color filter process is performed on a substrate without a bonding process.

[0397] In one example, Fig.35 is a cross-sectional view of a boundary region between the first color sub-pixel R_SP and the second color sub-pixel G_SP.

[0398] A passivation layer 218 as a planarization layer is provided on the pixel circuit area PCA, specifically, on the first color pixel circuit area R_PCA and the second color pixel circuit area G_PCA. A first electrode 221 (eg, an anode electrode) of the organic light emitting diode 220 is formed on the passivation layer 218.

[0399] The first electrodes 221 spaced apart from each other are formed in the first color sub-pixel region and the second color sub-pixel region, respectively. The bank layer 231 is formed on the first electrode 221. In order to expose the portion of the first electrode 221 corresponding to the light emitting region to the outside, the portion of the bank layer 231 corresponding to the light emitting region is removed. Then the bank layer is patterned.

[0400] That is, the bank layer 231 may serve as a boundary between adjacent sub-pixels. The region corresponding to the bank layer 231 may be a non-transmission region NTA. On and above the first electrode 221, an organic light emitting layer 223 is formed to cover the bank layer 231. The second electrode 225 is formed on the organic light emitting layer 223.

[0401] When the organic light emitting layer 223 and the second electrode 225 are stacked on the first electrode 221 in an overlapping manner to form the organic light emitting diode 220, a region of the first electrode 221 exposed to the outside through the opening region of the bank layer 231 may be a light emitting region.

[0402] The encapsulation layer 250 may be formed on the second electrode 225. The color filter CF may be formed on the encapsulation layer 250.

[0403] The first color filter R_CF corresponding to the first color sub-pixel R_SP may have a first color, and the second color filter G_CF corresponding to the second color sub-pixel G_SP may have a second color.

[0404] Both the first color filter R_CF and the second color filter G_CF may be formed as wide as possible so that at least partial areas thereof overlap with the bank layer 231 .

[0405] In one example, the first color sub-pixel R_SP and the second color sub-pixel G_SP are adjacent to each other. Therefore, in order to minimize the mixing of light beams of different colors adjacent to each other and to make the boundaries between light-emitting areas of different colors clear, an opaque black matrix G_CF can be set between the first color filter R_CF and the second color filter.

[0406] The black matrix may be formed in a pattern corresponding to the bank layer 231 forming a boundary, and may be formed to be narrower than the bank layer 231 and may be disposed inside the bank layer 231 .

[0407] In one example, if Fig.36 As shown, the substrate has a non-display area surrounding the display area. The non-display area may include an outermost virtual pixel pattern area DPA arranged to surround the display area. Specifically, the display area includes a plurality of sub-pixels SP. The virtual pixel pattern area DPA may include a plurality of virtual pixels or virtual sub-pixels DSP.

[0408] The dummy pixel or dummy sub-pixel DSP is formed to minimize process deviations and side effects (eg, loading effects) that may occur during the manufacturing process of the transparent display device. The dummy pixel may surround the sub-pixel to serve as a buffer zone.

[0409] The virtual pixel may have an organic light emitting element layer and a circuit area such as a driving thin film transistor as in a sub-pixel. However, a signal is not applied to each element layer and circuit area of ​​the virtual pixel. Therefore, a separate pixel contact hole SP_H is not required to electrically connect its components to each other. As a result, the organic light emitting element layer in the virtual pixel pattern area does not emit light. Circuit areas such as the driving thin film transistor of the virtual pixel do not work.

[0410] The outermost virtual pixel pattern area surrounding the display area may include a top row direction area and a bottom row direction area above and below the display area, such as Fig.37 As shown, the outermost virtual pixel pattern area surrounding the display area may include a left column direction area and a right column direction area on the left and right sides of the display area, such as Fig.37 As shown. Static electricity may invade the GIP areas on the left and right of the display area through the gate line. Therefore, the left column direction area and the right column direction area of ​​the virtual pixel pattern area may be thicker than the top row direction area and the bottom row direction area thereof.

[0411] Hereinafter, a transparent display panel according to another embodiment of the present disclosure, which obtains the effects of the present disclosure as described above without reducing the transmittance of a display area, and a transparent display device including the same will be described in detail.

[0412] like Fig.38 As shown, in a transparent display panel including a display area and a non-display area, the display area includes: a plurality of light-emitting areas, a plurality of transmission areas, a plurality of line areas spaced apart from each other and arranged in one direction, and a plurality of pixel circuit areas electrically connected to the light-emitting areas to respectively drive the light-emitting areas.

[0413] First, each line area CLA extends in the vertical direction of the display area. The alternately adjacent line areas CLA include alternately adjacent VSS voltage connection lines 323 and VDD voltage connection lines 333, respectively.

[0414] In this case, the line area CLA including the VSS voltage connection line 323 includes a plurality of reference voltage (Vref) connection lines 343 symmetrically arranged around the VSS voltage connection line 323 and a plurality of data (Vdata) lines 313 symmetrically arranged around the VSS voltage connection line 323 .

[0415] Furthermore, the line area CLA including the VDD voltage connection line 333 includes a plurality of reference voltage connection lines 343 symmetrically arranged around the VDD voltage connection line 333 and a plurality of data lines 313 symmetrically arranged around the VDD voltage connection line 333 .

[0416] For example, when a line area including the VDD voltage connection line 333 is defined as the first column line area CLA1 , the first column line area CLA1 includes two reference voltage connection lines 343 symmetrically arranged around the VDD voltage connection line 333 and two data lines 313 symmetrically arranged around the VDD voltage connection line 333 .

[0417] Furthermore, the second column line area CLA2 adjacent to the first column line area CLA1 includes the VSS voltage connection line 323. In this case, the second column line area CLA2 includes two reference voltage connection lines 343 symmetrically arranged around the VSS voltage connection line 323 and two data lines 313 symmetrically arranged around the VSS voltage connection line 323.

[0418] According to the present disclosure, both VSS voltage connection line 323 and VDD voltage connection line 333 extend across the display area. Therefore, opaque and thick connection lines, especially VSS voltage connection lines, can be removed from the non-display area, so that the size of the transparent area of ​​the frame can be maximized and the frame can be thinned.

[0419] In particular, instead of providing an opaque and thick VSS voltage connection line in the non-display area, the VSS voltage connection line is formed inside the display area and is divided into a plurality of thin lines. Therefore, the VSS voltage connection line can connect the upper first VSS voltage line and the lower second VSS voltage line with the display area sandwiched therebetween, thereby minimizing the reduction in transmittance of the display area.

[0420] In other words, when multiple VSS voltage connection lines and multiple VDD voltage connection lines are arranged in the display area together with data lines and reference voltage connection lines, the reduction in transmittance of the display area can be minimized compared to a structure in which no VSS voltage connection line is formed in the display area.

[0421] The plurality of light-emitting regions include a first color light-emitting region Rij, a second color light-emitting region Gij, and a third color light-emitting region Bij. Each of the second color light-emitting region and the third color light-emitting region may overlap at least partially with each line region. Thus, the first color light-emitting region may be placed between line regions adjacent to each other. Each of the second color light-emitting region and the third color light-emitting region may be arranged symmetrically around each line region.

[0422] In one example, the first color subpixel Rij_SP includes a first color light emitting region Rij and a first color pixel circuit region Rij_PCA electrically connected to the first color light emitting region Rij to drive the first color light emitting region Rij to emit light. The first color light emitting region Rij and the first color pixel circuit region Rij_PCA may be electrically connected to each other via a first color subpixel contact hole Rij_H.

[0423] Furthermore, each of the second color sub-pixel Gij_SP and the third color sub-pixel Bij_SP may be configured in the same manner as the first color sub-pixel Rij_SP in terms of a light emitting area, a pixel circuit area, a sub-pixel contact hole, and the like.

[0424] Therefore, a plurality of pixel circuit regions are arranged above the substrate and are respectively electrically connected to the light-emitting regions to drive the light-emitting regions. The pixel circuit regions include a first color pixel circuit region electrically connected to the first color light-emitting region, a second color pixel circuit region electrically connected to the second color light-emitting region, and a third color pixel circuit region electrically connected to the third color light-emitting region.

[0425] In this case, each of the plurality of pixel circuit regions may be arranged symmetrically with respect to each line region. In addition, as the pixel circuit region extends away from the center of each line region, each pixel circuit region may have a narrower shape. Specifically, the first color pixel circuit region may be arranged symmetrically with respect to the second color pixel circuit region and the third color pixel circuit region around the corresponding line region.

[0426] For example, the second color light emitting area G12 may be symmetrically arranged around the second column line area CLA2. In addition, the first color pixel circuit area R11_PCA and the second color pixel circuit area G12_PCA may be symmetrically arranged with each other around the second column line area CLA2.

[0427] Specifically, as the first color pixel circuit area R11_PCA extends away from the center of the second column line area CLA2 in the left direction, the first color pixel circuit area R11_PCA has a narrowing shape. As the second color pixel circuit area extends away from the center of the second column line area CLA2 in the right direction, the second color pixel circuit area G12_PCA may have a narrowing shape.

[0428] In this manner, the first color pixel circuit area R12_PCA and the third color pixel circuit area B13_PCA may be arranged symmetrically to each other around the third column line area CLA3.

[0429] In addition, the first color pixel circuit area may overlap at least partial areas of the first color light emitting area and the second color light emitting area, and may overlap at least partial areas of the first color light emitting area and the third color light emitting area.

[0430] The second color pixel circuit area may overlap at least a portion of the first color light emitting area and the second color light emitting area. The third color pixel circuit area may overlap at least a portion of the first color light emitting area and the third color light emitting area.

[0431] The arrangement of the pixel circuit area is due to the arrangement of the light-emitting area and the transmission area. As the light-emitting area extends away from the center of the corresponding line area, the light-emitting area becomes narrower. Therefore, the pixel circuit area is arranged in the light-emitting area so as not to overlap with the transmission area, thereby not reducing the transmittance of the display area.

[0432] Therefore, according to the present disclosure, the VSS voltage connection line and the VDD voltage connection line are alternately arranged in adjacent line areas within the display area. Each pixel circuit area connected to each light-emitting area corresponding to each color has a symmetrical structure. Therefore, a new pixel arrangement structure that can maximize the area of ​​the transparent area of ​​the frame and minimize the haze value without reducing the transmittance of the display area can be achieved.

[0433] In one example, the pixel circuit region may include a driving thin film transistor, a capacitor, and a plurality of switching thin film transistors. That is, each of the first color pixel circuit region, the second color pixel circuit region, and the third color pixel circuit region may include a driving thin film transistor, a capacitor, and a plurality of switching thin film transistors.

[0434] Fig.39 Shown in the enlarged Fig.38 The K-K' region is the connection relationship between the line region and the pixel circuit region. Fig.40 A circuit diagram of the pixel circuit area is shown.

[0435] One sub-pixel may include an organic light emitting diode OLED, a driving thin film transistor DR, a plurality of switching thin film transistors T1, T2, T3, T4 and T5, and a capacitor Cst. The switching thin film transistor may include first to fifth switching thin film transistors T1, T2, T3, T4 and T5.

[0436] The organic light emitting diode OLED emits light using a current provided via the driving thin film transistor DR. The anode electrode of the organic light emitting diode OLED may be connected to the drain electrode of the driving thin film transistor DR. Its cathode electrode may be connected to a VSS voltage connection line VSS provided with a VSS power supply voltage. The VSS voltage connection line VSS may be used as a low-level voltage line to which a low-level power supply voltage is provided.

[0437] The organic light emitting diode OLED may include an anode electrode, an organic light emitting layer 223 and a cathode electrode. The organic light emitting layer 223 includes a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL). In the organic light emitting diode OLED, when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons are transferred to the light emitting layer EML via the hole injection layer (HIL) and the hole transport layer (HTL) and the electron injection layer (EIL) and the electron transport layer (ETL), respectively. Holes and electrons are combined with each other in the light emitting layer EML to emit light.

[0438] The driving thin film transistor DR is disposed between a VDD voltage connection line VDD supplied with a VDD power voltage and the organic light emitting diode OLED and adjusts current flowing from the VDD voltage connection line VDD to the organic light emitting diode OLED based on a voltage difference between a gate electrode and a source electrode.

[0439] The gate electrode of the driving thin film transistor DR may be connected to one electrode of the capacitor Cst and the second electrode of the second switching thin film transistor T2. The source electrode of the driving thin film transistor DR may be connected to the anode electrode of the organic light emitting diode OLED. The drain electrode of the driving thin film transistor DR may be connected to a VDD voltage connection line VDD. The VDD voltage connection line VDD may be used as a high-level voltage line to which a high-level power supply voltage is supplied.

[0440] The first switching thin film transistor T1 is turned on based on the first selection signal of the first scan line Scan1 to provide the voltage of the data line Vdata to the other electrode of the capacitor Cst. The gate electrode of the first switching thin film transistor T1 can be connected to the first scan line Scan1. The first electrode of the first switching thin film transistor T1 can be connected to the data line Vdata. The second electrode of the first switching thin film transistor T1 can be connected to the other electrode of the capacitor Cst.

[0441] The second switching thin film transistor T2 is turned on based on the second selection signal of the second scan line Scan2 to connect the gate electrode and the drain electrode of the driving thin film transistor DR to each other. The gate electrode of the second switching thin film transistor T2 can be connected to the second scan line Scan2. The first electrode of the second switching thin film transistor T2 can be connected to the drain electrode of the driving thin film transistor DR. The second electrode of the second switching thin film transistor T2 can be connected to the gate electrode of the driving thin film transistor DR.

[0442] The third switch thin film transistor T3 is turned on based on the light emission signal of the light emission line EM to initialize the other electrode of the capacitor Cst to a reference voltage. The gate electrode of the third switch thin film transistor T3 may be connected to the light emission line EM. The first electrode of the third switch thin film transistor T3 may be connected to the other electrode of the capacitor Cst. The second electrode of the third switch thin film transistor T3 may be connected to a reference voltage connection line Vref provided with a reference voltage.

[0443] The fourth switching thin film transistor T4 is turned on based on the light emission signal of the light emission line EM to connect the drain electrode of the driving thin film transistor DR and the anode electrode of the organic light emitting diode OLED to each other. The gate electrode of the fourth switching thin film transistor T4 can be connected to the light emission line EM. The first electrode of the fourth switching thin film transistor T4 can be connected to the drain electrode of the driving thin film transistor DR. The second electrode of the fourth switching thin film transistor T4 can be connected to the anode electrode of the organic light emitting diode OLED.

[0444] The fifth switch thin film transistor T5 is turned on based on the second selection signal of the second scan line Scan2 to initialize the anode electrode of the organic light emitting diode OLED to the reference voltage. The gate electrode of the fifth switch thin film transistor T5 can be connected to the second scan line Scan2. The first electrode of the fifth switch thin film transistor T5 can be connected to the anode electrode of the organic light emitting diode OLED. The second electrode of the fifth switch thin film transistor T5 can be connected to the reference voltage connection line Vref.

[0445] A first electrode of each of the first to fifth switching thin film transistors T1 , T2 , T3 , T4 , and T5 may function as a source electrode, and a second electrode thereof may function as a drain electrode. However, the present disclosure is not limited thereto.

[0446] The capacitor Cst is formed between the gate electrode of the driving thin film transistor DR and the second electrode of the first switching thin film transistor T1. The capacitor Cst stores therein a voltage difference between the voltage of the gate electrode of the driving thin film transistor DR and the voltage of the second electrode of the first switching thin film transistor T1.

[0447] One electrode of the capacitor Cst may be connected to the gate electrode of the driving thin film transistor DR and the second electrode of the second switching thin film transistor T2 , and the other electrode of the capacitor Cst may be connected to the second electrode of the first switching thin film transistor T1 and the first electrode of the third switching thin film transistor T3 .

[0448] In one embodiment of the present disclosure, an example has been described in which each of the driving thin film transistor DR and the first to fifth switching thin film transistors T1, T2, T3, T4, and T5 can be implemented as a P-type MOSFET (metal oxide semiconductor field effect) transistor. However, the present disclosure is not limited thereto. Each of the driving thin film transistor DR and the first to fifth switching thin film transistors T1, T2, T3, T4, and T5 can be implemented as an N-type MOSFET (metal oxide semiconductor field effect) transistor.

[0449] In one example, the driving thin film transistor DR included in the pixel circuit region connected to the first color sub-pixel may at least partially overlap the second color light emitting region of the second color sub-pixel or the third light emitting region of the third color sub-pixel.

[0450] For example, Fig.38As shown, the first color pixel circuit region R11_PCA connected to the first color sub-pixel R11_SP may at least partially overlap with the second color emission region G12 of the second color sub-pixel G12_SP disposed on the right side of the first color sub-pixel R11_SP. Specifically, the driving thin film transistor DR included in the first color pixel circuit region R11_PCA may at least partially overlap with the second color emission region G12.

[0451] In addition, the pixel circuit regions may be arranged symmetrically with respect to one another around one line region. In this case, one pixel circuit region including a driving thin film transistor DR driving a light emitting region at least partially overlapping with the line region may be provided on one side of the line region. Another pixel circuit region may be provided on the other side of the line region, the other pixel circuit region being associated with a color different from that of the one pixel region and including a driving thin film transistor DR driving a corresponding line region and a light emitting region between the line regions adjacent thereto.

[0452] That is, a driving thin film transistor driving a light emitting area at least partially overlapping the line area can be arranged on one side of the line area, and a driving thin film transistor driving a light emitting area between the line area and an adjacent line area can be arranged on the other side of the line area.

[0453] For example, the line area CLA2 at least partially overlaps the second color light emitting area G12. The first color pixel circuit area R11_PCA and the second color pixel circuit area G12_PCA may be arranged symmetrically to each other at one side of the line area CLA2.

[0454] Therefore, a driving thin film transistor driving the second color emission region G12 at least partially overlapping the line region CLA2 may be disposed on one side of the line region CLA2. A driving thin film transistor driving the emission region R11 between the line region CLA2 and the adjacent line region CLA1 may be disposed on the other side of the line region CLA2.

[0455] Figure 41 to Figure 43 They are shown respectively Fig.38 Cross-sectional views of the L-L', M-M' and N-N' regions.

[0456] like Fig.41 As shown, the buffer layer 20 , the gate insulating layer 213 , the first interlayer insulating layer 215 , the second interlayer insulating layer 216 , and the passivation layer 218 may be sequentially stacked in this order over the first substrate 200 .

[0457] A line region including two reference voltage connection lines 343 spaced apart from each other and symmetrically arranged around the VDD voltage connection line 333 and two data lines 313 spaced apart from each other and symmetrically arranged around the VDD voltage connection line 333 may be provided on the passivation layer 218. The VDD voltage connection line 333 may be thicker than each of the reference voltage connection line 343 and the data line 313.

[0458] The planarization layer 219 may be disposed on the line region. The organic light emitting element OLED 220 composed of the first electrode 221, the organic light emitting layer 223, and the second electrode 225 may be disposed on the planarization layer 219. In this case, a bank layer 231 is formed between the first electrode 221 and the organic light emitting layer 223.

[0459] The encapsulation layer 250 is formed on the second electrode 225. An adhesive layer 251 made of OCR (optically clear adhesive) may be formed on the encapsulation layer 250. A color filter CF may be formed on the adhesive layer 251. The color filter CF may extend to the boundary between the transmission area TA and the emission area EA, so that the color filter CF may be formed in the non-transmission area NTA area. Therefore, the area where the color filter CF is formed may be defined as an area corresponding to the emission area. The top substrate may be adhered to the color filter CF as a second substrate 270.

[0460] like Fig.42 As shown, the buffer layer 201 , the gate insulating layer 213 , the first interlayer insulating layer 215 , the second interlayer insulating layer 216 , and the passivation layer 218 may be sequentially stacked in this order over the first substrate 200 .

[0461] On the passivation layer 218, a line area including two reference voltage connection lines 343 spaced apart from each other and symmetrically arranged around the VSS voltage connection line 323 and two data lines 313 spaced apart from each other and symmetrically arranged around the VSS voltage connection line 323 may be provided. In this case, the VSS voltage connection line 323 may be thicker than each of the reference voltage connection line 343 and the data line 313.

[0462] The planarization layer 219 may be disposed in the line region. Fig.41 Therefore, the repeated description thereof will be omitted.

[0463] like Fig.43 As shown, a buffer layer 201 is formed on a first substrate 200. A driving thin film transistor 210 including an active layer 212, a source electrode 217a, a drain electrode 217b and a gate electrode 214, and a capacitor Cst composed of a first capacitor electrode 204 and a second capacitor electrode 206 may be formed on the buffer layer 201.

[0464] In this case, a gate insulating layer 213 may be formed between the active layer 212 and the gate electrode 214 and the first capacitor electrode 204. A first interlayer insulating layer 215 may be formed on the gate electrode 214 and the first capacitor electrode 204, and a second capacitor electrode 206 may be formed on the first interlayer insulating layer 215.

[0465] A second interlayer insulating layer 216 may be formed on the second capacitor electrode 206. A source electrode 217a and a drain electrode 217b may be formed on the second interlayer insulating layer 216. A passivation layer 218 may extend over the capacitor Cst and the driving thin film transistor 210. A planarization layer 219 may be formed on the passivation layer 218.

[0466] On the planarization layer 219, an organic light emitting element 220 including a first electrode 221, an organic light emitting layer 223, and a second electrode 225 may be provided. In this case, a bank layer 231 may be formed between the first electrode 221 and the organic light emitting layer 223.

[0467] An encapsulation layer 250 may be formed on the second electrode 225. An adhesive layer 251 made of OCR (Optically Clear Adhesive) may be formed on the encapsulation layer 250. A color filter CF may be formed on the adhesive layer 251. A top substrate as a second substrate 270 may be adhered to the color filter CF.

[0468] Hereinafter, another embodiment according to the present disclosure will be described in detail, in which the occurrence of non-uniformity in brightness in a display panel can be minimized by introducing an auxiliary electrode region that can reduce the resistance of a transparent electrode.

[0469] like Fig.44 and Fig.45 As shown, the transparent display panel includes a display area and a non-display area. The display area includes a plurality of light emitting areas, a plurality of transmission areas TA, a plurality of line areas CLA arranged in one direction and spaced apart from each other, and a plurality of auxiliary electrode areas AE arranged on the line areas CLA.

[0470] The light emitting area includes a first color light emitting area Rij, a second color light emitting area Gij, and a third color light emitting area Bij. Each of the second color light emitting area Gij and the third color light emitting area Bij may be disposed on a corresponding line area CLA.

[0471] The first color light emitting region Rij may be disposed between the second color light emitting region Gij and the third color light emitting region Bij, which are respectively disposed on different line regions CLA. The auxiliary electrode region AE may be disposed between the second color light emitting region Gij and the third color light emitting region Bij on the same line region CLA. The light emitting region may include an organic light emitting element 220, which includes a first electrode 221, an organic light emitting layer 223, and a second electrode 225.

[0472] The first electrode 221 may include at least one of a transparent conductive material such as indium tin oxide (ITO), antimony tin oxide (ATO), and indium zinc oxide (IZO).

[0473] Since the organic light emitting layer 223 is made of a low organic material with a low step coverage, the organic light emitting layer 223 has a low diffraction characteristic. Therefore, when the organic light emitting layer 223 is formed using a deposition process, the organic light emitting layer 223 may not penetrate well into the bottom surface of the step that is not exposed to the outside. Therefore, the organic light emitting layer 223 can be formed using a vapor deposition process such as a vapor deposition method that has good linearity for the vapor deposition object material.

[0474] The second electrode 225 may include at least one of a transparent conductive material such as indium tin oxide (ITO), Mg:Ag, Ca—Ag, and indium zinc oxide (IZO).

[0475] In particular, indium zinc oxide (IZO) is a material with high step coverage and has high diffraction characteristics. Therefore, when the second electrode 225 made of IZO is formed through a vapor deposition process, the second electrode 225 can penetrate well under the step that is not exposed to the outside.

[0476] Each of the plurality of line areas CLA extends in a vertical direction of the display area. Adjacent line areas CLA arranged alternately include a VSS voltage connection line 323 and a VDD voltage connection line 333, respectively.

[0477] The auxiliary electrode area AE is disposed on the line area CLA including the VSS voltage connection line 323 .

[0478] Specifically, the auxiliary electrode area AE includes: an auxiliary electrode 221a electrically connected to the VSS voltage connection line 323; a partition wall 241 disposed on the auxiliary electrode 221a, wherein a width W4 of a top surface of the partition wall 241 is greater than a width W5 of a bottom surface thereof; and an electrode contact EC consisting of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 directly contacting each other. The auxiliary electrode 221a and the first electrode 221 may be made of the same material and may constitute the same layer.

[0479] For example, when the first electrode 221 is used as an anode electrode, the auxiliary electrode 221a may be formed through the same patterning process as that used to form the anode electrode. Therefore, the auxiliary electrode 221a may be spaced apart from the anode electrode.

[0480] The auxiliary electrode 221a serves as a bridge electrode electrically connecting the second electrode 225 to the VSS voltage connection line 323 in the display area. Therefore, the auxiliary electrode 221a is formed on the VSS voltage connection line 323 and contacts and is electrically connected thereto.

[0481] In other words, in an embodiment of the present disclosure, the VSS voltage connection line 323 is disposed in the display region. Therefore, the auxiliary electrode 221a and the VSS voltage connection line 323 may contact each other in the display region. Therefore, a contact hole may be formed in the passivation layer 218 covering the VSS voltage connection line 323. The auxiliary electrode 221a and the VSS voltage connection line 323 may be electrically connected to each other via the contact hole.

[0482] On the auxiliary electrode 221a, a bank layer 231 may be provided. The bank layer 231 may extend along a boundary between the line area CLA and the transmission area TA. The bank layer 231 may be patterned to cover each of the two ends of the auxiliary electrode 221a. Therefore, a portion of the auxiliary electrode 221a not covered by the bank layer 231 may be exposed to the outside.

[0483] The boundary portion of the bank layer 231, which is extended to cover each of the two ends of the auxiliary electrode 221a, may serve as a boundary between the non-transmission area NTA and the transmission area TA. Therefore, the auxiliary electrode 221a may be formed to correspond to the line area CLA, and thus may be arranged in the non-transmission area NTA. For example, the auxiliary electrode 221a may be formed to correspond to the distal end of each of the pair of data lines 313. However, the present disclosure is not limited thereto.

[0484] A partition wall 241 may be formed on a portion of the auxiliary electrode 221a between the adjacent bank layers 231 that respectively cover both ends of the auxiliary electrode 221a. A width W4 of the top surface of the partition wall 241 is greater than a width W5 of the bottom surface. Therefore, the partition wall 241 may have an inverted tapered shape. However, the present disclosure is not limited thereto. The partition wall 241 may be disposed on the auxiliary electrode 221a and may contact the auxiliary electrode 221a.

[0485] Since the width W4 of the top surface of the partition wall 241 is greater than the width W5 of the bottom surface of the partition wall 241, the top surface of the partition wall 241 serves as a kind of eaves. Therefore, the auxiliary electrode 221a disposed below the partition wall 241 may have a region as shown below, in which the auxiliary electrode 221a overlaps with the top surface of the partition wall 241 serving as an eaves but does not contact the partition wall 241. The auxiliary electrode 221a and the second electrode 225 directly contact each other in this region to form an electrode contact EC.

[0486] That is, the electrode contact EC consisting of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 that are in direct contact with each other is disposed inside the region of the partition wall 241. In other words, the electrode contact EC is disposed in a region that is further inside than the end of the partition wall 241, so that the electrode contact EC is disposed inwardly than the end of the partition wall 241. Therefore, the electrode contact EC overlaps the top surface of the partition wall 241 and is located below the partition wall 241.

[0487] Specifically, the partition wall 241 includes a first partition wall structure 241 a and a second partition wall structure 241 b stacked on the first partition wall structure 241 a .

[0488] Therefore, the electrode contact EC is disposed in a region between one distal end of the first partition wall structure 241a and one distal end of the second partition wall structure 241b. Specifically, the electrode contact EC is located in a portion of this region where the auxiliary electrode 221a is exposed to the outside.

[0489] The first partition wall structure 241a may be in contact with the auxiliary electrode 221a, and the second partition wall structure 241b may be spaced apart from the auxiliary electrode 221a. In addition, the first partition wall structure 241a may overlap with the second partition wall structure 241b, and may be arranged inside the region of the second partition wall structure 241b. In other words, the first partition wall structure 241a is arranged in a region further inside than the end of the second partition wall structure 241b, so that the first partition wall structure 241a is arranged inwardly than the end of the second partition wall structure 241b.

[0490] The bottom surface of the first partition wall structure 241a serves as the bottom surface of the partition wall 241, and the top surface of the second partition wall structure 241b serves as the top surface of the partition wall 241. The first partition wall structure 241a and the bank layer 231 may be made of the same material and may constitute the same layer. The first partition wall structure 241a may be formed to be spaced apart from the bank layer 231 covering each of the two ends of the auxiliary electrode 221a.

[0491] Therefore, the bank layer 231 may not exist in a region between the first partition wall structure 241a and each of the bank layers 231 covering both ends of the auxiliary electrode 221a, respectively. Therefore, this region may serve as an opening region BO of the bank layer exposing the auxiliary electrode 221a to the outside.

[0492] In this case, the distal end of the second partition wall structure 241b, that is, the eaves of the second partition wall structure 241b may not overlap with the bank layer 231 disposed on each of both ends of the partition wall 241, thereby increasing the area of ​​the opening region BO of the bank layer as much as possible.

[0493] In this case, it is preferred that the eaves of the second partition wall structure 241b coincide with or be spaced apart from the boundary of the bank 231. That is, it is desirable that the width of the opening region BO of the bank is at least equal to or greater than the width of the electrode contact EC.

[0494] In particular, when the eaves of the second partition wall structure 241b coincide with the boundary of the bank layer 231, the resistance of the second electrode can be reduced while the area of ​​the transmission region can be ensured as much as possible.

[0495] Therefore, when the eaves of the second partition wall structure 241b do not overlap with the bank layer 231 or are spaced apart from the bank layer 231 by a certain distance, the area of ​​the electrode contact EC consisting of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 in direct contact with each other can be ensured as much as possible.

[0496] The first partition wall structure 241a may be patterned using the same mask process as that used to form the bank layer 231. The first partition wall structure 241a may have the same shape as the bank layer 231. However, the present disclosure is not limited thereto.

[0497] The first partition wall structure 241a may have a non-inverse tapered shape in which the first partition wall structure 241a gradually narrows as the first partition wall structure 241a extends upward. The side of the first partition wall structure 241a may be gently curved.

[0498] The second partition wall structure 241b may be made of a photoresist material. For example, the second partition wall structure 241b may be made of a negative photoresist material. However, the present disclosure is not limited thereto.

[0499] The second partition wall structure 241b may have an inverted tapered shape in which the second partition wall structure 241b gradually narrows as the second partition wall structure 241b extends downward. A side surface of the second partition wall structure 241b may be gently curved.

[0500] For example, when the second partition wall structure 241 b is made of a negative photoresist material, the second partition wall structure 241 b may be formed as follows.

[0501] First, a negative photoresist material is applied to cover the first partition wall structure 241a, and then a local area of ​​the material is exposed to a material such as a polymerization initiator through a mask. The area of ​​the negative photoresist exposed to the polymerization initiator is cured via a thermal curing step to form an inverted tapered shape. Then, the remaining negative photoresist except the inverted tapered shape structure is removed by a liquid chemical infiltration process, thereby forming a second partition wall structure 241b in an inverted tapered shape.

[0502] That is, although the partition wall 241 according to the embodiment of the present disclosure includes the first partition wall structure 241a having a non-inverted tapered shape and the second partition wall structure 241b having an inverted tapered shape stacked on the first partition wall structure 241a, the entire partition wall 241 may have an inverted tapered shape in which the width W4 of the top surface is greater than the width W5 of the bottom surface thereof, because the width W4 of the top surface of the second partition wall structure 241b is greater than the width W5 of the bottom surface of the first partition wall structure 241a, as shown in FIG. Fig.46A shown.

[0503] Due to the above-described shape of the partition wall 241 , the auxiliary electrode area AE includes an electrode contact EC consisting of a portion of the auxiliary electrode 221 a and a portion of the second electrode 225 that are in direct contact with each other.

[0504] Specifically, at least a portion of the removed region of the bank layer 231 in the region of the partition wall 241 may be a region of the electrode contact EC. Since the partition wall 241 has a top surface width W4 greater than its bottom surface width W5, at least a portion of the removed region of the bank layer 231 may be shielded by the top surface of the partition wall 241 and not in contact with the bottom surface of the partition wall 241, so that the auxiliary electrode 221a may be exposed to the outside.

[0505] In this manner, a portion of the auxiliary electrode 221 a , which is shielded by the top surface of the partition wall 241 but does not contact the bottom surface of the partition wall 241 , may constitute the electrode contact EC.

[0506] For example, when the organic light-emitting layer 223 and the second electrode 225 are formed over the entire display area, the auxiliary electrode 221a and the second electrode 225 may not directly contact each other because the organic light-emitting layer 223 and the second electrode 225 are sequentially stacked on the auxiliary electrode 221a exposed to the outside without the partition wall 241.

[0507] Furthermore, even in the presence of the partition wall 241, when the partition wall 241 has a non-inverted tapered shape in which the width W4 of the top surface of the partition wall 241 is smaller than the width W5 of the bottom surface thereof, the organic light emitting layer 223 and the second electrode 225 are formed and connected to each other along the partition wall 241. Therefore, the organic light emitting layer 223 and the second electrode 225 are sequentially stacked on the auxiliary electrode 221a, so that the auxiliary electrode 221a and the second electrode 225 may not directly contact each other.

[0508] However, as in one embodiment of the present disclosure, when the width W4 of the top surface of the partition wall 241 is greater than the width W5 of the bottom surface thereof, although the organic light emitting layer 223 is disposed over the entire display area, the organic light emitting layer 223 may also be discontinuous (such discontinuity may be caused by the partition wall 241). In addition, the second electrode 225 may be disposed over the entire display area, but may not be discontinuous.

[0509] This configuration is attributed to the low diffraction characteristics of the organic light emitting layer 223 and the high diffraction characteristics of the second electrode 225. Specifically, the organic light emitting layer 223 is formed by depositing a material having a low diffraction characteristic and high linearity. Therefore, the material forming the organic light emitting layer 223 cannot penetrate well into the inner region of the auxiliary electrode 221a shielded by the top surface of the partition wall 241 used as an eave, so that the organic light emitting layer 223 may not be formed.

[0510] Therefore, the organic light emitting layer 223 may be formed in an island form on the top surface of the partition wall 241. However, the organic light emitting layer 223 may not be formed on the auxiliary electrode 221a shielded by the partition wall 241. Therefore, the organic light emitting layer 223 may be discontinuous (this discontinuity may occur due to the partition wall 241).

[0511] In contrast, the second electrode 225 is formed by depositing a material having high diffraction characteristics such as IZO. Therefore, the material forming the second electrode 225 can well penetrate into the inner region of the auxiliary electrode 221a shielded by the top surface of the partition wall 241 used as an eave, so that the second electrode 225 can be formed.

[0512] In particular, the second electrode 225 may be made of a material having high diffraction characteristics and thus may penetrate into the region of the partition wall 241 and cover the side of the partition wall 241. Therefore, the second electrode 225 may be deposited to surround the partition wall 241, and thus the second electrode 225 may not be discontinuous.

[0513] In one example, if Fig.46BAs shown, in the region where the first partition wall structure 241a and the second partition wall structure 241b contact each other, the bottom surface of the second partition wall structure 241b can extend toward the top surface of the second partition wall structure 241b in an upwardly inclined manner. Therefore, the path of the second electrode 225 surrounding the partition wall 241 can be longer, and the second electrode 225 can be continuous.

[0514] In addition, each side surface of the first and second partition wall structures 241 a and 241 b may be gently curved, thereby preventing the second electrode 225 surrounding the partition wall 241 from becoming discontinuous.

[0515] As described above, according to an embodiment of the present disclosure, the second electrode surrounding the partition wall can have a longer path and can be continuous. Therefore, compared with the case where the second electrode is discontinuous, its contact area with the auxiliary electrode can be larger. Therefore, the effect of reducing brightness unevenness can be more effectively achieved by reducing the resistance of the second electrode.

[0516] like Fig.45 As shown, an example is described in which the second electrode 225 is deposited to surround the partition wall 241 and the second electrode 225 is not discontinuous. However, the present disclosure is not limited thereto. The second electrode 225 may be discontinuous due to the partition wall 241.

[0517] Although the second electrode 225 is discontinuous due to the partition wall 241, because the second electrode 225 has better diffraction than the organic light-emitting layer 223 and therefore penetrates deeply into the area of ​​the partition wall 241, an electrode contact EC consisting of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 in direct contact with each other can be formed.

[0518] Therefore, the organic light emitting layer 223 may not exist on at least a portion of a region where the auxiliary electrode 221a overlaps with the partition wall 241 but does not contact the partition wall 241, specifically, on a portion where a portion of the auxiliary electrode 221a is close to a bottom surface of the partition wall 241. An electrode contact EC consisting of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 in direct contact with each other may be formed.

[0519] In this manner, the second electrode 225 contacts the auxiliary electrode 221 a via the electrode contact EC, and the auxiliary electrode 221 a is electrically connected to and contacts the VSS voltage connection line 323. As a result, the second electrode 225 may be electrically connected to the VSS voltage connection line 323.

[0520] As described above, when the second electrode 225 is used as a transparent electrode with high surface resistance, the difference between the rising values ​​of the low-level voltage VSS at various positions of the display panel increases. As a result, brightness non-uniformity occurs in the display panel, which may cause a problem of deterioration of display quality.

[0521] However, as in one embodiment of the present disclosure, the auxiliary electrode region AE including the partition wall 241 whose top surface width W4 is greater than the bottom surface width W5 is disposed on the line region CLA in the display region. The second electrode 225 of the organic light emitting element 220 and the VSS voltage connection line 323 may be electrically connected to each other via the auxiliary electrode 221a, thereby reducing the resistance of the second electrode 225 as a transparent electrode.

[0522] In addition, as in one embodiment of the present disclosure, a partition wall 241 whose top surface width W4 is greater than the bottom surface width W5 is included in the auxiliary electrode region AE. Therefore, even in the presence of the partition wall 241, the organic light emitting layer 223 may be discontinuous, and the second electrode 225 may be prevented from being discontinuous. Therefore, a separate mask process is not required, thereby increasing process efficiency.

[0523] In one example, it is preferred that the organic light emitting layer 223 is not formed on a portion of the auxiliary electrode 221a shielded by the top surface of the partition wall 241. However, the organic light emitting layer 223 may penetrate into a portion of the partition wall 241 and thus be formed on the auxiliary electrode 221a.

[0524] This may be caused by a design error or other process error of the partition wall 241. In addition, this may occur because the material forming the organic light emitting layer 223 has a low diffraction characteristic.

[0525] Therefore, when the organic light emitting layer 223 penetrates to a portion of the region of the partition wall 241 and is formed on the auxiliary electrode 221a, the area of ​​the electrode contact EC is reduced as much as the area where the organic light emitting layer 223 is formed. Therefore, the contact area between the auxiliary electrode 221a and the second electrode 225 can be reduced.

[0526] When the area of ​​the electrode contact EC is reduced, the resistance of the second electrode 225 is correspondingly increased. Therefore, it may be difficult to minimize the brightness non-uniformity of the entire panel area.

[0527] Therefore, when introducing a partition wall 241 in which a second partition wall structure 241b is stacked on the first partition wall structure 241a as part of the bank layer 231 and separated from the auxiliary electrode 221a, the area of ​​the electrode contact EC can be further increased, further reducing the resistance of the second electrode 225 as a transparent electrode.

[0528] For example, Fig.47A A region of the electrode contact EC that may be formed when the partition wall 241 of a single layer having an inverse tapered shape is formed is shown. Fig.47B As one embodiment of the present disclosure, a region where an electrode contact EC may be formed when the partition wall 241 includes a stack of a first partition wall structure and a second partition wall structure in an inverse tapered shape.

[0529] like Fig.47A As shown, when the partition wall 241 has an inverted tapered shape but is formed of a single layer, the area where the partition wall 241 contacts the auxiliary electrode 221a increases. Therefore, the area of ​​the auxiliary electrode 221a that is shielded by the top surface of the partition wall 241 but exposed to the outside may not be large. Therefore, the area of ​​the electrode contact EC composed of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 that are in direct contact with each other and disposed inside the region of the partition wall 241 may not be large.

[0530] However, if Fig.47B As shown, when the partition wall 241 is formed by stacking the second partition wall structure 241b in an inverted tapered shape on the first partition wall structure 241a, only the first partition wall structure 241a contacts the auxiliary electrode 221a, and the second partition wall structure 241b is spaced apart from the auxiliary electrode 221a. Therefore, the area of ​​the auxiliary electrode 221a that is shielded by the top surface of the partition wall 241 but exposed to the outside can be larger. As a result, the area of ​​the electrode contact EC composed of a portion of the auxiliary electrode 221a and a portion of the second electrode 225 that are in direct contact with each other and disposed inside the region of the partition wall 241 can be larger.

[0531] That is, assuming Fig.47A The dimensions of the partition wall 241 shown are similar to Fig.47B The sizes of the second partition wall structures 241 b shown are the same, and when the partition wall 241 is formed by stacking the second partition wall structure 241 b having an inverse tapered shape on the first partition wall structure 241 a , the area of ​​the electrode contact EC may be increased.

[0532] Therefore, as in an embodiment of the present disclosure, when a partition wall 241 is introduced in which a second partition wall structure 241b is stacked on the first partition wall structure 241a as a part of the bank layer 231 and is spaced apart from the auxiliary electrode 221a, the area of ​​the electrode contact EC can be further increased, further reducing the resistance of the second electrode 225. In addition, the size of the partition wall 241 can be reduced to improve transmittance.

[0533] In addition, according to an embodiment of the present disclosure, the auxiliary electrode area AE is formed on each of the plurality of line areas CLA that respectively include the VSS voltage connection line 323 extending across the display area. Therefore, the electrical connection between the VSS voltage connection line 323 and the auxiliary electrode 221a can occur within the display area. Therefore, the current can be supplied to each pixel in the display area in a smooth manner. Therefore, the brightness distribution across the panel can be made more uniform.

[0534] For example, when the VSS voltage connection line 323 is not disposed in the display area but surrounds the display area like a frame of the non-display area, electrical connection of the VSS voltage connection line 323 and the auxiliary electrode 221 a may occur in the non-display area.

[0535] In particular, in a large-area transparent display device, a difference between a VSS voltage supplied to a pixel near the VSS voltage connection line 323 and a VSS voltage supplied to a pixel in a central portion of a display area away from the VSS voltage connection line 323 may be large. Therefore, a difference between rising values ​​of the low-level voltage VSS at positions of the display panel may increase.

[0536] However, as in one embodiment of the present disclosure, each of the plurality of line areas CLA including the VSS voltage connection line 323 may extend across the display area. In this case, the change in the distance between the plurality of pixels existing in the display panel and the VSS voltage connection line 323 may be small. Therefore, the difference between the rising values ​​of the low-level voltage VSS at the position of the display panel may be reduced.

[0537] In addition, the partition wall 241 of the auxiliary electrode area AE may be used as a spacer. Therefore, a process of forming a separate spacer and a separate area for forming the spacer are not required, thereby achieving high process efficiency and panel space utilization.

[0538] Fig.48A and Fig.48B ΔVSS values ​​are shown in the case where the partition wall 241 is present and in the case where the partition wall 241 is not present. Specifically, Fig.48A and Fig.48B The measurement of the low level voltage VSS of the pixels of the panel based on the horizontal pixel number of the panel×the vertical pixel number of the panel of 1440×540 is shown.

[0539] like Fig.48A As shown in FIG. 1 , when there is no partition wall, the difference ΔVSS between the maximum value and the minimum value of the low-level voltage is measured to be 1.0161 V. On the other hand, as Fig.48B As shown, when the partition wall is present, the difference ΔVSS=0.2084V between the maximum value and the minimum value of the low-level voltage is measured.

[0540] Therefore, it can be seen that when the partition wall exists, the difference between the rising values ​​of the low-level voltage VSS at the positions of the panel is significantly smaller than when the partition wall does not exist, thereby minimizing the brightness unevenness.

[0541] Fig.49A The changes in the area and resistance of the electrode contact according to the width of the partition wall are shown.

[0542] like Fig.49A As shown, the electrode contact area increases as the width of the top surface of the partition wall increases. Therefore, the resistance of the second electrode decreases. In other words, the electrode contact area and the resistance of the second electrode are inversely proportional to each other. Therefore, increasing the width of the top surface of the partition wall can allow maximizing the electrode contact area, so that the resistance of the second electrode is reduced.

[0543] Fig.49B The change in the area and resistance of the electrode contact depending on the size of the opening region BO of the bank layer is shown.

[0544] As in Fig.49B As can be seen in FIG. 1 , the area of ​​the electrode contact increases as the width of the opening region of the bank layer increases. Therefore, the resistance of the second electrode decreases.

[0545] In particular, in a portion where the width of the opening area of ​​the bank layer is less than or equal to a certain width, specifically, in a portion where the width of the opening area of ​​the bank layer is 1.75 μm or less, the area of ​​the electrode contact increases rapidly. Therefore, the resistance of the second electrode decreases. In this portion, the eaves of the partition wall begin to overlap at least partially with the bank layer, so that the width of the opening area of ​​the bank layer becomes smaller than the width of the electrode contact. Therefore, the area of ​​the electrode contact can be reduced accordingly.

[0546] However, in the portion where the width of the opening area of ​​the bank layer is 1.75 μm or more, that is, in the portion where the eaves of the partition wall do not overlap the bank layer, the area of ​​electrode contact increases as the width of the opening area of ​​the bank layer increases. Therefore, the resistance of the second electrode decreases accordingly.

[0547] In one example, in a portion where the width of the opening region of the bank layer is 3.75 μm or more, the area of ​​electrode contact no longer increases and becomes constant. Therefore, in order to ensure as much transmission area as possible, it is desirable to set the width of the opening region of the bank layer to 3.75 μm or less.

[0548] The present disclosure may include the following aspects and implementations.

[0549] A first aspect of the present disclosure provides a transparent display panel, which includes a display area and a non-display area, wherein the display area includes: a plurality of light-emitting areas; a plurality of transmission areas; a plurality of line areas spaced apart from each other, each line area extending in one direction; and a plurality of auxiliary electrode areas arranged on corresponding line areas; wherein the light-emitting area includes an organic light-emitting element, the organic light-emitting element includes a first electrode, an organic light-emitting layer, and a second electrode, wherein at least one line area includes a VSS voltage connection line, wherein the auxiliary electrode area is arranged on the line area including the VSS voltage connection line, wherein the auxiliary electrode area includes: an auxiliary electrode electrically connected to the VSS voltage connection line; a partition wall arranged on the auxiliary electrode, wherein the width of the top surface of the partition wall is greater than the width of the bottom surface thereof; and an electrode contact, which is composed of a portion of the auxiliary electrode and a portion of the second electrode that are in direct contact with each other, wherein the electrode contact is arranged inwardly than an end of the partition wall.

[0550] In an implementation of the first aspect, the light-emitting area includes a first color light-emitting area, a second color light-emitting area and a third color light-emitting area, wherein the second color light-emitting area and each of the second color light-emitting areas are arranged on a corresponding line area, wherein the first color light-emitting area is arranged between the second color light-emitting area and the third color light-emitting area respectively arranged on different line areas, and wherein the auxiliary electrode area is arranged between the second color light-emitting area and the third color light-emitting area arranged on the same line area.

[0551] In an implementation of the first aspect, the second electrode is made of indium zinc oxide (IZO).

[0552] In an implementation of the first aspect, the partition wall includes a first partition wall structure and a second partition wall structure stacked on the first partition wall structure, wherein the first partition wall structure is in contact with the auxiliary electrode, and wherein the second partition wall structure is spaced apart from the auxiliary electrode.

[0553] In an implementation of the first aspect, a side surface of the second partition wall structure is curved.

[0554] In an implementation of the first aspect, in a region where the first partition wall structure contacts the second partition wall structure, a bottom surface of the second partition wall structure extends toward a top surface of the second partition wall structure in an upwardly inclined manner.

[0555] In an implementation of the first aspect, the first partition wall structure overlaps the second partition wall structure and is disposed inwardly of an end portion of the second partition wall structure.

[0556] In an implementation of the first aspect, the transparent display panel further includes a bank layer extending along a boundary between the line area and the transmission area, wherein the first partition wall structure and the bank layer are made of the same material and constitute the same layer.

[0557] In an implementation of the first aspect, the second partition wall structure and the bank layer do not overlap each other.

[0558] In an implementation manner of the first aspect, the auxiliary electrode and the first electrode are made of the same material and constitute the same layer.

[0559] In an implementation of the first aspect, the transparent display panel further includes: a first VSS voltage line and a second VSS voltage line disposed in the non-display area and interposing the display area therebetween, wherein the VSS voltage connection line electrically connects the first VSS voltage line and the second VSS voltage line to each other.

[0560] In an implementation of the first aspect, the electrode contact is a region between an end portion of one side of the first partition wall structure and an end portion of one side of the second partition wall structure.

[0561] A second aspect of the present disclosure provides a transparent display device comprising: a transparent display panel as defined above; a data driver that provides a data voltage to the transparent display panel; a gate driver that provides a scan signal to the transparent display panel; and a timing controller that controls the gate driver and the data driver.

[0562] As described above, the present disclosure is described with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments and drawings disclosed in this specification. It will be apparent that various modifications may be made thereto by those skilled in the art within the scope of the present disclosure. In addition, although the effects caused by the features of the present disclosure are not explicitly described in the description of the embodiments of the present disclosure, it is apparent that the predictable effects caused by the features of the present disclosure should be recognized.

Claims

1. A transparent display panel, comprising a display area and a non-display area, wherein: The display area includes: Multiple light-emitting areas; a plurality of transmissive regions; and a plurality of line regions, the plurality of line regions being spaced apart from each other, each line region extending in one direction, The light-emitting region includes an organic light-emitting element, and the organic light-emitting element includes a first electrode, an organic light-emitting layer, and a second electrode. wherein at least one of the line areas comprises a VSS voltage connection line, wherein the auxiliary electrode region is disposed above the line region including the VSS voltage connection line, Wherein, the auxiliary electrode region includes: an auxiliary electrode, the auxiliary electrode being electrically connected to the VSS voltage connection line; a partition wall disposed on the auxiliary electrode, wherein a width of a top surface of the partition wall is greater than a width of a bottom surface of the partition wall; and an electrode contact, the electrode contact consisting of a portion of the auxiliary electrode and a portion of the second electrode, the portion of the auxiliary electrode and the portion of the second electrode being in contact with each other and electrically connected to each other, wherein the electrode contact is disposed inwardly of an end portion of the partition wall, The light-emitting area includes a first color light-emitting area, a second color light-emitting area and a third color light-emitting area. wherein each of the second color light emitting area and the third color light emitting area is disposed above a corresponding line area, and The auxiliary electrode region is arranged between the second color light emitting region and the third color light emitting region which are arranged above the same line region.

2. The transparent display panel according to claim 1, wherein: The organic light emitting layer is formed of a material having a diffraction characteristic higher than a diffraction characteristic of the second electrode.

3. The transparent display panel according to claim 1, wherein: The first color light emitting area is disposed between the second color light emitting area and the third color light emitting area which are respectively disposed over different line areas.

4. The transparent display panel according to claim 1, wherein: The second electrode is made of indium zinc oxide IZO.

5. The transparent display panel according to claim 1, wherein: The partition wall includes a first partition wall structure and a second partition wall structure stacked on the first partition wall structure, wherein the first partition wall structure is in contact with the auxiliary electrode, Wherein, the second partition wall structure is spaced apart from the auxiliary electrode.

6. The transparent display panel according to claim 5, wherein: A width of a top surface of the second partition wall structure is greater than a width of a bottom surface of the first partition wall structure.

7. The transparent display panel according to claim 5, wherein: The first partition wall structure has a non-inverse tapered shape in which the first partition wall structure gradually narrows as the first partition wall structure extends upward.

8. The transparent display panel according to claim 5, wherein: The second partition wall structure has an inverse tapered shape in which the second partition wall structure gradually narrows as the second partition wall structure extends downward.

9. The transparent display panel according to claim 5, wherein: The side surfaces of the second partition wall structure are curved.

10. The transparent display panel according to claim 5, wherein: In a region where the first partition wall structure contacts the second partition wall structure, a bottom surface of the second partition wall structure extends in an upwardly inclined manner toward a top surface of the second partition wall structure.

11. The transparent display panel according to claim 5, wherein: The first partition wall structure overlaps the second partition wall structure and is disposed inwardly of an end portion of the second partition wall structure.

12. The transparent display panel according to claim 5, wherein: The transparent display panel further includes a bank layer extending along a boundary between the line area and the transmission area. The first partition wall structure and the bank layer are made of the same material and constitute the same layer.

13. The transparent display panel according to claim 12, wherein: The bank layer has an opening region, and the auxiliary electrode is exposed to the outside in the opening region.

14. The transparent display panel according to claim 13, wherein: The width of the opening region is in the range from 1.75 μm to 3.75 μm.

15. The transparent display panel according to claim 13, wherein: The second partition wall structure and the bank layer do not overlap each other.

16. The transparent display panel according to claim 1, wherein: The auxiliary electrode and the first electrode are made of the same material and constitute the same layer.

17. The transparent display panel according to claim 1, wherein: The transparent display panel further includes a first VSS voltage line and a second VSS voltage line, the first VSS voltage line and the second VSS voltage line are disposed in the non-display area, and the display area is interposed between the first VSS voltage line and the second VSS voltage line, and The VSS voltage connection line electrically connects the first VSS voltage line and the second VSS voltage line to each other.

18. The transparent display panel according to claim 5, wherein: The inner region of the partition wall is a region between one end portion of the first partition wall structure and one end portion of the second partition wall structure.

19. The transparent display panel according to claim 1, wherein: An outer profile of each of the plurality of transmission areas is at least partially curved.

20. A transparent display device, comprising: The transparent display panel according to any one of claims 1 to 19; a data driver, the data driver providing a data voltage to the transparent display panel; a gate driver, the gate driver providing a scan signal to the transparent display panel; as well as A timing controller controls the data driver and the gate driver.

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