A data interaction method, apparatus, terminal device, and storage medium

Abstract

This application proposes a data interaction method, apparatus, terminal device, and storage medium. The method includes: acquiring a data frame through a Management Data Input / Output (MDIO) interface; triggering a pulse signal corresponding to the data frame, wherein the pulse signal is determined by a clock signal based on an Advanced Peripheral Bus (APB) interface; and performing data interaction with the APB interface based on the pulse signal and the data frame, thereby improving the efficiency of data interaction during ATE testing.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a data interaction method, apparatus, terminal device, and storage medium. Background Technology

[0002] Integrated circuit design incorporates a variety of interface protocols, each suited to different application scenarios. Some are used for communication within the chip, typically characterized by parallel transmission and high protocol speeds. Others are used for inter-chip communication, and these protocols can be further divided into high-speed and low-speed categories. High-speed protocols are more complex, often including sophisticated fault-tolerance mechanisms or encoding formats; low-speed protocols are relatively simpler, but typically have fewer interface signals compared to on-chip communication protocols.

[0003] In the design of System-on-Chips (SoCs), multiple analog devices are often integrated, such as SerDes and Double Data Rate (DDR) physical interfaces (PHYs). These analog devices are mostly provided as configuration interfaces for the Advanced Peripheral Bus (APB) interface, used for initialization. Additionally, these analog devices require the design of necessary Automatic Test Equipment (ATE) logic to facilitate chip screening via the ATE interface after chip fabrication.

[0004] Currently, the Joint Test Action Group (JTAG) is used as the ATE interface. On-chip, the JTAG protocol is converted to the APB protocol to access the APB configuration interface of these analog devices, enabling test configuration of these analog designs. JTAG is a widely used interface protocol and is also widely used for ATE testing. However, the JTAG interface generally requires five signal lines (TCK, TRST, TMS, TDI, TDO), selecting the scan link through the Instruction Register (IR) and manipulating link data through the Data Register (DR). The protocol specification is relatively complex, making the conversion from JTAG to APB protocol relatively complex. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a data interaction method, apparatus, terminal device, and storage medium, which improves the efficiency of data interaction during ATE testing.

[0006] This application provides a data interaction method, including:

[0007] Data frames are obtained through the MDIO interface for managing data input and output.

[0008] A pulse signal is triggered corresponding to the data frame, wherein the pulse signal is determined based on a clock signal from the Advanced Peripheral Bus (APB) interface;

[0009] Based on the pulse signal and the data frame, data interaction is performed with the APB interface.

[0010] This application provides a data interaction device, including:

[0011] The acquisition module is configured to acquire data frames through the Management Data Input / Output (MDIO) interface;

[0012] The triggering module is configured to trigger a pulse signal corresponding to the data frame, wherein the pulse signal is determined based on a clock signal from the Advanced Peripheral Bus (APB) interface.

[0013] The interaction module is configured to interact with the APB interface based on the pulse signal and the data frame.

[0014] This application provides a terminal device, including:

[0015] One or more processors;

[0016] Storage device for storing one or more programs;

[0017] When the one or more programs are executed by the one or more processors, the one or more processors implement any of the methods in the embodiments of this application.

[0018] This application provides a storage medium storing a computer program, which, when executed by a processor, implements any of the methods described in this application.

[0019] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0020] Figure 1 A flowchart illustrating a data interaction method provided in this application;

[0021] Figure 1a A schematic diagram of the structure of the data interaction device for executing the data interaction method of this application;

[0022] Figure 2 A schematic diagram of the structure of a data interaction device provided in this application;

[0023] Figure 3 This is a schematic diagram of the structure of a terminal device provided in this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0025] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0026] In one exemplary implementation Figure 1 This application provides a flowchart illustrating a data interaction method applicable to the conversion from the MDIO protocol to the APB protocol. This method can be executed by the data interaction device provided in this application, which can be implemented in software and / or hardware and integrated into a terminal device. The terminal device can be a separate device implementing the MDIO protocol to APB protocol conversion, or it can be a Field Programmable Gate Array (FPGA) device.

[0027] like Figure 1 As shown, the data interaction method provided in this application includes S110, S120 and S130.

[0028] S110. Obtain data frames through the Management Data Input / Output (MDIO) interface.

[0029] A data frame can be one or more of the following: an address frame, a read data frame, and a write data frame.

[0030] After reading the data frame through the MDIO interface, this application can analyze the data frame and convert it into the APB protocol.

[0031] S120. Trigger the pulse signal corresponding to the data frame, wherein the pulse signal is determined based on the clock signal of the Advanced Peripheral Bus (APB) interface.

[0032] After reading a data frame, the corresponding pulse signal can be triggered to implement the function associated with that data frame. For example, the corresponding function can be executed on the rising edge of the pulse signal.

[0033] For example, when the data frame is a write operation frame, the pulse signal can be a write pulse signal. After the write pulse signal is triggered, the first data information included in the data frame can be written into the device corresponding to the APB interface. When the data frame is a read data frame, the pulse signal can be a read pulse signal. After the read pulse signal is triggered, the second data information can be read from the APB interface, and the address can be obtained from the data frame. When the data frame is an address frame, the pulse signal can be an address pulse. After the address pulse is triggered, the address information in the data can be stored.

[0034] When converting the MDIO protocol to the APB protocol, the trigger pulse signal can be determined based on the clock signal of the APB interface, such as using the clock signal of the APB interface as the trigger pulse signal.

[0035] S130. Based on the pulse signal and the data frame, perform data interaction with the APB interface.

[0036] This application enables data interaction between the MDIO interface and the APB interface based on data frames, triggered by a pulse signal.

[0037] Different data frames can have different data interaction methods, which are not limited here. The key is to provide the APB interface with address information and the first data information when sending a data frame read from the MDIO interface to the APB interface for write operations. Similarly, to provide the APB interface with address information when sending a data frame read from the MDIO interface to the APB interface for read operations.

[0038] Furthermore, when the data frame is a read data frame, the data sent to the APB interface may also include APB write information, that is, this information may indicate that data is currently being written to the APB interface. When the data frame is a write data frame, the data sent to the APB interface may also include APB read information, which may indicate that data is currently being read from the APB interface.

[0039] This application provides a data interaction method, which first acquires a data frame through the Management Data Input / Output (MDIO) interface; then triggers a pulse signal corresponding to the data frame, wherein the pulse signal is determined by a clock signal based on the Advanced Peripheral Bus (APB) interface; finally, based on the pulse signal and the data frame, data interaction is performed with the APB interface. This method can improve the efficiency of data interaction during ATE testing.

[0040] Based on the above embodiments, modified embodiments of the above embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in the modified embodiments.

[0041] In one embodiment, the data frame includes at least one of the following: address information, physical interface PHY identification information, DEV identification information, and first data information, wherein the first data information is information written to the APB interface.

[0042] When the data frame is an address frame, it can include address information and PHY identification information, i.e., PHY_ID. This application can store the PHY identification information and address information in a storage module so that, during read / write operations, the corresponding address information is determined based on the PHY identification information, thereby avoiding sending the address frame during read / write operations. If no address frame is sent and the address information is not latched, a default address can be selected for read / write operations. The default address information is not limited; for example, address 0 can be used as the default address.

[0043] When the data frame is a read data frame, the data frame may include PHY identification information. Based on the PHY identification information, the address information corresponding to the PHY identification information can be determined from the latched address information, and the address information is sent to the APB interface to read the data under the address information. The data is then fed back to the MDIO interface, and the data may be second data information.

[0044] When the data frame is a write data frame, the data frame may include PHY identification information and first data information. Based on the PHY identification information, the address information corresponding to the PHY identification information is read from the stored address information, and the address information and the first data information are sent to the APB interface to write the first data information to the address information of the APB interface.

[0045] In this application, the DEV identification information can be used when storing address information based on the address frame. That is, when both PHY_ID and DEV_ID are 0, the address information in the address frame is stored in correspondence with PHY_ID.

[0046] In one embodiment, the pulse signal that triggers the data frame includes:

[0047] When the data frame is a write operation frame and the write operation has ended, a write pulse signal is triggered;

[0048] When the data frame is a read operation frame and the read operation has ended, a read pulse signal is triggered;

[0049] When the data frame is an address frame and the address frame has ended, an address pulse signal is triggered.

[0050] It should be noted that the determination of whether a data frame is a write operation frame, a read operation frame, or an address frame, as well as the determination of the end of a write operation, the end of a read operation, and the end of an address frame, can be based on the MDIO protocol and is not limited here.

[0051] When the data frame is a write operation frame and the write operation has ended, a write pulse signal can trigger the write operation. The write pulse signal can be considered as the pulse signal that triggers the execution of the write operation.

[0052] When the data frame is a read operation frame and the read operation has ended, the read pulse signal can trigger the execution of the read operation. The read pulse signal can be considered as the pulse signal that triggers the execution of the read operation.

[0053] When the data frame is an address frame and the address frame has ended, triggering the address pulse signal can trigger the execution of the address latch operation. The address pulse signal can be considered as a pulse signal that triggers the storage of address information.

[0054] In one embodiment, the data interaction with the APB interface based on the pulse signal and the data frame includes:

[0055] When the PHY identifier information in the data frame is non-zero, the address information and first data information corresponding to the PHY identifier information are sent to the APB interface based on the pulse signal to update the status information of the APB interface. The pulse signal is a write pulse signal.

[0056] When the PHY identifier information in the data frame is non-zero, the address information corresponding to the PHY identifier information is sent to the APB interface based on the pulse signal, the second data information under the address information sent by the APB interface is received, and the second data information is sent to the MDIO interface. The pulse signal is a read pulse signal, and the second data information is information read from the APB interface.

[0057] When the data frame is a write operation frame and the write operation is complete, this application can trigger a write pulse signal. If the PHY identifier information in the data frame is non-zero, the address information corresponding to the PHY identifier information and the first data information in the data frame can be sent to the APB interface upon triggering the pulse signal (e.g., performing a transmit operation on the rising edge of the pulse signal). The address information corresponding to the PHY identifier information can be obtained from latched address information, such as determining the address information corresponding to the PHY identifier information from pre-stored address information. This application can store the address information in a storage module, such as the DEFAULT_SLV module. In the case of writing data, this application can also send APB write information to the APB interface to indicate that data is currently being written to the APB interface.

[0058] When the data frame is a read operation frame and the read operation is complete, this application can trigger a read pulse signal. If the PHY identifier information in the data frame is non-zero, the address information corresponding to the PHY identifier information can be sent to the APB interface under the trigger of the pulse signal. The determination of the address information is described in the write operation frame and will not be repeated here. When reading data, this application can also send APB read information to the APB interface to indicate that data is currently being written to the APB interface.

[0059] After sending address information to the APB interface, you can receive second data information from the APB interface. This second data information can be the data under that address information. Then, send this second data information to the MDIO interface to complete the read operation.

[0060] In one embodiment, the method further includes one or more of the following:

[0061] When the data frame is a read data frame, the read operation is completed, and the PHY identifier information in the data frame is zero, the third data information under the address information corresponding to the PHY identifier information is sent to the MDIO interface.

[0062] If the data frame is a write operation frame, the write operation has ended, and the PHY identifier information in the data frame is zero, update the address information corresponding to the PHY identifier information.

[0063] If the data frame is a read data frame, the read operation is complete, and the PHY identifier information in the data frame is zero, the data can be returned to the storage module, such as the read data RDATA under the address information corresponding to the PHY identifier information in DEFAULT_SLV, i.e., the third data information. The third data information can be understood as the data under the address information corresponding to the PHY identifier information read from the storage module. In this application, the read data under the address information can be considered as the data under the address identified by the address information.

[0064] When the data frame is a write operation frame, the write operation is complete, and the PHY identifier information in the data frame is zero, address information latching can be achieved, that is, the address information corresponding to the PHY identifier information is updated and stored.

[0065] In one embodiment, when at least two devices are connected to the APB interface, the data interaction with the APB interface based on the pulse signal and the data frame includes:

[0066] Based on the pulse signal, the data frame, and the chip select information corresponding to the PHY identifier information in the data frame, data interaction is performed with the APB interface.

[0067] When at least two devices are connected to the APB interface, this application triggers read / write operations on the corresponding devices based on the chip select information of each device. For example, to write data to device A, this application enables the chip select of device A to write data to device A. That is, this application can perform data interaction with the APB interface based on data frames under the trigger of a pulse signal, and the device to be interacted with is determined based on the chip select information during the interaction. The PHY identification information and the chip select information, i.e., APB_SEL, have a one-to-one correspondence; one PHY identification information corresponds to one chip select information, and one chip select information corresponds to one device connected to the APB interface.

[0068] In one embodiment, the method further includes:

[0069] When the data frame is an address frame and the address frame has ended, the address information corresponding to the PHY identification information is stored based on the pulse signal, where the pulse signal is an address pulse signal.

[0070] When the data frame is an address frame and the address frame has ended, this application can trigger an address pulse signal. Then, triggered by the address pulse signal, the address information corresponding to the PHY identification information is stored to achieve address information latching. The storage location is not limited, as long as a correspondence between the PHY identification information and the address information can be established, such as storing it in a storage module.

[0071] The following is an exemplary description of this application. The data interaction method described in this application can be considered as a protocol conversion method from MDIO to APB. This method relates to the field of integrated circuit design, and in particular to the conversion of interface protocols in integrated circuit design.

[0072] The protocols MDIO and APB involved in this application are typical inter-chip interface protocols and intra-chip interface protocols, respectively. Of course, the distinction between inter-chip and intra-chip is not absolute. In some designs or commercial products, MDIO can be used as an intra-chip interface to manage multiple PHYs (physical interfaces); in some designs, when there are enough interfaces, APB is used directly as the inter-chip interface (this design approach is relatively rare, or often the address and data of APB are converted into a variant of serial data stream).

[0073] Currently, JTAG is used as the ATE interface. When converting the JTAG protocol to the APB protocol on-chip, the JTAG protocol specification is relatively complex and does not have native concepts such as address and data. Therefore, the designer needs to specially design the conversion relationship between APB.

[0074] This application proposes a method to convert MDIO to APB, transforming the MDIO protocol into the APB protocol. Since MDIO requires two signal lines (MDC, MDIO), it further reduces the number of chip interfaces occupied. The MDIO protocol is simpler than JTAG, and concepts such as address and data read / write are inherent, making the conversion between MDIO and APB more direct. Therefore, this application has the following advantages:

[0075] 1. The number of interfaces has been further reduced;

[0076] 2. The protocol conversion is direct, and the applications are more extensive;

[0077] 3. This application can design the conversion of different MDIO PHY identification information (i.e., ID) into different APB interfaces to enable access to multiple APB devices. The APB devices can be those connected to the APB interface. The PHY identification information can be mapped to the chip select of the APB interface to identify each device connected to the APB interface.

[0078] The technical problems to be solved by this invention include at least: further reducing the number of interfaces required for JTAG as the ATE test interface; improving the conversion efficiency of interface protocol to APB protocol; (this is aimed at the functional testing of simulated devices. For Scan testing in ATE, the JTAG protocol has better advantages and is not the scope of this application).

[0079] Figure 1a A schematic diagram of the structure of the data interaction device for implementing the data interaction method of this application is provided in this application. See also: Figure 1aThis device can be considered as a device for converting between the MDIO protocol and the APB protocol, namely MDIO2APB device 1. This device includes the MDIO2APB_TOP module, which is the top-level module of this application and includes interfaces for MDIO and APB. The device includes an MDIO processing module (MDIO_SYS), a storage module (DEFAULT_SLV), and an APB processing module (APB_SYS module). The device also includes interfaces for clock signals and / or reset signals (Clk / Rst). MDIO_SYS can be a module that converts the MDIO protocol into internal signals; DEFAULT_SLV can map PHY_ID=0 and DEV_ID=0 to this module to access some internal registers of this application, such as the status of the APB interface. PHY_ID and DEV_ID can be read from the data frame. DEV_ID is the device identifier. APB_SYS can convert internal signals into the APB protocol. The data interaction method described in this application parses the MDIO protocol into internal signals; converts the internal signals into the APB protocol, reducing the number of ports, i.e., the number of interfaces; the protocol conversion is more direct; and it supports more devices connecting to the APB interface.

[0080] This method may specifically include the following steps:

[0081] 1) MDIO_SYS: Design a state machine based on the MDIO protocol specification, extract the address (i.e., ADDR), PHY_ID (i.e., PHY identification information), DEV_ID (i.e., DEV identification information), write data WDATA (i.e., first data information) from the protocol specification; receive read data RDATA.

[0082] 2) After the address frame of MDIO ends, an ADDR_PULSE of the Clk clock field is triggered (i.e., the ADDR_PULSE pulse is aligned with Clk). Here, Clk can be the clock signal of the APB interface, and the ADDR_PULSE pulse can be the address pulse signal. The DEFAULT_SLV module updates the address latched under the corresponding PHY_ID under this pulse, that is, the PHY_ID and the corresponding address in the data frame received from the MDIO interface are latched into the DEFAULT_SLV module.

[0083] 3) When the MDIO frame is a write operation frame, after the write operation is completed, a W_PULSE signal in the Clk clock domain is triggered, i.e., a write pulse signal; if PHY_ID is zero, the register in the corresponding DEFAULT_SLV is updated through the address latched when PHY_ID is zero; if PHY_ID is not zero, the corresponding PHY_ID address (the address under this PHY_ID latched in step 2) is sent on APB_SYS, the data is the received WDATA, and APB_SEL (chip select information of the APB interface) is a write operation with the PHY_ID bit valid; the return information and status of APB (i.e., status information) are updated to the corresponding status bit of DEFAULT_SLV;

[0084] 4) When the MDIO frame is a read operation frame, after receiving PHY_ID, an R_PULSE signal in the Clk clock domain is immediately triggered, i.e., a read pulse signal; if PHY_ID is zero, DEFAULT_SLV returns the read data at the corresponding address to RDATA (i.e., the third data information) and sends it to the MDIO interface; if PHY_ID is not zero, an APB read at the address corresponding to PHY_ID is issued on APB_SYS (i.e., sending APB read information and the address information corresponding to PHY_ID), and APB_SEL selects the corresponding PHY_ID bit as valid; the returned read data of APB is sent to MDIO as RDATA (i.e., the second data information); and the status information of APB is updated to the status bit corresponding to DEFAULT_SLV.

[0085] By appropriately selecting the frequencies of Clk and MDIO, it is ensured that the APB read response returns within 7 MDIO clock cycles. The selection of Clk and MDIO frequencies can be based on the read and write speeds of the devices connected to the APB interface. When the read and write speeds are high, a higher Clk frequency and a lower MDIO frequency can be selected.

[0086] In addition to the above processing steps, for application scenarios where only one device is connected to the APB interface, i.e., there is an APB slave device (i.e., SLAVE), this application can be modified to the following process steps. Compared with the above implementation method, the cached address (i.e., the address cached in DEFAULT_SLV) can be used to reduce the number of MDIO address frames, improve efficiency, and shorten the duration of ATE stimulus.

[0087] Specifically, by storing the PHY_ID and ADDR included in the address frame into DEFAULT_SLV, the address frame is avoided when sending read data frames and write data frames.

[0088] 1) MDIO_SYS: Design a state machine based on the MDIO protocol specification, extracting the address ADDR, PHY_ID, DEV_ID, write data WDATA, and receive / read data RDATA from the protocol specification.

[0089] 2) After the address frame of MDIO ends, an ADDR_PULSE of the Clk clock field is triggered; the DEFAULT_SLV module updates the address latched under the corresponding PHY_ID under this pulse;

[0090] 3) When the MDIO frame is a write operation frame, after the write operation is completed, a W_PULSE in the Clk clock domain is triggered; if PHY_ID is zero, the register in the corresponding DEFAULT_SLV is updated through the address latched by PHY_ID being zero; if PHY_ID is not zero, the address of the corresponding PHY_ID (the address under this PHY_ID latched in step 2) is sent on APB_SYS, and the data is the received WDATA; the return information and status of APB are updated to the corresponding status bit of DEFAULT_SLV;

[0091] 4) When the MDIO frame is a read operation frame, after receiving PHY_ID, immediately trigger an R_PULSE in the Clk clock field; if PHY_ID is zero, return DEFAULT_SLV to return the read data at the corresponding address to RDATA; if PHY_ID is not zero, issue an APB read at the address corresponding to PHY_ID on APB_SYS; (by reasonably selecting the frequencies of CLK and MDIO, ensure that the APB read response is returned within 7 MDIO clock cycles;) send the returned read data of APB as RDATA to MDIO; and update the status information of APB to the status bit corresponding to DEFAULT_SLV.

[0092] As shown above, since there are 64 PHY_IDs, excluding the one occupied by Default_SLV, there can be 63 address caches. The addresses commonly used for ATE test stimuli are cached in the cache. Therefore, for accessing these addresses, it is not necessary to send MDIO address frames. Only read and write access frames and the corresponding PHY_ID are required. For ATE stimuli, the access to a few valid addresses is concentrated. Compared with the above implementation method, the efficiency can be improved by 50%.

[0093] This application provides a data interaction device. Figure 2 This application provides a schematic diagram of the structure of a data interaction device, which can be integrated into a terminal device, such as... Figure 2As shown, the device includes: an acquisition module 21, configured to acquire data frames through a Management Data Input / Output (MDIO) interface; a trigger module 22, configured to trigger a pulse signal corresponding to the data frame, wherein the pulse signal is determined by a clock signal based on an Advanced Peripheral Bus (APB) interface; and an interaction module 23, configured to perform data interaction with the APB interface based on the pulse signal and the data frame.

[0094] The data interaction device provided in this embodiment is used to implement the data interaction method of the present application embodiment. The implementation principle and technical effect of the data interaction device provided in this embodiment are similar to those of the data interaction method of the present application embodiment, and will not be repeated here.

[0095] Based on the above embodiments, modified embodiments of the above embodiments are proposed. It should be noted that, in order to keep the description brief, only the differences from the above embodiments are described in the modified embodiments.

[0096] In one embodiment, the data frame includes at least one of the following: address information, physical interface PHY identification information, DEV identification information, and first data information, wherein the first data information is information written to the APB interface.

[0097] In one embodiment, the triggering module 22 is specifically configured as follows:

[0098] When the data frame is a write operation frame and the write operation has ended, a write pulse signal is triggered;

[0099] When the data frame is a read operation frame and the read operation has ended, a read pulse signal is triggered;

[0100] When the data frame is an address frame and the address frame has ended, an address pulse signal is triggered.

[0101] In one embodiment, the interaction module 23 is specifically configured as follows:

[0102] When the PHY identifier information in the data frame is non-zero, the address information and first data information corresponding to the PHY identifier information are sent to the APB interface based on the pulse signal to update the status information of the APB interface. The pulse signal is a write pulse signal.

[0103] When the PHY identifier information in the data frame is non-zero, the address information corresponding to the PHY identifier information is sent to the APB interface based on the pulse signal, the second data information under the address information sent by the APB interface is received, and the second data information is sent to the MDIO interface. The pulse signal is a read pulse signal, and the second data information is information read from the APB interface.

[0104] In one embodiment, the device further includes one or more of the following:

[0105] The sending module is configured to send the third data information under the address information corresponding to the PHY identifier to the MDIO interface when the data frame is a read data frame, the read operation is completed, and the PHY identifier information in the data frame is zero.

[0106] The update module is configured to update the address information corresponding to the PHY identifier when the data frame is a write operation frame, the write operation has ended, and the PHY identifier information in the data frame is zero.

[0107] In one embodiment, the interaction module 23 is specifically configured to perform data interaction with the APB interface based on the pulse signal, the data frame, and the chip select information corresponding to the PHY identification information in the data frame when at least two devices are connected to the APB interface.

[0108] In one embodiment, the device further includes: a storage module configured to:

[0109] When the data frame is an address frame and the address frame has ended, the address information corresponding to the PHY identification information is stored based on the pulse signal, where the pulse signal is an address pulse signal.

[0110] This application also provides a terminal device. Figure 3 This is a structural schematic diagram of a terminal device provided in this application. Figure 3 As shown, the terminal device provided in this application includes: one or more processors 31 and a storage device 32; the processor 31 in the terminal device may be one or more. Figure 3 Taking a processor 31 as an example; storage device 32 is used to store one or more programs; the one or more programs are executed by the one or more processors 31, causing the one or more processors 31 to implement the method as described in the embodiments of this application.

[0111] The terminal equipment also includes: a communication device 33, an input device 34, and an output device 35.

[0112] The processor 31, storage device 32, communication device 33, input device 34, and output device 35 in the terminal device can be connected via a bus or other means. Figure 3 Taking the example of a connection between China and Israel via a bus.

[0113] Input device 34 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the terminal device. Output device 35 may include a display device such as a screen. Input device 34 can be an MDIO interface and / or an APB interface. Output device 35 can be an MDIO interface and / or an APB interface.

[0114] The communication device 33 may include a receiver and a transmitter. The communication device 33 is configured to perform information transmission and reception communication under the control of the processor 31. The information includes, but is not limited to, data frames and data exchanged with the APB interface.

[0115] Storage device 32, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, and modules, such as program instructions / modules corresponding to the methods described in the embodiments of this application (e.g., acquisition module 21, trigger module 22, and interaction module 23 in a data interaction device). Storage device 32 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created based on the use of the terminal device, etc. Furthermore, storage device 32 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, storage device 32 may further include memory remotely located relative to processor 31, and these remote memories can be connected to the terminal device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0116] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements any of the methods described in this application. The method includes: acquiring a data frame via a Management Data Input / Output (MDIO) interface; triggering a pulse signal corresponding to the data frame, wherein the pulse signal is determined by a clock signal based on an Advanced Peripheral Bus (APB) interface; and performing data interaction with the APB interface based on the pulse signal and the data frame.

[0117] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be—but is not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device, or any suitable combination thereof. The computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0118] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0119] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0120] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0121] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0122] Those skilled in the art will understand that the term "terminal" encompasses any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicle-mounted mobile stations.

[0123] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0124] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0125] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on memory. Memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and processors based on multi-core processor architectures.

[0126] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of this application. Therefore, the proper scope of this application will be determined by the claims.

Claims

1. A data interaction method, characterized in that, include: Data frames are obtained through the MDIO interface for managing data input and output. A pulse signal is triggered corresponding to the data frame, wherein the pulse signal is determined based on a clock signal from the Advanced Peripheral Bus (APB) interface; Based on the pulse signal and the data frame, data interaction is performed with the APB interface; The pulse signal that triggers the corresponding data frame includes: When the data frame is a write operation frame and the write operation has ended, a write pulse signal is triggered; If the data frame is a read operation frame and the read operation has ended, a read pulse signal is triggered; When the data frame is an address frame and the address frame has ended, an address pulse signal is triggered.

2. The method according to claim 1, characterized in that, The data frame includes at least one of the following: address information, physical interface PHY identification information, device DEV identification information, and first data information, wherein the first data information is information written to the APB interface.

3. The method according to claim 1, characterized in that, The data interaction with the APB interface based on the pulse signal and the data frame includes: When the PHY identifier information in the data frame is non-zero, the address information and first data information corresponding to the PHY identifier information are sent to the APB interface based on the pulse signal to update the status information of the APB interface. The pulse signal is a write pulse signal. When the PHY identifier information in the data frame is non-zero, the address information corresponding to the PHY identifier information is sent to the APB interface based on the pulse signal, the second data information under the address information sent by the APB interface is received, and the second data information is sent to the MDIO interface. The pulse signal is a read pulse signal, and the second data information is information read from the APB interface.

4. The method according to claim 1, characterized in that, It also includes one or more of the following: When the data frame is a read data frame, the read operation is completed, and the PHY identifier information in the data frame is zero, the third data information under the address information corresponding to the PHY identifier information is sent to the MDIO interface. If the data frame is a write operation frame, the write operation has ended, and the PHY identifier information in the data frame is zero, update the address information corresponding to the PHY identifier information.

5. The method according to claim 1, characterized in that, When at least two devices are connected to the APB interface, the data interaction with the APB interface based on the pulse signal and the data frame includes: Based on the pulse signal, the data frame, and the chip select information corresponding to the PHY identifier information in the data frame, data interaction is performed with the APB interface.

6. The method according to claim 1, characterized in that, Also includes: When the data frame is an address frame and the address frame has ended, the address information corresponding to the PHY identification information is stored based on the pulse signal, where the pulse signal is an address pulse signal.

7. A data interaction device, characterized in that, include: The acquisition module is configured to acquire data frames through the Management Data Input / Output (MDIO) interface; The triggering module is configured to trigger a pulse signal corresponding to the data frame, wherein the pulse signal is determined based on a clock signal from the Advanced Peripheral Bus (APB) interface. The pulse signal that triggers the corresponding data frame includes: When the data frame is a write operation frame and the write operation has ended, a write pulse signal is triggered; If the data frame is a read operation frame and the read operation has ended, a read pulse signal is triggered; When the data frame is an address frame and the address frame has ended, an address pulse signal is triggered. The interaction module is configured to interact with the APB interface based on the pulse signal and the data frame.

8. A terminal device, characterized in that, include: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-6.

9. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method described in any one of claims 1-6.

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