Delay circuit for digital signals, in particular for clock signals
By using a delay circuit based on an internal clock signal, and utilizing an oscillator and multiple delay channels, the problem of frequency and environmental variation in existing technologies is solved, realizing a high-frequency, low-power, and small-space delay circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RENESAS ELECTRONICS AMERICA INC
- Filing Date
- 2020-11-20
- Publication Date
- 2026-07-03
AI Technical Summary
Existing delay circuits have limitations in minimum pulse width and operating frequency, and are affected by process angle and temperature angle, resulting in high manufacturing costs and large chip area.
It employs a delay circuit based on an internal clock signal, uses an oscillator to generate an internal clock signal, and adds delay to the digital input signal through multiple delay channels to support higher input frequencies without relying on RC components. It also incorporates an oscillator with process, voltage, and temperature compensation to reduce sensitivity to environmental changes.
It enables high-frequency operation over a wide frequency range, reduces power consumption and manufacturing complexity, reduces the required space, and supports higher input frequencies.
Smart Images
Figure CN112825480B_ABST