Memory array and method of manufacturing the same
By using a manufacturing method that involves interlacing single-crystal silicon pillars and wavy word lines, the problem of narrow process windows in the 4F2 structure was solved, resulting in higher storage capacity and smaller memory chip size.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2019-11-22
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, the narrow process window of the 4F2 structure makes mass production difficult and limits the expansion of storage capacity.
The memory array is fabricated on the SOI wafer by using staggered single-crystal silicon pillars and a wavy word line structure, through etching and deposition processes. This increases the gate spacing near the single-crystal silicon pillars and utilizes memory cells arranged in a honeycomb pattern to reduce the difficulty of the process.
Without reducing the density of memory cells, the gate spacing was increased, the manufacturing process became easier, the storage capacity per unit area was increased, and the size of the memory chip was reduced.
Smart Images
Figure CN112838085B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a memory array with higher memory cell density and a method for manufacturing the same. Background Technology
[0002] To address the difficulty in expanding storage capacity, a new method—4F—has been proposed to increase net modulus and reduce cell size. 2 structure. Figure 1 It's 4F 2 Top view of the structure. (Reference) Figure 1 4F 2 The structure can be fabricated using GAA (Gate All-Around) 3D transistors. The transistors are positioned perpendicular to the substrate surface, and the capacitors are electrically connected to the upper surface of the transistors. From bottom to top, the bit lines (BL), dielectric layer, word lines (WL), and capacitors are arranged in this order. The bit lines, dielectric layer, and word lines all surround a single-crystal silicon pillar, which serves as the main body of the transistor. This pillar includes the source located between the bit lines and word lines and connected to them, the gate enclosed by the bit lines, and the gate located between the word lines and the capacitors. From a top-down view, in this technology, multiple transistors (and capacitors above them) are arranged at the intersections of the bit lines and word lines in a checkerboard pattern, i.e., a checkerboard arrangement.
[0003] In the above three-dimensional structure, in order for the transistor to work properly, the gate material (word line) is preferably wrapped around the single-crystal silicon pillar. The gate spacing near the single-crystal silicon pillar is very small. This narrow control makes the process window very narrow, increasing the difficulty of mass production.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this disclosure is to provide a storage array and a method for manufacturing the same, which at least partially overcomes the problem of high manufacturing difficulty caused by limitations and defects in related technologies.
[0006] According to one aspect of this disclosure, a storage array is provided, comprising:
[0007] mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns;
[0008] n parallel bit lines, each bit line wrapping around the lower part of a column of single-crystal silicon pillars;
[0009] The word lines are arranged in parallel rows of m / 2 rows, each word line wraps around the middle of two adjacent rows of single-crystal silicon pillars, and each word line connects to a different single-crystal silicon pillar. The word lines are wavy lines.
[0010] mn / 2 capacitors, the lower plates of which are electrically connected to the upper parts of mn / 2 single-crystal silicon pillars.
[0011] In one exemplary embodiment of this disclosure, the capacitor is aligned with the axis of the monocrystalline silicon pillar.
[0012] In one exemplary embodiment of this disclosure, the axis of the capacitor and the axis of the single-crystal silicon pillar have a first displacement along the bit line, the first displacements in adjacent columns have opposite signs, and the first displacements in the same column have the same sign.
[0013] In one exemplary embodiment of this disclosure, the cross-section of the single-crystal silicon pillar is circular.
[0014] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal, and the spacing between the word lines is equal.
[0015] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines.
[0016] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal to the spacing between the word lines. times.
[0017] In one exemplary embodiment of this disclosure, a dielectric layer is disposed between the bit line and the word line, and the dielectric layer is made of silicon nitride and / or silicon oxide.
[0018] In one exemplary embodiment of this disclosure, the bit line is a straight line.
[0019] According to one aspect of this disclosure, a method for manufacturing a storage array is provided, comprising:
[0020] Provide SOI wafers;
[0021] The device layer silicon of the SOI wafer is etched to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.
[0022] n parallel rows of bit lines are fabricated on the silicon device layer, and each bit line wraps around the lower part of a row of single-crystal silicon pillars;
[0023] A dielectric is deposited on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar;
[0024] After surface oxidation of the single-crystal silicon pillar, m / 2 rows of parallel word lines are manufactured on the dielectric layer. Each word line wraps around the middle of two adjacent rows of single-crystal silicon pillars. The single-crystal silicon pillars wrapped by each word line are different. The word lines are wavy lines. The upper surface of the word lines is not higher than the upper surface of the single-crystal silicon pillars.
[0025] A capacitor is fabricated above the upper part of the single-crystal silicon pillar.
[0026] In one exemplary embodiment of this disclosure, the fabrication of n parallel rows of bit lines on the device layer silicon includes:
[0027] The device layer silicon is etched downwards into n columns of parallel bit lines.
[0028] In one exemplary embodiment of this disclosure, the fabrication of n parallel rows of bit lines on the device layer silicon includes:
[0029] The bit lines are fabricated in n parallel columns on the silicon layer of the device by a deposition process.
[0030] In one exemplary embodiment of this disclosure, the capacitor is aligned with the axis of the monocrystalline silicon pillar.
[0031] In one exemplary embodiment of this disclosure, the axis of the capacitor and the axis of the single-crystal silicon pillar have a first displacement along the bit line, the first displacements in adjacent columns have opposite signs, and the first displacements in the same column have the same sign.
[0032] In one exemplary embodiment of this disclosure, the cross-section of the single-crystal silicon pillar is circular.
[0033] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal, and the spacing between the word lines is equal.
[0034] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines.
[0035] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal to the spacing between the word lines. times.
[0036] In one exemplary embodiment of this disclosure, the dielectric layer is made of silicon nitride and / or silicon oxide.
[0037] In one exemplary embodiment of this disclosure, the bit line is a straight line.
[0038] In one exemplary embodiment of this disclosure, it further includes:
[0039] Before etching the single-crystal silicon pillar, a first ion is implanted into the silicon layer of the device.
[0040] In one exemplary embodiment of this disclosure, it further includes:
[0041] Before or after the bit line is fabricated, a second ion is injected into the region corresponding to the bit line.
[0042] This embodiment of the invention, by setting memory cells arranged in a honeycomb pattern and setting wavy word lines, can increase the gate spacing near the single-crystal silicon pillar while making the word lines wrap around the single-crystal silicon pillar, effectively reducing the process difficulty.
[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0045] Figure 1 It's 4F 2 A top view of the structure.
[0046] Figure 2 This is a schematic diagram of the structure of the storage array in an exemplary embodiment of this disclosure.
[0047] Figure 3 This is a flowchart of the manufacturing process of the storage array in this embodiment of the present disclosure.
[0048] Figure 4 yes Figure 3 A schematic diagram of step S31.
[0049] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of step S32.
[0050] Figures 6A to 6D yes Figure 3 A schematic diagram of step S33.
[0051] Figure 7 yes Figure 3 A schematic diagram of step S34.
[0052] Figure 8A and Figure 8B yes Figure 3A schematic diagram of step S35.
[0053] Figures 9A to 9C yes Figure 3 A schematic diagram of step S36. Detailed Implementation
[0054] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.
[0055] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted.
[0056] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0057] Figure 2 This is a schematic diagram of the structure of the storage array in an exemplary embodiment of this disclosure.
[0058] refer to Figure 2 The storage array 200 may include:
[0059] There are mn / 2 single-crystal silicon pillars 21 arranged in m rows and n columns. The single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.
[0060] n parallel bit lines 22, each bit line wrapping around the lower part of a column of single-crystal silicon pillars;
[0061] The word lines 23 are arranged in parallel rows of m / 2 rows. Each word line wraps around the middle of two adjacent rows of single-crystal silicon pillars. The single-crystal silicon pillars wrapped by each word line are different. The word lines are wavy lines.
[0062] There are two capacitors, mn / 2 and 24, with their lower plates electrically connected to the upper parts of the mn / 2 single-crystal silicon pillars.
[0063] exist Figure 2In the illustrated embodiment, bit line 22 is a straight line, the cross-section of the single-crystal silicon pillar is circular, the cross-section of the capacitor is circular, and the capacitor is aligned with the axis of the single-crystal silicon pillar. As can be seen from the figure, compared to... Figure 1 The memory cells are arranged in a checkerboard pattern. In this embodiment of the invention, the adjacent memory cells have a large gate distance, which reduces the process difficulty without reducing the distribution density of memory cells.
[0064] In addition, Figure 2 In the illustrated embodiment, the spacing between bit lines 22 is equal, and the spacing between word lines 23 is equal (the spacing here refers to the spacing between adjacent straight sections of two word lines); in other embodiments of this disclosure, the spacing between bit lines 22 may also have two or more sizes, and the spacing between word lines 23 may also have two or more sizes, and this disclosure does not impose any special restrictions on this.
[0065] When the spacing between bit lines 22 and word lines 23 are equal, the spacing between word lines 23 can be set to be equal to the spacing between bit lines 22. This means that the spacing between single-crystal silicon pillars in different columns is greater than the spacing between adjacent single-crystal silicon pillars in the same column. In some embodiments, the spacing between single-crystal silicon pillars in different columns can also be set to be equal to the spacing between adjacent single-crystal silicon pillars in the same column, that is, the spacing between bit lines 22 is set to be the same as the spacing between word lines 23. times.
[0066] Figure 3 This is a flowchart of the manufacturing process of the storage array in this embodiment of the present disclosure.
[0067] refer to Figure 3 The storage array manufacturing method 300 may include:
[0068] Step S31: Provide an SOI wafer;
[0069] Step S32: Etch the device layer silicon of the SOI wafer to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.
[0070] Step S33: n parallel bit lines are fabricated on the device layer silicon, and each bit line wraps around the lower part of a column of single crystal silicon pillars;
[0071] Step S34: Deposit dielectric on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar;
[0072] Step S35: After surface oxidation of the single-crystal silicon pillar, m / 2 rows of parallel word lines are manufactured on the dielectric layer. Each word line wraps around the middle of two adjacent rows of single-crystal silicon pillars. The single-crystal silicon pillars wrapped by each word line are different. The word lines are wavy lines. The upper surface of the word lines is not higher than the upper surface of the single-crystal silicon pillars.
[0073] Step S36: Fabricate a capacitor above the upper part of the single-crystal silicon pillar.
[0074] Figure 4 Figure 9 is Figure 3 The process flow diagram shown is a schematic diagram of the technological process.
[0075] Figure 4 yes Figure 3 A schematic diagram of step S31.
[0076] In this embodiment of the disclosure, the memory array is fabricated on an SOI wafer. SOI (Silicon-On-Insulator) refers to the presence of a buried oxide layer 42 (SiO2) between a substrate silicon layer 41 and a device layer silicon layer 43.
[0077] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of step S32.
[0078] refer to Figure 5A The device layer silicon 43 can be etched into mn / 2 single-crystal silicon pillars 21 arranged in m rows and n columns by processes such as masking and exposure. Figure 5B As shown, m = 10, n = 5, number of single-crystal silicon pillars = 25), such that the single-crystal silicon pillars 21 are located in odd-numbered rows and even-numbered columns, or in odd-numbered rows and even-numbered columns. In one embodiment of this disclosure, the pillar holes (i.e., the cross-section of the single-crystal silicon pillars) are circular to provide a larger conductive area with a smaller perimeter. In other embodiments, the pillar holes (i.e., the cross-section of the single-crystal silicon pillars) may also be other shapes, which can be determined by those skilled in the art.
[0079] In one embodiment, if subsequent Figure 6A In the etching process shown to manufacture bit lines, in step S32, it is not necessary to control the etching of the single-crystal silicon pillar down to the oxide layer 42; a certain thickness of the device layer silicon is retained for etching the bit lines. In another embodiment, if subsequent... Figure 6C The deposition process shown creates bit lines. In order to ensure the insulation between the single-crystal silicon pillars, the etching depth of the oxide layer 42 can be controlled when forming the single-crystal silicon pillars.
[0080] Figure 5B yes Figure 5AThe diagram shows a top-down view of the manufacturing process. From Figure 5B It can be seen that, due to the honeycomb-like staggered arrangement of the single-crystal silicon pillars, the vertical distance between two adjacent rows of single-crystal silicon pillars can be increased, which provides the conditions for subsequently increasing the gate spacing.
[0081] Figures 6A to 6D yes Figure 3 A schematic diagram of step S33.
[0082] refer to Figure 6A In one embodiment, the method of fabricating n parallel rows of bit lines on the device layer silicon can be achieved, for example, by etching the device layer silicon, i.e., etching the device layer silicon downwards to fabricate n parallel rows of bit lines 22.
[0083] Because the doping types of the silicon in the device layer are different, and the doping type of the bit line region needs to be different from that of the silicon in the device layer, a first ion implantation is required before etching the single-crystal silicon pillar. A second ion implantation is also required in the bit line region before or after etching the bit line to change the doping type of the bit line region (e.g., ...). Figure 6B As shown), it finally forms as follows Figure 6C The effect shown.
[0084] In another embodiment, the method of fabricating n parallel rows of bit lines 22 on the device layer silicon can be achieved, for example, by performing a deposition process on the device layer silicon (the implementation effect is as follows). Figure 6C (As shown). The deposition process can be applied to the fabrication of bit lines in both semiconductor and metal materials.
[0085] Figure 6D yes Figure 6C The top view of the steps shown.
[0086] Figure 7 yes Figure 3 A schematic diagram of step S34 is shown. In step S34, the material of the deposited dielectric layer 44 is, for example, silicon dioxide (SiO2) or silicon nitride (Si3N4), and this disclosure does not impose any special limitations on it. The dielectric layer 44 can not only effectively isolate bit lines, but also isolate bit lines and word lines, and the area of the single-crystal silicon pillar it encloses corresponds to the source of the transistor.
[0087] Figure 8A and Figure 8B yes Figure 3 A schematic diagram of step S35. In step S35, bit lines connecting to the gate are fabricated. First, the surface of the single-crystal silicon pillar corresponding to the bit line region is oxidized to create a gate oxide layer. Then, metal word lines 23 arranged in parallel m / 2 rows with a wavy shape are fabricated by metal deposition and etching (including dry etching or wet etching) processes.
[0088] In this embodiment, the word lines 23 are wavy, so that each word line wraps around two adjacent rows of single-crystal silicon pillars 21, and the single-crystal silicon pillars wrapped by each word line 23 are different. By manufacturing wavy word lines 23, the gate material can wrap around the single-crystal silicon pillars while increasing the vertical edge distance between two adjacent rows of single-crystal silicon pillars. At the same time, a larger gate pitch is achieved by utilizing the larger row spacing of the single-crystal silicon pillars, which reduces the process difficulty while ensuring more stable operation.
[0089] Figure 8B yes Figure 8A A top view diagram illustrating the steps shown.
[0090] Figures 9A to 9C yes Figure 3 A schematic diagram of step S36.
[0091] refer to Figure 9A Storage capacitors 24 can be fabricated above the upper part of the single-crystal silicon pillar 21, forming a structure like... Figure 2 or Figure 9B The storage array structure is shown. Because adjacent columns of single-crystal silicon pillars are located in different rows in this embodiment, after manufacturing the storage capacitors, from... Figure 9A From a side viewpoint, the storage capacitors block each other. The structure of storage capacitor 24 is, for example, cup-shaped.
[0092] from Figure 9B As can be seen, due to the staggered arrangement of the single-crystal silicon pillars, the vertical spacing between word lines is increased, meaning the spacing between the gates of adjacent rows of memory cells is increased, significantly increasing the bridging margin between gates and reducing the manufacturing complexity. Furthermore, because the memory cells are arranged in a honeycomb pattern, the storage capacitors 24 can achieve a higher density arrangement without changing the diameter, thus manufacturing more memory cells per unit area and effectively increasing the storage capacity of the memory array per unit area. With the same number of memory cells, Figure 9B The structure shown is relatively Figure 1 The structure shown occupies 13% less area, which can effectively reduce the size of the memory chip without reducing the storage capacity.
[0093] Figure 9C This is a manufacturing effect diagram of the storage capacitor 24 in yet another embodiment of this disclosure.
[0094] Since the wavy word lines are difficult to shape, this embodiment proposes to set the storage capacitor 24 and the single crystal silicon pillar 21 non-axially symmetrically, thereby reducing the curvature of the word lines and further reducing the process difficulty.
[0095] refer to Figure 9CIn one embodiment of this disclosure, the storage capacitor 24 has a circular cross-section, and the axis of the capacitor has a first displacement with the axis extension line of the single-crystal silicon pillar. The signs of the first displacements of adjacent columns are opposite, and the signs of the first displacements of the same column are the same. For example, if the first displacement corresponding to a column is L (as shown in the figure), then the first displacement corresponding to its adjacent column is -L. The value of L can be set by those skilled in the art.
[0096] In summary, the memory array manufacturing method provided in this disclosure, by setting staggered single-crystal silicon pillars and wavy word lines, can not only increase the gate spacing between adjacent word lines and increase the process margin, but also increase the density of memory cells per unit area and increase the storage capacity of the memory array.
[0097] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.
Claims
1. A storage array, characterized in that, include: mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns; n parallel bit lines, each bit line wrapping around the lower part of a column of single-crystal silicon pillars; The word lines are arranged in parallel rows of m / 2 rows, each word line wraps around the middle of two adjacent rows of single-crystal silicon pillars, and each word line connects to a different single-crystal silicon pillar. The word lines are wavy lines. mn / 2 capacitors, the lower plates of which are electrically connected to the upper parts of mn / 2 single-crystal silicon pillars.
2. The storage array as described in claim 1, characterized in that, The capacitor is aligned with the axis of the monocrystalline silicon pillar.
3. The storage array as described in claim 1, characterized in that, The axis of the capacitor and the axis of the single-crystal silicon pillar have a first displacement along the bit line, the first displacements in adjacent columns have opposite signs, and the first displacements in the same column have the same sign.
4. The storage array as described in claim 1, characterized in that, The cross-section of the single-crystal silicon pillar is circular.
5. The storage array as described in claim 1, characterized in that, The spacing between the bit lines is equal, and the spacing between the word lines is equal.
6. The storage array as described in claim 5, characterized in that, The spacing between the word lines is equal to the spacing between the bit lines.
7. The storage array as described in claim 5, characterized in that, The spacing between the bit lines is the same as the spacing between the word lines. times.
8. The storage array as claimed in claim 1, characterized in that, A dielectric layer is disposed between the bit line and the word line, and the dielectric layer is made of silicon nitride and / or silicon oxide.
9. The storage array as claimed in claim 1, characterized in that, The bit line is a straight line.
10. A method for manufacturing a storage array, characterized in that, include: Provide SOI wafers; The device layer silicon of the SOI wafer is etched to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns. n parallel rows of bit lines are fabricated on the silicon device layer, and each bit line wraps around the lower part of a row of single-crystal silicon pillars; A dielectric is deposited on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar; After surface oxidation of the single-crystal silicon pillar, m / 2 rows of parallel word lines are manufactured on the dielectric layer. Each word line wraps around the middle of two adjacent rows of single-crystal silicon pillars. The single-crystal silicon pillars wrapped by each word line are different. The word lines are wavy lines. The upper surface of the word lines is not higher than the upper surface of the single-crystal silicon pillars. A capacitor is fabricated above the upper part of the single-crystal silicon pillar.
11. The method for manufacturing a storage array as described in claim 10, characterized in that, The fabrication of n parallel bit lines on the silicon device layer includes: The device layer silicon is etched downwards into n columns of parallel bit lines.
12. The method for manufacturing a storage array as described in claim 10, characterized in that, The fabrication of n parallel bit lines on the silicon device layer includes: The bit lines are fabricated in n parallel columns on the silicon layer of the device by a deposition process.
13. The method for manufacturing a storage array as described in claim 10, characterized in that, The capacitor is aligned with the axis of the monocrystalline silicon pillar.
14. The method for manufacturing a storage array as described in claim 10, characterized in that, The axis of the capacitor and the axis of the single-crystal silicon pillar have a first displacement along the bit line, the first displacements in adjacent columns have opposite signs, and the first displacements in the same column have the same sign.
15. The method for manufacturing a storage array as described in claim 10, characterized in that, The cross-section of the single-crystal silicon pillar is circular.
16. The method for manufacturing a storage array as described in claim 10, characterized in that, The spacing between the bit lines is equal, and the spacing between the word lines is equal.
17. The method for manufacturing a storage array as described in claim 16, characterized in that, The spacing between the word lines is equal to the spacing between the bit lines.
18. The method for manufacturing a storage array as described in claim 16, characterized in that, The spacing between the bit lines is the same as the spacing between the word lines. times.
19. The method for manufacturing a storage array as described in claim 10, characterized in that, The dielectric layer is made of silicon nitride and / or silicon oxide.
20. The method for manufacturing a storage array as described in claim 10, characterized in that, The bit line is a straight line.
21. The method for manufacturing a storage array as described in claim 10, characterized in that, Also includes: Before etching the single-crystal silicon pillar, a first ion is implanted into the silicon layer of the device.
22. The method for manufacturing a storage array as described in claim 11, characterized in that, Also includes: Before or after the bit line is fabricated, a second ion is injected into the region corresponding to the bit line.