Memory array and method of manufacturing the same

Abstract

The present disclosure provides a storage array and a manufacturing method thereof. The storage array comprises: mn / 2 single crystal silicon pillars arranged in m rows and n columns, the single crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or located in odd rows and odd columns and even rows and even columns; n columns of parallel arranged bit lines, each of the bit lines wraps a lower part of a column of the single crystal silicon pillars; m / 2 rows of parallel arranged word lines, each of the word lines connects a middle part of two adjacent rows of single crystal silicon pillars, the single crystal silicon pillars connected by each of the word lines are all different, and the word lines are straight lines; and mn / 2 capacitors, lower plates of the capacitors are electrically connected with upper parts of the mn / 2 single crystal silicon pillars respectively. The embodiments of the present disclosure can increase the density of storage units in the storage array.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a memory array with higher memory cell density and a method for manufacturing the same. Background Technology

[0002] To address the difficulty in expanding storage capacity, a new method—4F—has been proposed to increase net modulus and reduce cell size. 2 structure. Figure 1 It's 4F 2 Top view of the structure. (Reference) Figure 1 4F 2 The structure can be fabricated using GAA (Gate All-Around) 3D transistors. The transistors are positioned perpendicular to the substrate surface, and the capacitors are electrically connected to the upper surface of the transistors. From bottom to top, the bit lines (BL), dielectric layer, word lines (WL), and capacitors are arranged in this order. The bit lines, dielectric layer, and word lines all surround a single-crystal silicon pillar, which serves as the main body of the transistor. This pillar includes the source located between the bit lines and word lines and connected to them, the gate enclosed by the bit lines, and the gate located between the word lines and the capacitors. From a top-down view, in this technology, multiple transistors (and capacitors above them) are arranged at the intersections of the bit lines and word lines in a checkerboard pattern, i.e., a checkerboard arrangement.

[0003] In the aforementioned three-dimensional structure, the capacitor area is limited due to the checkerboard arrangement, making it impossible to further increase the storage capacity. Therefore, further improving the storage capacity of the storage array has become a key research focus for those skilled in the art.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a storage array and a method for manufacturing the same, which at least partially overcomes the problem of limited storage cell density caused by limitations and defects in related technologies.

[0006] According to a first aspect of this disclosure, a storage array is provided, comprising:

[0007] mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns;

[0008] n parallel bit lines, each bit line wrapping around the lower part of a column of single-crystal silicon pillars;

[0009] The word lines are arranged in parallel rows of m / 2 rows, each word line connecting the middle of two adjacent rows of single-crystal silicon pillars. Each word line connects to a different single-crystal silicon pillar, and the word lines are straight lines.

[0010] mn / 2 capacitors, the lower plates of which are electrically connected to the upper parts of mn / 2 single-crystal silicon pillars.

[0011] In one exemplary embodiment of this disclosure, the capacitor is aligned with the axis of the monocrystalline silicon pillar.

[0012] In one exemplary embodiment of this disclosure, the cross-section of the single-crystal silicon pillar is circular.

[0013] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal, and the spacing between the word lines is equal.

[0014] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines.

[0015] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal to the spacing between the word lines. times.

[0016] In one exemplary embodiment of this disclosure, a dielectric layer is disposed between the bit line and the word line, and the dielectric layer is made of silicon nitride and / or silicon oxide.

[0017] In one exemplary embodiment of this disclosure, the bit line is a straight line.

[0018] According to one aspect of this disclosure, a method for manufacturing a storage array is provided, comprising:

[0019] Provide SOI wafers;

[0020] The device layer silicon of the SOI wafer is etched to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.

[0021] n parallel rows of bit lines are fabricated on the silicon device layer, and each bit line wraps around the lower part of a row of single-crystal silicon pillars;

[0022] A dielectric is deposited on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar;

[0023] After surface oxidation of the single-crystal silicon pillar, m / 2 rows of parallel word lines are manufactured on the dielectric layer. Each word line connects the middle of two adjacent rows of single-crystal silicon pillars. Each word line encloses a different single-crystal silicon pillar. The word lines are straight lines, and the upper surface of the word lines is not higher than the upper surface of the single-crystal silicon pillar.

[0024] A capacitor is fabricated above the upper part of the single-crystal silicon pillar.

[0025] In one exemplary embodiment of this disclosure, the fabrication of n parallel rows of bit lines on the device layer silicon includes:

[0026] The device layer silicon is etched downwards into n columns of parallel bit lines.

[0027] In one exemplary embodiment of this disclosure, the fabrication of n parallel rows of bit lines on the device layer silicon includes:

[0028] The bit lines are fabricated in n parallel columns on the silicon layer of the device by a deposition process.

[0029] In one exemplary embodiment of this disclosure, the capacitor is aligned with the axis of the monocrystalline silicon pillar.

[0030] In one exemplary embodiment of this disclosure, the cross-section of the single-crystal silicon pillar is circular.

[0031] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal, and the spacing between the word lines is equal.

[0032] In one exemplary embodiment of this disclosure, the spacing between the word lines is equal to the spacing between the bit lines.

[0033] In one exemplary embodiment of this disclosure, the spacing between the bit lines is equal to the spacing between the word lines. times.

[0034] In one exemplary embodiment of this disclosure, the dielectric layer is made of silicon nitride and / or silicon oxide.

[0035] In one exemplary embodiment of this disclosure, the bit line is a straight line.

[0036] In one exemplary embodiment of this disclosure, it further includes:

[0037] Before etching the single-crystal silicon pillar, a first ion is implanted into the silicon layer of the device.

[0038] In one exemplary embodiment of this disclosure, it further includes:

[0039] Before or after the bit line is fabricated, a second ion is injected into the region corresponding to the bit line.

[0040] The embodiments disclosed herein, by setting storage cells in a honeycomb pattern, have a higher storage cell density than the storage cells arranged in a checkerboard pattern in related technologies, which can effectively increase the number of storage cells in the storage array and increase the storage capacity per unit area of ​​the chip.

[0041] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0043] Figure 1 It's 4F 2 Top view of the structure;

[0044] Figure 2 This is a schematic diagram of the structure of the storage array in an exemplary embodiment of this disclosure.

[0045] Figure 3 This is a flowchart of the manufacturing process of the storage array in this embodiment of the present disclosure.

[0046] Figure 4 yes Figure 3 A schematic diagram of step S31.

[0047] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of step S32.

[0048] Figures 6A to 6D yes Figure 3 A schematic diagram of step S33.

[0049] Figure 7 yes Figure 3 A schematic diagram of step S34.

[0050] Figure 8A and Figure 8B yes Figure 3 A schematic diagram of step S35.

[0051] Figure 9A and Figure 9B yes Figure 3 A schematic diagram of step S36. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of these specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0053] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted.

[0054] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0055] Figure 2 This is a schematic diagram of the structure of the storage array in an exemplary embodiment of this disclosure.

[0056] refer to Figure 2 The storage array 200 may include:

[0057] There are mn / 2 single-crystal silicon pillars 21 arranged in m rows and n columns. The single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.

[0058] n parallel bit lines 22, each bit line wrapping around the lower part of a column of single-crystal silicon pillars;

[0059] The word lines 23 are arranged in parallel rows of m / 2 rows. Each word line connects the middle of two adjacent rows of single-crystal silicon pillars. Each single-crystal silicon pillar 21 connected by each word line 23 is different. The word lines are straight lines.

[0060] There are two capacitors, mn / 2 and 24, with their lower plates electrically connected to the upper parts of the mn / 2 single-crystal silicon pillars.

[0061] exist Figure 2 In the illustrated embodiment, bit line 12 and word line 13 are both straight lines, the cross-section of the single-crystal silicon pillar 21 is circular, the cross-section of the capacitor 24 is circular, and the capacitor is aligned with the axis of the single-crystal silicon pillar. As can be seen from the figure, compared to... Figure 1The storage cells in this embodiment are arranged in a checkerboard pattern, resulting in a higher storage cell density without sacrificing the radius of the capacitors. In other embodiments, the cross-sections of the single-crystal silicon pillars and capacitors may also be square or other shapes, and this disclosure is not limited thereto.

[0062] In addition, Figure 2 In the illustrated embodiment, the spacing between bit lines 22 is equal, and the spacing between word lines 23 is equal (the spacing here refers to the spacing between adjacent straight sections of two word lines); in other embodiments of this disclosure, the spacing between bit lines 22 may also have two or more sizes, and the spacing between word lines 23 may also have two or more sizes, and this disclosure does not impose any special restrictions on this.

[0063] When the spacing between bit lines 22 and word lines 23 are equal, the spacing between word lines 23 can be set to be equal to the spacing between bit lines 22. This means that the spacing between single-crystal silicon pillars in different rows is greater than the spacing between adjacent single-crystal silicon pillars in the same row. In some embodiments, the spacing between single-crystal silicon pillars in different rows can also be set to be equal to the spacing between adjacent single-crystal silicon pillars in the same row, that is, the spacing between word lines 23 is set to be the spacing between bit lines 22. times.

[0064] Figure 3 This is a flowchart of the manufacturing process of the storage array in this embodiment of the present disclosure.

[0065] refer to Figure 3 The storage array manufacturing method 300 may include:

[0066] Step S31: Provide an SOI wafer;

[0067] Step S32: Etch the device layer silicon of the SOI wafer to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns. The single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns.

[0068] Step S33: Fabricate n parallel bit lines on the device layer silicon, with each bit line wrapping around the lower part of a column of single-crystal silicon pillars;

[0069] Step S34: Deposit dielectric on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar;

[0070] Step S35: After surface oxidation of the single-crystal silicon pillars, m / 2 rows of parallel word lines are manufactured on the dielectric layer. Each word line connects the middle of two adjacent rows of single-crystal silicon pillars. The single-crystal silicon pillars connected by each word line are different. The word lines are straight lines and the upper surface of the word lines is not higher than the upper surface of the single-crystal silicon pillars.

[0071] Step S36: Fabricate a capacitor above the upper part of the single-crystal silicon pillar.

[0072] Figure 4 Figure 9 is Figure 3 The process flow diagram shown is a schematic diagram of the technological process.

[0073] Figure 4 yes Figure 3 A schematic diagram of step S31.

[0074] In this embodiment of the disclosure, the memory array is fabricated on an SOI wafer. SOI (Silicon-On-Insulator) refers to the presence of a buried oxide layer 42 (SiO2) between a substrate silicon layer 41 and a device layer silicon layer 43.

[0075] Figure 5A and Figure 5B yes Figure 3 A schematic diagram of step S32.

[0076] refer to Figure 5A and Figure 5B The device layer silicon 43 can be etched into mn / 2 single-crystal silicon pillars 21 arranged in m rows and n columns by processes such as masking and exposure. Figure 5B As shown, m = 10, n = 5, number of single-crystal silicon pillars = 25), such that the single-crystal silicon pillars 21 are located in odd-numbered rows and even-numbered columns, or in odd-numbered rows and even-numbered columns. In one embodiment of this disclosure, the pillar holes (i.e., the cross-section of the single-crystal silicon pillars) are circular to provide a larger conductive area with a smaller perimeter. In other embodiments, the pillar holes (i.e., the cross-section of the single-crystal silicon pillars) may also be other shapes, which can be determined by those skilled in the art.

[0077] In one embodiment, if subsequent Figure 6A In the etching process shown to manufacture bit lines, in step S32, it is not necessary to control the etching of the single-crystal silicon pillar down to the oxide layer 42; a certain thickness of the device layer silicon is retained for etching the bit lines. In another embodiment, if subsequent... Figure 6C The deposition process shown creates bit lines. In order to ensure the insulation between the single-crystal silicon pillars, the etching depth of the oxide layer 42 can be controlled when forming the single-crystal silicon pillars.

[0078] Figure 5B yes Figure 5A The diagram shows a top-down view of the manufacturing process. From Figure 5B As can be seen, due to the staggered arrangement of the single-crystal silicon pillars, the horizontal distance between the single-crystal silicon pillars can be reduced, allowing more single-crystal silicon pillars to be manufactured in the same area, thus providing conditions for the subsequent manufacture of more memory cells.

[0079] Figures 6A to 6D yes Figure 3 A schematic diagram of step S33.

[0080] refer to Figure 6A In one embodiment, the method of fabricating n parallel rows of bit lines on the device layer silicon can be achieved, for example, by etching the device layer silicon, i.e., etching the device layer silicon downwards to fabricate n parallel rows of bit lines 22.

[0081] Because the doping types of the silicon in the device layer are different, and the doping type of the bit line region needs to be different from that of the silicon in the device layer, a first ion implantation is required before etching the single-crystal silicon pillar. A second ion implantation is also required in the bit line region before or after etching the bit line to change the doping type of the bit line region (e.g., ...). Figure 6B As shown), it finally forms as follows Figure 6C The effect shown.

[0082] In another embodiment, the method of fabricating n parallel rows of bit lines 22 on the device layer silicon can be achieved, for example, by performing a deposition process on the device layer silicon (the implementation effect is as follows). Figure 6C (As shown). The deposition process can be applied to the fabrication of bit lines in both semiconductor and metal materials.

[0083] Figure 6D yes Figure 6C A top-down view of the effect shown. From Figure 6D As can be seen, due to the staggered arrangement of the single-crystal silicon pillars, the horizontal distance between the single-crystal silicon pillars is reduced, and the distance between the bit lines 22 is also reduced, allowing more bit lines to be set per unit area.

[0084] Figure 7 yes Figure 3 A schematic diagram of step S34 is shown. In step S34, the material of the deposited dielectric layer 44 is, for example, silicon dioxide (SiO2) or silicon nitride (Si3N4), and this disclosure does not impose any special limitations on it. The dielectric layer 44 can not only effectively isolate bit lines, but also isolate bit lines and word lines, and the area of ​​the single-crystal silicon pillar it encloses corresponds to the source of the transistor.

[0085] Figure 8A and Figure 8B yes Figure 3 A schematic diagram of step S35. In step S35, bit lines connecting to the gate are fabricated. First, the surface of the single-crystal silicon pillar corresponding to the bit line region is oxidized to create a gate oxide layer. Then, m / 2 rows of parallel metal word lines 23 are fabricated through metal deposition and etching (including dry etching or wet etching) processes.

[0086] In this embodiment of the present disclosure, each word line 23 connects two adjacent rows of single-crystal silicon pillars 21. In this embodiment of the present disclosure, both the word line 23 and the bit line 22 are straight lines. Those skilled in the art can set the width of the word line 23 so that the word line 23 can connect as many adjacent rows of single-crystal silicon pillars as possible and evenly, and the word lines are not connected to each other.

[0087] Figure 8B yes Figure 8A A top view diagram illustrating the steps shown.

[0088] Figure 9A and Figure 9B yes Figure 3 A schematic diagram of step S36.

[0089] refer to Figure 9A Storage capacitors 24 can be fabricated above the upper part of the single-crystal silicon pillar 21, forming a structure like... Figure 2 or Figure 9B The storage array structure is shown. Because adjacent columns of single-crystal silicon pillars are located in different rows in this embodiment, after manufacturing the storage capacitors, from... Figure 9A From a side viewpoint, the storage capacitors block each other. The structure of storage capacitor 24 is, for example, cup-shaped.

[0090] from Figure 9B As can be seen, due to the staggered arrangement of the single-crystal silicon pillars, the horizontal distance between the pillars is reduced. Correspondingly, the storage capacitors 24 can achieve a higher density arrangement while maintaining the same diameter, thereby manufacturing more storage cells per unit area and effectively increasing the storage capacity of the storage array per unit area. With the same number of storage cells, Figure 9B The structure shown is relatively Figure 1 The structure shown occupies 13% less area, which can effectively reduce the size of the memory chip without reducing the storage capacity.

[0091] In summary, the memory array manufacturing method provided in this disclosure can effectively increase the density of memory cells and reduce manufacturing costs by setting staggered single-crystal silicon pillars.

[0092] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A storage array, characterized in that, include: mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns; n parallel bit lines, each bit line wrapping around the lower part of a column of single-crystal silicon pillars; The word lines are arranged in parallel rows of m / 2 rows, each word line connecting the middle of two adjacent rows of single-crystal silicon pillars. Each word line connects to a different single-crystal silicon pillar, and the word lines are straight lines. mn / 2 capacitors, the lower plates of which are electrically connected to the upper parts of mn / 2 single-crystal silicon pillars.

2. The storage array as described in claim 1, characterized in that, The capacitor is aligned with the axis of the monocrystalline silicon pillar.

3. The storage array as described in claim 1, characterized in that, The cross-section of the single-crystal silicon pillar is circular.

4. The storage array as described in claim 1, characterized in that, The spacing between the bit lines is equal, and the spacing between the word lines is equal.

5. The storage array as described in claim 4, characterized in that, The spacing between the word lines is equal to the spacing between the bit lines.

6. The storage array as described in claim 4, characterized in that, The spacing between the bit lines is the same as the spacing between the word lines. times.

7. The storage array as claimed in claim 1, characterized in that, A dielectric layer is disposed between the bit line and the word line, and the dielectric layer is made of silicon nitride and / or silicon oxide.

8. The storage array as claimed in claim 1, characterized in that, The bit line is a straight line.

9. A method for manufacturing a storage array, characterized in that, include: Provide SOI wafers; The device layer silicon of the SOI wafer is etched to form mn / 2 single-crystal silicon pillars arranged in m rows and n columns, wherein the single-crystal silicon pillars are located in odd rows and even columns and even rows and odd columns, or in odd rows and odd columns and even rows and even columns. n parallel rows of bit lines are fabricated on the silicon device layer, and each bit line wraps around the lower part of a row of single-crystal silicon pillars; A dielectric is deposited on the bit line to create a dielectric layer that encloses the bit line and the lower part of the single-crystal silicon pillar; After surface oxidation of the single-crystal silicon pillar, m / 2 rows of parallel word lines are manufactured on the dielectric layer. Each word line connects the middle of two adjacent rows of single-crystal silicon pillars. Each word line encloses a different single-crystal silicon pillar. The word lines are straight lines, and the upper surface of the word lines is not higher than the upper surface of the single-crystal silicon pillar. A capacitor is fabricated above the upper part of the single-crystal silicon pillar.

10. The method for manufacturing a storage array as described in claim 9, characterized in that, The fabrication of n parallel bit lines on the silicon device layer includes: The device layer silicon is etched downwards into n columns of parallel bit lines.

11. The method for manufacturing a storage array as described in claim 9, characterized in that, The fabrication of n parallel bit lines on the silicon device layer includes: The bit lines are fabricated in n parallel columns on the silicon layer of the device by a deposition process.

12. The method for manufacturing a storage array as described in claim 9, characterized in that, The capacitor is aligned with the axis of the monocrystalline silicon pillar.

13. The method for manufacturing a storage array as described in claim 9, characterized in that, The cross-section of the single-crystal silicon pillar is circular.

14. The method for manufacturing a storage array as described in claim 9, characterized in that, The spacing between the bit lines is equal, and the spacing between the word lines is equal.

15. The method for manufacturing a storage array as described in claim 14, characterized in that, The spacing between the word lines is equal to the spacing between the bit lines.

16. The method for manufacturing a storage array as described in claim 14, characterized in that, The spacing between the bit lines is the same as the spacing between the word lines. times.

17. The method for manufacturing a storage array as described in claim 9, characterized in that, The dielectric layer is made of silicon nitride and / or silicon oxide.

18. The method for manufacturing a storage array as described in claim 9, characterized in that, The bit line is a straight line.

19. The method for manufacturing a storage array as described in claim 9, characterized in that, Also includes: Before etching the single-crystal silicon pillar, a first ion is implanted into the silicon layer of the device.

20. The method for manufacturing a storage array as described in claim 10, characterized in that, Also includes: Before or after the bit line is fabricated, a second ion is injected into the region corresponding to the bit line.

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