Storage device and method of operating the same

Abstract

Storage devices and methods of operating the same are provided. The storage device includes a non-volatile memory and a memory controller. The non-volatile memory includes memory blocks each including a plurality of word lines. The memory controller determines a word line strength for each of the plurality of word lines, adjusts a state count for each of the plurality of word lines based on the word line strength, and adjusts a program parameter for each of the plurality of word lines to reduce program time variation among the plurality of word lines.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0156120, filed on November 28, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a storage device, and more specifically, to a storage device and a method of operating thereof that adjusts the number of states programmed in a non-volatile memory cell in units of word lines. Background Technology

[0003] In non-volatile memory, flash memory retains its stored data even when power is cut off. During programming and erasing operations performed on the word lines of flash memory, high voltage is applied to the memory cells connected to the word lines. Therefore, the word lines age over time, and their strength deteriorates. When the lifetime of one word line included in a memory block ends, the lifetime of that memory block ends. In other words, if one word line in a memory block fails, the entire memory block becomes unusable. Summary of the Invention

[0004] One aspect is to provide a storage device and a method of operating the same, the storage device and the method of operating the same being to provide loss equalization for each word line based on the strength adjustment of a state count of each of a plurality of word lines, the state count representing the number of levels on each of the plurality of word lines that program a memory cell.

[0005] According to one aspect of the embodiments, a storage device is provided, the storage device comprising: a non-volatile memory including a plurality of memory blocks, each comprising a plurality of word lines; and a memory controller configured to determine a word line strength of each of the plurality of word lines, adjust a state count of each of the plurality of word lines based on the word line strength, and adjust programming parameters of each of the plurality of word lines to reduce programming time variations among the plurality of word lines.

[0006] According to another aspect of the embodiments, a method of operating a storage device including non-volatile memory is provided, the method comprising: calculating the word line strength of each word line among a plurality of word lines of the non-volatile memory; adjusting the state count of each word line among the plurality of word lines based on the word line strength; and adjusting the programming parameters of each word line among the plurality of word lines to reduce the programming time variation among the plurality of word lines.

[0007] According to another aspect of the embodiments, a method of operating a storage device including non-volatile memory is provided, the method comprising: calculating the word line strength of each word line among a plurality of word lines included in the non-volatile memory; grouping the plurality of word lines into a plurality of word line groups based on the word line strength; adjusting the state count of the word lines in each of the plurality of word line groups according to the word line strength; and adjusting the programming parameters of the word lines in each of the plurality of word line groups according to the word line groups to reduce the programming time variation between the word lines of the plurality of word line groups. Attached Figure Description

[0008] Various embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a storage device according to an embodiment;

[0010] Figure 2A and Figure 2B Examples of adjusting the state count of word lines in a storage device according to various embodiments are shown;

[0011] Figure 3A This is a block diagram illustrating a memory controller according to an embodiment, and Figure 3B This illustrates an embodiment. Figure 3A A flowchart of the operation method of the memory controller;

[0012] Figures 4A to 4C This is a flowchart illustrating a method for determining whether to adjust the state count in a memory controller according to various embodiments;

[0013] Figure 5 This is a system diagram of a memory controller according to an embodiment;

[0014] Figure 6 This is a block diagram illustrating a non-volatile memory according to an embodiment;

[0015] Figure 7A and Figure 7B This illustrates various embodiments. Figure 6 A diagram illustrating an example implementation of a memory cell array with non-volatile components;

[0016] Figure 8A This is a circuit diagram representing an example of a memory block included in a memory controller according to an embodiment, and Figure 8B According to the embodiments Figure 8A A 3D view of the memory block;

[0017] Figure 9A It is a graph showing the threshold voltage distribution of word lines according to various embodiments, and Figure 9B This illustrates an embodiment. Figure 9A A table of programming parameters and status metrics for each word line;

[0018] Figure 10 This is a timing diagram illustrating the programming operation of a non-volatile memory according to an embodiment;

[0019] Figure 11A This is a graph showing the threshold voltage distribution of word lines when the state count of each word line is adjusted according to an embodiment, and Figure 11B This illustrates an embodiment. Figure 11A A table of programming parameters and status metrics for each word line;

[0020] Figure 12A This is a graph showing the threshold voltage distribution of the word lines when the state count of the word lines is adjusted according to an embodiment, and Figure 12B This illustrates an embodiment. Figure 12A A table of programming parameters and status metrics for each word line;

[0021] Figure 13 This is a table describing a method for storing fractional bits in each memory cell according to an embodiment;

[0022] Figure 14A and Figure 14B Describes methods for storing fractional bits in each memory cell according to various embodiments;

[0023] Figure 15A This is a block diagram representing a memory controller according to an embodiment, and Figure 15B According to the embodiments Figure 15A A flowchart of the operation method of the memory controller;

[0024] Figure 16 The operation method of the reinforcement learning module according to an embodiment is shown;

[0025] Figure 17A This is a block diagram representing a memory controller according to an embodiment, and Figure 17B According to the embodiments Figure 17A A flowchart of the operation method of the memory controller;

[0026] Figure 18A and Figure 18B This illustrates the grouping of multiple word lines according to various embodiments; and

[0027] Figure 19 This is a block diagram representing a solid-state drive (SSD) system according to an embodiment. Detailed Implementation

[0028] In the following description, various embodiments will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a storage device 100 according to an embodiment.

[0030] Reference Figure 1 The storage device 100 may include a memory controller 110 and a non-volatile memory (NVM) 120. The storage device 100 may communicate with a host through various interfaces to store data received from the host or send data stored therein to the host.

[0031] In some embodiments, storage device 100 may be an internal memory device embedded in an electronic device. For example, storage device 100 may be a solid-state drive (SSD), embedded universal flash memory (UFS), or embedded multimedia card (eMMC). In some embodiments, storage device 100 may be an external memory that can be attached to / removed from an electronic device. For example, storage device 100 may be a portable SSD, UFS, compact flash memory (CF) card, secure digital card (SD) card, micro-secure digital card (micro-SD) card, mini-secure digital card (mini-SD) card, extreme digital card (xD) card, or Memory Stick.

[0032] The electronic device equipped with or connected to the storage device 100 can be, for example, a personal computer (PC), a data server, network-attached storage, an Internet of Things (IoT) device, or a portable electronic device. Examples of portable electronic devices may include laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital cameras, digital camcorders, audio equipment, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game controllers, e-readers, or wearable devices.

[0033] The non-volatile memory 120 can represent a memory or memory device that has the characteristic that the data stored therein is retained even when the power is cut off. Therefore, even when the power supply to the storage device 100 is cut off, the data stored in the non-volatile memory 120 can be retained. The data can be, for example, user data.

[0034] The non-volatile memory 120 can operate under the control of the memory controller 110. For example, the non-volatile memory 120 can receive a command CMD, an address ADDR, and a control signal CTRL from the memory controller 110, and in response to the received command CMD, the non-volatile memory 120 can write data DT corresponding to the address ADDR, or it can read data DT corresponding to the address ADDR and send the read data DT to the memory controller 110.

[0035] The non-volatile memory 120 may include multiple memory blocks BLK1 to BLKz, each of which may include multiple word lines. Here, z may represent a positive integer of 2 or greater, so the number of memory blocks BLK1 to BLKz may vary depending on various embodiments. Each word line may connect to multiple memory cells, and the multiple memory cells connected to the same word line may be configured as physical pages. When a memory cell is a multi-layered cell storing two or more bits of data, data corresponding to multiple logical pages may be stored in a single word line. For example, a memory block may be a unit of erasure, and a page may be a unit of programming and reading. In other words, according to embodiments, erasure may be performed per memory block, and programming and reading may be performed per page. In some embodiments, the non-volatile memory 120 may include multiple planes, multiple dies, or multiple chips.

[0036] In some embodiments, the non-volatile memory 120 may include a NAND flash memory device. In some embodiments, the non-volatile memory 120 may be a planar NAND flash memory device having a two-dimensional (2D) horizontal array structure, or it may be a vertical NAND (VNAND) flash memory device having a three-dimensional (3D) array structure. However, these are merely examples, and embodiments are not limited thereto; the non-volatile memory 120 may include resistive memory devices (such as resistive random access memory (RAM) (ReRAM), phase-change RAM (PRAM), and / or magnetic RAM (MRAM)). Hereinafter, for ease of description, the non-volatile memory 120 will be described as NAND flash memory, but it is understood that embodiments are not limited thereto.

[0037] The memory controller 110 can control the overall operation of the storage device 100. The memory controller 110 can control write operations, read operations, and erase operations performed on the non-volatile memory 120, and can set and adjust parameters associated with write operations, read operations, and / or erase operations.

[0038] For example, in response to a request from the host, the memory controller 110 can write data received from the host into the non-volatile memory 120, or it can read data DT from the non-volatile memory 120 and send the read data DT to the host. The memory controller 110 can encode the data DT and send the encoded data to the non-volatile memory 120, which can program the data encoded in page units into the corresponding word lines. The memory controller 110 can decode the data DT read from the non-volatile memory 120.

[0039] Memory cells can be programmed to one of several states (i.e., erase state and one or more programming states) based on a set number of bits (integer bits or non-integer bits, e.g., fractional bits). For example, when a memory cell stores 2 bits of data, it can be programmed to have four (=2) states. 2 One of six states. When a memory cell stores 2.5 bits of data, it can be programmed into one of six states. Therefore, data can be written to the non-volatile memory 120.

[0040] The memory controller 110 can set or adjust the state count of each of the multiple word lines included in the unit memory on a memory-by-memory basis for the non-volatile memory 120. Specifically, the memory controller 110 can set or adjust the number (i.e., state count) of states (erase states and at least one programming state) that can be programmed in memory cells connected to corresponding word lines of the multiple word lines. In this case, the unit memory can be a unit block, a unit chip, or a unit wafer.

[0041] The memory controller 110 can calculate multiple word line strengths (hereinafter referred to as "strengths") corresponding to multiple word lines respectively (i.e., the strength of each word line), and can set or adjust the state count of each of the multiple word lines based on the calculated multiple strengths. The memory controller 110 can set or adjust the state count of each of the multiple word lines such that more states are assigned to word lines with relatively high strengths (i.e., strong word lines) compared to word lines with relatively low strengths (i.e., weak word lines).

[0042] In NAND flash memory, when a large number of programming or erasing operations are performed on a given word line, stress (e.g., high voltage) is repeatedly applied to the word line, causing it to age. The stress applied to each word line can vary over time, so multiple word lines can have different strengths (i.e., word line strength). As word lines age, their word line strength decreases, making the word lines weaker.

[0043] According to various embodiments, the memory controller 110 can adjust the state count of each of the multiple word lines based on multiple strengths corresponding to the multiple word lines, thereby performing wear leveling on the multiple word lines. As the number of states assigned to a word line increases, the stress applied to the word line increases when the word line is programmed. Therefore, a small number of states can be assigned to weak word lines, and a relatively large number of states can be assigned to strong word lines, thereby reducing the stress applied to weak word lines. Thus, it is possible to prevent certain word lines from aging faster than other word lines.

[0044] In some embodiments, the memory controller 110 can group multiple word lines into multiple word line groups based on the word line strength of each word line, and can dynamically adjust the state count and programming parameters of the word lines in each of the multiple word line groups. In other words, in some embodiments, word lines included in a word line group can be adjusted together, rather than individually.

[0045] In some embodiments, the memory controller 110 can adjust the state count of each of the multiple word lines using reinforcement learning. The memory controller 110 can perform reinforcement learning based on pre-collected profile information.

[0046] In some embodiments, the memory controller 110 may periodically adjust the state count of each of the multiple word lines during the runtime of the storage device 100. In other embodiments, the memory controller 110 may adjust the state count of each of the multiple word lines non-periodically during the runtime of the storage device 100. However, the embodiments are not limited thereto. In other embodiments, the memory controller 110 may preset the state count of each of the multiple word lines (e.g., a preset state count stored in memory in advance) and may control programming and reading operations of the non-volatile memory 120 based on the preset state count during the runtime of the storage device 100.

[0047] In some embodiments, the memory controller 110 can adjust the state count of each of a plurality of word lines to dynamically adjust the programming parameters of each of the plurality of word lines. For example, the programming time of a word line with a high state count may be longer than the programming time of a word line with a low state count. In this case, the programming time may represent the time spent from the start of programming operations on the word line until the programming operations are completed. The memory controller 110 can dynamically adjust the programming parameters of each of the plurality of word lines to reduce the variation in programming time among the plurality of word lines.

[0048] As described above, the storage device 100 according to the embodiment can calculate the strength of each of a plurality of word lines and can adjust the state count of each word line based on the calculated strengths corresponding to the plurality of word lines respectively. A relatively large number of states can be assigned to strong word lines, and a relatively small number of states can be assigned to weak word lines. Therefore, the state count of strong word lines can be increased, and the state count of weak word lines can be decreased. After the state count is adjusted, the storage device 100 can dynamically adjust the programming parameters of each word line to reduce the programming time variation between word lines. For example, the programming time can be increased for word lines with a small number of states compared to the programming time for word lines with a large number of states.

[0049] When it is no longer possible to perform write and / or read operations on at least one of the multiple word lines—in other words, when it is no longer possible to decode the data read from the word line—write and read operations can be stopped on the memory block including that word line. The storage device 100 according to the embodiment can adjust the state count of each word line such that a relatively large number of states are assigned to strong word lines and a relatively small number of states are assigned to weak word lines, thereby performing wear leveling on each word line. Therefore, write and / or read operations can be prevented from failing due to aging of specific word lines, thus increasing the lifetime of each memory block. Therefore, the reliability of the non-volatile memory 120 and the storage device 100 can be enhanced.

[0050] Figure 2A and Figure 2B Examples of adjusting the state count of word lines in a storage device according to various embodiments are shown.

[0051] For ease of description, Figure 2A In the example, two word lines (e.g., the first word line WL1 and the second word line WL2) will be described. Figure 2B In this example, three word lines (e.g., first word line WL1, second word line WL2, and third word line WL3) will be described. However, the embodiments are not limited to this, and the state count adjustment can be performed on a memory-by-memory basis. For example, the state count adjustment can be performed on multiple word lines included in a memory block or memory chip.

[0052] Reference Figure 2A Eight states (e.g., erase state E and first programming states P1 through seventh programming states P7) can be applied to each of the first word line WL1 and the second word line WL2, and during the programming process, the first word line WL1 and the second word line WL2 can be programmed into one of the eight states. Therefore, 3 bits of data can be stored in each of the memory cells of the first word line WL1 and the second word line WL2.

[0053] Because programming, reading, and erasing operations are performed on each of the first word line WL1 and the second word line WL2, both word lines WL1 and WL2 will age over time. For example, if the second word line WL2 is used more frequently over time, the strength of the first word line WL1 may increase relatively, while the strength of the second word line WL2 may decrease relatively. For example, when the number of times the first word line WL1 is programmed and / or read is less than the number of times the second word line WL2 is programmed and / or read, the strength of the first word line WL1 may be greater than the strength of the second word line WL2.

[0054] The state counts of each of the first word lines WL1 and WL2 can be adjusted so that a large number of states are assigned to strong word lines and a small number of states are assigned to weak word lines. The state count of the first word line WL1 can be increased, and the state count of the second word line WL2 can be decreased. For example, the state count of the first word line WL1 can be increased from eight to twelve, and the state count of the second word line WL2 can be decreased from eight to four. As shown, sixteen states (e.g., erase state E and first programming states P1 to fifteenth programming states P15) can be assigned to the first word line WL1, and four states (e.g., erase state E and first programming states P1 to third programming states P3) can be assigned to the second word line WL2. Therefore, 4 bits of data can be stored in one memory cell of the first word line WL1, and 2 bits of data can be stored in one memory cell of the second word line WL2.

[0055] Reference Figure 2B Four states (i.e., erase state E and first programming states P1 to third programming states P3) can be assigned to each of the first word line WL1, the second word line WL2, and the third word line WL3, and during the programming process, the first word line WL1, the second word line WL2, and the third word line WL3 can be programmed into one of the four states. Therefore, 2 bits of data can be stored in one memory cell of the first word line WL1, one memory cell of the second word line WL2, and one memory cell of the third word line WL3.

[0056] Because each word line performs programming, reading, and erasing operations, the first word line WL1, the second word line WL2, and the third word line WL3 will age over time. The strength of the first word line WL1, the second word line WL2, and the third word line WL3 can be -1, -2, and -3, respectively. That is, the first word line WL1 can be the strongest, and the third word line WL3 can be the weakest.

[0057] The state counts of each of the first word line WL1, the second word line WL2, and the third word line WL3 can be adjusted so that a large number of states are assigned to strong word lines and a small number of states are assigned to weak word lines. For example, the state count of the first word line WL1 can be increased from four to six, the state count of the second word line WL2 can remain at four, and the state count of the third word line WL3 can be decreased from four to three. Therefore, 2.5 bits of data can be stored in one memory cell of the first word line WL1, 2 bits of data can be stored in one memory cell of the second word line WL2, and 1.5 bits of data can be stored in one memory cell of the third word line WL3.

[0058] As referenced above Figure 2A and Figure 2B The aforementioned configuration allows for state count adjustment to be performed, adjusting the state count of each of the multiple word lines based on the strength of each of the multiple word lines. In one embodiment, as... Figure 2B As shown, the state count of the word line can have 2 in addition to representing integer bits. s Values ​​other than (where s is a positive integer), such as fractional bit data, can be stored in a memory cell of the word line.

[0059] Figure 3A This is a block diagram illustrating a memory controller according to an embodiment. Figure 3B This illustrates an embodiment. Figure 3A A flowchart of the operation method of the memory controller. Figure 3B The operation method can be performed on the storage device ( Figure 1 The runtime of the non-volatile memory 120 (e.g., processing of write, read and erase operations on the non-volatile memory 120 based on host requests) is performed, or it may be performed before the runtime (e.g., during the manufacturing or booting process of the storage device).

[0060] Reference Figure 3A The memory controller 110 may include an intensity calculation module (SCM), a state count adjustment module (CAM), and a programming parameter control module (PCM).

[0061] In various embodiments, elements according to the embodiments may be referred to by the term "module". A "module" may be implemented as various hardware devices (such as integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware or software driven in the hardware device, or a combination of hardware devices and software. In addition, a "module" may include intellectual property (IP) or circuitry configured with semiconductor devices.

[0062] The Strength Calculation Module (SCM) can calculate the strength of each of multiple word lines. The SCM can calculate the strength of each word line based on programming parameters and state metrics (e.g., state metrics associated with programming, reading, and erasing operations).

[0063] The State Count Adjustment Module (CAM) can adjust the state count of each of the multiple word lines based on the calculated strength of each of the multiple word lines.

[0064] The programming parameter control module (PCM) can adjust the programming parameters for each of the multiple word lines. For example, programming parameters may include at least one of a programming start voltage, a programming voltage difference, and a programming verification voltage. The PCM can adjust the programming parameters to reduce the time difference between performing programming operations on the multiple word lines (hereinafter referred to as programming time variation).

[0065] Reference Figure 3B In operation S110, the memory controller 110 can obtain state metrics for multiple word lines. For example, the strength calculation module SCM can obtain state metrics based on signals received from the non-volatile memory 120. State metrics may include, for example, actual programming time, erase time, read time, read error bits, read level offset values, and state counts. For example, when a programming operation is performed on each word line of the non-volatile memory 120, the memory controller 110 can obtain and store the actual programming time. In some embodiments, the memory controller 110 can obtain and store state metrics each time a programming operation is performed; in other embodiments, the memory controller 110 can obtain and store state metrics periodically.

[0066] In operation S120, the strength calculation module SCM can calculate the strength of multiple word lines corresponding to multiple word lines. In other words, the strength calculation module SCM can calculate the strength of each of the multiple word lines. The strength calculation module SCM can calculate the strength of each word line based on programming parameters and state measurements acquired in operation S110.

[0067] In one embodiment, the strength calculation module (SCM) can calculate strength based on the expected programming time and the actual programming time for each word line. For example, the SCM can calculate the expected programming time for each word line based on preset programming parameters and preset state counts, and can calculate strength based on the difference between the expected programming time and the actual programming time. In one embodiment, the SCM can include a strength calculation function that uses programming parameters and at least one state metric as variables. However, the embodiments are not limited to this; for example, the SCM can further calculate strength based on at least one of other state metrics (e.g., erase time, read error bit, and read level offset value).

[0068] In operation S130, the State Count Adjustment (CAM) module can adjust the state count of each of multiple word lines based on the strength of multiple word lines. The CAM module adjusts the state count of each of the multiple word lines so that a large number of states are assigned to strong word lines and a small number of states are assigned to weak word lines. Therefore, loss equalization can be performed on each word line, and the strength difference between word lines can be reduced.

[0069] Operations S120 and S130 can be performed based on reinforcement learning. For example, the strength calculation module SCM and the state count adjustment module CAM can both be implemented as agents for reinforcement learning, which can calculate the state count for each word line based on programming time, state counts, programming parameters, and state metrics stored in word lines. The following will refer to... Figures 15A to 15B The process of calculating the state count for each word line based on reinforcement learning is described in detail.

[0070] In operation S140, the programming parameter control module (PCM) can adjust the programming parameters of each of the multiple word lines based on the adjustment of the state count. The PCM can adjust the programming parameters of each of the multiple word lines to reduce the difference in time between performing programming operations on the multiple word lines (hereinafter referred to as programming time variation).

[0071] For example, in Figure 2A In the example, assuming the state count of the first word line WL1 is adjusted to twelve and the state count of the second word line WL2 is adjusted to four, when programming the first word line WL1 and the second word line WL2 based on the same parameters, the time required to program the first word line WL1 (i.e., the programming time of the first word line WL1) will become longer than the programming time of the second word line WL2. In other words, if in Figure 2A The fifteen programming states P1 to P15 of the first word line WL1 shown at the bottom all have the same characteristics as in... Figure 2A The programming times for the seven programming states P1 to P7 of the first word line WL1 shown at the top are the same, and similarly, if in Figure 2A The three programming states P1 to 3 of the second word line WL2 shown at the bottom all have the same characteristics as in... Figure 2AIf the programming times of the seven programming states P1 to P7 of the second word line WL2 shown at the top are the same, then the total programming time of the adjusted first word line WL1 will become significantly longer than the total programming time of the adjusted second word line WL2. Therefore, the programming parameter control module PCM can adjust one or more programming parameters of the first word line WL1 and / or the second word line WL2 so that the actual programming time of the first word line WL1 becomes more similar to the actual programming time of the second word line WL2. In other words, as shown in Figure 2A As shown at the bottom, the programming time for each state of the first word line WL1 can be reduced, and the programming time for each state of the second word line WL2 can be increased, so that the total programming time for the first word line WL1 and the second word line WL2 becomes more similar (i.e., the programming time variation is reduced).

[0072] For example, the programming parameter control module (PCM) can increase the programming start voltage of the first word line WL1 or decrease the programming start voltage of the second word line WL2, thereby reducing the programming time variation between the first word line WL1 and the second word line WL2. The PCM can adjust at least one of the following for each of the multiple word lines: programming start voltage, programming voltage difference, and programming verification voltage.

[0073] In operation S150, the memory controller 110 may send a status count and programming parameters for each of a plurality of word lines to the non-volatile memory 120. In one embodiment, the memory controller 110 may send to the non-volatile memory 120 an address representing a word line to which programming will be performed, along with the corresponding word line's status count and one or more programming parameters. The non-volatile memory 120 may then perform programming on the word line represented by the address based on the received status count and one or more programming parameters. In another embodiment, the memory controller 110 may send to the non-volatile memory 120 a status count and one or more programming parameters for each of a plurality of word lines. The non-volatile memory 120 may store the received status count and one or more programming parameters for each of the plurality of word lines. Subsequently, the memory controller 110 may send to the non-volatile memory 120 an address to which programming will be performed. The non-volatile memory 120 may then perform programming on that word line based on the status count and one or more programming parameters corresponding to the received address.

[0074] Figures 4A to 4C This is a flowchart illustrating a method for determining whether to adjust the state count in a memory controller according to various embodiments.

[0075] Reference Figure 4A The memory controller 110 can determine whether to adjust the state count based on the programming time variation ΔtPGM between multiple word lines.

[0076] In operation S11, a programming operation can be performed on each of the multiple word lines. In operation S12, the memory controller 110 can monitor the programming time of each of the multiple word lines. The memory controller 110 can send a command CMD corresponding to the programming of the word line and can obtain the programming time of the word line based on response signals (e.g., ready signal and busy signal) received from the non-volatile memory 120. For example, the memory controller 110 can obtain the programming time based on the time elapsed from receiving the busy signal until receiving the ready signal.

[0077] In operation S13, the memory controller 110 can determine whether the programming time variation ΔtPGM between multiple word lines is equal to or greater than a threshold time Tth. For example, the memory controller 110 can determine whether the maximum value of the programming time variation ΔtPGM between multiple word lines is equal to or greater than the threshold time Tth. Optionally, the memory controller 110 can adjust the state count on a unit of at least two word lines and can determine whether the programming time variation ΔtPGM between at least two word lines is equal to or greater than the threshold time Tth.

[0078] When the programming time variation ΔtPGM among multiple word lines is equal to or greater than the threshold time Tth, in operation S14, the memory controller 110 can adjust the state count of each of the multiple word lines. The memory controller 110 can adjust the state count of each word line based on the above reference. Figure 3B The described method adjusts the state count.

[0079] On the other hand, when the programming time variation ΔtPGM between multiple word lines is less than the threshold time Tth, in operation S15, the memory controller 110 can maintain a state count for each of the multiple word lines. A predetermined state count can be maintained for each of the multiple word lines.

[0080] Reference Figure 4B The memory controller 110 can determine whether to adjust the status count based on the programming and erasing (P / E) cycles of multiple word lines.

[0081] In operation S21, programming, reading and erasing operations can be performed on each of the multiple word lines, and the memory controller 110 can store P / E cycles in units of word lines and update the P / E cycles whenever a programming or reading operation is performed.

[0082] In operation S22, the memory controller 110 may determine whether the P / E cycle is equal to or greater than a threshold VUth. For example, the memory controller 110 may determine whether the P / E cycle of one or more word lines is equal to or greater than the threshold VUth. As another example, the memory controller 110 may determine whether the average P / E cycle (i.e., the average P / E cycle) of each of the multiple word lines is equal to or greater than the threshold VUth.

[0083] When the P / E cycle (or average P / E cycle) is equal to or greater than the threshold VUth, in operation S23, the memory controller 110 can adjust the state count of each of the multiple word lines. When the P / E cycle (or average P / E cycle) is less than the threshold VUth, in operation S24, the memory controller 110 can maintain the state count of each of the multiple word lines.

[0084] Reference Figure 4C When storage device ( Figure 1 When the 100) is powered on, the memory controller 110 can determine whether to adjust the state count.

[0085] In operation S31, the storage device 100 can be powered on. The storage device 100 can receive power from an external source and can be powered on based on the received power. In operation S32, the memory controller 110 can determine whether to adjust the state count. For example, the memory controller 110 can determine during the boot process whether the conditions for adjusting the state count are met. For example, as referred to above... Figure 4A and Figure 4B The memory controller 110 can determine whether the conditions for adjusting the state count are met based on the programming time variation ΔtPGM between multiple word lines and / or the P / E cycles of the multiple word lines. However, the embodiment is not limited to this, and the conditions for performing the state count adjustment can be met by various methods.

[0086] When it is determined that an adjustment to the state count is required, that is, when the conditions for performing an adjustment to the state count are met, the state count of each of the multiple word lines can be adjusted in operation S33. And when it is determined that no adjustment to the state count is required, a predetermined state count can be maintained for each of the multiple word lines in operation S34.

[0087] The memory controller 110 can periodically or non-periodically adjust the state count of each of the multiple word lines. For example, whether to adjust the state count can be based on the above reference. Figures 4A to 4C The method described is used to determine this.

[0088] Figure 5 This is a system diagram of the memory controller 110 according to an embodiment.

[0089] Reference Figure 5 The memory controller 110 may include a processor 111, random access memory (RAM) 112, an encoding and decoding module (or encoding / decoding module) 113, read-only memory (ROM) 114, a host interface 115, and a memory interface 116. Elements of the memory controller 110 (e.g., processor 111, RAM 112, encoding and decoding module 113, ROM 114, host interface 115, and memory interface 116) can send and receive data via a system bus 117. Furthermore, in various embodiments, the memory controller 110 may also include other elements.

[0090] Processor 111 may include a central processing unit (CPU) or a microprocessor and may control the overall operation of memory controller 110. Processor 111 may include program code configured to perform specific operations, or may include one or more processor cores that include an instruction set for executing the program code. Processor 111 may execute instruction code of firmware stored in ROM 114. In one embodiment, processor 111 may be implemented as a multi-core processor, for example, as a dual-core or quad-core processor.

[0091] RAM 112 can operate as at least one of the following: buffer memory, cache memory, working memory, and main memory of the memory controller 110. RAM 112 can be implemented as dynamic RAM (DRAM), static RAM (SRAM), etc., and firmware can be loaded into RAM 112. The firmware may include features using the above-mentioned references. Figures 1 to 4C The described memory controller 110 includes program code implementing its operating algorithm. For example, the firmware may include a strength calculation module (SCM), a status count adjustment module (CAM), and a programming parameter control module (PCM).

[0092] The encoding and decoding module 113 can perform encoding and decoding on data, and can perform error correction on the data. The encoding and decoding module 113 can encode data to be stored in the non-volatile memory 120, and can generate error correction codes. The encoding and decoding module 113 can decode data read from the non-volatile memory 120, detect errors in the data based on the error correction codes, and correct the detected errors. In one embodiment, the encoding and decoding module 113 can be implemented in hardware. In another embodiment, the encoding and decoding module 113 can be implemented in software or firmware and can be loaded into RAM 112. When data read from the non-volatile memory 120 cannot be decoded, i.e., when errors in the data cannot be corrected using error correction codes, the lifetime of the corresponding word line from which the data was read and the lifetime of the memory block including the corresponding word line can be determined to have ended.

[0093] ROM 114 can store various information required to operate the memory controller 110. For example, ROM 114 can store various information in firmware form. When the storage device ( Figure 1 When the ROM 110 is powered on, the firmware stored in the ROM 114 can be loaded into the RAM 112.

[0094] The memory controller 110 can communicate with external devices (e.g., a host) via the host interface 115. For example, the host interface 115 may include various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), and Non-Volatile Memory High Speed ​​(NVM-e)).

[0095] The memory interface 116 can provide an interface between the memory controller 110 and the non-volatile memory 120. For example, commands, addresses, control signals (e.g., status counts and programming parameters), programming data, read data, and response signals can be sent and received between the memory controller 110 and the non-volatile memory 120 through the memory interface 116.

[0096] Figure 6 This is a block diagram illustrating a non-volatile memory 120 according to an embodiment.

[0097] Reference Figure 6 The non-volatile memory 120 may include a memory cell array 121, control logic 122, voltage generator 123, address decoder 124, page buffer circuit 125, and data input / output (I / O) circuit 126.

[0098] The memory cell array 121 can be connected to multiple word lines WL and multiple bit lines BL. Memory blocks can be connected to one or more string select lines SSL and one or more ground select lines GSL. The memory cell array 121 can include multiple memory blocks, each of which can include multiple memory cells disposed in multiple regions where the multiple word lines WL and the multiple bit lines BL intersect. Figure 8A (MC1 to MC8).

[0099] In one embodiment, each of the plurality of memory cells may store 1 bit of data or more bits of data. In another embodiment, each of the plurality of memory cells may store a fractional bit of data.

[0100] When an erase voltage is applied to the memory cell array 121, multiple memory cells can be in an erased state, and a programming voltage can be applied to a selected word line of the memory cell array 121, thereby allowing multiple memory cells connected to the selected word line to be programmed into a set state. Figure 2A and Figure 2B As shown, each of the plurality of memory cells may have an erase state E divided based on a threshold voltage Vth and at least one programming state.

[0101] Based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 110, the control logic 122 can program data in the memory cell array 121, or can output various control signals for reading data from or erasing the memory cell array 121.

[0102] Various control signals output from control logic 122 can be provided to voltage generator 123, address decoder 124, page buffer circuit 125, and data I / O circuit 126. Specifically, control logic 122 can provide the voltage control signal CON_vol to voltage generator 123, the row address R_ADDR to address decoder 124, the programming control signal CON_P to page buffer circuit 125, and the data I / O control signal CON_I / O to data I / O circuit 126. However, this disclosure is not limited thereto; control logic 122 can also provide different control signals to voltage generator 123, address decoder 124, page buffer circuit 125, and data I / O circuit 126.

[0103] Voltage generator 123 can generate various voltages for performing programming, reading, and erasing operations on memory cell array 121 based on voltage control signal CON_vol. Specifically, voltage generator 123 can generate multiple word line drive voltages VWL for driving multiple word lines WL. Word line drive voltages VWL can include, for example, programming voltages (or write voltages), read voltages, erase voltages, disable voltages, or programming verification voltages. Voltage generator 123 can also generate serial select line drive voltages for driving multiple serial select lines SSL and ground select line drive voltages for driving multiple ground select lines GSL.

[0104] Address decoder 124 can be connected to memory cell array 121 via multiple word lines WL, and can select some word lines from the multiple word lines WL in response to row address R_ADDR received from control logic 122. During programming operations, address decoder 124 can apply a programming voltage to the selected word lines and can apply a disable voltage to the unselected word lines.

[0105] Page buffer circuit 125 can be connected to memory cell array 121 via multiple bit lines BL. Specifically, in programming operations, page buffer circuit 125 can operate as a write driver to program the state corresponding to the data DT to be stored in memory cell array 121. In reading operations, page buffer circuit 125 can operate as a sense amplifier to output the data DT stored in memory cell array 121.

[0106] Through multiple I / O pins or a data bus (e.g., data line DL), data I / O circuit 126 can send data DT from external input to page buffer circuit 125, or can send data DT output from page buffer circuit 125 to memory controller. Figure 1 (of 110).

[0107] According to the embodiment, the control logic 122 can be based on the memory controller ( Figure 1 The control logic 122 receives the state count and programming parameters of each of the multiple word lines WL to generate a voltage control signal CON_vol and a programming control signal CON_P. The programming parameters may include at least one of a programming start voltage, a programming voltage difference, and a programming verification voltage. The control logic 122 can generate the voltage control signal CON_vol based on the programming parameters.

[0108] Furthermore, when performing programming operations on a word line, control logic 122 can generate a programming control signal CON_P based on a state count received from memory controller 110, such that each of the plurality of memory cells included in the word line is programmed to be assigned to one of the plurality of states of the word line, and can provide the programming control signal CON_P to page buffer circuit 125.

[0109] Figure 7A and Figure 7B This illustrates various embodiments. Figure 6 A diagram illustrating an example implementation of a memory cell array.

[0110] Reference Figure 7A and Figure 7B The memory cell arrays 121a and 121b may include multiple memory blocks (e.g., first memory block BLK1 to third memory block BLK3), each of which may have a three-dimensional (3D) structure (or referred to as a vertical structure).

[0111] Each of the first memory blocks BLK1 to the third memory blocks BLK3 may include multiple structures extending along multiple directions X, Y, and Z corresponding to the 3D structure. Each of the first memory blocks BLK1 to the third memory blocks BLK3 may include multiple NAND cell strings extending along a direction perpendicular to the substrate SUB (Z direction).

[0112] like Figure 7A As shown, the first memory block BLK1 to the third memory block BLK3 can be stacked along a direction perpendicular to the base SUB, or as... Figure 7B As shown, the first memory block BLK1 to the third memory block BLK3 can be arranged parallel to the base SUB in a direction (e.g., the X direction or the Y direction).

[0113] Figure 8A This is a circuit diagram representing an example of a memory block included in a memory controller according to an embodiment.

[0114] Reference Figure 8A The memory block BLK can be a NAND flash memory with a vertical structure. Figure 7A and Figure 7B At least one of the multiple memory blocks shown can be implemented as Figure 8A The memory block BLK is shown in the image.

[0115] The memory block BLK may include multiple NAND strings NS11 to NS33, multiple word lines WL1 to WL8, multiple bit lines BL1 to BL3, a ground select line GSL, multiple string select lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines may be varied depending on the embodiment.

[0116] Multiple NAND strings NS11 to NS33 can be connected between multiple bit lines BL1 to BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a series-connected string select transistor SST, multiple memory cells (e.g., first memory cell to eighth memory cell) MC1 to MC8, and a ground select transistor GST. In one embodiment, at least one dummy cell may be disposed between the string select transistor SST and the first memory cell MC1 and / or between the string select transistor SST and the eighth memory cell MC8.

[0117] The serial select transistor SST can be connected to serial select lines SSL1 to SSL3. Multiple memory cells MC1 to MC8 can be connected to their corresponding word lines WL1 to WL8. The ground select transistor GST can be connected to the ground select line GSL. The serial select transistor SST can be connected to the corresponding bit line (e.g., BL1), and the ground select transistor GST can be connected to the common source line CSL.

[0118] In multiple NAND strings NS11 to NS33, multiple first word lines WL1 connected to (e.g., multiple NAND strings NS11 to NS33) memory cells MC1 located at the same height can be connected together, and string select lines (e.g., first string select lines to third string select lines) SSL1 to SSL3 can be separated from each other. The first string select line SSL1 can be selected, and when a programming voltage is applied to the first word line WL1, the memory cells included in the first row of NAND strings NS11 to NS13 and connected to the first word line WL1 can be programmed. Therefore, programming operations can be performed on a page-by-page basis.

[0119] Figure 8B According to the embodiments Figure 8A A 3D view of the memory block.

[0120] Reference Figure 8B The memory block BLK can be formed in a direction perpendicular to the substrate SUB. A common source line CSL can be disposed on the substrate SUB, and multiple gate electrodes GE and insulating layers IL can be alternately stacked on the substrate SUB. Furthermore, a charge storage layer CS can be formed between adjacent gate electrodes GE and insulating layers IL.

[0121] A pillar P can be formed by vertically patterning multiple alternatingly stacked gate electrodes GE and insulating layer IL. The pillar P can be V-shaped. The pillar P can pass through the gate electrodes GE and insulating layer IL and can be connected to the substrate SUB. The outer O of the pillar P can include a semiconductor material and can be used as a channel region, while the inner I of the pillar P can include an insulating material (such as silicon oxide).

[0122] The gate electrode GE of the memory block BLK can be connected to the ground select line GSL, multiple word lines WL1 to WL8, and the serial select line SSL. Additionally, the pillar P of the memory block BLK can be connected to multiple bit lines BL1 to BL3. Figure 8B In the diagram, the memory block BLK is shown as including two select lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, but is not limited thereto; the memory block BLK may include more or fewer lines.

[0123] like Figure 8A and Figure 8BAs shown, the position of word lines in a memory block BLK with a 3D vertical structure affects the strength of the word lines. For example, due to the structural characteristics of the memory block BLK, during programming, verification, and erasing operations, the stress applied to word lines located at the top or bottom of the memory block BLK (e.g., the first word line WL1 adjacent to the ground select line GSL or the eighth word line WL8 adjacent to the serial select line SSL) is greater than the stress applied to other word lines. Therefore, the strength of these word lines is relatively lower than that of the other word lines. On the other hand, word lines located at the center of the memory block BLK may be stronger than word lines located at the edges of the memory block BLK. However, the embodiments are not limited to this, and the trends of multiple strengths corresponding to multiple word lines may vary based on other factors (such as the manufacturing process of the memory block BLK, the level of the voltage applied to the word lines, etc.).

[0124] When calculating the strength of multiple word lines, the memory controller according to the embodiment ( Figure 1 110) can take into account the position of each of the multiple word lines in the memory block BLK (e.g., the center or edge position as discussed above, the position near the GSL or SSL, etc.) by reflecting the structural characteristics of the memory block BLK with a 3D vertical structure.

[0125] Figure 9A This is a graph showing the threshold voltage distribution of the word lines according to various embodiments. Figure 9B This illustrates various embodiments. Figure 9A A table of programming parameters and status metrics for each word line. Figure 9B The changes in programming parameters and state metrics are shown as a result of aging of each word line.

[0126] exist Figure 9A and Figure 9B For ease of description, the threshold voltage distribution and table of the word lines will be described below with reference to the fourth word line WL4 and the twenty-third word line WL23. The fourth word line WL4 and the twenty-third word line WL23 can be located at different positions in the memory block, or they can be located adjacent to each other.

[0127] Reference Figure 9A Eight state counts can be initially assigned to each of the fourth word line WL4 and the twenty-third word line WL23. For example, the memory cell of each of the fourth word line WL4 and the twenty-third word line WL23 can be programmed to an erase state E and one of the first programming states P1 to the seventh programming states P7, such that 3 bits of data can be stored for each memory cell.

[0128] Reference Figure 9BThe programming parameters and state metrics of the fourth word line WL4 and the second thirteenth word line WL23 can be initially identical. For example, the programming start voltage V for each of the fourth word line WL4 and the second thirteenth word line WL23 can be the same. ST Programming voltage difference ΔV ISPP And program verification voltage V VF It can be applied equivalently. See below for reference. Figure 10 Describe the programming starting voltage V ST Programming voltage difference ΔV ISPP And program verification voltage V VF .

[0129] Figure 10 This is a timing diagram illustrating the programming operations of a non-volatile memory according to an embodiment. Figure 10 In the diagram, the horizontal axis (i.e., the t-axis) represents time, and the vertical axis (i.e., the V-axis) represents the voltage applied to the word line WL (e.g., the fourth word line WL4 or the twenty-third word line WL23) during the programming operation.

[0130] Reference Figure 10 The programming operation may include multiple programming loops LOOP1 to LOOPj (where j is a natural number of 2 or greater). In each of the multiple programming loops LOOP1 to LOOPj, programming voltages Vpgm1, Vpgm2, Vpgm3, ..., or Vpgmj (or referred to as programming pulses) may be applied to the word line WL, and programming verification voltage V VF It can be applied to the word line WL. Based on Incremental Step Pulse Programming (ISPP), the voltage levels of the programming voltages (e.g., the first programming voltage to the j-th programming voltage) Vpgm1, Vpgm2, Vpgm3, ..., or Vpgmj applied to the programming cycles (e.g., the first programming cycle to the j-th programming cycle) LOOP1 to LOOPj can be increased.

[0131] In the first programming loop LOOP1, the first programming voltage Vpgm1 applied to the word line WL can be referred to as the programming start voltage V. ST The voltage difference between programming voltages (e.g., the voltage difference between the first programming voltage Vpgm1 and the second programming voltage Vpgm2) can be referred to as the programming voltage difference ΔV. ISPPIn one embodiment, the voltage difference between programming voltages can be the same during continuous programming cycles. For example, the voltage difference between the first programming voltage Vpgm1 and the second programming voltage Vpgm2 can be the same as the voltage difference between the second programming voltage Vpgm2 and the third programming voltage Vpgm3. In another embodiment, the voltage difference between programming voltages can be different during continuous programming cycles. For example, the voltage difference between the second programming voltage Vpgm2 and the third programming voltage Vpgm3 can be greater than the voltage difference between the first programming voltage Vpgm1 and the second programming voltage Vpgm2.

[0132] Programming to verify voltage V VF This can be a voltage used to verify whether multiple memory cells connected to the word line WL have been programmed to the target state. When the threshold voltage of the memory cell is higher than the programming verification voltage V... VF When the threshold voltage of the memory cell is higher than the programming verification voltage V, it can be determined that the memory cell is programmed to the target state, and when the threshold voltage of the memory cell is higher than the programming verification voltage V VF When the value is low, it can be determined that the memory cell has not been programmed to the target state.

[0133] Return to reference Figure 9B The expected programming time tPGM for each of the fourth word line WL4 and the twenty-third word line WL23. E And actual programming time tPGM R The initial time can be equivalent to 5ms (see...) Figure 9B (Left side). Expected programming time tPGM E Compared to actual programming time tPGM R The difference can be calculated as word line strength STR (or aging value), and because of the expected programming time tPGM E Compared to actual programming time tPGM R Since they are the same, the word line strength STR can be 0.

[0134] Programming, reading, and erasing operations can be performed on the fourth word line WL4 and the thirteenth word line WL23. The fourth word line WL4 and the thirteenth word line WL23 can be programmed based on the same programming parameters. As programming, reading, and erasing operations are performed, both the fourth word line WL4 and the thirteenth word line WL23 age. Therefore, the actual programming time tPGM for the fourth word line WL4... R This can be reduced to 4ms, the actual programming time tPGM for the 23rd word line WL23. R It can be reduced to 3ms (see) Figure 9B (Right side). Due to the expected programming time tPGM E Compared to actual programming time tPGM RThe difference is that the strength STR of the fourth line WL4 can be calculated as -1, and the strength STR of the twenty-third line WL23 can be calculated as -2.

[0135] The following will refer to Figure 11A and Figure 11B Describe the process of adjusting the state count and programming parameters of each line in the fourth word line WL4 and the twenty-third word line WL23.

[0136] Figure 11A This is a graph showing the threshold voltage distribution of word lines when the state count of each word line is adjusted according to various embodiments. Figure 11B This illustrates various embodiments. Figure 11A A table of programming parameters and status metrics for each word line. Figure 11B This demonstrates how programming parameters and state metrics are adjusted based on the state count of each word line.

[0137] Reference Figure 11A The state count for each line in the fourth word line WL4 and the twenty-third word line WL23 can be adjusted. For example... Figure 9B As shown on the right, the strength STR of the fourth line WL4 can be higher than the strength STR of the twenty-third line WL23, therefore, as Figure 11A As shown, the state count of the fourth word line WL4 can increase from eight to sixteen, and the state count of the twenty-third word line WL23 can decrease from eight to four. The memory cell of the fourth word line WL4 can be programmed to an erase state E and one of the first programming states P1 to the fifteenth programming states P15, and the memory cell of the twenty-third word line WL23 can be programmed to an erase state E and one of the first programming states P1 to the third programming states P3.

[0138] As referenced above Figure 9A Before the state count is adjusted, 3 bits of data can be stored in one memory cell of each of the fourth word line WL4 and the second thirteenth word line WL23. Therefore, 6 bits of data can be stored in two memory cells of the fourth word line WL4 and the second thirteenth word line WL23. After the state count is adjusted, 4 bits of data can be stored in one memory cell of the fourth word line WL4, and 2 bits of data can be stored in one memory cell of the second thirteenth word line WL23. Therefore, 6 bits of data can be stored in two memory cells of the fourth word line WL4 and the second thirteenth word line WL23. The amount of data stored in the fourth word line WL4 and the second thirteenth word line WL23 can remain unchanged before and after the state count is adjusted.

[0139] Reference Figure 11B Based on state count adjustments, the expected programming time tPGM for the fourth word line WL4E It can be increased to 7ms, the expected programming time tPGM for the 23rd line WL23. E It can be reduced to 4ms (see) Figure 11B (Left side). The intensity STR before adjusting the state count can be the same as the intensity STR after adjusting the state count; therefore, the actual programming time tPGM of the fourth word line WL4 is... R The actual programming time (tPGM) for the 23rd line WL23 can be 6ms. R It can be 2ms. This is to reduce the actual programming time (tPGM) of the fourth word line (WL4) and the twenty-third word line (WL23). R The difference between them, one or more programming parameters of the fourth word line WL4 and / or the twenty-third word line WL23 can be adjusted.

[0140] For example, such as Figure 11B As shown, the programming start voltage V of the fourth word line WL4 ST The voltage can be increased from 14.5V to 15V, with a programming voltage difference ΔV on the fourth word line WL4. ISPP The voltage can be increased from 0.5V to 0.6V; the programming verification voltage V for the fourth word line WL4. VF The default voltage DF can be reduced by 0.5V. Therefore, the expected programming time tPGM for the fourth word line WL4 is... E This can be reduced to 5ms, the actual programming time tPGM for the fourth word line WL4. R This can be reduced to 4ms. Furthermore, the programming start voltage V for the 23rd line WL23... ST The voltage can be reduced from 14.5V to 14V, the programming voltage difference ΔV of the 23rd line WL23. ISPP The voltage can be reduced from 0.5V to 0.4V. The programming verification voltage V for line 23 (WL23) is... VF The default voltage DF can be increased by 0.5V. Therefore, the expected programming time tPGM for the 23rd word line WL23 is... E It can be increased to 6ms, the actual programming time tPGM of the 23rd word line WL23. R It can be increased to 4ms. The actual programming time tPGM for the fourth word line WL4 and the second thirteenth word line WL23 can be increased by adjusting their programming parameters. R They can be the same or similar.

[0141] exist Figure 11B The text describes adjusting programming parameters to reduce the actual programming time (tPGM) of the fourth word line WL4. R And increase the actual programming time tPGM of the 23rd character line WL23. RThis is one embodiment, but not limited to. In another embodiment, the programming parameters of the fourth word line WL4 can be adjusted to reduce the actual programming time tPGM of the fourth word line WL4. R The programming parameters for the 23rd word line WL23 can be kept at the same value. In another embodiment, the programming parameters for the 4th word line WL4 can be kept at the same value, and the programming parameters for the 23rd word line WL23 can be adjusted to increase the actual programming time tPGM of the 23rd word line WL23. R .

[0142] The above has been referred to Figure 11A and Figure 11B An embodiment is described in which the state count of each of the fourth word line WL4 and the twenty-third word line WL23 is adjusted to 2. s (Where s is a positive integer), therefore, integer bit data is stored in one memory cell of each of the fourth word line WL4 and the twenty-third word line WL23. However, the embodiment is not limited to this; the state count of each of the fourth word line WL4 and the twenty-third word line WL23 can be adjusted such that fractional bit data is stored in said one memory cell of each of the fourth word line WL4 and the twenty-third word line WL23. The following will refer to... Figures 12A to 14B This will be described.

[0143] Figure 12A This is a graph showing the threshold voltage distribution of word lines when the state count of the word lines is adjusted according to various embodiments. Figure 12B This illustrates various embodiments. Figure 12A A table of programming parameters and status metrics for each word line. Figure 12B This demonstrates how programming parameters and state metrics are adjusted based on the state count of each word line.

[0144] Reference Figure 12A The state count for each line in the fourth word line WL4 and the twenty-third word line WL23 can be adjusted. (See above regarding...) Figure 9B The strength STR of the fourth line WL4 discussed can be higher than the strength STR of the twenty-third line WL23, therefore, as Figure 12AAs shown, the state count of the fourth word line WL4 can increase from eight to twelve, and the state count of the twenty-third word line WL23 can decrease from eight to six. The memory cell of the fourth word line WL4 can be programmed to an erase state E and one of the first programming states P1 to eleventh programming states P11, and the memory cell of the twenty-third word line WL23 can be programmed to an erase state E and one of the first programming states P1 to fifth programming states P5. Therefore, 3.5 bits of data can be stored in one memory cell of the fourth word line WL4, and 2.5 bits of data can be stored in one memory cell of the twenty-third word line WL23, thus a total of 6 bits of data can be stored in two memory cells of the fourth word line WL4 and the twenty-third word line WL23.

[0145] As referenced above Figure 9A As described above, before the state count is adjusted, 6 bits of data can be stored in two memory cells: the fourth word line WL4 and the second thirteenth word line WL23. Therefore, the amount of data stored in the fourth word line WL4 and the second thirteenth word line WL23 can remain unchanged before and after the state count is adjusted. The following will refer to... Figures 13 to 14B Describes a method for storing fractional bits in a memory cell on a word line.

[0146] Reference Figure 12B Based on state count adjustments, the expected programming time tPGM for the fourth word line WL4 E It can be increased to 6ms, the expected programming time tPGM for the 23rd line WL23. E This can be reduced to 4.5ms. The intensity STR before adjusting the state count can be the same as the intensity STR after adjusting the state count; therefore, the actual programming time tPGM for the fourth word line WL4 is reduced. R It can be 5ms, the actual programming time tPGM of the 23rd line WL23. R It can be 2.5ms. This is to reduce the actual programming time (tPGM) of the fourth word line (WL4) and the twenty-third word line (WL23). R The difference between them, one or more programming parameters of the fourth word line WL4 and / or the twenty-third word line WL23 can be adjusted.

[0147] For example, such as Figure 12B As shown, the programming start voltage V of the fourth word line WL4 ST The voltage can be increased from 14.5V to 14.75V, with a programming voltage difference ΔV on the fourth word line WL4. ISPP The voltage can be increased from 0.5V to 0.55V; the programming verification voltage V for the fourth word line WL4. VF The default voltage DF can be reduced by 0.25V. Therefore, the expected programming time tPGM for the fourth word line WL4 is...E This can be reduced to 5ms, the actual programming time tPGM for the fourth word line WL4. R This can be reduced to 4ms. Furthermore, the programming start voltage V for the 23rd line WL23... ST The voltage can be reduced from 14.5V to 14.25V; the programming voltage difference ΔV for the 23rd digit line WL23 is [missing value]. ISPP The voltage can be reduced from 0.5V to 0.45V. The programming verification voltage V for the 23rd digit line WL23 is... VF The default voltage DF can be increased by 0.25V. Therefore, the expected programming time tPGM for the 23rd line WL23 is... E It can be increased to 6ms, the actual programming time tPGM of the 23rd word line WL23. R It can be increased to 4ms. The actual programming time tPGM for the fourth word line WL4 and the second thirteenth word line WL23 can be increased by adjusting their programming parameters. R They can be the same or similar.

[0148] Figure 13 This is a table describing a method for storing fractional bits in each memory cell according to an embodiment.

[0149] Figure 13 An embodiment is shown in which a total of 5 bits of data are stored in the first memory cell MC1 and the second memory cell MC2, and 2.5 bits of data are stored in each memory cell.

[0150] Reference Figure 13 The first memory cell MC1 and the second memory cell MC2 can be paired (or grouped), and programming and reading operations can be performed on both the first memory cell MC1 and the second memory cell MC2. Furthermore, there are thirty-two states (2...) corresponding to 5 bits of data. 5 =32) can be calculated based on five states assigned to each of the first memory cell MC1 and the second memory cell MC2 (e.g., a combination of the first programming state P1 to the fifth programming state P5 and the erase state E). A total of thirty-six states can be calculated by multiplying the six states of the first memory cell MC1 and the six states of the second memory cell MC2, and the thirty-two states (e.g., the first state S0 to the thirty-second state S31) of the thirty-six states can correspond to the thirty-two states corresponding to 5 bits of data (e.g., the erase state E and the first programming states P1 to the thirty-first programming states P31).

[0151] Therefore, the encoding and decoding module 113 of the memory controller 110 (see...) Figure 5The first memory cell MC1 and the second memory cell MC2 can be identified as a pair, and encoding and decoding can be performed on the pair. In the non-volatile memory 120, programming operations and / or reading operations can be performed simultaneously on the first memory cell MC1 and the second memory cell MC2. Therefore, 2.5 bits of data can be stored in each of the first memory cell MC1 and the second memory cell MC2, and 2.5 bits of data can be read from each of the first memory cell MC1 and the second memory cell MC2.

[0152] Figure 13 An embodiment is shown in which 5 bits of data are stored in two memory cells, and therefore, 2.5 bits of fractional data are stored in each of the two memory cells. However, the embodiment is not limited to this; programming and reading operations can be performed on groups of three or more memory cells, and fractional data can be stored in each memory cell. This will be described. To store fractional data, Equation 1 must be satisfied.

[0153] [Formula 1]

[0154]

[0155] Here, n can be a natural number of 2 or greater, and can represent the number of memory cells on which programming and / or reading operations will be performed simultaneously, S k S1 can represent the state count allocated to the k-th memory cell (where k is a natural number from 1 to n), and B can represent the total number of bits to be stored in the memory cell. For example, in the case where a total of 5 bits of data are stored in two memory cells, the product of the state counts S1 and S2 allocated to each of the two memory cells must be 2. 5 (That is, 32) or greater. Figure 13 As shown, the state counts S1 and S2 allocated to the first memory unit MC1 and the second memory unit MC2 can be 6. Therefore, according to Equation 1, S k The number of states can be 36, 32, or greater. Therefore, a total of 5 bits of data can be stored in the first memory unit MC1 and the second memory unit MC2. For example, if five states and eight states, or six states and seven states are respectively assigned to the first memory unit MC1 and the second memory unit MC2, Equation 1 can be satisfied, and a total of 5 bits of data can be stored in the first memory unit MC1 and the second memory unit MC2.

[0156] Figure 14A and Figure 14B A method for storing fractional bits in each memory cell according to an embodiment is described.

[0157] As referenced above Figure 13 In order to store fractional bits of data in each memory cell, multiple memory cells are operated as a pair or a group, and programming operations and read operations are performed on multiple memory cells.

[0158] Figure 14A An example is shown where two memory cells on a word line operate as a pair. Figure 14B An example is shown where two memory cells with two word lines operate as a pair.

[0159] Reference Figure 14A Multiple memory cells C10 to C1m (where m is a positive even number) can be included in the fourth word line WL4, and multiple memory cells C20 to C2m can be included in the twenty-third word line WL23. In the multiple memory cells C10 to C1m of the fourth word line WL4, every two memory cells (e.g., C10 and C11, C12 and C13, etc.) can be operated as a pair, and 7 bits of data can be stored in each pair of memory cells. In other words, 7 bits of data can be stored in C10 and C11, 7 bits of data can be stored in C12 and C13, and so on. For example, with twelve states assigned to the fourth word line WL4, the product of the state counts assigned to C10 and C11 can be 144. 144 can be greater than 128 (= 2^3). 7 And less than 256 (=2) 8 Therefore, 7 bits of data can be stored in pairs C10 and C11, and thus 3.5 bits of data can be stored in each of C10 and C11.

[0160] In the multiple memory cells C20 to C2m of the 23rd word line WL23, every two memory cells (e.g., C30 and C31, C32 and C33, etc.) can be operated as a pair, and 5 bits of data can be stored in each pair of memory cells. For example, in the case where six states are assigned to the 23rd word line WL23, the product of the state counts assigned to C20 and C21 can be 36. 36 can be greater than 32 (= 2^32). 5 And less than 64 (=2) 6 Therefore, 5 bits of data can be stored in each pair of C20 and C21, and thus 2.5 bits of data can be stored in each of C20 and C21.

[0161] As described above, during programming operations, 3.5 bits of data can be stored in the memory cell (e.g., C10) of the fourth word line WL4, and 2.5 bits of data can be stored in the memory cell (e.g., C20) of the twenty-third word line WL23. Therefore, a total of 6 bits of data can be stored in the two memory cells of the fourth word line WL4 and the twenty-third word line WL23. Thus, even when the state count of the fourth word line WL4 is adjusted from eight to twelve, and the state count of the twenty-third word line WL23 is adjusted from eight to six, the amount of data stored in the fourth word line WL4 and the twenty-third word line WL23 remains the same before and after the state count adjustment.

[0162] As mentioned above, Figure 14A An embodiment is shown in which two memory cells on a word line operate as a pair, according to various embodiments. However, the embodiments are not limited thereto. Figure 14B An embodiment is shown in which two memory cells with two word lines operate as a pair, according to various embodiments. Furthermore, with... Figure 14A The implementation methods differ, in Figure 14B In the embodiments, m can be a positive integer.

[0163] Reference Figure 14B A memory cell in the fourth word line WL4 and a memory cell in the twentieth word line WL23 can be operated as a pair. For example, C10 in the fourth word line WL4 and C20 in the twentieth word line WL23 can be operated as a pair, C11 in the fourth word line WL4 and C21 in the twentieth word line WL23 can be operated as a pair, and so on. In other words, C10 in the fourth word line WL4 and C20 in the twentieth word line WL23 can be programmed and / or read simultaneously. For example, when twelve state counts are assigned to the fourth word line WL4 and six state counts are assigned to the twentieth word line WL23, the product of the state counts assigned to C10 and C20 can be 72 (=12×6). Because 72 is greater than 64 (=2 6 And less than 128 (=2) 7 Therefore, a total of 6 bits of data can be stored in pairs C10 and C20. Thus, 3.5 bits of data can be stored in C10, and 2.5 bits of data can be stored in C20. As another example, when eleven state counts are assigned to the fourth word line WL4 and six state counts are assigned to the twenty-third word line WL23, the product of the state counts assigned to C10 and C20 can be 66 (=11×6). Because 66 is greater than 64 (=2… 6 And less than 128 (=2) 7 Therefore, a total of 6 bits of data can be stored in pairs C10 and C20.

[0164] Therefore, even when the state count of the fourth word line WL4 is adjusted from eight to twelve or eleven, and the state count of the twenty-third word line WL23 is adjusted from eight to six, the amount of data stored in the fourth word line WL4 and the twenty-third word line WL23 can be the same before and after the state count adjustment.

[0165] As referenced above Figures 13 to 14B As mentioned above, by adjusting the state count, it can be related to 2 s Different state counts are assigned to word lines, which can be more than 2. s The state count case allows for more precise state count adjustments and makes it easier to perform loss leveling on each word line.

[0166] Figure 15A This is a block diagram representing the memory controller 110a according to an embodiment. Figure 15B According to the embodiments Figure 15A A flowchart of the operation method of the memory controller 110a.

[0167] Reference Figure 15A The memory controller 110a may include a reinforcement learning module (RLM), a data collection and storage module (PIS), and a programming parameter control module (PCM).

[0168] The Reinforcement Learning Module (RLM) can adjust the state count of each of multiple word lines using reinforcement learning. Specifically, the RLM can perform state count adjustment by using word line strength as a feature. (See above for reference.) Figure 3B In the calculation of word line strength, the expected programming time can be calculated based on programming parameters (e.g., at least one of programming start voltage, programming voltage difference, and programming verification voltage), and the corresponding word line strength can be calculated based on the expected programming time and the actual programming time. Furthermore, features associated with the conditions for performing a read operation (e.g., read level offset value, read error bit, etc.) can be considered in the process of calculating the word line strength.

[0169] The reinforcement learning module (RLM) can be implemented, for example, by storing data in ROM (...). Figure 5 In 114), in the storage device ( Figure 1 The runtime of 100) is loaded in RAM. Figure 5 112) in and by the processor ( Figure 5 The firmware executed by 111).

[0170] The information collection storage (PIS) can store pre-collected characteristic information (e.g., configuration information, initial value information about the state counts of each of multiple word lines, and threshold information about the state counts that can be assigned to word lines). For example, the RAM 112 of the memory controller 110 (see...) Figure 5 It can be used as a PIS for collecting and storing information. For example, the collected characteristic information can be stored in non-volatile memory (NROM). Figure 1 120) or ROM ( Figure 5 In 114), and when the storage device ( Figure 1 When the 100 is booted, the collected feature information can be loaded into RAM 112.

[0171] When the programming time variation between multiple word lines increases by adjusting the state count, the programming parameter control module (PCM) can adjust the programming parameters to reduce the programming time variation.

[0172] Reference Figure 15B In operation S210, the memory controller 110a can obtain the status metric for each of the multiple word lines. The memory controller 110a can store the actual programming time, erase time, read time, read error bit, read level offset value, and status count.

[0173] In operation S220, the reinforcement learning module RLM can adjust the state count of each of the multiple word lines based on the programming parameters and state metrics obtained in operation S210. In this case, the reinforcement learning module RLM can perform reinforcement learning based on the collected information PI, thus preventing reinforcement learning from being performed in an unintended direction (e.g., increasing the intensity difference between the multiple word lines). For example, the reinforcement learning module RLM can perform reinforcement learning based on the initial state count of each of the multiple word lines. As another example, the reinforcement learning module RLM can perform reinforcement learning on threshold information about the state counts that can be assigned to word lines, for example, on a threshold that maximizes the state counts assigned to a single word line or on the difference between the state counts of multiple word lines. Therefore, reinforcement learning can be prevented from being performed under worst-case conditions.

[0174] In operation S230, the programming parameter control module PCM can adjust the programming parameters of each of the multiple word lines based on the adjustment of the status count. In operation S240, the memory controller 110 can send the status count and programming parameters of each of the multiple word lines to the non-volatile memory 120.

[0175] Figure 16 The operation method of the reinforcement learning module RLM according to an embodiment is shown.

[0176] Reference Figure 16The reinforcement learning module (RLM) can set the state of reinforcement learning based on conditional information about each of the multiple word lines of the non-volatile memory 120. For example, for each word line (e.g., WL#, where # is a natural number of 1 or greater), parameters such as programming parameters PP, expected programming time tPGM, etc., are considered. E Features such as the state count (SC) can be set as states in reinforcement learning. Additionally, the erase time (tBERS), read level offset (RLS), and read error bit (REB) as supplementary features can also be set as states in reinforcement learning. The word line strength (STR, or aging level) can be based on the programming parameters (PP) and the expected programming time (tPGM). E To be confirmed.

[0177] The Reinforcement Learning Module (RLM) can adjust (increase or decrease) the state count of each word line. For example, adjusting the state count of each of multiple word lines can be performed as a reinforcement learning action. The RLM can perform actions based on the reinforcement learning state to maximize the reward. Therefore, the state count of each of multiple word lines can be increased or decreased. (See above for reference.) Figure 4A and Figure 4B The programming time variation ΔtPGM or P / E cycle of multiple word lines can be set as a trigger condition for performing actions.

[0178] The reward for reinforcement learning can be set based on the intensity difference dSTR between multiple word lines, calculated using features used to set the state of the reinforcement learning module. For example, the function value F(dSTR) calculated based on the intensity difference dSTR can be set as the reward. The reinforcement learning module RLM can perform actions to maximize the function value F(dSTR), in other words, to minimize the intensity difference dSTR between the multiple word lines.

[0179] In one embodiment, when the programming time change ΔtPGM is set as a trigger condition for executing an action, the time difference dT between multiple actions (e.g., the time spent from the execution of a state count adjustment until the state count adjustment is executed again) can be set as a reward. The time difference dT between multiple actions can increase when the state count adjustment is executed appropriately.

[0180] Figure 17A This is a block diagram representing a memory controller according to an embodiment. Figure 17B According to the embodiments Figure 17A A flowchart of the operation method of the memory controller.

[0181] Figure 17A yes Figure 3A Modified embodiments, Figure 17B The operation method can be Figure 3BThis is a modified embodiment of the method. Therefore, for the sake of brevity, repeated descriptions of the same elements will be omitted, and the differences will be mainly described below.

[0182] Reference Figure 17A The memory controller 110b may include an intensity calculation module (SCM), a clustering module (CLM), a state count adjustment module (CAM), and a programming parameter control module (PCM).

[0183] The above has been referred to Figure 3A The strength calculation module (SCM), the state counting adjustment module (CAM), and the programming parameter control module (PCM) are described. Therefore, for the sake of brevity, their repeated descriptions are omitted.

[0184] The Clustering Module (CLM) can perform clustering based on the characteristics of each of the multiple word lines (e.g., word line strength), thus grouping multiple word lines into multiple word line groups. The State Count Adjustment Module (CAM) can adjust the state count of each of the multiple word line groups, and the Programming Parameter Control Module (PCM) can adjust the programming parameters of each of the multiple word line groups.

[0185] Reference Figure 17B In operation S310, the memory controller 110 can obtain status metrics for each of the multiple word lines. Status metrics may include, for example, actual programming time, erase time, read time, read error bit, read level offset value, and / or status count.

[0186] In operation S320, the strength calculation module SCM can calculate the strength of multiple word lines corresponding to multiple word lines respectively. The strength calculation module SCM can calculate the strength of word lines based on the programming parameters and state metrics obtained in operation S310.

[0187] In operation S330, the clustering module CLM can determine whether grouping of multiple word lines is necessary. When grouping is necessary (S330, Yes), in operation S340, clustering can be performed based on the characteristics of each of the multiple word lines (e.g., word line strength). The multiple word lines can be grouped into multiple word line groups.

[0188] For example, when the number of word lines managed for adjusting state counts is equal to or greater than a threshold number, the load on the State Count Adjustment Module (CAM) increases, and the amount of information to be managed (e.g., the amount of data needed to obtain state metrics) becomes large. When the number of word lines managed for adjusting state counts is equal to or greater than the threshold number, the Clustering Module (CLM) can determine that grouping is needed, and the CLM can perform grouping based on clustering (i.e., clustering techniques) based on the characteristics of each of the multiple word lines.

[0189] Clustering can be performed using at least one of the following algorithms: K-means clustering, K-medoids clustering, hierarchical clustering, density-based clustering, and neural network algorithms.

[0190] In operation S350, the State Count Adjustment Module (CAM) can adjust the state count. The CAM can adjust the state count of each of the multiple word line groups based on the strength of the multiple word lines corresponding to those groups. When clustering in operation S340 is not performed, the CAM can adjust the state count on a word line basis.

[0191] In operating the S360, the programming parameter control module (PCM) can adjust the programming parameters of each or each of the multiple word lines in multiple word line groups.

[0192] In operation S370, the memory controller 110 can send programming parameters and status counts for each of the multiple word lines in a group of word lines to the non-volatile memory 120.

[0193] Figure 18A and Figure 18B The grouping of multiple word lines according to an embodiment is shown.

[0194] Reference Figure 18A The adjustment of the state count can be performed on a unit of a memory block BLK, and multiple word lines included in the memory block BLK (e.g., first word line WL1 to twelfth word line WL12) can be grouped into multiple word line groups.

[0195] Multiple word lines (e.g., first word line WL1 to twelfth word line WL12) can have different intensities STR, and the memory controller (e.g., Figure 17A The clustering module of the memory controller 110b) (e.g., Figure 17AThe clustering module (CLM) can perform clustering based on intensity STR to group word lines from the first word line WL1 to the twelfth word line WL12 into multiple word line groups (e.g., group G1, group G2, and group G3). For example, the clustering module CLM can set clustering criteria based on the intensity STR distribution of the first word line WL1 to the twelfth word line WL12. For example, the clustering module CLM can group multiple word lines with intensity STR equal to or less than 0 and greater than -2 into group G1, multiple word lines with intensity STR equal to or less than -2 and greater than -3 into group G2, and multiple word lines with intensity STR equal to or less than -3 into group G3. Therefore, the third line WL3, the fourth line WL4, the fifth line WL5, and the twelfth line WL12 can be grouped into the first group G1; the second line WL2, the sixth line WL6, the cross line WL10, and the eleventh line WL11 can be grouped into the second group G2; and the first line WL1, the seventh line WL7, the eighth line WL8, and the ninth line WL9 can be grouped into the third group G3.

[0196] Reference Figure 18B The adjustment of the state count can be performed on a unit of memory blocks (e.g., first memory block and second memory block) BLK1 and BLK2, and multiple word lines included in memory blocks (e.g., first word lines WL1 to eighth word lines WL8 of first memory block BLK1 and first word lines WL1 to eighth word lines WL8 of second memory block BLK2) can be grouped into multiple word line groups.

[0197] The first word lines WL1 to WL8 of the first memory block BLK1 and the first word lines WL1 to WL8 of the second memory block BLK2 can have different strengths STR, and the memory controller (e.g., Figure 17A The clustering module of the memory controller 110b) (e.g., Figure 17A The clustering module (CLM) can perform clustering based on the intensity STR to group the first word lines WL1 to the eighth word line WL8 of the first memory block BLK1 and the first word lines WL1 to the eighth word line WL8 of the second memory block BLK2 into multiple word line groups (e.g., first group G1, second group G2 and third group G3).

[0198] For example, the clustering module CLM can set clustering criteria based on the intensity STR distribution of the first word line WL1 to the eighth word line WL8 in each of the first memory block BLK1 and the second memory block BLK2. For example, the clustering module CLM can group multiple word lines with an intensity STR equal to or less than 0 and greater than -2 into a first group G1, multiple word lines with an intensity STR equal to or less than -2 and greater than -3 into a second group G2, and multiple word lines with an intensity STR equal to or less than -3 into a third group G3.

[0199] Therefore, the fifth word line WL5 of the first memory block BLK1 and the fourth to sixth word lines WL4 of the second memory block BLK2 can be grouped into the first group G1. The third word lines WL3 and WL4 of the first memory block BLK1 and the second word lines WL2, WL3, and WL7 of the second memory block BLK2 can be grouped into the second group G2. Furthermore, the first word lines WL1, WL2, WL7, and WL8 of the first memory block BLK1 and the first and eighth word lines WL8 of the second memory block BLK2 can be grouped into the third group G3.

[0200] Adjustments to state counts can be based on representatives. Figure 18A and Figure 18B The intensity of each word line group in the first word line group G1 to the third word line group G3 (i.e., the first group G1 to the third group G3 mentioned above) is performed. For example, the average intensity of each word line group can be calculated to represent the intensity of the corresponding word line group, and the adjustment of the state count can be performed based on the average intensity. As another example, the minimum intensity of each word line group can be calculated to represent the intensity of the corresponding word line group, and the adjustment of the state count can be performed based on the minimum intensity. However, the embodiment is not limited to this, and the adjustment of the state count of multiple word line groups can be performed in various ways.

[0201] Figure 18A An embodiment is shown that adjusts the state count on a unit of a memory block. Figure 18B An embodiment is shown in which state count adjustments are performed on a per-block basis. However, the embodiment is not limited thereto, and state count adjustments can be performed on a chip-by-chip or wafer-by-wafer basis. For example, in the case where state count adjustments are performed on a wafer-by-wafer basis, the state counts can be set for each word line or each group of word lines during the manufacturing process of the memory device, and the set state counts can be stored in the memory controller (…). Figure 1 110) non-volatile storage (e.g., ROM) or non-volatile memory ( Figure 1 In (120), for example, the set state count can be used during the runtime of storage device 100.

[0202] Figure 19 This is a block diagram representing a solid-state drive (SSD) system 1000 according to an embodiment.

[0203] Reference Figure 19 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can communicate with the host 1100 and can send signals (e.g., commands, addresses, and data) to and receive signals (e.g., commands, addresses, and data) from the host 1100. The SSD 1200 can receive power from the host 1100 to operate.

[0204] SSD 1200 may include an SSD controller 1210, multiple non-volatile memory devices 1220, 1230, and 1240, and a buffer memory 1300. The multiple non-volatile memory devices 1220, 1230, and 1240 may be implemented as multiple semiconductor chips (e.g., flash memory 1 to flash memory n, where n is a positive integer). SSD controller 1210 may communicate with non-volatile memory devices 1220, 1230, and 1240 through multiple channels CH1, CH2, and CHn. Buffer memory 1300 may be implemented as volatile memory or resistive memory, for example, DRAM. Buffer memory 1300 may temporarily store data received from host 1100 and to be stored in non-volatile memory devices 1220, 1230, and 1240, or may temporarily store data read from non-volatile memory devices 1220, 1230, and 1240 and to be sent to host 1100.

[0205] All of the above are referenced Figures 1 to 18B The described storage device 100 and memory controller 110 can be applied to SSD 1200 and SSD controller 1210, respectively. SSD controller 1210 can adjust the state count of each of one or more word lines in multiple word lines, on a unit basis (one memory block, multiple memory blocks, or one semiconductor chip) within non-volatile memory devices 1220, 1230, and 1240, and can adjust the programming parameters of each of one or more word lines. Therefore, the data reliability and lifespan of SSD 1200 can be enhanced.

[0206] The storage system according to the embodiment can be equipped in or applied to a memory card system, universal flash memory (UFS), embedded storage, and SSD system 1000.

[0207] According to some embodiments, the operations described as being performed by the memory controller 110 can be executed by at least one processor for executing program code including instructions corresponding to the operations. The instructions can be stored in memory. Here, the term "processor" can refer to, for example, a hardware-implemented data processing device including circuitry physically structured for performing a specific operation, which includes operations expressed as code or instructions contained in a program. In at least some embodiments, the hardware-implemented data processing device can include, but is not limited to, a microprocessor, a central processing unit (CPU), a processor core, a multiprocessor core, a multiprocessor, an application-specific integrated circuit (ASIC), and a field-programmable gate array (FPGA).

[0208] Although the inventive concept has been specifically shown and described with reference to various embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A storage device, the storage device comprising: Non-volatile memory, comprising multiple memory blocks, each containing multiple word lines; as well as A memory controller is configured to: determine the word line strength of each of the plurality of word lines, adjust the state count of each of the plurality of word lines based on the word line strength, and adjust the programming parameters of each of the plurality of word lines to reduce programming time variations between the plurality of word lines. The memory controller is configured to adjust the state count of each word line among the plurality of word lines such that the state count assigned to the first word line with a first word line strength is greater than the state count assigned to the second word line with a second word line strength, and the second word line strength is lower than the first word line strength. The word line strength is calculated based on the word line's programming parameters and state metrics. The programming parameters include at least one of the following: programming start voltage, programming voltage difference, and programming verification voltage.

2. The storage device according to claim 1, wherein, The memory controller is configured to calculate word line strength based on the expected programming time and the actual programming time when the programming operation is performed.

3. The storage device according to claim 1, wherein, The memory controller is configured to adjust the state count of each of the plurality of word lines when the difference between the actual programming times of at least two of the word lines is equal to or greater than a reference time.

4. The storage device according to claim 1, wherein, The memory controller is configured to adjust the state count of each word line among the plurality of word lines to 2 based on integer bit data. S , where S is a positive integer.

5. The storage device according to claim 1, wherein, The memory controller is configured to adjust the state count in units of N word lines out of the plurality of word lines, and to adjust the state count of each of the N word lines to a state count based on fractional bit data, where N is an integer of 2 or greater.

6. The storage device according to claim 5, wherein, The memory controller is configured to adjust the state count such that 2 is set for every two memory cells in one of the N word lines. S There are states, where S is a positive integer.

7. The storage device according to claim 5, wherein, The memory controller is configured to adjust the state count such that 2 is set for each of the N memory cells corresponding to the N word lines. S There are states, where S is a positive integer.

8. The storage device according to claim 1, wherein, The memory controller is configured to dynamically group the multiple word lines into multiple word line groups based on word line strength, and to jointly adjust the state count of the word lines included in each of the multiple word line groups according to the word line groups.

9. The storage device according to any one of claims 1 to 8, wherein, The memory controller is configured to obtain programming parameters and state metrics for each of the plurality of word lines, and to adjust the state metrics through reinforcement learning based on the programming parameters and state metrics.

10. The storage device according to claim 9, wherein, The memory controller is configured to perform reinforcement learning based on pre-stored collected information.

11. The storage device according to claim 9, wherein, The memory controller is configured to store multiple state counts and multiple programming parameters corresponding to each of the multiple word lines, and to perform programming operations on the non-volatile memory based on the state metrics and programming parameters adjusted for each of the multiple word lines during the operation of the memory device.

12. The storage device according to any one of claims 1 to 8, wherein, The memory controller is configured to dynamically adjust the state count and programming parameters of each of the multiple word lines during the runtime of the memory device.

13. A method of operating a storage device including non-volatile memory, the method comprising: Calculate the word line strength of each word line in a multi-word-line array of a non-volatile memory. The state count of each of the multiple word lines is adjusted based on the word line strength; as well as Adjust the programming parameters of each of the multiple word lines to reduce the programming time variation between the multiple word lines. The step of adjusting the state count of each of the plurality of word lines includes: adjusting the state count of each of the plurality of word lines such that the state count assigned to the first word line with a first word line intensity is greater than the state count assigned to the second word line with a second word line intensity, and the second word line intensity is lower than the first word line intensity. The word line strength is calculated based on the word line's programming parameters and state metrics. The programming parameters include at least one of the following: programming start voltage, programming voltage difference, and programming verification voltage.

14. The operating method according to claim 13, wherein, The steps for calculating word line strength include: The expected programming time for word lines is calculated based on preset programming parameters and preset state counts; and Word line strength is calculated based on the expected programming time and the measured actual programming time of the word line.

15. The operating method according to claim 13, wherein, When the maximum value of the programming time variation among the multiple word lines is equal to or greater than the threshold time, the step of adjusting the state count is executed.

16. The operating method according to claim 13, wherein, The step of adjusting the state count includes: determining a first state count for one of the two word lines among the plurality of word lines and determining a second state count for the other of the two word lines among the plurality of word lines, such that the product of the first state count and the second state count is equal to or greater than the value of the product of a first previous state count preset for the one of the two word lines and a second previous state count preset for the other of the two word lines.

17. The operating method according to claim 16, wherein, Simultaneously perform write and / or read operations on the two word lines.

18. The method of operation according to any one of claims 13 to 17, wherein, The steps of calculating word line strength and adjusting state counts are performed through reinforcement learning. The action of reinforcement learning is the adjustment of state counts, and the time difference between the action and the next action is set as the reward for reinforcement learning.

19. The operating method according to claim 18, further comprising: The multiple word lines are grouped into multiple word line groups by performing clustering based on word line strength. Specifically, the steps of adjusting the state count and adjusting the programming parameters are performed for each of the plurality of word line groups.

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