Read / write circuit for one-time programmable memory

Abstract

The present disclosure provides a read-write circuit of one-time programmable memory, comprising: an anti-fuse array, comprising: n*n anti-fuse units coupled between a first node and a second node, control ends of switch elements in the anti-fuse units being coupled to different AND signals of different word line signals and bit line signals respectively; a first switch element and a first capacitor connected in parallel between the second node and a second voltage source; a reference array, comprising: a reference resistance and a reference switch element connected in series between the first node and a third node, a control end of the reference switch element being coupled to an OR signal of the n*n AND signals; a second switch element and a second capacitor connected in parallel between the third node and the second voltage source; and a comparison circuit, a first input end being coupled to the second node, and a second input end being coupled to the third node. The embodiments of the present disclosure have a relatively simple circuit connection, a relatively small circuit area and a relatively high circuit reliability.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a read / write circuit for a one-time programmable memory. Background Technology

[0002] One-Time Programmable (OTP) memory can store data in multiple OTP cells, each in either an unprogrammed or programmed state. OTP cells typically include fuses or antifuse elements. Once programmed, the fuses or antifuse elements are in an unrecoverable state, unaffected by power outages, thus ensuring stable data storage.

[0003] In DRAM (Dynamic Random Access Memory), OTP (Optical Point Terminal) cells are typically used to control the enabling or disabling of redundant memory cells. For example, when a memory cell in a memory cell region corresponding to a word line is defective, the corresponding OTP cell will be programmed (the output state of the OTP cell changes from "0" to "1"). The DRAM control circuit will then disable read and write operations to the memory cells in this region, enable read and write operations to a memory cell in the redundant region, and replace the defective memory cell in the redundant region with the memory cell in the redundant region, thus repairing the DRAM defect.

[0004] Figure 1 This is a schematic diagram of the read / write circuit of an OTP unit in related technologies. From... Figure 1 As can be seen, each memory cell is connected to a corresponding antifuse element and a detection element. In large-scale integrated circuits, this connection method results in a large circuit area and complex wiring. Due to the large number of components and complex wiring, the circuit reliability will also be reduced accordingly.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a read / write circuit for a one-time programmable memory, which at least to some extent overcomes the problems of large read / write circuit area, circuit complexity, and low reliability caused by the limitations and defects of related technologies.

[0007] According to one aspect of this disclosure, a read / write circuit for a one-time programmable memory is provided, comprising:

[0008] Antifuse array, including:

[0009] There are n*n antifuse units, each of which includes an antifuse element and a switching element coupled together. The first end of the antifuse unit is coupled to a first node, and the second end is coupled to a second node. The control terminal of the switching element in each antifuse unit is coupled to the AND signal of different word line signals and bit line signals respectively. The first node is coupled to a mirror current source, and the mirror current source is electrically connected to a first voltage source.

[0010] A first capacitor and a first switching element are connected in parallel between the second node and the second voltage source, and the control terminal of the first switching element is coupled to a first control signal;

[0011] The reference array includes:

[0012] A reference resistor and a reference switch element are connected in series between the first node and the third node, and the control terminal of the reference switch element is coupled to n*n OR signals of the AND signal;

[0013] A second capacitor and a second switching element are connected in parallel between the third node and the second voltage source, and the control terminal of the second switching element is coupled to a second control signal;

[0014] The comparator circuit has a first input terminal coupled to the second node and a second input terminal coupled to the third node, and is used to determine whether the antifuse has undergone programming operation based on the voltage comparison result between the second node and the third node.

[0015] In one exemplary embodiment of this disclosure, in the write state, the first switching element is turned on and the second switching element is turned off; in the read state, the first control signal and the second control signal are pulse signals with the same phase.

[0016] In an exemplary embodiment of this disclosure, during the read state, within half a cycle of the pulse signal, the ratio of the voltage of the second node to the voltage of the third node is greater than a first preset value, or the ratio of the voltage of the second node to the voltage of the third node is less than a second preset value.

[0017] In one exemplary embodiment of this disclosure, during the read state, when one word line is enabled and one bit line is enabled, the first switching element and the second switching element are simultaneously turned on.

[0018] In one exemplary embodiment of this disclosure, the first voltage source is at a first level during the write state and at a second level during the read state, wherein the first level is greater than the second level.

[0019] In one exemplary embodiment of this disclosure, the first switching element, the second switching element, and the reference switching element are all NMOS switching transistors.

[0020] In one exemplary embodiment of this disclosure, the resistance value of the reference resistor is less than the blocking resistance value of the antifuse element and greater than the conducting resistance value of the antifuse element.

[0021] In one exemplary embodiment of this disclosure, the resistance value of the reference resistor is less than or equal to one-tenth of the blocking resistance value of the antifuse element, and greater than or equal to ten times the conducting resistance value of the antifuse element.

[0022] In one exemplary embodiment of this disclosure, the reference resistor is a variable resistor.

[0023] In one exemplary embodiment of this disclosure, the capacitance values ​​of the first capacitor and the second capacitor are equal.

[0024] In this embodiment, by connecting n*n antifuse units between the first node and the second node, controlling the opening and closing state of one antifuse unit with a control signal, and connecting a first switching element and a first capacitor in parallel at the second node, and connecting the second node to the input of a comparator, a reference array is used to compare the voltage of the second node. This allows for the detection of the fuse state with fewer components and a smaller circuit area, thus improving circuit reliability.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of the read / write circuit of the OTP unit in related technologies.

[0028] Figure 2 This is a schematic diagram of the structure in an exemplary embodiment of this disclosure.

[0029] Figure 3 yes Figure 2 The circuit shown is a schematic diagram of the signal connection of the antifuse unit.

[0030] Figure 4 This is a timing diagram of the control signals for the read / write circuit in an embodiment of this disclosure.

[0031] Figures 5A-5C yes Figure 4 The circuit state diagram corresponding to the control timing shown is shown. Detailed Implementation

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0033] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0034] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0035] Figure 2 This is a schematic diagram of the structure in an exemplary embodiment of this disclosure.

[0036] refer to Figure 2 The read / write circuit 100 may include:

[0037] Antifuse array 21, including:

[0038] There are n*n antifuse units 21xy, each of which includes a coupled antifuse element C_x_y (where x corresponds to the sequence number of the write signal line, y is the sequence number of the corresponding read signal line, x≤n, y≤n) and a switching element MN_x_y. The first end of each antifuse element is coupled to a mirror current source MP1 through a first node N1, and the mirror current source MP1 is electrically connected to a first voltage source VDD_W / R. The first end of the switching element is coupled to the second end of each antifuse element, and the second end is coupled to a second node N2. The control end is coupled to the AND signal WL_x&BL_y of different word line signals WL_x and bit line signals BL_y.

[0039] The first switching element MN1 is coupled between the second node N2 and the second voltage source VSS, and the control terminal is coupled to the first control signal V_CTRL1;

[0040] The first capacitor C1 is connected in parallel to the first switching element MN1;

[0041] Reference array 22 includes:

[0042] Reference resistor R1, the first end of reference resistor R1 is coupled to mirror current source MP1 through first node N1;

[0043] The reference switch element MN3 has its first terminal coupled to the second terminal of the reference resistor R1, and its second terminal coupled to the third node N3. The control terminal is coupled to n*n OR signals WL_BL that are the same as signals WL_x & BL_y, i.e., WL_BL = WL_0 & BL_0 + WL_0 & BL_1 + ... + WL_n-1 & BL_n-2 + WL_n-1 & BL_n-1.

[0044] The second switching element MN2 is coupled between the third node N3 and the second voltage source VSS, and its control terminal is coupled to the second control signal V_CTRL2;

[0045] The second capacitor C2 is connected in parallel to the second switching element MN2;

[0046] The comparator circuit 23 has a first input terminal coupled to the second node N2 and a second input terminal coupled to the third node N3. It is used to determine whether a certain antifuse element in the antifuse array has undergone a programming operation based on the voltage comparison result between the second node N2 and the third node N3.

[0047] The antifuse element can be composed of a MOSFET, which is equivalent to a capacitor. It is in the off state before being programmed and in the on state after being programmed.

[0048] Figure 3 yes Figure 2 The circuit shown is a schematic diagram of the signal connection of the antifuse unit.

[0049] refer to Figure 3 In this embodiment, each antifuse unit 32 is connected to only one control signal line. This control signal line is connected to the output of the logic circuit 31 and is used to output the AND signal WL_x&BL_y of different word line signals WL_x and bit line signals BL_y. The input of the logic circuit 31 is connected to all word lines and bit lines. When the number of word lines and bit lines is large, the logic circuit 31 can convert m+n word line / bit line signals into m*n control signals, compared to... Figure 1Compared to the complex circuit connections in traditional fuse / anti-fuse units (where one fuse / anti-fuse unit requires connection to three signal lines), the anti-fuse unit in this embodiment has a simpler circuit connection and occupies less space.

[0050] Figure 4 This is a timing diagram of the control signals for the read / write circuit in an embodiment of this disclosure.

[0051] Figures 5A-5C yes Figure 4 The circuit state diagram corresponding to the control timing shown is shown.

[0052] exist Figure 4 In this embodiment, the first switching element MN1, the second switching element MN2, the reference switching element MN3, and the switching elements in each antifuse unit are all NMOS switching transistors. In this case, each switching element is turned on when high and turned off when low. In other embodiments, each switching element can also be a PMOS switching transistor. In this case, the control signal can be adaptively adjusted according to the switching characteristics of the PMOS switching transistor, and this disclosure is not limited thereto.

[0053] refer to Figure 4 and Figure 5A In this embodiment of the disclosure, during the write state (i.e., programming the antifuse unit), the first voltage source VDD_W / R is at a first level, and during the read state (i.e., detecting the state of the antifuse unit), the first voltage source VDD_W / R is at a second level. In some embodiments, the first level is a high voltage (e.g., 5-6V), and the second level is a low voltage (e.g., 1.0-1.2V).

[0054] During write operation, the first control signal V_CTRL1 is high, turning on the first switching element; the second control signal V_CTRL2 is low, turning off the second switching element. At this time, if both any word line signal and any bit line signal are enabled, the switch of a certain antifuse unit will turn on, and the two ends of a certain antifuse element will be connected to the first and second voltage sources respectively, causing it to blow and resulting in an irreversible change in state.

[0055] refer to Figure 4 and Figure 5B , Figure 5C In the read state, the first control signal V_CTRL1 and the second control signal V_CTRL2 are pulse signals with the same phase. One pulse corresponds to the output of one read signal (one word line is enabled and one bit line is enabled). Therefore, within one cycle of the pulse signal, the first switching element and the second switching element experience one simultaneous turn-on and simultaneous turn-off.

[0056] When reading the state of the antifuse cell corresponding to word line x and bit line y (where x and y can be any positive integer less than n), word line x is enabled, bit line y is enabled, the control signal of reference element MN3 is enabled, and reference switch element MN3 is turned on. Therefore, in the read state, as long as any antifuse cell in the antifuse array is enabled, reference switch element MN3 is turned on. Similarly, if all antifuse cells in the antifuse array are disabled, then reference switch element MN3 is turned off.

[0057] refer to Figure 5B When both the first switching element MN1 and the second switching element MN2 are turned on (corresponding to stages T1, T3, and T5 in the timing diagram), the voltage at the second node is zero, and the first capacitor C1 discharges through the first switching element MN1; the voltage at the third node N3 is zero, and the second capacitor C2 discharges through the second switching element MN2. Therefore, within this interval, the voltages on both the first capacitor C1 and the second capacitor C2 are zero, preparing for charging.

[0058] refer to Figure 5C When both the first switching element MN1 and the second switching element MN2 are turned off (corresponding to stages T2 and T4 in the timing diagram), the first voltage source charges the second capacitor C2 through the mirror current source MP1, the reference resistor R1 and the reference switching element MN3, and the voltage of the third node N3 depends on the charging speed of the second capacitor C2.

[0059] At this time, if the antifuse element C_x_y corresponding to the read word line x and the read bit line y is in an unprogrammed state (blocking state), the first voltage source charges the first capacitor C1 through the mirror current source MP1, the blocking resistor of the antifuse element C_x_y, and the switching element MN_x_y. The voltage of the second node N2 depends on the charging speed of the first capacitor C1. If the antifuse element C_x_y corresponding to the read word line x and the read bit line y is in a programmed state (conducting state), the first voltage source charges the first capacitor C1 through the mirror current source MP1, the conducting resistor of the antifuse element C_x_y, and the switching element MN_x_y. The voltage of the second node N2 depends on the charging speed of the first capacitor C1. Figure 4 The Vn2 signal in stage T2 corresponds to the charging state of the antifuse unit in the programmed state (enabled state) (the resistance is small, so C1 charges faster), while the Vn2 signal in stage T4 corresponds to the charging state of the antifuse unit in the unprogrammed state (disabled state) (the resistance is large, so C1 charges slower).

[0060] Comparator circuit 23 determines whether the currently read antifuse cell has been programmed by comparing the voltages of the second node N2 and the third node N3. For example, in Figure 4In stage T2, since Vn2 is significantly greater than Vn3 for a period of time, it can be determined that the currently read antifuse unit is in an enabled state; Figure 4 In the T4 stage, since Vn2 is significantly smaller than Vn3 for a period of time, it can be determined that the antifuse unit being read is in an unenabled state.

[0061] In this embodiment of the disclosure, voltage comparison is achieved by controlling the charging speed of the first capacitor and the second capacitor to maintain a voltage difference between the first capacitor and the second capacitor for a certain period of time.

[0062] Methods for controlling the charging speed of the first and second capacitors include reducing the overall charging speed and controlling the charging speed difference through the resistance difference, where the difference is more significant. In this embodiment, for ease of calculation, the capacitance values ​​of the first and second capacitors can be set to be equal.

[0063] One method to reduce the overall charging speed is, for example, by controlling the gate voltage of the mirror current source MP1. In this embodiment, the control terminal of the mirror current source MP1 is connected to a control signal V_MIR, which is provided by a voltage source / current source module. By setting the voltage value of V_MIR, the magnitude of the mirror current when the mirror current source MP1 is turned on can be set. The magnitude of the current when the mirror current source MP1 is turned on can be determined based on the capacitance values ​​(charging time) of the first capacitor C1 and the second capacitor C2. For example, when the capacitance values ​​of the first capacitor and the second capacitor are equal, and the capacitance values ​​of the first capacitor and the second capacitor are 1 to 1000 fF, the mirror current can be set to 1 to 100 nA.

[0064] The method of controlling the charging speed difference by the resistance difference can be, for example, by setting the resistance value of the reference resistor R1 based on the resistance of the antifuse element before and after programming, i.e., the blocking resistance value and the conducting resistance value.

[0065] Specifically, the blocking resistance of the antifuse element when it is not broken down is R_NP, and the conducting resistance after it is broken down is R_P. The resistance of resistor R1 should be greater than R_P and less than R_NP. That is, the resistance of the reference resistor should be greater than the conducting resistance of the antifuse element and less than the blocking resistance of the antifuse element.

[0066] Since R_P is typically two orders of magnitude smaller than R_NP, in the embodiments of this disclosure, R1 is set to be one order of magnitude larger than R_P, and R_NP is one order of magnitude larger than R1. That is, the resistance value of the reference resistor can be set to be less than or equal to one-tenth of the blocking resistance value of the antifuse element, and greater than or equal to ten times the conducting resistance value of the antifuse element.

[0067] Subsequently, the resistance value of the reference resistor R1 can be further determined according to the design requirements by the ratio of the preset charging time of capacitors C1 and C2. Finally, when the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are 1 to 1000 fF, the resistance value of the reference resistor R1 can be set to 1 KΩ to 100 KΩ.

[0068] In the above embodiments, the reference resistor R1 can be either a fixed resistor or an adjustable resistor. Since the resistance value of a fixed resistor usually has an error, setting the reference resistor R1 as an adjustable resistor helps to provide more accurate control of the capacitor charging time.

[0069] Taking the antifuse element C_0_0 as an example, let its resistance be R001 when it is not programmed and R002 after it is programmed. Assume that R001 = 100 * R002 = 10 * R1 and C1 = C2. When reading the state of C_0_0, that is, when word line 0 is enabled and bit line 0 is enabled, two cases need to be considered.

[0070] If C_0_0 is not programmed, the first voltage source VDD_W / R charges the first capacitor C1 through the mirror current source MP1, the blocking resistor of the antifuse element C_x_y, and the switching element MN_x_y, and charges the second capacitor C2 through the mirror current source MP1, the reference resistor R1, and the reference switching element MN3.

[0071] Let the voltage at the first node be Vn1, the capacitance of the first capacitor C1 be C1, and the charging time be t1. Let the capacitance of the second capacitor C2 be C2, and the charging time be t2. Then we have:

[0072] ((Vn1-Vn2) / R001)*t1=C1*Vn2……………………(1)

[0073] ((Vn1-Vn3) / R1)*t2=C2*Vn3……………………(2)

[0074] Right now:

[0075] Vn2=(t1*Vn1) / (t1+R001*C1)……………………(3)

[0076] Vn3=(t2*Vn1) / (t2+R1*C2)……………………(4)

[0077] Under the condition that C1=C2=c, i.e. t1=t2=t, we can conclude that:

[0078] Vn3 / Vn2=(t+R001*c) / (t+R1*c)……………………(5)

[0079] When R001 = 100K, R1 = 10K, c = 1000f, and t = 1us, Vn3 / Vn2 ≈ 10.

[0080] That is, when the resistance of the first resistor R1 is one-tenth of the blocking resistance of the antifuse element, the voltage Vn3 of the third node N3 is 10 times the voltage Vn2 of the second node N2 for a period of time.

[0081] If C_0_0 has been programmed, the first voltage source VDD_W / R charges the first capacitor C1 through the mirror current source MP1, the on-resistance of the antifuse element C_x_y, and the switching element MN_x_y, and charges the second capacitor C2 through the mirror current source MP1, the reference resistor R1, and the reference switching element MN3. After replacing R001 (blocking resistor) in the above formulas (1), (3), and (5) with R002 (conduction resistor), when R002 = 1K, R1 = 10K, c = 1000f, and t = 1us, Vn3 / Vn2 ≈ 0.1.

[0082] That is, when the resistance of the first resistor R1 is ten times the on-resistance of the antifuse element, the voltage Vn3 of the third node N3 is one-tenth of the voltage Vn2 of the second node N2 for a period of time.

[0083] With the above setting method, regardless of whether the antifuse element has been programmed or not, the voltage of the second node and the voltage of the third node have a large difference over a period of time. Therefore, the comparator 23 can determine the state of the antifuse unit without high sensitivity, which can greatly reduce the component cost.

[0084] In summary, the embodiments disclosed herein not only simplify circuit connections and reduce the number of components, thereby improving circuit reliability, but also reduce the parameter requirements for components, further reducing manufacturing costs.

[0085] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0086] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A read / write circuit for a one-time programmable memory, characterized in that, include: Antifuse array, including: There are n*n antifuse units, each of which includes an antifuse element and a switching element coupled together. The first end of the antifuse unit is coupled to a first node, and the second end is coupled to a second node. The control terminal of the switching element in each antifuse unit is coupled to the AND signal of different word line signals and bit line signals respectively. The first node is coupled to a mirror current source, and the mirror current source is electrically connected to a first voltage source. A first capacitor and a first switching element are connected in parallel between the second node and the second voltage source, and the control terminal of the first switching element is coupled to a first control signal; The reference array includes: a reference resistor, a reference switching element, a second capacitor, and a second switching element; The reference resistor and the reference switch element are connected in series between the first node and the third node, and the control terminal of the reference switch element is coupled to n*n OR signals of the AND signal; The second capacitor and the second switching element are connected in parallel between the third node and the second voltage source, and the control terminal of the second switching element is coupled to the second control signal; The comparator circuit has a first input terminal coupled to the second node and a second input terminal coupled to the third node, and is used to determine whether the antifuse has undergone programming operation based on the voltage comparison result between the second node and the third node. The one-time programmable memory is configured to program the antifuse unit in such a way that when a first control signal is high, the first switching element is turned on, and when a second control signal is low, the second switching element is turned off.

2. The read / write circuit as described in claim 1, characterized in that, In the read state, the first control signal and the second control signal are pulse signals with the same phase.

3. The read / write circuit as described in claim 2, characterized in that, In the read state, within half a cycle of the pulse signal, the ratio of the voltage of the second node to the voltage of the third node is greater than a first preset value, or the ratio of the voltage of the second node to the voltage of the third node is less than a second preset value.

4. The read / write circuit as described in claim 2 or 3, characterized in that, In read mode, when one word line is enabled and one bit line is enabled, the first switching element and the second switching element are simultaneously turned on.

5. The read / write circuit as described in claim 1, characterized in that, In write mode, the first voltage source is at a first voltage level; in read mode, the first voltage source is at a second voltage level, and the first voltage level is greater than the second voltage level.

6. The read / write circuit as described in claim 1, characterized in that, The first switching element, the second switching element, and the reference switching element are all NMOS switching transistors.

7. The read / write circuit as described in claim 1, characterized in that, The resistance value of the reference resistor is less than the blocking resistance value of the antifuse element and greater than the conducting resistance value of the antifuse element.

8. The read / write circuit as described in claim 2, characterized in that, The resistance value of the reference resistor is less than or equal to one-tenth of the blocking resistance value of the antifuse element, and greater than or equal to ten times the conducting resistance value of the antifuse element.

9. The read / write circuit as described in claim 7 or 8, characterized in that, The reference resistor is a variable resistor.

10. The read / write circuit as described in claim 1, characterized in that, The first capacitor has the same capacitance value as the second capacitor.

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