Display device and method of manufacturing the same

Abstract

The present application relates to a display device and a method for manufacturing a display device. The display device includes: a substrate including a display area having a pixel area and a non-display area adjacent to the display area; and a pixel arranged in each of the pixel areas. The pixel includes: a sub-electrode, a first conductive line and a second conductive line, located on the substrate; a first insulating layer, located above the sub-electrode and the first conductive line and the second conductive line; a first electrode to a fourth electrode, located on the first insulating layer; a second insulating layer, completely overlapping the first electrode and the second electrode above the first electrode and the second electrode, and the second insulating layer exposing the third electrode and the fourth electrode; a light-emitting element, between the first electrode and the second electrode; a first contact electrode, located on the first electrode; and a second contact electrode, located on the second electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0144494 filed in the Korean Intellectual Property Office on November 12, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to display devices and methods of manufacturing display devices. Background Art

[0004] Light-emitting diodes show relatively satisfactory durability even under harsh environmental conditions and have excellent performance in terms of lifespan and brightness.

[0005] In order to apply light-emitting diodes to lighting devices, display devices, etc., it may be necessary to electrically connect electrodes that apply power to the light-emitting diodes. The arrangement or relationship between light-emitting diodes and electrodes has been widely studied in terms of use purpose, reduction of space occupied by electrodes, manufacturing methods, driving methods, etc.

[0006] It should be understood that the technical background section is intended to provide, in part, a background useful for understanding the technology. However, the technical background section may also include ideas, concepts or understandings of a part that was not known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] Embodiments provide a display device formed through a manufacturing process by reducing the number of masks and a method of manufacturing the display device.

[0008] In an embodiment, a display device may include: a substrate including a display area having a plurality of pixel areas and a non-display area adjacent to the display area; and a pixel provided in each of the pixel areas.

[0009] The pixel may include: a sub-electrode, a first conductive line, and a second conductive line, which are arranged on a substrate, wherein the sub-electrode, the first conductive line, and the second conductive line may be spaced apart from each other; a first insulating layer, which is arranged on the sub-electrode and the first conductive line and the second conductive line; a first electrode to a fourth electrode, which are arranged on the first insulating layer, wherein the first electrode to the fourth electrode may be spaced apart from each other; a second insulating layer, which is arranged on the first electrode and the second electrode to completely overlap with the first electrode and the second electrode, and the second insulating layer exposes the third electrode and the fourth electrode; a plurality of light-emitting elements, which are arranged on the second insulating layer between the first electrode and the second electrode; a first contact electrode, which is arranged on the first electrode, wherein the second insulating layer may be arranged between the first contact electrode and the first electrode; and a second contact electrode, which is arranged on the second electrode, wherein the second insulating layer may be arranged between the second contact electrode and the second electrode.

[0010] The pixel may include: a third conductive line and a fourth conductive line, which are arranged on the substrate, and the third conductive line and the fourth conductive line are arranged between the first conductive line and the second conductive line; and a first intermediate electrode and a second intermediate electrode, which are arranged on the first insulating layer, and the first intermediate electrode and the second intermediate electrode are arranged between the first electrode and the second electrode.

[0011] The second insulating layer may be disposed over the first intermediate electrode and the second intermediate electrode to completely overlap the first intermediate electrode and the second intermediate electrode.

[0012] The first electrode may extend on the first insulating layer in the same direction as the first conductive line, the second electrode may extend on the first insulating layer in the same direction as the second conductive line, the first intermediate electrode may extend on the first insulating layer in the same direction as the third conductive line, and the second intermediate electrode may extend on the first insulating layer in the same direction as the fourth conductive line.

[0013] The first electrode may overlap the first conductive line, the second electrode may overlap the second conductive line, the first intermediate electrode may overlap the third conductive line, and the second intermediate electrode may overlap the fourth conductive line.

[0014] The first insulating layer may include a plurality of contact holes exposing a portion of the sub-electrode, a portion of each of the first to fourth conductive lines, and another portion of the second conductive line.

[0015] The first electrode may be electrically connected to the exposed portion of the first conductive line, the second electrode and the fourth electrode may be electrically connected to the exposed portion of the second conductive line, respectively, the first intermediate electrode may be electrically connected to the exposed portion of the third conductive line, the second intermediate electrode may be electrically connected to the exposed portion of the fourth conductive line, and the third electrode may be electrically connected to the exposed portion of the sub-electrode.

[0016] The first conductive wire and the first electrode may be connected to each other to form a double-layer structure including a first insulating layer disposed between the first conductive wire and the first electrode, the second conductive wire and the second electrode may be connected to each other to form a double-layer structure including a first insulating layer disposed between the second conductive wire and the second electrode, the third conductive wire and the first intermediate electrode may be connected to each other to form a double-layer structure including a first insulating layer disposed between the third conductive wire and the first intermediate electrode, and the fourth conductive wire and the second intermediate electrode may be connected to each other to form a double-layer structure including a first insulating layer disposed between the fourth conductive wire and the second intermediate electrode.

[0017] The second conductive line, the second electrode, and the fourth electrode may be electrically connected to each other.

[0018] The first contact electrode may be directly disposed on the third electrode and one end of each of the plurality of light emitting elements, and the second contact electrode may be directly disposed on the fourth electrode and the other end of each of the plurality of light emitting elements.

[0019] The first contact electrode may electrically connect the third electrode and one end of each of the plurality of light emitting elements, and the second contact electrode may electrically connect the fourth electrode and the other end of each of the plurality of light emitting elements.

[0020] The pixel may include: a third contact electrode, which is separated from the first contact electrode and the second contact electrode and is arranged on the first intermediate electrode, and the second insulating layer is arranged between the third contact electrode and the first intermediate electrode; and a fourth contact electrode, which is separated from the first contact electrode to the third contact electrode and is arranged on the second intermediate electrode, and the second insulating layer is arranged between the fourth contact electrode and the second intermediate electrode.

[0021] The third contact electrode and the first intermediate electrode may be electrically isolated from each other, and the fourth contact electrode and the second intermediate electrode may be electrically isolated from each other.

[0022] The pixel may include: a transistor disposed between the substrate and the first to fourth conductive lines; and a signal line electrically connected to the transistor. The transistor may be electrically connected to the sub-electrode.

[0023] The pixel may include a third insulating layer disposed on an upper surface of each of the plurality of light emitting elements. The first contact electrode and the second contact electrode may be disposed on the third insulating layer.

[0024] The first contact electrode and the second contact electrode may be provided in the same layer.

[0025] The first contact electrode and the second contact electrode may be provided in different layers.

[0026] Each of the plurality of light emitting elements may include: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0027] A method of manufacturing a display device is also provided. The method may include forming a pixel in each pixel region.

[0028] Forming a pixel may include: forming a sub-electrode and a first conductive line to a fourth conductive line on a substrate, the sub-electrode and the first conductive line to the fourth conductive line are spaced apart from each other; forming a first insulating layer on the sub-electrode and the first conductive line to the fourth conductive line; forming a first electrode to a fourth electrode and a first intermediate electrode and a second intermediate electrode on the first insulating layer, wherein the first electrode to the fourth electrode and the first intermediate electrode and the second intermediate electrode are spaced apart from each other; forming a second insulating layer on the first electrode and the second electrode and the first intermediate electrode and the second intermediate electrode. Forming the second insulating layer may include: forming a second insulating layer that completely overlaps with each of the first electrode and the second electrode and the first intermediate electrode and the second intermediate electrode and does not overlap with the third electrode and the fourth electrode. The method may also include: aligning a plurality of light-emitting elements on the second insulating layer between two adjacent electrodes of the first electrode and the second electrode and the first intermediate electrode and the second intermediate electrode; and forming a first contact electrode to a fourth contact electrode on the second insulating layer.

[0029] The first contact electrode may be electrically connected to one of the third electrode and the fourth electrode, and the fourth contact electrode may be electrically connected to the other of the third electrode and the fourth electrode.

[0030] Forming the first insulating layer may include: applying an insulating material on the sub-electrode and the first to fourth conductive lines; and forming a plurality of contact holes by removing a portion of the insulating material, the plurality of contact holes exposing a portion of the sub-electrode, a portion of each of the first to fourth conductive lines, and another portion of the second conductive line.

[0031] Forming a pixel may include: connecting a first conductive line and a first electrode to form a double-layer structure including a first insulating layer disposed between the first conductive line and the first electrode; connecting a second conductive line and a second electrode to form a double-layer structure including a first insulating layer disposed between the second conductive line and the second electrode; connecting a third conductive line and a first intermediate electrode to form a double-layer structure including a first insulating layer disposed between the third conductive line and the first intermediate electrode; and connecting a fourth conductive line and a second intermediate electrode to form a double-layer structure including a first insulating layer disposed between the fourth conductive line and the second intermediate electrode.

[0032] Forming the pixel may include forming a transistor and a signal line electrically connected to the transistor on the substrate before forming the sub-electrode and the first to fourth conductive lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Now, the embodiments will be described more fully below with reference to the accompanying drawings; however, the embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and fully convey the scope of the present disclosure to those skilled in the art.

[0034] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment.

[0035] Figure 1B yes Figure 1A Schematic cross-sectional view of a light emitting element shown in FIG.

[0036] Figure 2A is a perspective view schematically showing a light emitting element according to an embodiment.

[0037] Figure 2B yes Figure 2A Schematic cross-sectional view of a light emitting element shown in FIG.

[0038] Figure 3A is a perspective view schematically showing a light emitting element according to an embodiment.

[0039] Figure 3B yes Figure 3A Schematic cross-sectional view of a light emitting element shown in FIG.

[0040] Figure 4A is a perspective view schematically showing a light emitting element according to an embodiment.

[0041] Figure 4B yes Figure 4A Schematic cross-sectional view of a light emitting element shown in FIG.

[0042] Figure 5 A display device according to an embodiment is shown, and is used Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0043] FIG. 6A to FIG. 6E It is shown Figure 50 is an equivalent circuit diagram of various embodiments of electrical connections between components included in one pixel shown in FIG.

[0044] Fig. 7A and Figure 7B It is shown Figure 5 0 is an equivalent circuit diagram of an embodiment of electrical connections between components included in one pixel shown in .

[0045] Figure 8 It is schematically shown Figure 5 A plan view of one of the pixels shown in FIG.

[0046] Fig.9A is along Figure 8 A schematic cross-sectional view taken along line II′ shown in FIG.

[0047] Fig. 9B Shows Fig.9A The first contact electrode and the second contact electrode are shown in the embodiment of the present invention, and correspond to Figure 8 Schematic cross-sectional view along line II′ shown in FIG.

[0048] Fig.10 is along Figure 8 A schematic cross-sectional view taken along line II-II′ shown in FIG.

[0049] Fig.11 is along Figure 8 A schematic cross-sectional view taken along line III-III′ shown in FIG.

[0050] Fig.12 is along Figure 8 A schematic cross-sectional view taken along line IV-IV′ shown in FIG.

[0051] Fig.13 Shows Fig.12 The first bank pattern shown in the embodiment of the present invention corresponds to Figure 8 Schematic cross-sectional view along line IV-IV′ shown in FIG.

[0052] Fig.14 Shows Fig.12 The embodiment of the display element portion shown in FIG. 1 corresponds to Figure 8 Schematic cross-sectional view along line IV-IV′ shown in FIG.

[0053] Fig.15 Shows Fig.12 The embodiment of the display element portion shown in FIG. 1 corresponds to Figure 8 Schematic cross-sectional view along line IV-IV′ shown in FIG.

[0054] FIG. 16A to FIG. 16F It is shown in sequence that the manufacturing Figure 8 A schematic plan view of the method for one pixel is shown in FIG.

[0055] FIG. 17A to FIG. 17I It is shown in sequence that the manufacturing Fig.9A A schematic cross-sectional view of the method for one pixel is shown in FIG. DETAILED DESCRIPTION

[0056] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0057] In order to describe the embodiments of the present disclosure, some parts irrelevant to the description may not be provided, and the same reference numerals denote the same elements throughout the specification.

[0058] When a layer, film, zone, substrate or region is referred to as being "on" another layer, film, zone, substrate or region, it may be directly on another layer, film, zone, substrate or region, or there may be an intervening layer, film, zone, substrate or region between them. Conversely, when a layer, film, zone, substrate or region is referred to as being "directly" "on" another layer, film, zone, substrate or region, there may not be an intervening layer, film, zone, substrate or region between them. In addition, when a layer, film, zone, substrate or region is referred to as being "below" another layer, film, zone, substrate or region, it may be directly below another layer, film, zone, substrate or region, or there may be an intervening layer, film, zone, substrate or region between them. Conversely, when a layer, film, zone, substrate or region is referred to as being "directly" "below" another layer, film, zone, substrate or region, there may not be an intervening layer, film, zone, substrate or region between them. Furthermore, "on" or "upper" may include positioning above or below an object and does not necessarily imply a direction based on gravity.

[0059] For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It should be understood that in addition to the orientation depicted in the drawings, the spatially relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device shown in the figure is turned over, a device positioned "below" or "below" another device can be placed "above" the other device. Therefore, the illustrative term "below" can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0060] Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element, or “electrically connected” to the other element with one or more intervening elements interposed therebetween. It should also be understood that when the terms “comprises,” “comprising,” “includes,” and / or “including” are used in this specification, they or it may specify the presence of the features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0061] In the accompanying drawings, the size and thickness of the elements may be exaggerated for better understanding, clarity and ease of description. However, the present disclosure is not limited to the sizes and thicknesses shown. In the accompanying drawings, the thickness of layers, films, panels, regions and other elements may be exaggerated for clarity. In the accompanying drawings, the thickness of some layers and regions may be exaggerated for better understanding and ease of description.

[0062] Furthermore, in this specification, the phrase “in a plan view” means that an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” means that a schematic cross section taken by vertically cutting the object portion is viewed from the side.

[0063] In addition, the term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" can include layers, stacks, facing (face) or facing (facing), extending coverage, covering or partially covering or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where the third element is inserted between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, but still facing each other. When an element is described as "not overlapping (notoverlapping)" or "not overlapping (to not overlap)" with another element, this can include elements spaced apart from each other, offset from each other or arranged side by side with each other, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0064] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable deviation range of the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%.

[0065] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one" is intended to include the meaning of "at least one selected from the following groups". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0066] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the embodiments belong. In addition, it will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0068] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, the singular form in the present disclosure is intended to include the plural form as well.

[0069] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment. Figure 1B yes Figure 1A Schematic cross-sectional view of a light emitting element shown in FIG. Figure 2A is a perspective view schematically showing a light emitting element according to an embodiment. Figure 2B yes Figure 2A Schematic cross-sectional view of a light emitting element shown in FIG. Figure 3Ais a perspective view schematically showing a light emitting element according to an embodiment. Figure 3B yes Figure 3A Schematic cross-sectional view of a light emitting element shown in FIG. Figure 4A is a perspective view schematically showing a light emitting element according to an embodiment. Figure 4B yes Figure 4A Schematic cross-sectional view of a light emitting element shown in FIG.

[0070] For convenience, a description will be given showing a light emitting element manufactured by an etching process. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A and Figure 3B , and then will describe the light emitting element manufactured by the growth process Figure 4A and Figure 4B In an embodiment, the type or type and / or shape of the light emitting element is not limited to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B Therefore, other types and / or shapes of light emitting elements may be included within the spirit and scope of the present disclosure.

[0071] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A and Figure 3B , each light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 inserted or disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an example, the light emitting element LD may be a light emitting stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be sequentially stacked.

[0072] According to an embodiment, the light emitting element LD may be provided in a shape extending in one direction. In the case where the extending direction of the light emitting element LD may be a length direction, the light emitting element LD may have an end portion along the extending direction and another end portion. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at an end portion of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other end portion of the light emitting element LD.

[0073] The light emitting element LD may be arranged in various shapes or formed by various shapes. In an example, the light emitting element LD may have a generally rod-like shape or a rod-like shape, and the light emitting element LD may be long in its length direction, for example, its aspect ratio may be greater than 1. In an embodiment, the length L of the light emitting element LD in the length direction may be greater than the diameter D (or the width of the cross section) of the light emitting element LD. The light emitting element LD may include, for example, a light emitting diode that is manufactured small enough to have a diameter D and / or a length L in the range of micrometer scale to nanometer scale. In an embodiment, the size of the light emitting element LD may be modified to be suitable for the requirements (or design conditions) of a lighting element or a self-luminous display device to which the light emitting element LD may be applied.

[0074] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and may include an n-type semiconductor layer doped with a first conductive dopant (e.g., Si, Ge, or Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto. For example, the first semiconductor layer 11 may include various materials.

[0075] The active layer 12 may be formed or disposed on the first semiconductor layer 11, and may be formed as a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be changed differently depending on the kind or type of the light emitting element LD. The active layer 12 may emit light having a wavelength in the range of about 400nm to about 900nm, and a double heterostructure may be used. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed or disposed on the top and / or bottom of the active layer 12. In an example, the cladding layer may be formed as an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12. For example, the active layer 12 may include various materials.

[0076] When an electric field having a predetermined voltage or higher is applied to both ends of the light emitting element LD, the light emitting element LD may emit light as electron-hole pairs recombine in the active layer 12. The light emission of the light emitting element LD may be controlled using the recombination of the electron-hole pairs, so that the light emitting element LD may be used as a light source for various light emitting devices including pixels of a display device.

[0077] The second semiconductor layer 13 may be formed or disposed on the active layer 12, and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto. For example, the second semiconductor layer 13 may include various materials.

[0078] In an embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) in the length direction of the light emitting element LD. In an example, along the length direction of the light emitting element LD, the first semiconductor layer 11 may have a width (or thickness) that is relatively wider (or thicker) than the width (or thickness) of the second semiconductor layer 13. Figures 1A to 3B As shown in , the active layer 12 of the light emitting element LD may be positioned or disposed closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11 .

[0079] According to an embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light emitting element LD may include an additional electrode 15 disposed on top of the second semiconductor layer 13. Figure 3A and Figure 3B As shown in , the light emitting element LD may include another additional electrode 16 disposed at one end of the first semiconductor layer 11 .

[0080] The additional electrodes 15 and 16 may be ohmic contact electrodes, but the present disclosure is not limited thereto. In an embodiment, the additional electrodes 15 and 16 may be Schottky contact electrodes. The additional electrodes 15 and 16 may include a metal or a metal oxide. For example, the additional electrodes 15 and 16 may include one of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), and any oxide or alloy thereof, or a mixture of the above materials, but the present disclosure is not limited thereto.

[0081] The materials respectively included in the additional electrodes 15 and 16 may be the same as each other, substantially the same as each other, or different from each other. The additional electrodes 15 and 16 may be substantially transparent or translucent. Therefore, the light generated in the light emitting element LD may be emitted to the outside of the light emitting element LD by passing through the additional electrodes 15 and 16. In an embodiment, when the light generated in the light emitting element LD does not pass through the additional electrodes 15 and 16 and is emitted to the outside of the light emitting element LD through regions other than both ends of the light emitting element LD, the additional electrodes 15 and 16 may include an opaque metal.

[0082] In an embodiment, the light emitting element LD may include an insulating film 14. However, in an embodiment, the insulating film 14 may be omitted and provided to cover or overlap only portions of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0083] The insulating film 14 can prevent an electrical short circuit that may occur when the active layer 12 is in electrical contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 can be formed so that surface defects of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. When the light emitting elements LD are densely arranged, the insulating film 14 can prevent an undesirable short circuit that may occur between the light emitting elements LD. Whether the insulating film 14 is provided is not limited as long as the active layer 12 can be prevented from being short-circuited with an external conductive material.

[0084] like Figure 1A and Figure 1B As shown in , the insulating film 14 may be provided in a shape that completely surrounds the periphery of the light emitting stacked structure including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15. For ease of description, in Figure 1A , a case where a portion of the insulating film 14 may be omitted, and the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 that may be included in an actual light emitting element LD may be surrounded by the insulating film 14 .

[0085] Although the case where the insulating film 14 may be provided in a shape completely surrounding the circumference of each of the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 is described in the above embodiment, the present disclosure is not limited thereto.

[0086] In an embodiment, if Figure 2A and Figure 2BAs shown in , the insulating film 14 may surround the circumference of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not surround the circumference of the additional electrode 15 provided on the second semiconductor layer 13 at all. Alternatively, the insulating film 14 may surround only a portion of the circumference of the additional electrode 15, and may not surround another portion of the circumference of the additional electrode 15. However, the insulating film 14 may expose at least two ends of the light emitting element LD. In the example, the insulating film 14 may expose one end of the first semiconductor layer 11 in addition to the additional electrode 15 provided at one end of the second semiconductor layer 13. In an embodiment, as Figure 3A and Figure 3B As shown in FIG. 1 , when the additional electrodes 15 and 16 are provided at both ends of the light emitting element LD, the insulating film 14 may expose at least one region of each of the additional electrodes 15 and 16. Alternatively, in an embodiment, the insulating film 14 may not be provided.

[0087] According to an embodiment, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from the group consisting of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 However, the present disclosure is not limited thereto, and various materials having insulating properties may be used for the insulating film 14 .

[0088] When the insulating film 14 is provided in the light emitting element LD, the active layer 12 can be prevented from being short-circuited with the first electrode (not shown) and / or the second electrode (not shown). As an example, the insulating film 14 can be formed or provided so that surface defects of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. When the light emitting elements LD are densely arranged, the insulating film 14 can prevent an undesirable short circuit that may occur between the light emitting elements LD.

[0089] The above-mentioned light emitting element LD can be used as a light source of various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, when the light emitting element LD is mixed in a liquid solution (or solvent) to be provided to each light emitting area (for example, the light emitting area of ​​each pixel or the light emitting area of ​​each sub-pixel), each light emitting element LD can be surface treated so that the light emitting element LD can be uniformly dispersed in the solution instead of being unevenly aggregated in the solution.

[0090] The light emitting device including the above-mentioned light emitting element LD can be used in various types of equipment (including display equipment) that may require a light source. When the light emitting element LD is arranged in the light emitting area of ​​each pixel of the display panel, the light emitting element LD can be used as the light source of the pixel. However, the application field of the light emitting element LD is not limited to the above-mentioned example. For example, the light emitting element LD can be used in other types of equipment (such as lighting equipment) that may require a light source.

[0091] Will refer to Figure 4A and Figure 4B The light emitting element LD manufactured by the growth process is described.

[0092] In the description of the light emitting element LD manufactured by the growth process, the parts different from those of the above-mentioned embodiment will be mainly described to avoid redundancy. The parts not specifically described in the light emitting element LD manufactured by the growth process may follow the parts of the above-mentioned embodiment. Components similar to and / or identical to those of the above-mentioned embodiment are represented by the same reference numerals.

[0093] refer to Figure 4A and Figure 4B , the light emitting element LD according to the embodiment includes a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed or disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an embodiment, the light emitting element LD may include a light emitting pattern 10 having a core-shell structure including the first semiconductor layer 11 located or disposed at the center thereof, the active layer 12 surrounding at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounding at least one side of the active layer 12, and the additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0094] The light emitting element LD may be arranged in a generally polygonal pyramid shape extending in one direction. In an example, the light emitting element LD may be arranged in a generally hexagonal pyramid shape. In the case where the extension direction of the light emitting element LD may be the length direction of the light emitting element LD, the light emitting element LD may have one end (or lower end) and another end (or upper end) along the length direction. A portion of one of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at one end (or lower end) of the light emitting element LD, and a portion of the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. In an example, a portion of the first semiconductor layer 11 may be exposed at one end (or lower end) of the light emitting element LD, and a portion of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. When the light emitting element LD is used as a light source of a display device, the exposed portion of the first semiconductor layer 11 may be electrically contacted with one of the driving electrodes for driving the light emitting element LD, and the exposed portion of the second semiconductor layer 13 may be electrically contacted with the other of the driving electrodes.

[0095] In an embodiment, when the light emitting element LD includes the additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. When the light emitting element LD is used as a light source of a display device, the exposed portion of the additional electrode 15 may be electrically contacted with another driving electrode to be electrically connected to one electrode.

[0096] In an embodiment, the first semiconductor layer 11 may be located or disposed at the core, for example, at the center (or middle) of the light emitting element LD. The light emitting element LD may be disposed in a shape corresponding to the shape of the first semiconductor layer 11. In an example, when the first semiconductor layer 11 has a substantially hexagonal pyramid shape, the light emitting element LD and the light emitting pattern 10 may also have a substantially hexagonal pyramid shape.

[0097] The active layer 12 may be disposed and / or formed in a shape surrounding the periphery of the first semiconductor layer 11 in the length direction of the light emitting element LD. For example, the active layer 12 may be disposed and / or formed in a shape surrounding other regions between both ends of the first semiconductor layer 11 except for the other end disposed at the lower side in the length direction of the light emitting element LD.

[0098] The second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12 in the length direction of the light emitting element LD and include a semiconductor layer having a different type from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0099] In an implementation, the light emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode, which may be electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto.

[0100] As described above, the light emitting element LD may be a substantially hexagonal pyramid shape having two protruding ends, and may include a light emitting pattern 10 having a core-shell structure including a first semiconductor layer 11 located or disposed at the center thereof, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The first semiconductor layer 11 may be disposed at one end (or lower end) of the light emitting element LD having a substantially hexagonal pyramid shape, and the additional electrode 15 may be disposed at the other end (or upper end) of the light emitting element LD.

[0101] In an implementation, the light emitting element LD may include an insulating film 14 provided or disposed on the outer circumference of the light emitting pattern 10 having the core-shell structure. The insulating film 14 may include a transparent insulating material.

[0102] Figure 5 A display device according to an embodiment is shown, and for example, a display device using Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0103] exist Figure 5 In the embodiment, for convenience, the structure of the display device is shown based on the display area in which one or more images can be displayed. However, in an embodiment, at least one driving circuit (e.g., a scan driver and a data driver) and / or a signal line not shown may be provided in the display device.

[0104] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B and Figure 5According to an embodiment, a display device may include a substrate SUB, pixels PXL, a driving unit (not shown), and a line unit (not shown), wherein the pixels PXL may be disposed on the substrate SUB and each pixel PXL may include at least one light emitting element LD, the driving unit (not shown) may be disposed on the substrate SUB and drive the pixels PXL, and the line unit (not shown) may electrically connect the pixels PXL and the driving unit.

[0105] According to the method of driving the light emitting element LD, the display device can be divided into a passive matrix type display device and an active matrix type display device. In an example, when the display device is implemented as an active matrix type display device, each of the pixels PXL may include a driving transistor for controlling the amount of current supplied to the light emitting element LD, a switching transistor for transmitting a data signal to the driving transistor, and similar elements within the spirit and scope of the present disclosure.

[0106] From the viewpoints of resolution, contrast, and operating speed, active matrix display devices that can selectively emit light for each pixel PXL have recently become mainstream. However, the present disclosure is not limited thereto, and passive matrix display devices that can emit light for each group of pixels PXL may also use components (e.g., first electrodes, second electrodes, etc.) for driving the light emitting element LD.

[0107] The substrate SUB may include a display area DA and a non-display area NDA.

[0108] In an embodiment, the display area DA may be disposed in a central area of ​​the display device, and the non-display area NDA may be disposed in an edge area of ​​the display device or adjacent to an edge area of ​​the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto and may be changed within the spirit and scope of the present disclosure.

[0109] The display area DA may be an area in which pixels PXL for displaying one or more images may be disposed. The non-display area NDA may be an area in which a driving unit for driving the pixels PXL and a portion of a line unit electrically connecting the pixels PXL and the driving unit may be disposed.

[0110] The display area DA may have various shapes. For example, the display area DA may be set to a closed substantially polygonal shape including substantially linear sides. The display area DA may be set to a substantially circular shape and / or a substantially elliptical shape including substantially curved sides. The display area DA may be set to various shapes including substantially linear and substantially curved sides, such as a substantially semicircular shape or a substantially semielliptical shape.

[0111] The non-display area NDA may be disposed at at least one side of the display area DA. In an embodiment, the non-display area NDA may surround a periphery (or edge) of the display area DA.

[0112] The substrate SUB may include a transparent insulating material to enable light to be transmitted through the substrate SUB. The substrate SUB may be a rigid substrate or a flexible substrate.

[0113] One area on the substrate SUB may be set as a display area DA so that the pixel PXL may be disposed therein, and another area on the substrate SUB may be set as a non-display area NDA. In an example, the substrate SUB may include a display area DA including a pixel area in which a corresponding pixel PXL may be disposed, and a non-display area NDA disposed at the periphery of the display area DA.

[0114] Each of the pixels PXL may be provided or disposed in the display area DA. In an embodiment, the pixels PXL may be arranged or disposed in a stripe or PenTile arrangement structure in the display area DA, but the present disclosure is not limited thereto.

[0115] Each pixel PXL may include at least one light emitting element LD driven by a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size ranging from micrometer to nanometer, and may be electrically connected in parallel to a light emitting element LD disposed near it. However, the present disclosure is not limited thereto. The light emitting element LD may constitute a light source of each pixel PXL.

[0116] Each pixel PXL may include at least one light source driven by a predetermined signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first driving power source and a second driving power source). Figures 1A to 4B The light emitting element LD shown in the embodiment shown in , for example, includes at least one micro light emitting element LD having a small size ranging from micrometer level to nanometer level. However, in the embodiment, the kind or type of the light emitting element LD that can be used as the light source of the pixel PXL is not limited thereto.

[0117] In an embodiment, the color, kind or type and / or number of the pixels PXL are not particularly limited. In an example, the color of light emitted by each pixel PXL may be changed within the spirit and scope of the present disclosure.

[0118] The driving unit may provide a predetermined signal and a predetermined power to each pixel PXL through the line unit, and thus, may control the driving of the pixel PXL. Figure 5 In the figure, for the convenience of description, the line unit can be omitted.

[0119] The driving unit may include a scan driver, an emission driver, a data driver, and a timing controller. The scan driver may provide a scan signal to the pixel PXL through a scan line, the emission driver may provide an emission control signal to the pixel PXL through an emission control line, and the data driver may provide a data signal to the pixel PXL through a data line. The timing controller may control the scan driver, the emission driver, and the data driver.

[0120] FIG. 6A to FIG. 6E It is shown Figure 5 0 is an equivalent circuit diagram of an embodiment of electrical connections between components included in one pixel shown in .

[0121] For example, FIG. 6A to FIG. 6E The embodiment of electrical connection between components included in the pixel PXL applicable to the active matrix display device is shown. However, the kind or type of components included in the pixel PXL applicable to the embodiment is not limited thereto.

[0122] exist FIG. 6A to FIG. 6E In the present invention, the pixel PXL can not only include FIG. 6A to FIG. 6E The components included in each of the pixels PXL shown in FIG. 1 and FIG. 2 may also include a region in which the components may be provided or disposed. In an embodiment, FIG. 6A to FIG. 6E Each of the pixels PXL shown in FIG. 1 may be provided or arranged in Figure 5 The pixels PXL may be any one of the pixels PXL in the display device shown in FIG. 1 , and the pixels PXL may have structures substantially the same as or similar to each other.

[0123] refer to Figures 1A to 4B , Figure 5 as well as FIG. 6A to FIG. 6E One pixel PXL (hereinafter, referred to as a "pixel") may include a light emitting unit EMU that may generate light having brightness corresponding to a data signal. The pixel PXL may include a pixel circuit 144 that may drive the light emitting unit EMU.

[0124] In an embodiment, the light emitting unit EMU may include a light emitting element LD electrically connected in parallel between a first power line PL1 and a second power line PL2, a first driving power source VDD may be applied to the first power line PL1, and a second driving power source VSS may be applied to the second power line PL2. For example, the light emitting unit EMU may include a first electrode EL1 (or "first alignment electrode") electrically connected to the first driving power source VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") electrically connected to the second driving power source VSS via the second power line PL2, and a light emitting element LD electrically connected in parallel between the first electrode EL1 and the second electrode EL2 in the same direction. In an embodiment, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0125] In an embodiment, each of the light emitting elements LD included in the light emitting unit EMU may include one end electrically connected to the first driving power source VDD through the first electrode EL1 and the other end electrically connected to the second driving power source VSS through the second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. In an example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. During the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0126] As described above, the light emitting elements LD electrically connected in parallel between the first electrode EL1 and the second electrode EL2 which may be supplied with different voltages in the same direction (eg, forward direction) may respectively form effective light sources. The effective light sources may constitute the light emitting unit EMU of the pixel PXL.

[0127] Each of the light emitting elements LD of the light emitting unit EMU may emit light having a brightness corresponding to the driving current provided by the corresponding pixel circuit 144. For example, the pixel circuit 144 may provide the light emitting unit EMU with a driving current corresponding to the grayscale value of the corresponding frame data during each frame period. The driving current provided to the light emitting unit EMU may flow through the light emitting elements LD electrically connected in the same direction separately. Therefore, the light emitting unit EMU may emit light having a brightness corresponding to the driving current, and at the same time, each light emitting element LD may emit light having a brightness corresponding to the current flowing therethrough.

[0128] At the same time, despite FIG. 6A to FIG. 6E, the light emitting element LD can be electrically connected between the first driving power source VDD and the second driving power source VSS in the same direction, but the present disclosure is not limited thereto. In an embodiment, in addition to the light emitting element LD forming the corresponding effective light source, the light emitting unit EMU may include at least one ineffective light source. In the example, Fig.6D and Fig. 6E As shown in , at least one reverse light emitting element LDr may be electrically connected between the first electrode EL1 and the second electrode EL2 of the light emitting unit EMU. The reverse light emitting element LDr may be electrically connected in parallel with the light emitting element LD forming an effective light source between the first electrode EL1 and the second electrode EL2, and may be electrically connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the direction in which the light emitting element LD may be electrically connected. Although a predetermined driving voltage (e.g., a forward driving voltage) may be applied between the first electrode EL1 and the second electrode EL2, the reverse light emitting element LDr may remain in an inactive state, and therefore, no current may substantially flow through the reverse light emitting element LDr.

[0129] The pixel circuit 144 may be electrically connected to the scan line and the data line of the corresponding pixel PXL. In an example, in the case where the pixel PXL may be arranged on the i-th (i is a natural number) row and the j-th (j is a natural number) column of the display area DA, the pixel circuit 144 of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, as Fig. 6A and Figure 6B As shown in FIG. 1 , the pixel circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to Fig. 6A and Figure 6B The embodiment shown in .

[0130] refer to Fig. 6A , the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0131] A first terminal of the second transistor T2 (switching transistor) may be electrically connected to the data line Dj, and a second terminal of the second transistor T2 may be electrically connected to the first node N1. The first terminal and the second terminal of the second transistor T2 may be different terminals. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode. As an example, a gate electrode of the second transistor T2 may be electrically connected to the scan line Si.

[0132] When a scan signal having a voltage (e.g., a low voltage) at which the second transistor T2 can be turned on is provided, the second transistor T2 can be turned on to electrically connect the data line Dj and the first node N1. The data signal of the corresponding frame can be provided to the data line Dj. Therefore, the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be charged in the storage capacitor Cst.

[0133] A first terminal of the first transistor T1 (driving transistor) may be electrically connected to a first driving power source VDD, and a second terminal of the first transistor T1 may be electrically connected to a first electrode EL1 of each of the light emitting elements LD. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 may control the amount of driving current supplied to the light emitting element LD corresponding to a voltage of the first node N1.

[0134] One electrode of the storage capacitor Cst may be electrically connected to the first driving power source VDD, and the other electrode of the storage capacitor Cst may be electrically connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to the data signal supplied to the first node N1, and may maintain the charged voltage until a data signal of the next frame may be supplied.

[0135] exist Fig. 6A and Figure 6B In each of the figures, a pixel circuit 144 is shown, and the pixel circuit 144 may include a second transistor T2, a storage capacitor Cst, and a first transistor T1, the second transistor T2 may transmit a data signal to the inside of the pixel PXL, the storage capacitor Cst may store the data signal, and the first transistor T1 may provide a driving current corresponding to the data signal to the light emitting element LD.

[0136] However, the present disclosure is not limited thereto, and various modifications and implementations may be made to the structure of the pixel circuit 144 within the spirit and scope of the present disclosure. In an example, the pixel circuit 144 may include at least one transistor element, such as a transistor element that can compensate for the threshold voltage of the first transistor T1, a transistor element that can initialize the first node N1, and / or a transistor element that can control the emission time of the light emitting element LD, or other circuit elements such as a boost capacitor that can boost the voltage of the first node N1.

[0137] although Fig. 6A 14 shows a case where all transistors (e.g., the first transistor T1 and the second transistor T2 included in the pixel circuit 144) may be P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be an N-type transistor.

[0138] refer to Figures 1A to 4B , Figure 5 and Figure 6B According to an embodiment, the first transistor T1 and the second transistor T2 may be N-type transistors. Figure 6B The configuration or operation of the pixel circuit 144 shown in FIG. 1 may be similar to that of FIG. Fig. 6A The configuration or operation of the pixel circuit 144 shown in FIG. 1 is different in that the electrical connection positions of some components may be changed due to the change of the transistor type. Therefore, this point will be described briefly.

[0139] In an embodiment, Figure 6B The pixel circuit 144 shown in the figure may include a first transistor T1 and a second transistor T2 as N-type transistors and a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are N-type transistors, the light emitting unit EMU may be electrically connected between the first driving power supply VDD and the pixel circuit 144 to achieve stability of the storage capacitor Cst, and the storage capacitor Cst may be charged with a voltage corresponding to the data signal provided to the first node N1. However, the present disclosure is not limited thereto. In an embodiment, Figure 6B The light emitting unit EMU shown in FIG. 1 may be electrically connected between the pixel circuit 144 and the second driving power source VSS. In an embodiment, the configuration of the pixel circuit 144 is not limited to Fig. 6A and Figure 6B In an example, the pixel circuit 144 can be as shown in FIG. Figure 6C and Fig.6D As shown in the embodiment shown in .

[0140] like Figure 6C and Fig.6D As shown in , the pixel circuit 144 can be electrically connected to the scan line Si and the data line Dj of the pixel PXL. In the example, when it is assumed that the pixel PXL is set on the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the corresponding pixel PXL can be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0141] In an embodiment, the pixel circuit 144 may be electrically connected to at least another scan line. For example, the pixel PXL disposed on the i-th row of the display area DA may be electrically connected to the (i-1)th scan line Si-1 and / or the (i+1)th scan line Si+1. In an embodiment, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit 144 may be electrically connected to a third power supply. For example, the pixel circuit 144 may be electrically connected to the initialization power supply Vint.

[0142] The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0143] One electrode (e.g., source electrode) of the first transistor T1 (driving transistor) may be electrically connected to the first driving power source VDD via the fifth transistor T5, and the other electrode (e.g., drain electrode) of the first transistor T1 may be electrically connected to one end of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current flowing through the light emitting element LD between the first driving power source VDD and the second driving power source VSS corresponding to the voltage of the first node N1.

[0144] The second transistor T2 (switching transistor) may be electrically connected between the jth data line Dj electrically connected to the pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 may be electrically connected to the ith scan line Si electrically connected to the pixel PXL. When a scan signal having a gate-on voltage (e.g., a low voltage) may be supplied to the ith scan line Si, the second transistor T2 may be turned on to electrically connect the jth data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal provided from the jth data line Dj may be transmitted to the first transistor T1.

[0145] The third transistor T3 may be electrically connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be electrically connected to the i-th scan line Si. When a scan signal having a gate-on voltage may be provided from the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0146] The fourth transistor T4 may be electrically connected between the first node N1 and the initialization power line IPL, and the initialization power supply Vint may be applied to the initialization power line IPL. The gate electrode of the fourth transistor T4 may be electrically connected to a previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal having a gate-on voltage may be provided to the (i-1)th scan line Si-1, the fourth transistor T4 may be turned on to transfer the voltage of the initialization power supply Vint to the first node N1. The initialization power supply Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0147] The fifth transistor T5 may be electrically connected between the first driving power source VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be electrically connected to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage may be provided to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and the fifth transistor T5 may be turned on in other cases.

[0148] The sixth transistor T6 may be electrically connected between the first transistor T1 and one end of the light emitting element LD. The gate electrode of the sixth transistor T6 may be electrically connected to the i-th emission control line Ei. When the emission control signal having the gate-off voltage may be provided to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0149] The seventh transistor T7 may be electrically connected between one end of the light emitting element LD and a power line (e.g., an initialization power line IPL to which the initialization power supply Vint may be applied). The gate electrode of the seventh transistor T7 may be electrically connected to any one of the scan lines of the next stage, e.g., the (i+1)th scan line Si+1. When a scan signal having a gate-on voltage may be provided to the (i+1)th scan line Si+1, the seventh transistor T7 may be turned on to provide the voltage of the initialization power supply Vint to one end of the light emitting element LD.

[0150] The storage capacitor Cst may be electrically connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal supplied to the first node N1 in each frame period and a threshold voltage of the first transistor T1.

[0151] Despite Figure 6C and Fig.6D 144 may be shown as a case where all transistors (eg, the first transistor T1 to the seventh transistor T7) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be replaced with an N-type transistor.

[0152] In an embodiment, the configuration of the pixel circuit 144 is not limited to FIG. 6A to FIG. 6D In an example, the pixel circuit 144 can be as shown in FIG. Fig. 6E As shown in the embodiment shown in .

[0153] like Fig. 6E As shown in FIG. 1 , the pixel circuit 144 may be electrically connected to the control line CLi and the sensing line SENj. In an example, the pixel circuit 144 of the pixel PXL disposed on the i-th row and the j-th column of the display area DA may be electrically connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. Fig. 6A and Figure 6B In addition to the first transistor T1 and the second transistor T2 shown in FIG. 1 , the pixel circuit 144 may include a third transistor T3 .

[0154] The third transistor T3 may be electrically connected between the first transistor T1 and the sensing line SENj. For example, one electrode of the third transistor T3 may be electrically connected to one electrode (e.g., source electrode) of the first transistor T1 electrically connected to the first electrode EL1, and the other electrode of the third transistor T3 may be electrically connected to the sensing line SENj. Meanwhile, when the sensing line SENj is omitted, the gate electrode of the third transistor T3 may be electrically connected to the data line Dj.

[0155] In an embodiment, the gate electrode of the third transistor T3 may be electrically connected to the control line CLi. Meanwhile, when the control line CLi is omitted, the gate electrode of the third transistor T3 may be electrically connected to the scan line Si. The third transistor T3 may be turned on by a control signal having a gate-on voltage (e.g., a high level) to electrically connect the sensing line SENj and the first transistor T1, and the control signal may be provided to the control line CLi during a predetermined sensing period.

[0156] In an embodiment, the sensing period may be a period in which characteristic information (e.g., a threshold voltage of the first transistor T1, etc.) of each of the pixels PXL arranged or set in the display area DA is extracted. During the sensing period, a predetermined reference voltage that can turn on the first transistor T1 may be provided to the first node N1 through the data line Dj and the second transistor T2, or within the spirit and scope of the present disclosure, when each pixel PXL is electrically connected to a current source, etc., the first transistor T1 may be turned on. When the third transistor T3 is turned on by providing a control signal having a gate-on voltage to the third transistor T3, the first transistor T1 may be electrically connected to the sensing line SENj. Therefore, characteristic information (e.g., including the threshold voltage of the first transistor T1) of each pixel PXL may be extracted through the sensing line SENj. The extracted characteristic information may be used to convert image data, so that characteristic deviations between the pixels PXL may be compensated.

[0157] At the same time, despite Fig. 6E , an embodiment in which all of the first to third transistors T1 to T3 may be N-type transistors is shown, but the present disclosure is not limited thereto. For example, at least one of the first to third transistors T1 to T3 may be replaced by a P-type transistor. Fig. 6E , an embodiment in which the light emitting unit EMU may be electrically connected between the pixel circuit 144 and the second driving power source VSS is shown, but the light emitting unit EMU may be electrically connected between the first driving power source VDD and the pixel circuit 144 .

[0158] Despite FIG. 6A to FIG. 6E, all of the light emitting elements LD constituting each light emitting unit EMU can be electrically connected in parallel, but the present disclosure is not limited thereto. In an embodiment, the light emitting unit EMU may include at least one series connection stage including light emitting elements LD electrically connected in parallel to each other. For example, the light emitting unit EMU may be configured in a series / parallel hybrid structure. This will be referred to later. Fig. 7A and Figure 7B Give a description.

[0159] The structure of the pixel PXL applicable to the present disclosure is not limited to FIG. 6A to FIG. 6E , and the corresponding pixel PXL may have various structures. In the embodiment of the present disclosure, for example, each pixel PXL may be inside a passive matrix light-emitting display device. Therefore, the pixel circuit 144 may be omitted, and both ends of the light-emitting element LD included in the light-emitting unit EMU may be directly electrically connected to the scan lines Si-1, Si and Si+1, the data line Dj, the first power line PL1 to which the first drive power VDD may be applied, the second power line PL2 to which the second drive power VSS may be applied, and / or a predetermined control line.

[0160] Fig. 7A and Figure 7B It is shown Figure 5 An equivalent circuit diagram of an embodiment of electrical connections between components included in one pixel shown in FIG. Fig. 7A and Figure 7B In the embodiment, the light emitting unit EMU of each pixel PXL may include series connected stages in series. Fig. 7A and Figure 7B In the description of the embodiment shown in FIG. 1 , detailed description of components (for example, FIG. 6A to FIG. 6E The pixel circuits 144 of the embodiment shown in FIG. 1 are similar or identical to the pixel circuits 144 of the embodiment shown in FIG. 1 to avoid redundancy.

[0161] Reference Fig. 7A , the light emitting unit EMU may include light emitting elements LD electrically connected in series with each other. In an example, the light emitting unit EMU may include a first light emitting element LD1, a second light emitting element LD2, a third light emitting element LD3, and a fourth light emitting element LD4, which may be electrically connected in series in a forward direction between a first driving power source VDD and a second driving power source VSS. In subsequent embodiments, when at least one of the first light emitting element LD1 to the fourth light emitting element LD4 may be arbitrarily specified, or when the first light emitting element LD1 to the fourth light emitting element LD4 may be inclusively specified, one or more light emitting elements may be referred to as one or more light emitting elements LD.

[0162] One end of the first light emitting element LD1 (e.g., the second semiconductor layer) can be electrically connected to the first driving power supply VDD through the first electrode EL1, and the other end of the first light emitting element LD1 (e.g., the first semiconductor layer) can be electrically connected to one end of the second light emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 electrically connected between the first series stage and the second series stage.

[0163] One end of the second light emitting element LD2 can be electrically connected to the first intermediate electrode CTE1, and the other end of the second light emitting element LD2 (e.g., the first semiconductor layer) can be electrically connected to one end of the third light emitting element LD3 (e.g., the second semiconductor layer) through the second intermediate electrode CTE2 electrically connected between the second series stage and the third series stage.

[0164] One end of the third light emitting element LD3 can be electrically connected to the second intermediate electrode CTE2, and the other end of the third light emitting element LD3 (e.g., the first semiconductor layer) can be electrically connected to one end of the fourth light emitting element LD4 (e.g., the second semiconductor layer) through the third intermediate electrode CTE3 electrically connected between the third series stage and the fourth series stage.

[0165] One end of the fourth light emitting element LD4 may be electrically connected to the third intermediate electrode CTE3 , and the other end (eg, the first semiconductor layer) of the fourth light emitting element LD4 may be electrically connected to the second driving power source VSS through the second electrode EL2 .

[0166] As described above, the first to fourth light emitting elements LD1 to LD4 may be electrically connected in series between the first and second electrodes EL1 and EL2 of the light emitting unit EMU of the pixel PXL.

[0167] Compared with the light emitting unit EMU having a structure in which the light emitting elements LD can be electrically connected in parallel, in the light emitting unit EMU having a structure in which the light emitting elements LD can be electrically connected in series, the voltage applied between the first electrode EL1 and the second electrode EL2 can be increased, and the magnitude of the driving current flowing through the light emitting unit EMU can be reduced. Therefore, when the light emitting unit EMU of each pixel PXL is configured in a series structure, the power consumption of the display device can be reduced.

[0168] In an embodiment, at least one series connection stage may be configured to include light emitting elements LD electrically connected in parallel with each other. Therefore, the light emitting unit EMU of each pixel PXL may be configured as a series / parallel hybrid structure. For example, the light emitting unit EMU may be configured as follows: Figure 7B as shown in .

[0169] refer to Figure 7B, the pixel PXL may include a pixel circuit 144 and a light emitting unit EMU electrically connected to the pixel circuit 144. The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst. In an embodiment, the pixel circuit 144 may have a Figure 6C and Fig.6D The pixel circuit 144 has the same configuration as described above, and therefore, a description thereof will be omitted.

[0170] The light-emitting unit EMU of the pixel PXL may include a series stage electrically connected sequentially between a first driving power source VDD and a second driving power source VSS. For example, each of the series stages may include one or more light-emitting elements LD electrically connected in a forward direction between two electrodes of an electrode pair constituting the corresponding series stage. In an example, the light-emitting unit EMU may include a first series stage SET1 to a third series stage SET3 electrically connected sequentially between the first driving power source VDD and the second driving power source VSS. Each of the first series stage SET1 to the third series stage SET3 may include two electrodes EL1 and CE1a, CE1b and CE2a, or CE2b and EL2 constituting an electrode pair of the corresponding series stage and a light-emitting element LD electrically connected in parallel between the two electrodes EL1 and CE1a, CE1b and CE2a, or CE2b and EL2 in a forward direction (e.g., the same direction).

[0171] The first series stage SET1 may include the first electrode EL1 and the 1a-th intermediate electrode CE1a of the electrodes EL1 and CE1a, CE1b and CE2a, and CE2b and EL2 constituting the electrode pair included in the light emitting unit EMU, and may include at least one first light emitting element LD1 electrically connected between the first electrode EL1 and the 1a-th intermediate electrode CE1a. In an example, the first series stage SET1 may include the first electrode EL1 electrically connected to the first driving power source VDD via the pixel circuit 144, the 1a-th intermediate electrode CE1a electrically connected to the second driving power source VSS, and the first light emitting element LD1 electrically connected between the first electrode EL1 and the 1a-th intermediate electrode CE1a.

[0172] One end (e.g., the second semiconductor layer) of each first light emitting element LD1 may be electrically connected to the first electrode EL1 of the first series stage SET1, and the other end (e.g., the first semiconductor layer) of the first light emitting element LD1 may be electrically connected to the 1ath intermediate electrode CE1a of the first series stage SET1. The first light emitting element LD1 may be electrically connected in parallel between the first electrode EL1 and the 1ath intermediate electrode CE1a of the first series stage SET1, and may be electrically connected between the first electrode EL1 and the 1ath intermediate electrode CE1a in the same direction (e.g., the forward direction). In an embodiment, at least one reverse light emitting element (see Fig.6D 1a) may be electrically connected to the first series stage SET1. The reverse light emitting element LDr may be electrically connected in parallel with the first light emitting element LD1 constituting an effective light source between the first electrode EL1 and the 1a-th intermediate electrode CE1a, and may be electrically connected between the first electrode EL1 and the 1a-th intermediate electrode CE1a in a direction opposite to that of the first light emitting element LD1. Although a predetermined driving voltage (e.g., a driving voltage in a reverse direction) may be applied between the first electrode EL1 and the 1a-th intermediate electrode CE1a, the reverse light emitting element LDr may be maintained in an inactive state, and therefore, no current may substantially flow through the reverse light emitting element LDr.

[0173] The second series stage SET2 may include the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a of the electrodes EL1 and CE1a, CE1b and CE2a, and CE2b and EL2 constituting the electrode pair included in the light emitting unit EMU, and may include at least one second light emitting element LD2 electrically connected between the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a. In an example, the second series stage SET2 may include the 1b intermediate electrode CE1b electrically connected to the first driving power source VDD via the pixel circuit 144 and the first series stage SET1, the 2a intermediate electrode CE2a electrically connected to the second driving power source VSS, and the second light emitting element LD2 electrically connected between the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a. One end (e.g., the second semiconductor layer) of each second light emitting element LD2 may be electrically connected to the 1b intermediate electrode CE1b of the second series stage SET2, and the other end (e.g., the first semiconductor layer) of the second light emitting element LD2 may be electrically connected to the 2a intermediate electrode CE2a of the second series stage SET2. The second light emitting element LD2 may be electrically connected in parallel between the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a of the second series stage SET2, and may be electrically connected in the same direction (e.g., forward direction) between the first driving power source VDD and the second driving power source VSS through the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a. Fig.6D The reverse light emitting element LDr shown in FIG. 1 may be electrically connected between the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a. The reverse light emitting element LDr may be electrically connected in parallel with the second light emitting element LD2 constituting an effective light source between the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a, and may be electrically connected between the 1b intermediate electrode CE1b and the 2a intermediate electrode CE2a in a direction opposite to that of the second light emitting element LD2.

[0174] In an embodiment, the 1a intermediate electrode CE1a of the first tandem stage SET1 and the 1b intermediate electrode CE1b of the second tandem stage SET2 may be integrally provided or arranged to be electrically connected to each other. For example, the 1a intermediate electrode CE1a of the first tandem stage SET1 and the 1b intermediate electrode CE1b of the second tandem stage SET2 may constitute the first intermediate electrode CE1 that may electrically connect the first tandem stage SET1 and the second tandem stage SET2. As described above, when the 1a intermediate electrode CE1a of the first tandem stage SET1 and the 1b intermediate electrode CE1b of the second tandem stage SET2 may be integrally provided, the 1a intermediate electrode CE1a and the 1b intermediate electrode CE1b may be different regions of the first intermediate electrode CE1.

[0175] The third series stage SET3 may include the 2b middle electrode CE2b and the second electrode EL2 of the electrodes EL1 and CE1a, CE1b and CE2a, and CE2b and EL2 constituting the electrode pair that may be included in the light emitting unit EMU, and may include at least one third light emitting element LD3 electrically connected between the 2b middle electrode CE2b and the second electrode EL2. In an example, the third series stage SET3 may include the 2b middle electrode CE2b electrically connected to the first driving power source VDD via the pixel circuit 144 and the previous series stage (e.g., the first series stage SET1 and the second series stage SET2), the second electrode EL2 electrically connected to the second driving power source VSS, and the third light emitting element LD3 electrically connected between the 2b middle electrode CE2b and the second electrode EL2. One end (e.g., the second semiconductor layer) of each third light emitting element LD3 may be electrically connected to the 2b middle electrode CE2b of the third series stage SET3, and the other end (e.g., the first semiconductor layer) of the third light emitting element LD3 may be electrically connected to the second electrode EL2 of the third series stage SET3. The third light emitting element LD3 may be electrically connected in parallel between the 2b intermediate electrode CE2b and the second electrode EL2 of the third series stage SET3, and may be electrically connected between the first driving power source VDD and the second driving power source VSS in the same direction (e.g., forward direction) through the 2b intermediate electrode CE2b and the second electrode EL2. Fig.6D The reverse light emitting element LDr shown in FIG. 1 may be electrically connected between the 2b intermediate electrode CE2b and the second electrode EL2. The reverse light emitting element LDr may be electrically connected in parallel with the third light emitting element LD3 constituting an effective light source between the 2b intermediate electrode CE2b and the second electrode EL2, and may be electrically connected between the 2b intermediate electrode CE2b and the second electrode EL2 in a direction opposite to that of the third light emitting element LD3.

[0176] In an embodiment, the 2a intermediate electrode CE2a of the second series stage SET2 and the 2b intermediate electrode CE2b of the third series stage SET3 may be integrally provided or arranged to be electrically connected to each other. For example, the 2a intermediate electrode CE2a of the second series stage SET2 and the 2b intermediate electrode CE2b of the third series stage SET3 may constitute the second intermediate electrode CE2 that may electrically connect the second series stage SET2 and the third series stage SET3. As described above, when the 2a intermediate electrode CE2a of the second series stage SET2 and the 2b intermediate electrode CE2b of the third series stage SET3 may be integrally provided, the 2a intermediate electrode CE2a and the 2b intermediate electrode CE2b may be different regions of the second intermediate electrode CE2.

[0177] In the above embodiment, the first electrode EL1 of the first series stage SET1 may be the anode electrode of the light emitting unit EMU of each pixel PXL, and the second electrode EL2 of the third series stage SET3 may be the cathode electrode of the light emitting unit EMU.

[0178] As described above, the light emitting unit EMU of the pixel PXL (which may include light emitting elements LD electrically connected in a series / parallel hybrid structure) may easily control driving current / voltage conditions to specifications suitable for products to which the light emitting unit EMU may be applied.

[0179] As an example, compared with the light-emitting unit EMU including the light-emitting element LD electrically connected in parallel, the light-emitting unit EMU of the pixel PXL (which may include the light-emitting element LD electrically connected in a series / parallel hybrid structure) can reduce the driving current. Compared with the light-emitting unit EMU including the light-emitting element LD electrically connected in series, the light-emitting unit EMU of the pixel PXL (which may include the light-emitting element LD electrically connected in a series / parallel hybrid structure) can reduce the driving voltage applied to both ends of the light-emitting unit EMU. When all the light-emitting elements LD can be electrically connected in series, when at least one of the light-emitting elements LD electrically connected in series may not be fully electrically connected in the forward direction (or when the reverse light-emitting element LDr may be included), the path through which the driving current passes may be blocked in the pixel PXL. Therefore, a dark spot defect may be caused. On the other hand, when the light-emitting element LD can be electrically connected in a series / parallel hybrid structure, even when some light-emitting elements LD are not electrically connected in the forward direction in the corresponding series stage (or when the reverse light-emitting element LDr may be included) or when defects occur in some light-emitting elements LD, the driving current may flow through another light-emitting element LD of each series stage. Therefore, defects of the pixel PXL may be prevented or minimized.

[0180] Figure 8 It is schematically shown Figure 5 A plan view of one of the pixels shown in FIG. Fig.9A is along Figure 8 A schematic cross-sectional view taken along line II′ shown in FIG. Fig. 9B Shows Fig.9A The first contact electrode and the second contact electrode are shown in the embodiment of the present invention, and correspond to Figure 8 Schematic cross-sectional view along line II′ shown in FIG. Fig.10 is along Figure 8 A schematic cross-sectional view taken along line II-II′ shown in FIG. Fig.11 is along Figure 8 A schematic cross-sectional view taken along line III-III′ shown in FIG. Fig.12 is along Figure 8 A schematic cross-sectional view taken along line IV-IV′ shown in FIG. Fig.13 Shows Fig.12 The first bank pattern shown in the embodiment of the present invention corresponds to Figure 8 A schematic cross-sectional view along line IV-IV′ shown in FIG. Fig.14 Shows Fig.12 The embodiment of the display element portion shown in FIG. 1 corresponds to Figure 8 A schematic cross-sectional view along line IV-IV′ shown in FIG. Fig.15 Shows Fig.12 The embodiment of the display element portion shown in FIG. 1 corresponds to Figure 8 A schematic cross-sectional view along line IV-IV′ shown in FIG.

[0181] Figure 8 The pixels shown in FIG. 1 may be FIG. 6A to FIG. 6E , Fig. 7A and Figure 7B Any one of the pixels shown in .

[0182] exist Figure 8 In the figure, for the sake of convenience, the illustration of the transistor electrically connected to the light emitting element may be omitted. Figure 8 , for convenience, only some of the signal lines provided or disposed in the pixel area PXA of each pixel PXL, for example, the data line Dj and the initialization power line IPL may be illustrated.

[0183] exist Figures 8 to 15 In the embodiment, the structure of one pixel PXL may be simplified and illustrated, for example, each electrode may be illustrated as a single electrode layer and each insulating layer may be illustrated as a single insulating layer. However, the present disclosure is not limited thereto.

[0184] In an embodiment, the term “formed and / or provided in the same layer” may mean formed in the same process, and the term “formed and / or provided in different layers” may mean formed in different processes.

[0185] In embodiments, the term "connected" between two components may include electrical connection, physical connection, or a combination thereof.

[0186] refer to Figures 1A to 5 as well as Figures 8 to 15 , a display device according to an embodiment may include a substrate SUB, a line unit, and a pixel PXL.

[0187] The substrate SUB may include a transparent insulating material to enable light to be transmitted through the substrate SUB. The substrate SUB may be a rigid substrate or a flexible substrate.

[0188] The rigid substrate may include, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. The flexible substrate may be one of a film substrate and a plastic substrate that may include a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0189] In a manufacturing process of the display device, a material applied to the substrate SUB may have resistance (or heat resistance) to a high processing temperature.

[0190] The substrate SUB may include a display area DA including at least one pixel area PXA in which the pixel PXL may be disposed, and a non-display area NDA disposed at a periphery of the display area DA or adjacent to the display area DA.

[0191] The pixel area PXA in which each pixel PXL may be disposed (or provided) may include an emission area EMA in which light may be emitted and a peripheral area surrounding the periphery of the emission area EMA. In an embodiment, the peripheral area may include a non-emission area that may not emit light.

[0192] The line unit may include a signal line that can transmit a signal (or voltage) to each pixel PXL. The signal line may include a scan line that can transmit a scan signal to each pixel PXL (for example, see Fig. 6A 'Si' shown in FIG), a data line Dj that can transmit a data signal to each pixel PXL, an initialization power line IPL that can transmit an initialization power to each pixel PXL, an emission control line that can transmit an emission control signal to each pixel PXL (eg, see Figure 6C'Ei' shown in ) and similar lines within the spirit and scope of the present disclosure. However, the present disclosure is not limited thereto. In an embodiment, in addition to the above-mentioned signal lines, the line unit may include signal lines that can transmit other signals.

[0193] The data line Dj may extend in one direction (eg, the second direction DR2 ). A data signal may be applied to the data line Dj. In an implementation, the data line Dj may be provided and / or formed and / or disposed on the first interlayer insulating layer ILD1 .

[0194] The first interlayer insulating layer ILD1 may be an inorganic insulating layer including an inorganic material. In an example, the first interlayer insulating layer ILD1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and metal oxides (such as AlO x The first interlayer insulating layer ILD1 may be provided as a single layer, but may also be provided as a multilayer including at least two layers.

[0195] The initialization power line IPL may extend in the same direction as the extension direction of the data line Dj, and may be disposed to be spaced apart from the data line Dj. The extension direction of the initialization power line IPL is not limited to the above-described embodiment. In an embodiment, the initialization power line IPL may extend in a first direction DR1 intersecting with the second direction DR2. An initialization power source may be applied to the initialization power line IPL. In an embodiment, the initialization power line IPL may be provided and / or formed and / or disposed on the first interlayer insulating layer ILD1.

[0196] Each pixel PXL may include a pixel circuit layer PCL and a display element layer DPL, which may be provided or disposed on a substrate SUB and may include a pixel circuit 144, and a display element layer DPL including a light emitting element LD. The light emitting element LD may be located or disposed in an emission area EMA of a pixel area PXA of each pixel PXL.

[0197] For convenience, the pixel circuit layer PCL will be described first, and the display element layer DPL will then be described.

[0198] The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 , and a passivation layer PSV.

[0199] The buffer layer BFL may be disposed on the substrate SUB and prevent impurities from diffusing into the pixel circuit (see FIG. 6A to FIG. 7B The buffer layer BFL may be an inorganic insulating layer including an inorganic material. In an example, the buffer layer BFL may include silicon nitride (SiN x), silicon oxide (SiO x ), silicon oxynitride (SiON), and metal oxides (such as AlO x ). The buffer layer BFL may be provided as a single layer, but may also be provided as a multilayer including at least two layers. When the buffer layer BFL is provided as a multilayer, the layers may be formed of the same or similar material or of different materials. Depending on the material of the substrate SUB and the process conditions, the buffer layer BFL may be omitted.

[0200] The pixel circuit 144 may include at least one transistor and a storage capacitor Cst. The transistor may include a driving transistor Tdr that can control the driving current of the light emitting element LD and a switching transistor Tsw electrically connected to the driving transistor Tdr. However, the present disclosure is not limited thereto, and in addition to the driving transistor Tdr and the switching transistor Tsw, the pixel circuit 144 may include a circuit element that can perform another function. In the following embodiments, when one of the driving transistor Tdr and the switching transistor Tsw is arbitrarily specified, or when the driving transistor Tdr and the switching transistor Tsw are inclusively specified, one or more transistors may be referred to as one or more transistors T.

[0201] Each of the driving transistor Tdr and the switching transistor Tsw may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be any one of a source electrode and a drain electrode, and the second terminal DE may be the other of the source electrode and the drain electrode. In an example, when the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0202] The transistor semiconductor pattern SCL may be provided and / or formed and / or disposed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region in contact with the first terminal SE and a second contact region in contact with the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be made of polycrystalline silicon, amorphous silicon, an oxide semiconductor, or other materials within the spirit and scope of the present disclosure. The channel region may be a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities.

[0203] The gate electrode GE may be provided and / or formed and / or disposed on the transistor semiconductor pattern SCL, and the gate insulating layer GI is interposed or disposed between the gate electrode GE and the transistor semiconductor pattern SCL.

[0204] The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. In an example, the gate insulating layer GI may include silicon nitride (SiN x), silicon oxide (SiO x ), silicon oxynitride (SiON), and metal oxides (such as AlO x ) at least one of. However, the material of the gate insulating layer GI is not limited to the above-mentioned embodiment. In an embodiment, the gate insulating layer GI may be an organic insulating layer including an organic material. The gate insulating layer GI may be provided as a single layer, but may also be provided as a multilayer including at least two layers.

[0205] The first terminal SE and the second terminal DE may respectively contact the first contact region and the second contact region of the transistor semiconductor pattern SCL through contact holes penetrating the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0206] In the above-mentioned embodiments, it has been described that the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be a separate electrode electrically connected to the transistor semiconductor pattern SCL, but the present disclosure is not limited thereto. In an embodiment, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be one of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL, and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. Therefore, the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be electrically connected to the light emitting element LD of the corresponding pixel PXL through a bridging electrode, a contact electrode, or such electrodes within the spirit and scope of the present disclosure.

[0207] In an embodiment, the transistor T included in the pixel circuit 144 may be a low temperature polycrystalline silicon (LTPS) thin film transistor, but the present disclosure is not limited thereto. In an embodiment, the transistor T may be an oxide semiconductor thin film transistor. As an example, a case where the transistor T is a thin film transistor having a top gate structure is described, but the present disclosure is not limited thereto. In an embodiment, the transistor T may be a thin film transistor having a bottom gate structure.

[0208] In an embodiment, the pixel circuit layer PCL may include a connection electrode STE disposed on the first interlayer insulating layer ILD1. The connection electrode STE may be electrically connected to a portion of the components of the driving transistor Tdr. In an example, the connection electrode STE may be electrically connected to the second contact region of the driving transistor Tdr. The connection electrode STE may be used as a bridge for electrically connecting components included in the pixel circuit 144 or may be used as one electrode of the storage capacitor Cst. The connection electrode STE may be provided and / or formed and / or disposed on the first interlayer insulating layer ILD1 and may be disposed to be spaced apart from the data line Dj and the initialization power line IPL.

[0209] A second interlayer insulating layer ILD2 may be provided or disposed over the driving transistor Tdr, the switching transistor Tsw, the data line Dj, the initialization power line IPL, and the connection electrode STE as described above. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In an embodiment, the second interlayer insulating layer ILD2 may include a material that is the same as or similar to the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single layer, but may also be provided as a multilayer including at least two layers. The second interlayer insulating layer ILD2 may include a first contact hole CH1 that exposes a portion of the driving transistor Tdr.

[0210] The sub-electrode SUE and the first to fourth conductive lines SL1 to SL4 may be disposed on the second interlayer insulating layer ILD2. The sub-electrode SUE and the first to fourth conductive lines SL1 to SL4 may be spaced apart from each other on the second interlayer insulating layer ILD2.

[0211] Each of the first to fourth conductive lines SL1 to SL4 may extend along the second direction DR2 and may be commonly provided to each pixel PXL and an adjacent pixel PXL located or arranged on the same pixel column as the pixel PXL. The first conductive line SL1 and the second conductive line SL2 may be spaced apart from each other by a certain or predetermined distance, the second conductive line SL2 and the third conductive line SL3 may be spaced apart from each other by a certain or predetermined distance, and the third conductive line SL3 and the fourth conductive line SL4 may be spaced apart from each other by a certain or predetermined distance. In the pixel area PXA of each pixel PXL, the first conductive line SL1 and the second conductive line SL2, the second conductive line SL2 and the third conductive line SL3, and the third conductive line SL3 and the fourth conductive line SL4 may be spaced apart from each other by the same distance. However, the present disclosure is not limited thereto. In an embodiment, the first conductive line SL1 and the second conductive line SL2, the second conductive line SL2 and the third conductive line SL3, and the third conductive line SL3 and the fourth conductive line SL4 may be spaced apart from each other by different distances.

[0212] The first conductive line SL1 may be electrically connected to a portion of the components, for example, the first electrode EL1 of the display element layer DPL, through the second contact hole CH2 penetrating the passivation layer PSV. When the light emitting element LD in the emission area EMA of each pixel PXL can be aligned, the first conductive line SL1 may allow the first electrode EL1 to be used as a first alignment electrode (or first alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the first electrode EL1. In an embodiment, the first conductive line SL1 may be used together with the first electrode EL1 as an alignment electrode (or alignment line), which may align the light emitting element LD in the emission area EMA of each pixel PXL.

[0213] The second conductive line SL2 may be electrically connected to a portion of the components, for example, the first intermediate electrode CE1 of the display element layer DPL, through the third contact hole CH3 penetrating the passivation layer PSV. When the light emitting element LD in the emission area EMA of each pixel PXL can be aligned, the second conductive line SL2 may allow the first intermediate electrode CE1 to be used as a second alignment electrode (or second alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the first intermediate electrode CE1. In an embodiment, the second conductive line SL2 may be used together with the first intermediate electrode CE1 as an alignment electrode (or alignment line), which may align the light emitting element LD in the emission area EMA of each pixel PXL.

[0214] The third conductive line SL3 may be electrically connected to a portion of the components, for example, the second intermediate electrode CE2 of the display element layer DPL, through the fourth contact hole CH4 penetrating the passivation layer PSV. When the light emitting element LD in the emission area EMA of each pixel PXL can be aligned, the third conductive line SL3 may allow the second intermediate electrode CE2 to be used as a third alignment electrode (or third alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the second intermediate electrode CE2. In an embodiment, the third conductive line SL3 may be used together with the second intermediate electrode CE2 as an alignment electrode (or alignment line), which may align the light emitting element LD in the emission area EMA of each pixel PXL.

[0215] The fourth conductive line SL4 may be electrically connected to a portion of the components, for example, the second electrode EL2 of the display element layer DPL, through the fifth contact hole CH5 penetrating the passivation layer PSV. When the light emitting element LD in the emission area EMA of each pixel PXL can be aligned, the fourth conductive line SL4 may allow the second electrode EL2 to be used as a fourth alignment electrode (or fourth alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the second electrode EL2. In an embodiment, the fourth conductive line SL4 may be used together with the second electrode EL2 as an alignment electrode (or alignment line), which may align the light emitting element LD in the emission area EMA of each pixel PXL.

[0216] The second driving power VSS that can drive the light emitting element LD can be applied to the fourth conductive line SL4 after the light emitting element LD can be aligned in the emission area EMA of each pixel PXL. In an example, the fourth conductive line SL4 can have a FIG. 6A to FIG. 7B The second power line PL2 is described with the same or similar configuration.

[0217] After the light emitting element LD may be aligned in the emission area EMA of each pixel PXL, a predetermined signal (or voltage) may be applied to each of the first to fourth conductive lines SL1 to SL4, or may not be applied to each of the first to fourth conductive lines SL1 to SL4. When a predetermined signal (or voltage) is applied to each of the first to fourth conductive lines SL1 to SL4, the same signal (or voltage) may be applied to the first and third conductive lines SL3, and the same signal (or voltage) may be applied to the second and fourth conductive lines SL2 and SL4. In an example, a first driving power source VDD may be applied to the first and third conductive lines SL1 and SL3, and a second driving power source VSS may be applied to the second and fourth conductive lines SL2 and SL4. The first and third conductive lines SL1 and SL3 may have the same voltage as the reference voltage. FIG. 6A to FIG. 7B The first power line PL1 described above has the same configuration, and the second conductive line SL2 and the fourth conductive line SL4 may have the same configuration as that of the reference FIG. 6A to FIG. 7B When a predetermined signal (or voltage) is not applied to each of the first to fourth conductive lines SL1 to SL4, the first to fourth conductive lines SL1 to SL4 may be in a floating state.

[0218] In an embodiment, the first to fourth conductive lines SL1 to SL4 may be disposed on the second interlayer insulating layer ILD2 to block an electric field induced from the transistor T included in the pixel circuit layer PCL and a signal line electrically connected to the transistor T, thereby preventing the electric field from affecting the alignment and / or driving of the light emitting element LD provided or disposed in the display element layer DPL. For example, the first to fourth conductive lines SL1 to SL4 may be used as electric field shielding lines.

[0219] The sub-electrode SUE may be spaced apart from the first conductive line SL1 to be electrically and / or physically separated from the first conductive line SL1. The sub-electrode SUE may be electrically connected to the driving transistor Tdr through the first contact hole CH1 penetrating the second interlayer insulating layer ILD2. Therefore, a predetermined signal applied to the driving transistor Tdr may be transmitted to the sub-electrode SUE.

[0220] The sub-electrode SUE may be electrically connected to a partial component, for example, the third electrode EL3 of the display element layer DPL, through the seventh contact hole CH7 penetrating the passivation layer PSV. After the light emitting element LD may be aligned in the emission area EMA of each pixel PXL, the sub-electrode SUE may allow the third electrode EL3 to function as a driving electrode of the light emitting element LD by transferring a predetermined signal applied to the driving transistor Tdr to the third electrode EL3.

[0221] The above-mentioned sub-electrode SUE and the first conductive line SL1 to the fourth conductive line SL4 can be arranged on the second interlayer insulating layer ILD2, and can include the same or similar materials. In the example, the sub-electrode SUE and the first conductive line SL1 to the fourth conductive line SL4 can be formed as a single layer including one selected from the group consisting of molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and any alloy or mixture thereof, or can be formed as a double-layer or multi-layer structure including molybdenum (Mo), aluminum (Al) or silver (Ag), which are low-resistance materials to reduce wiring resistance. In an embodiment, the sub-electrode SUE and the first conductive line SL1 to the fourth conductive line SL4 can be formed as a double layer in which a first layer and a second layer can be stacked. The first layer can be made of copper (Cu) and can have a thickness of about 1000 W. The second layer may be made of titanium (Ti) and may have a thickness of about However, the materials of the sub-electrode SUE and the first to fourth conductive lines SL1 to SL4 are not limited to the above-described embodiments.

[0222] A passivation layer PSV may be disposed on the sub-electrode SUE and the first to fourth conductive lines SL1 to SL4 .

[0223] The passivation layer PSV may include an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. The inorganic insulating layer may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and metal oxides (such as AlO x ). The organic insulating layer may include an organic insulating material through which light can pass. For example, the organic insulating layer may include at least one of a photoresist, a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0224] In an embodiment, the passivation layer PSV may include a second contact hole CH2 exposing a portion of the first conductive line SL1, a third contact hole CH3 exposing a portion of the second conductive line SL2, a fourth contact hole CH4 exposing a portion of the third conductive line SL3, a fifth contact hole CH5 exposing a portion of the fourth conductive line SL4, a sixth contact hole CH6 exposing another portion of the fourth conductive line SL4, and a seventh contact hole CH7 exposing a portion of the sub-electrode SUE.

[0225] The display element layer DPL may be disposed on the passivation layer PSV.

[0226] The display element layer DPL may include a first bank pattern BNK1 , first to fourth electrodes EL1 to EL4 , first and second intermediate electrodes CE1 and CE2 , a light emitting element LD, and a contact electrode CNE.

[0227] The first bank pattern BNK1 may be a support member that may support each of the first and second electrodes EL1 and EL2 to change a surface profile of each of the first and second electrodes EL1 and EL2 so that light emitted from the light emitting element LD may further advance in an image display direction of the display device.

[0228] The first bank pattern BNK1 may be disposed and / or formed between the passivation layer PSV and the first electrode EL1 and the second electrode EL2 in the emission area EMA of each pixel PXL. In an example, the first bank pattern BNK1 may be disposed and / or formed between the passivation layer PSV and the first electrode EL1 and between the passivation layer PSV and the second electrode EL2. The first bank pattern BNK1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. In an embodiment, the first bank pattern BNK1 may include an organic insulating layer disposed in a single layer and / or an inorganic insulating layer disposed in a single layer, but the present disclosure is not limited thereto. In an embodiment, the first bank pattern BNK1 may be disposed in the form of a multilayer, in which at least one organic insulating layer and at least one inorganic insulating layer may be stacked. However, the material of the first bank pattern BNK1 is not limited to the above-mentioned embodiment. In an embodiment, the first bank pattern BNK1 may include a conductive material.

[0229] The first bank pattern BNK1 may have a cross-section having a substantially trapezoidal shape, and the trapezoidal shape may become narrower as approaching the top of the passivation layer PSV from one surface thereof, but the present disclosure is not limited thereto. Fig.13 As shown in , the first bank pattern BNK1 may include a curved surface and have a cross section arranged in a substantially semi-elliptical shape, a substantially semicircular shape (or a substantially hemispherical shape), etc., which may become narrower as one surface of the passivation layer PSV approaches its top. When viewed in cross section, the shape of the first bank pattern BNK1 is not limited to the above-mentioned embodiment, and may be varied within a range or accordingly, so that the efficiency of light emitted from each of the light emitting elements LD may be improved. Adjacent first bank patterns BNK1 may be arranged on the same plane of the passivation layer PSV and may have the same height (or thickness).

[0230] The first bank pattern BNK1 may have a substantially bar shape extending in one direction, for example, the second direction DR2 (vertical direction) in a plan view. However, the present disclosure is not limited thereto, and the first bank pattern BNK1 may be provided in various shapes.

[0231] Although not directly shown in the drawings, a second bank pattern may be provided or disposed in a peripheral area of ​​the pixel area PXA of each pixel PXL.

[0232] The second embankment pattern may surround at least one side of the peripheral area included in the pixel area PXA of each pixel PXL. The second embankment pattern may be a structure that can define (or divide) the emission area EMA of each pixel PXL and the pixels PXL adjacent thereto, and may be, for example, a pixel defining layer. The second embankment pattern may include at least one light blocking material and / or at least one reflective material to prevent light leakage defects in which light (or light beams) may leak between each pixel PXL and the pixels PXL adjacent thereto. In an embodiment, a reflective material layer may be formed over the second embankment pattern to further improve the efficiency of light emitted from each pixel PXL. In an embodiment, the second embankment pattern may be formed or disposed in a layer different from that of the first embankment pattern BNK1, or may be formed or disposed in the same layer as the first embankment pattern BNK1.

[0233] Each of the first electrode EL1 and the second electrode EL2 may be provided or disposed in the pixel area PXA of each pixel PXL, and may extend along the second direction DR2. The first intermediate electrode CE1 and the second intermediate electrode CE2 may be disposed between the first electrode EL1 and the second electrode EL2. In an example, the first intermediate electrode CE1 may be disposed between the first electrode EL1 and the second electrode EL2, and the second intermediate electrode CE2 may be disposed between the first intermediate electrode CE1 and the second electrode EL2. In a plan view, the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be sequentially arranged or disposed along the first direction DR1.

[0234] Each of the first electrode EL1 and the second electrode EL2 and the first intermediate electrode CE1 and the second intermediate electrode CE2 may extend along the second direction DR2 and may be disposed in the pixel region PXA of each pixel PXL, or only in the pixel region PXA of each pixel PXL. The first electrode EL1 and the first intermediate electrode CE1 may be spaced apart from each other by a certain or predetermined distance, the first intermediate electrode CE1 and the second intermediate electrode CE2 may be spaced apart from each other by a certain or predetermined distance, and the second intermediate electrode CE2 and the second electrode EL2 may be spaced apart from each other by a certain or predetermined distance. In the pixel region PXA of each pixel PXL, the first electrode EL1 and the first intermediate electrode CE1, the first intermediate electrode CE1 and the second intermediate electrode CE2, and the second intermediate electrode CE2 and the second electrode EL2 may be spaced apart from each other by the same distance. However, the present disclosure is not limited thereto. In an embodiment, the first electrode EL1 and the first intermediate electrode CE1, the first intermediate electrode CE1 and the second intermediate electrode CE2, and the second intermediate electrode CE2 and the second electrode EL2 may be spaced apart from each other by different distances.

[0235] Each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be disposed and / or formed on the first bank pattern BNK1 to have a surface profile substantially corresponding to the shape of the first bank pattern BNK1. In an example, each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may include a protruding portion substantially corresponding to the first bank pattern BNK1 and a flat portion substantially corresponding to the passivation layer PSV. Each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be made of a material having a constant reflectivity to allow light emitted from each of the light emitting elements LD to advance in an image display direction of the display device.

[0236] Each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be made of a conductive material having a constant reflectivity. The conductive material may include an opaque metal, which is advantageous in that it reflects light emitted from the light emitting element LD in the image display direction of the display device. For example, the opaque metal may include a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or any alloy thereof. In an embodiment, each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may include a transparent conductive material. The transparent conductive material may include a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)), a conductive polymer (such as PEDOT), and similar transparent conductive materials within the spirit and scope of the present disclosure. When each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 includes a transparent conductive material, a separate conductive layer may be further included, which may be made of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device. However, the material of each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 is not limited to the above materials.

[0237] Each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be provided and / or formed as a single layer, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be provided and / or formed as a multilayer, in which two or more materials of metals, alloys, conductive oxides, and conductive polymers may be stacked. Each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be provided as a multilayer including at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to the two ends EP1 and EP2 of each of the light emitting elements LD. In an example, each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be provided as a multilayer in which indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO) may be stacked sequentially.

[0238] As described above, since each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may have a surface profile substantially corresponding to the shape of the first bank pattern BNK1 disposed on the bottom thereof, light emitted from each of the light emitting elements LD may be reflected by each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 to further advance in the image display direction of the display device. Therefore, the efficiency of light emitted from each of the light emitting elements LD may be further improved.

[0239] Each of the first bank pattern BNK1, the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2 and the second electrode EL2 may function as a reflective member that allows light emitted from the light emitting element LD to proceed in an image display direction of the display device, thereby improving light emission efficiency of the light emitting element LD.

[0240] In an embodiment, the first electrode EL1 may be disposed to substantially correspond to the first conductive line SL1, the first intermediate electrode CE1 may be disposed to substantially correspond to the second conductive line SL2, the second intermediate electrode CE2 may be disposed to substantially correspond to the third conductive line SL3, and the second electrode EL2 may be disposed to substantially correspond to the fourth conductive line SL4. The first electrode EL1 may be disposed on the first bank pattern BNK1 on the passivation layer PSV that may substantially correspond to the first conductive line SL1. The first intermediate electrode CE1 may be provided or disposed on the first bank pattern BNK1 on the passivation layer PSV that may substantially correspond to the second conductive line SL2. The second intermediate electrode CE2 may be provided or disposed on the first bank pattern BNK1 on the passivation layer PSV that may substantially correspond to the third conductive line SL3. The second electrode EL2 may be provided or disposed on the first bank pattern BNK1 on the passivation layer PSV that may substantially correspond to the fourth conductive line SL4.

[0241] In a plan view, the first electrode EL1 and the first conductive line SL1 may overlap each other, the first intermediate electrode CE1 and the second conductive line SL2 may overlap each other, the second intermediate electrode CE2 and the third conductive line SL3 may overlap each other, and the second electrode EL2 and the fourth conductive line SL4 may overlap each other.

[0242] The first electrode EL1 may be electrically connected to the first conductive line SL1 through a second contact hole CH2 penetrating the passivation layer PSV. Based on the passivation layer PSV, the first conductive line SL1 may be a lower conductive layer disposed on the bottom of the passivation layer PSV, and the first electrode EL1 may be an upper conductive layer disposed on the top of the passivation layer PSV. The first electrode EL1 may be electrically connected to the first conductive line SL1 through the second contact hole CH2 to be provided or disposed as a double layer with the first conductive line SL1, thereby minimizing distortion that may be caused by signal delay by reducing wiring resistance.

[0243] Although the case where the first electrode EL1 is electrically connected to the first conductive line SL1 to be provided or arranged as a double layer together with the first conductive line SL1 is shown in the above embodiment, the present disclosure is not limited thereto. In an embodiment, in order to minimize wiring resistance, the first electrode EL1 may be electrically connected to any one of the conductive layers disposed on the bottom of the first conductive line SL1 (for example, disposed on the first interlayer insulating layer ILD1) to be provided or arranged as a triple layer together with the conductive layer and the first conductive line SL1.

[0244] The first intermediate electrode CE1 may be electrically connected to the second conductive line SL2 through the third contact hole CH3 penetrating the passivation layer PSV. Based on the passivation layer PSV, the second conductive line SL2 may be a lower conductive layer disposed on the bottom of the passivation layer PSV, and the first intermediate electrode CE1 may be an upper conductive layer disposed on the top of the passivation layer PSV. The first intermediate electrode CE1 may be electrically connected to the second conductive line SL2 through the third contact hole CH3 to be provided or disposed as a double layer with the second conductive line SL2, thereby minimizing distortion that may be caused by signal delay by reducing wiring resistance.

[0245] Although the case where the first intermediate electrode CE1 may be electrically connected to the second conductive line SL2 to be provided or arranged as a double layer together with the second conductive line SL2 is shown in the above-mentioned embodiment, the present disclosure is not limited thereto. In an embodiment, in order to minimize wiring resistance, the first intermediate electrode CE1 may be electrically connected to any one of the conductive layers disposed on the bottom of the second conductive line SL2 (for example, disposed on the first interlayer insulating layer ILD1) to be provided or arranged as a triple layer together with the conductive layer and the second conductive line SL2.

[0246] The second intermediate electrode CE2 may be electrically connected to the third conductive line SL3 through a fourth contact hole CH4 penetrating the passivation layer PSV. Based on the passivation layer PSV, the third conductive line SL3 may be a lower conductive layer disposed on the bottom of the passivation layer PSV, and the second intermediate electrode CE2 may be an upper conductive layer disposed on the top of the passivation layer PSV. The second intermediate electrode CE2 may be electrically connected to the third conductive line SL3 through the fourth contact hole CH4 to be provided or disposed as a double layer with the third conductive line SL3, thereby minimizing distortion that may be caused by signal delay by reducing wiring resistance.

[0247] Although the case where the second intermediate electrode CE2 may be electrically connected to the third conductive line SL3 to be provided or arranged as a double layer together with the third conductive line SL3 is shown in the above-mentioned embodiment, the present disclosure is not limited thereto. In an embodiment, in order to minimize wiring resistance, the second intermediate electrode CE2 may be electrically connected to any one of the conductive layers disposed on the bottom of the third conductive line SL3 (for example, disposed on the first interlayer insulating layer ILD1) to be provided or arranged as a triple layer together with the conductive layer and the third conductive line SL3.

[0248] The second electrode EL2 may be electrically connected to the fourth conductive line SL4 through the fifth contact hole CH5 penetrating the passivation layer PSV. Based on the passivation layer PSV, the fourth conductive line SL4 may be a lower conductive layer disposed on the bottom of the passivation layer PSV, and the second electrode EL2 may be an upper conductive layer disposed on the top of the passivation layer PSV. The second electrode EL2 may be electrically connected to the fourth conductive line SL4 through the fifth contact hole CH5 to be provided or disposed as a double layer with the fourth conductive line SL4, thereby minimizing distortion that may be caused by signal delay by reducing wiring resistance.

[0249] Although the above-mentioned embodiment shows the case where the second electrode EL2 can be electrically connected to the fourth conductive line SL4 to be provided or arranged as a double layer together with the fourth conductive line SL4, the present disclosure is not limited thereto. In an embodiment, in order to minimize wiring resistance, the second electrode EL2 can be electrically connected to any one of the conductive layers arranged on the bottom of the fourth conductive line SL4 (for example, arranged on the first interlayer insulating layer ILD1) to be provided or arranged as a triple layer together with the conductive layer and the fourth conductive line SL4.

[0250] The first electrode EL1 , the first and second intermediate electrodes CE1 and CE2 , and the second electrode EL2 may be formed to be disposed in the pixel area PXA of each pixel PXL, or disposed only in the pixel area PXA of each pixel PXL.

[0251] The third electrode EL3 may be disposed on the passivation layer PSV to be spaced apart from the first electrode EL1, and may be electrically separated from the first electrode EL1. The third electrode EL3 may be electrically connected to the sub-electrode SUE through the seventh contact hole CH7 penetrating the passivation layer PSV. The third electrode EL3 may be electrically connected to the driving transistor Tdr of the pixel circuit layer PCL through the sub-electrode SUE. Therefore, a predetermined signal applied to the driving transistor Tdr may be transmitted to the third electrode EL3 via the sub-electrode SUE.

[0252] The fourth electrode EL4 may be disposed on the passivation layer PSV to be spaced apart from the second electrode EL2. The fourth electrode EL4 may be electrically connected to the fourth conductive line SL4 through a sixth contact hole CH6 penetrating the passivation layer PSV. The fourth electrode EL4 may be electrically connected to the second electrode EL2 through the fourth conductive line SL4. In an embodiment of the present disclosure, the second driving power source VSS may be applied to the fourth conductive line SL4. Therefore, the second driving power source VSS applied to the fourth conductive line SL4 may be applied to the second electrode EL2 and the fourth electrode EL4.

[0253] In an embodiment, each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may receive a predetermined alignment signal (or alignment voltage) transmitted from a corresponding conductive line, and each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 may be used together with the corresponding conductive line as an alignment electrode (or alignment line) that may align the light emitting element LD. In an example, the first electrode EL1 may receive a first alignment signal (or a first alignment voltage) transmitted from the first conductive line SL1, and the first electrode EL1 may be used together with the first conductive line SL1 as a first alignment electrode (or a first alignment line), and the first intermediate electrode CE1 may receive a second alignment signal (or a second alignment voltage) transmitted from the second conductive line SL2, and the first intermediate electrode CE1 may be used together with the second conductive line SL2 as a second alignment electrode (or a second alignment line). The second intermediate electrode CE2 can receive a third alignment signal (or a third alignment voltage) transmitted from the third conductive line SL3, and the second intermediate electrode CE2 can be used together with the third conductive line SL3 as a third alignment electrode (or a third alignment line), and the second electrode EL2 can receive a fourth alignment signal (or a fourth alignment voltage) transmitted from the fourth conductive line SL4, and the second electrode EL2 can be used together with the fourth conductive line SL4 as a fourth alignment electrode (or a fourth alignment line).

[0254] The first to fourth alignment signals may be signals having a voltage difference and / or a phase difference to such an extent that the light emitting element LD may be aligned between the first electrode EL1, the first and second intermediate electrodes CE1 and CE2, and the second electrode EL2. In an embodiment, among the first to fourth alignment signals, the first and third alignment signals may have the same voltage level, and the second and fourth alignment signals may have the same voltage level.

[0255] At least some of the first to fourth alignment signals may be alternating current (AC) signals, but the present disclosure is not limited thereto.

[0256] When a corresponding alignment signal may be applied to each of the first electrode EL1, the first and second intermediate electrodes CE1 and CE2, and the second electrode EL2, an electric field may be formed between the first electrode EL1 and the first intermediate electrode CE1, between the first and second intermediate electrodes CE1 and between the second intermediate electrodes CE2 and the second electrode EL2. The light emitting element LD may be aligned and / or disposed in the emission area EMA of each pixel PXL by the electric field formed between two adjacent electrodes.

[0257] In an embodiment, when the light emitting element LD can be aligned in the emission area EMA of each pixel PXL, an alignment signal (or alignment voltage) applied to each of the first electrode EL1, the first intermediate electrode CE1 and the second intermediate electrode CE2 and the second electrode EL2 can be controlled, or a magnetic field can be formed so that the light emitting element LD provided in the emission area EMA can be aligned to be relatively biased.

[0258] Each of the light-emitting elements LD can be a light-emitting element having a micron size, for example, having a small size in the range of nanometer to micrometer, and the light-emitting element LD can be manufactured using a material having an inorganic crystal structure. For example, each of the light-emitting elements LD can be a micro-light-emitting element manufactured by an etching process or a micro-light-emitting element manufactured by a growth process. However, the kind or type, size, shape, etc. of the light-emitting element LD can be changed differently within the spirit and scope of the present disclosure. At least two or dozens of light-emitting elements LD can be aligned and / or provided and / or arranged in the emission area EMA of each pixel PXL, but the number of light-emitting elements LD is not limited thereto. In an embodiment, the number of light-emitting elements LD aligned and / or provided and / or arranged in the emission area EMA of each pixel PXL can be changed differently within the spirit and scope of the present disclosure.

[0259] Each of the light emitting elements LD may be disposed between two electrodes adjacent in the first direction DR1. The light emitting element LD may include a first light emitting element LD1 disposed between the first electrode EL1 and the first intermediate electrode CE1, a second light emitting element LD2 disposed between the first intermediate electrode CE1 and the second intermediate electrode CE2, and a third light emitting element LD3 disposed between the second intermediate electrode CE2 and the second electrode EL2. In the following embodiments, when one of the first to third light emitting elements LD1 to LD3 is arbitrarily specified, or when the first to third light emitting elements LD1 to LD3 are inclusively specified, one or more light emitting elements may be referred to as one or more light emitting elements LD.

[0260] In an embodiment, each of the light emitting elements LD may emit any one of colored light and white light. Each of the light emitting elements LD may be aligned between two adjacent electrodes so that its length direction may be substantially parallel to the first direction DR1. The light emitting elements LD may be provided or arranged in a form in which they may be dispersed in a solution to be injected into the emission area EMA of each pixel PXL.

[0261] In an embodiment, the light emitting element LD may be injected into the emission area EMA of each pixel PXL by an inkjet printing process, a slit coating process, or other various processes within the spirit and scope of the present disclosure. In an example, the light emitting element LD may be mixed with a volatile solvent to be provided to the emission area EMA of each pixel PXL by an inkjet printing process or a slit coating process. When a corresponding alignment signal (or alignment voltage) is applied to each of the first conductive line SL1 to the fourth conductive line SL4 located or disposed in the pixel area PXA of each pixel PXL, an electric field may be formed between two adjacent electrodes of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2.

[0262] After the light emitting element LD may be aligned, the solvent may be volatilized or removed through another process, so that the light emitting element LD may be finally aligned and / or provided and / or disposed in the emission area EMA of each pixel PXL.

[0263] The above-mentioned light emitting element LD may be provided and / or formed and / or disposed on the first insulating layer INS1 in the emission area EMA of each pixel PXL.

[0264] The first insulating layer INS1 may be formed and / or provided and / or disposed on the bottom of each of the light emitting elements LD, and the light emitting element LD may be aligned and / or provided and / or disposed between the two electrodes in the emission area EMA of each pixel PXL. The first insulating layer INS1 may fill in the space between each of the light emitting elements LD and the passivation layer PSV to stably support the light emitting element LD and prevent the light emitting element LD from being separated from the passivation layer PSV.

[0265] The first insulating layer INS1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. In an embodiment, the first insulating layer INS1 may be an inorganic insulating layer that is conducive to protecting the light emitting element LD from the pixel circuit layer PCL of each pixel PXL, but the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be an organic insulating layer that is conducive to flattening the support surface of the light emitting element LD.

[0266] In an embodiment, the first insulating layer INS1 may be provided or disposed on each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2, and may cover or overlap the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2. The first insulating layer INS1 may not cover or overlap the third electrode EL3 and the fourth electrode EL4. Therefore, the third electrode EL3 and the fourth electrode EL4 may be exposed to the outside.

[0267] The upper surface of the first electrode EL1 may be completely covered or overlapped by the first insulating layer INS1 to be electrically insulated from the adjacent electrodes. The upper surface of the first intermediate electrode CE1 may be completely covered or overlapped by the first insulating layer INS1 to be electrically insulated from the adjacent electrodes. The upper surface of the second intermediate electrode CE2 may be completely covered or overlapped by the first insulating layer INS1 to be electrically insulated from the adjacent electrodes. The upper surface of the second electrode EL2 may be completely covered or overlapped by the first insulating layer INS1 to be electrically insulated from the adjacent electrodes.

[0268] A second insulating layer INS2 may be provided and / or formed and / or disposed on the light emitting element LD. The second insulating layer INS2 may be provided and / or formed and / or disposed on each of the light emitting elements LD to cover or overlap a portion of the upper surface of each of the light emitting elements LD and expose both end portions EP1 and EP2 of each of the light emitting elements LD to the outside. The second insulating layer INS2 may be formed as an independent pattern in the emission area EMA of each pixel PXL, but the present disclosure is not limited thereto.

[0269] The second insulating layer INS2 may be a single layer or a multilayer, and may include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may allow each of the light emitting elements LD aligned in the emission area EMA of each pixel PXL to be further fixed. In an embodiment, the second insulating layer INS2 may include an inorganic insulating layer that is beneficial for protecting the active layer 12 of each of the light emitting elements LD from external oxygen, moisture, and other damages within the spirit and scope of the present disclosure. However, the present disclosure is not limited thereto. Depending on the design conditions of the display device to which the light emitting element LD can be applied, the second insulating layer INS2 may include an organic insulating layer having an organic material.

[0270] In an embodiment, after the light emitting element LD can be completely aligned in the emission area EMA of each pixel PXL, a second insulating layer INS2 can be formed or disposed over the light emitting element LD, thereby preventing the light emitting element LD from being separated from the position where the light emitting element LD can be aligned. Fig.14 As shown in , before the second insulating layer INS2 can be formed, when there is a gap (or space) between the first insulating layer INS1 and the light emitting element LD, the gap can be filled with the second insulating layer INS2 in the process of forming the second insulating layer INS2. Therefore, the light emitting element LD may include an organic insulating layer that facilitates filling the gap between the first insulating layer INS1 and the light emitting element LD.

[0271] In an embodiment, a second insulating layer INS2 may be formed or disposed on each of the light emitting elements LD so that the active layer 12 of the light emitting element LD may be prevented from contacting an external conductive material. The second insulating layer INS2 may cover or overlap only a portion of the surface of each of the light emitting elements LD, and may expose both end portions EP1 and EP2 of each of the light emitting elements LD to the outside.

[0272] The contact electrode CNE may be disposed on the first insulating layer INS1 .

[0273] In an implementation, the contact electrode CNE may be a component electrically connected to each of the third electrode EL3 and the fourth electrode EL4 to transfer a corresponding signal (or voltage) to both end portions EP1 and EP2 of each of the light emitting elements LD.

[0274] The contact electrode CNE may be made of various transparent conductive materials. In an example, the contact electrode CNE may include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and may be substantially transparent or translucent to satisfy a predetermined transmittance. However, the material of the contact electrode CNE is not limited to the above-mentioned embodiments. In an embodiment, the contact electrode CNE may be made of various opaque conductive materials.

[0275] The contact electrode CNE may include a first contact electrode CNE1 disposed on the first electrode EL1 , a second contact electrode CNE2 disposed on the first intermediate electrode CE1 , a third contact electrode CNE3 disposed on the second intermediate electrode CE2 , and a fourth contact electrode CNE4 disposed on the second electrode EL2 .

[0276] The first contact electrode CNE1 may be directly disposed on the third electrode EL3 and may be disposed on one of the two ends EP1 and EP2 of each of the first light emitting elements LD1. The first contact electrode CNE1 may electrically connect the third electrode EL3 and one end of each of the first light emitting elements LD1. In a plan view, the first contact electrode CNE1 may overlap one end of each of the first light emitting elements LD1 and the third electrode EL3. The first contact electrode CNE1 may overlap the first electrode EL1.

[0277] Since the first contact electrode CNE1 may be directly electrically connected to the third electrode EL3, a signal of the driving transistor Tdr that may be applied to the third electrode EL3 through the sub-electrode SUE may be transferred to the first contact electrode CNE1. The signal transferred to the first contact electrode CNE1 may be applied to one end of each of the first light emitting elements LD1.

[0278] The second contact electrode CNE2 may be disposed on the first insulating layer INS1 over the first intermediate electrode CE1 and may be electrically connected to the other of the two ends EP1 and EP2 of each of the first light emitting elements LD1. The second contact electrode CNE2 may be electrically connected to one of the two ends EP1 and EP2 of each of the second light emitting elements LD2. In a plan view, the second contact electrode CNE2 may overlap with the other end of each of the first light emitting elements LD1 and one end of each of the second light emitting elements LD2. The second contact electrode CNE2 may be electrically and / or physically separated from the first intermediate electrode CE1 located or disposed thereunder by the first insulating layer INS1. In an embodiment, the second contact electrode CNE2 and the first intermediate electrode CE1 may not be electrically connected to each other.

[0279] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed to be spaced apart from each other. In an example, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed to be spaced apart from each other by a certain or predetermined distance on the second insulating layer INS2. However, the present disclosure is not limited thereto. In an embodiment, as shown in FIG. Fig. 9B As shown in , the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the upper surface of each first light emitting element LD1 to be spaced apart from each other by a certain or predetermined distance. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on an insulating film surrounding the periphery of the first light emitting element LD1 to be spaced apart from each other by a certain or predetermined distance.

[0280] In an embodiment of the present disclosure, one of the two ends EP1 and EP2 of each first light emitting element LD1 may be directly electrically connected to the first contact electrode CNE1, and the other end of the first light emitting element LD1 may be directly electrically connected to the second contact electrode CNE2. The first contact electrode CNE1 and the second contact electrode CNE2 may be provided or disposed in the same layer. However, the present disclosure is not limited thereto. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided or disposed in different layers. When the first contact electrode CNE1 and the second contact electrode CNE2 may be provided or disposed in different layers, a separate insulating layer may be provided or disposed between the first contact electrode CNE1 and the second contact electrode CNE2.

[0281] The third contact electrode CNE3 may be disposed on the first insulating layer INS1 above the second intermediate electrode CE2 and may be electrically connected to the other of the two ends EP1 and EP2 of each of the second light emitting elements LD2. The third contact electrode CNE3 may be electrically connected to one of the two ends EP1 and EP2 of each of the third light emitting elements LD3. In a plan view, the third contact electrode CNE3 may overlap with the other end of each of the second light emitting elements LD2 and one end of each of the third light emitting elements LD3. The third contact electrode CNE3 may be electrically and / or physically separated from the second intermediate electrode CE2 located thereunder or disposed thereunder by the first insulating layer INS1. In an embodiment, the third contact electrode CNE3 and the second intermediate electrode CE2 may not be electrically connected to each other.

[0282] The second contact electrode CNE2 and the third contact electrode CNE3 may be disposed to be spaced apart from each other. In an example, the second contact electrode CNE2 and the third contact electrode CNE3 may be disposed on the second insulating layer INS2 to be spaced apart from each other by a certain or predetermined distance. Although not directly shown in the drawings, the second contact electrode CNE2 and the third contact electrode CNE3 may be disposed on the upper surface of each second light emitting element LD2 to be spaced apart from each other by a certain or predetermined distance. In an embodiment, one of the two ends EP1 and EP2 of each second light emitting element LD2 may be directly electrically connected to the second contact electrode CNE2, and the other end of the second light emitting element LD2 may be directly electrically connected to the third contact electrode CNE3.

[0283] The second contact electrode CNE2 and the third contact electrode CNE3 may be provided or disposed in the same layer. However, the present disclosure is not limited thereto. In an embodiment, the second contact electrode CNE2 and the third contact electrode CNE3 may be provided or disposed in different layers. When the second contact electrode CNE2 and the third contact electrode CNE3 are provided or disposed in different layers, a separate insulating layer may be provided or disposed between the second contact electrode CNE2 and the third contact electrode CNE3.

[0284] The fourth contact electrode CNE4 may be disposed on the fourth electrode EL4 and may be disposed on the other of the two ends EP1 and EP2 of each of the third light emitting elements LD3. The fourth contact electrode CNE4 may electrically connect the fourth electrode EL4 and the other end of each of the third light emitting elements LD3. In a plan view, the fourth contact electrode CNE4 may overlap the other end of each of the third light emitting elements LD3 and the fourth electrode EL4. The fourth contact electrode CNE4 may overlap the second electrode EL2.

[0285] When the fourth contact electrode CNE4 is directly electrically connected to the fourth electrode EL4, the second driving power VSS applied to the fourth electrode EL4 through the fourth conductive line SL4 may be transferred to the fourth contact electrode CNE4. The second driving power VSS transferred to the fourth contact electrode CNE4 may be applied to the other end of each of the third light emitting elements LD3.

[0286] In an implementation, one of both ends EP1 and EP2 of each third light emitting element LD3 may be directly electrically connected to the third contact electrode CNE3 , and the other end of the third light emitting element LD3 may be directly electrically connected to the fourth contact electrode CNE4 .

[0287] The third contact electrode CNE3 and the fourth contact electrode CNE4 may be disposed to be spaced apart from each other. In an example, the third contact electrode CNE3 and the fourth contact electrode CNE4 may be disposed on the second insulating layer INS2 to be spaced apart from each other by a certain or predetermined distance. Although not directly shown in the drawings, the third contact electrode CNE3 and the fourth contact electrode CNE4 may be disposed on the upper surface of each third light emitting element LD3 to be spaced apart from each other by a certain or predetermined distance.

[0288] The third contact electrode CNE3 and the fourth contact electrode CNE4 may be provided or disposed in the same layer, but the present disclosure is not limited thereto. In an embodiment, the third contact electrode CNE3 and the fourth contact electrode CNE4 may be provided or disposed in different layers. Fig.15 As shown in , the third contact electrode CNE3 may be provided or disposed on the second insulating layer INS2 and may be covered or overlapped by the auxiliary insulating layer AUINS. The fourth contact electrode CNE4 may be provided or disposed on the auxiliary insulating layer AUINS and may be covered or overlapped by the third insulating layer INS3. The auxiliary insulating layer AUINS may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0289] In an implementation, the first contact electrode CNE1 may be an anode electrode of the light emitting unit EMU of each pixel PXL, and the fourth contact electrode CNE4 may be a cathode electrode of the light emitting unit EMU of each pixel PXL.

[0290] The third insulating layer INS3 may be provided and / or formed and / or disposed on the first to fourth contact electrodes CNE1 to CNE4. The third insulating layer INS3 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In an example, the third insulating layer INS3 may have a structure in which at least one inorganic insulating layer and at least one organic insulating layer may be alternately stacked. The third insulating layer INS3 may completely cover or overlap the display element layer DPL to block moisture, humidity, etc. from the outside from being introduced into the display element layer DPL including the light emitting element LD.

[0291] According to the above embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 spaced apart from each other and the first light emitting element LD1 electrically connected in parallel therebetween may constitute one series stage (e.g., a first series stage), the second contact electrode CNE2 and the third contact electrode CNE3 spaced apart from each other and the second light emitting element LD2 electrically connected in parallel therebetween may constitute another series stage (e.g., a second series stage), and the third contact electrode CNE3 and the fourth contact electrode CNE4 spaced apart from each other and the third light emitting element LD3 electrically connected in parallel therebetween may constitute a series stage (e.g., a third series stage).

[0292] The light emitting elements LD included in each of the two consecutive series stages may be electrically connected to each other by sharing one contact electrode CNE. The first light emitting element LD1 included in the first series stage and the second light emitting element LD2 included in the second series stage may be electrically connected to each other by sharing the second contact electrode CNE2. The second light emitting element LD2 included in the second series stage and the third light emitting element LD3 included in the third series stage may be electrically connected to each other by sharing the third contact electrode CNE3. In this way, the light emitting elements LD aligned in the emission area EMA of each pixel PXL may be electrically connected in a series / parallel hybrid structure to constitute the light emitting unit EMU of each pixel PXL.

[0293] When the driving current is supplied from the first power line (see FIG. 1 ) through the driving transistor Tdr included in the pixel circuit layer PCL in each pixel PXL, FIG. 6A to FIG. 7B In the case where the sub-electrode SUE and the first contact hole CH1 flow to the fourth conductive line SL4, the driving current can be introduced into the light emitting unit EMU of each pixel PXL through the sub-electrode SUE and the first contact hole CH1. In the example, the driving current flows into the second contact electrode CNE2 via the third electrode EL3 and the first contact electrode CNE1 through the sub-electrode SUE and the first contact hole CH1. Therefore, each of the first light emitting elements LD1 disposed between the first contact electrode CNE1 and the second contact electrode CNE2 can emit light having a brightness corresponding to the sub-current flowing thereto.

[0294] The driving current flowing to the second contact electrode CNE2 flows to the third contact electrode CNE3 via the second light emitting elements LD2. Therefore, each of the second light emitting elements LD2 can emit light having a brightness corresponding to the divided current flowing thereto.

[0295] The driving current flowing to the third contact electrode CNE3 flows to the fourth contact electrode CNE4 via the third light emitting elements LD3. Therefore, each of the third light emitting elements LD3 can emit light having a brightness corresponding to the divided current flowing thereto.

[0296] In the above manner, the driving current of each pixel PXL may flow by sequentially passing through the first light emitting element LD1 disposed between the first contact electrode CNE1 and the second contact electrode CNE2, the second light emitting element LD2 disposed between the second contact electrode CNE2 and the third contact electrode CNE3, and the third light emitting element LD3 disposed between the third contact electrode CNE3 and the fourth contact electrode CNE4. Therefore, each pixel PXL may emit light having brightness corresponding to the data signal provided during each frame period.

[0297] According to the above-described embodiment, an alignment signal (or alignment voltage) that can align the light emitting element LD can be transmitted to each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 through the first conductive line SL1 to the fourth conductive line SL4, so that the light emitting element LD can be aligned in the emission area EMA of each pixel PXL. The first electrode EL1 and the second electrode EL2 and the first intermediate electrode CE1 and the second intermediate electrode CE2 can be arranged in the pixel area PXA of each pixel PXL, or only in the pixel area PXA of each pixel PXL, to independently (or individually) drive each pixel PXL with the adjacent pixel PXL. Therefore, after the light emitting element LD can be aligned in the emission area EMA of each pixel PXL, for example, the process of removing some of the alignment electrodes can be omitted to independently (or individually) drive each of the pixels PXL. Therefore, the manufacturing process of the display device according to the above-described embodiment can be simplified.

[0298] According to the above-mentioned embodiment, each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2 can be set into a double-layer structure by being electrically connected to a conductive line having a relatively thick thickness, so that defects caused by signal delay can be minimized by reducing the wiring resistance of each of the first electrode EL1, the first intermediate electrode CE1, the second intermediate electrode CE2, and the second electrode EL2.

[0299] As an example, according to the above-described embodiment, each of the first electrode EL1 , the first and second intermediate electrodes CE1 and CE2 , and the second electrode EL2 may be covered or overlapped by the first insulating layer INS1 without being affected by static electricity introduced from the outside.

[0300] According to the above embodiment, the light emitting unit EMU can be provided or arranged in a series / parallel hybrid structure so that each pixel PXL can be stably driven. Therefore, the driving current flowing in the display panel of the display device can be reduced, thereby improving the power consumption efficiency of the display device.

[0301] FIG. 16A to FIG. 16F It is shown in sequence that the manufacturing Figure 8 A schematic plan view of the method for one pixel is shown in FIG. FIG. 17A to FIG. 17I It is shown in sequence that the manufacturing Fig.9A A schematic cross-sectional view of the method for one pixel is shown in FIG.

[0302] In the following, we will combine FIG. 16A to FIG. 16F as well as FIG. 17A to FIG. 17I The method is described in sequence in Figure 8 and Fig.9A A pixel according to an embodiment of the present disclosure is shown in FIG.

[0303] refer to Figures 1A to 5 , Figures 8 to 15 , Fig.16A and Fig.17A , some components of the pixel circuit layer PCL included in each of the pixels PXL may be formed or disposed on the substrate SUB. The pixel area PXA in which each pixel PXL may be provided (or formed or disposed) may include an emission area EMA in which light may be emitted and a peripheral area surrounding the periphery of the emission area EMA.

[0304] The components of the pixel circuit layer PCL may include a driving transistor Tdr, a switching transistor Tsw, a data line Dj, an initialization power line IPL, a connection electrode STE, and at least one insulating layer. The at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, and a first interlayer insulating layer ILD1 that may be sequentially formed or disposed on a substrate SUB.

[0305] refer to Figures 1A to 5 , Figures 8 to 15 , Fig. 16B , Fig.17A and Fig. 17B , a second interlayer insulating layer ILD2 including a first contact hole CH1 exposing a portion of the driving transistor Tdr may be formed or disposed on the first interlayer insulating layer ILD1.

[0306] The sub-electrode SUE and the first to fourth conductive lines SL1 to SL4 may be formed or disposed on the second interlayer insulating layer ILD2 .

[0307] The sub-electrode SUE may be provided or disposed in each of the pixels PXL. The sub-electrode SUE may be electrically connected to the driving transistor Tdr through the first contact hole CH1.

[0308] The first to fourth conductive lines SL1 to SL4 may be commonly disposed in pixels PXL located or disposed on the same pixel column in the display area DA. For example, the pixels PXL located or disposed on the same pixel column may be commonly connected to the first to fourth conductive lines SL1 to SL4.

[0309] refer to Figures 1A to 5 , Figures 8 to 15 as well as FIG. 17A to FIG. 17C After an insulating material layer may be formed or disposed on the sub-electrode SUE and the first to fourth conductive lines SL1 to SL4, a passivation layer PSV may be formed or disposed, and the passivation layer PSV may include a seventh contact hole CH7 exposing a portion of the sub-electrode SUE, a second contact hole CH2 exposing a portion of the first conductive line SL1, a third contact hole CH3 exposing a portion of the second conductive line SL2, and a fourth contact hole CH4 exposing a portion of the third conductive line SL3 (see Fig.10 ), a fifth contact hole CH4 exposing a portion of the fourth conductive line SL4, and a sixth contact hole CH6 exposing another portion of the fourth conductive line SL4.

[0310] refer to Figures 1A to 5 , Figures 8 to 15 , Fig. 16C as well as 17A to 17D , a first bank pattern BNK1 may be formed or disposed on the passivation layer PSV. The first bank pattern BNK1 may be spaced apart from an adjacent first bank pattern BNK1 by a certain or predetermined distance. In a plan view, the first bank pattern BNK1 may have a substantially rod shape extending in one direction (e.g., the second direction DR2), but the present disclosure is not limited thereto. The first bank pattern BNK1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material.

[0311] refer to Figures 1A to 5 , Figures 8 to 15 , Fig.16D as well as FIG. 17A to FIG. 17E, the first to fourth electrodes EL1 to EL4 and the first and second intermediate electrodes CE1 and CE2 may be formed or disposed on the passivation layer PSV including the first dam pattern BNK1, and the first to fourth electrodes EL1 to EL4 and the first and second intermediate electrodes CE1 and CE2 may include a conductive substance (or material) having high reflectivity.

[0312] Each of the first electrode EL1, the first and second intermediate electrodes CE1 and CE2, and the second electrode EL2 may be formed or disposed over the corresponding first bank pattern BNK1 in the emission area EMA of each pixel PXL and may be spaced apart from each other.

[0313] In an embodiment, the first electrode EL1, the first intermediate electrode CE1 and the second intermediate electrode CE2, and the second electrode EL2 may be provided or disposed in each of the pixels PXL. In an example, the first electrode EL1 disposed in one pixel PXL may be separated from the first electrode EL1 provided or disposed in each of the adjacent pixels PXL (which are disposed on the same pixel column as the one pixel PXL) without being electrically connected to the first electrode EL1. The first intermediate electrode CE1 provided or disposed in one pixel PXL may be separated from the first intermediate electrode CE1 provided or disposed in each of the adjacent pixels PXL (which are disposed on the same pixel column as the one pixel PXL) without being electrically connected to the first intermediate electrode CE1. The second intermediate electrode CE2 provided or disposed in one pixel PXL may be separated from the second intermediate electrode CE2 provided or disposed in each of the adjacent pixels PXL (which are disposed on the same pixel column as the one pixel PXL) without being electrically connected to the second intermediate electrode CE2. The second electrode EL2 provided or disposed in one pixel PXL may be separated from the second electrode EL2 provided or disposed in each of adjacent pixels PXL disposed on the same pixel column as the one pixel PXL without being electrically connected to the second electrode EL2 .

[0314] The first electrode EL1 may be electrically connected to the first conductive line SL1 through the second contact hole CH2, and may function together with the first conductive line SL1 as a first alignment electrode (or first alignment line) that may align the light emitting element LD. The first alignment electrode may be provided in a double-layer structure including the first conductive line SL1 and the first electrode EL1 electrically connected to the first conductive line SL1.

[0315] The first intermediate electrode CE1 may be electrically connected to the second conductive line SL2 through the third contact hole CH3, and may function together with the second conductive line SL2 as a second alignment electrode (or second alignment line) that may align the light emitting element LD. The second alignment electrode may be provided in a double-layer structure including the second conductive line SL2 and the first intermediate electrode CE1 electrically connected to the second conductive line SL2.

[0316] The second intermediate electrode CE2 may be electrically connected to the third conductive line SL3 through the fourth contact hole CH4, and may be used together with the third conductive line SL3 as a third alignment electrode (or third alignment line) that may align the light emitting element LD. The third alignment electrode may be provided in a double-layer structure including the third conductive line SL3 and the second intermediate electrode CE2 electrically connected to the third conductive line SL3.

[0317] The second electrode EL2 may be electrically connected to the fourth conductive line SL4 through the fifth contact hole CH5, and may be used together with the fourth conductive line SL4 as a fourth alignment electrode (or fourth alignment line) that may align the light emitting element LD. The fourth alignment electrode may be provided in a double-layer structure including the fourth conductive line SL4 and the second electrode EL2 electrically connected to the fourth conductive line SL4.

[0318] The third electrode EL3 may be electrically connected to the sub-electrode SUE through the seventh contact hole CH7 , and may be electrically connected to the driving transistor Tdr through the sub-electrode SUE.

[0319] The fourth electrode EL4 may be electrically connected to the fourth conductive line SL4 through the sixth contact hole CH6 .

[0320] refer to Figures 1A to 5 , Figures 8 to 15 as well as FIG. 17A to FIG. 17F , a first insulating layer INS1 may be formed on the first electrode EL1, the first and second intermediate electrodes CE1 and CE2, and the second electrode EL2. The first insulating layer INS1 may cover or overlap the first electrode EL1, the first and second intermediate electrodes CE1 and CE2, and the second electrode EL2. The first insulating layer INS1 may not cover or overlap the third electrode EL3 and the fourth electrode EL4. Therefore, the third electrode EL3 and the fourth electrode EL4 may be exposed to the outside.

[0321] Subsequently, a second bank pattern (not shown) may be formed in the peripheral region of each of the pixels PXL.

[0322] refer to Figures 1A to 5 , Figures 8 to 15 , Fig.16E as well as FIG. 17A to FIG. 17G, by applying a corresponding alignment signal (or alignment voltage) to each of the first to fourth conductive lines SL1 to SL4, an electric field may be formed between an electrode electrically connected to the corresponding conductive line and an electrode adjacent thereto. The same first alignment signal (or first alignment voltage) may be applied to the first conductive line SL1 and the third conductive line SL3, and the same second alignment signal (or second alignment voltage) may be applied to the second conductive line SL2 and the fourth conductive line SL4. The first alignment signal (or first alignment voltage) may be different from the second alignment signal (or second alignment voltage).

[0323] As described above, a mixed solution including a light-emitting element LD can be injected into the emission area EMA of each pixel PXL by an inkjet printing process, where an electric field can be formed between two adjacent electrodes. In the example, an inkjet nozzle can be provided above the first insulating layer INS1, and a solvent in which the light-emitting element LD can be mixed can be injected into the emission area EMA of each pixel PXL by the inkjet nozzle. The solvent may be at least one of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent may be provided in the form of ink or paste. The method of injecting the light-emitting element LD into the emission area EMA of each pixel PXL is not limited to the above-mentioned embodiments, and may be changed differently within the spirit and scope of the present disclosure.

[0324] After the light emitting element LD may be injected into the emission area EMA of each pixel PXL, the solvent may be removed.

[0325] When the light emitting element LD is injected into the emission area EMA of each pixel PXL, due to the electric field formed between the first electrode EL1 and the first intermediate electrode CE1, between the first intermediate electrode CE1 and the second intermediate electrode CE2, and between the second intermediate electrode CE2 and the second electrode EL2, self-alignment of the light emitting element LD may be induced. Therefore, the first light emitting element LD1 may be aligned between the first electrode EL1 and the first intermediate electrode CE1, the second light emitting element LD2 may be aligned between the first intermediate electrode CE1 and the second intermediate electrode CE2, and the third light emitting element LD3 may be aligned between the second intermediate electrode CE2 and the second electrode EL2. The first to third light emitting elements LD1 to LD3 may be aligned on the first insulating layer INS1 in the emission area EMA of each pixel PXL.

[0326] The second insulating layer INS2 may be continuously formed on each of the first to third light emitting elements LD1 to LD3. The second insulating layer INS2 may expose both end portions EP1 and EP2 of each of the light emitting elements LD to the outside by covering or overlapping at least a portion of the upper surface of each of the first to third light emitting elements LD1 to LD3.

[0327] refer to Figures 1A to 5 , Figures 8 to 15 , Fig.16F as well as 17A to 17H , first to fourth contact electrodes CNE1 to CNE4 may be formed or disposed on the first to fourth electrodes EL1 to EL4 and the first and second intermediate electrodes CE1 and CE2.

[0328] The first contact electrode CNE1 may overlap one end of each of the third electrode EL3, the first electrode EL1, and the first light emitting element LD1. The first contact electrode CNE1 may be directly formed or disposed on the third electrode EL3 to be electrically connected to the third electrode EL3 and to one end of each of the first light emitting elements LD1. The first contact electrode CNE1 may electrically connect the third electrode EL3 and one end of each of the first light emitting elements LD1.

[0329] The second contact electrode CNE2 may overlap the other end of each of the first light emitting elements LD1, the first intermediate electrode CE1, and one end of each of the second light emitting elements LD2. The second contact electrode CNE2 may electrically connect the other end of each of the first light emitting elements LD1 and one end of each of the second light emitting elements LD2. The second contact electrode CNE2 may not be electrically connected to the first intermediate electrode CE1 through the first insulating layer INS1. For example, the first intermediate electrode CE1 and the second contact electrode CNE2 may be electrically separated (or insulated) from each other.

[0330] The third contact electrode CNE3 may overlap with the other end of each of the second light emitting elements LD2, the second intermediate electrode CE2, and one end of each of the third light emitting elements LD3. The third contact electrode CNE3 may electrically connect the other end of each of the second light emitting elements LD2 and one end of each of the third light emitting elements LD3. The third contact electrode CNE3 may not be electrically connected to the second intermediate electrode CE2 through the first insulating layer INS1. For example, the second intermediate electrode CE2 and the third contact electrode CNE3 may be separated (or insulated) from each other.

[0331] The fourth contact electrode CNE4 may overlap the other end of each of the third light emitting elements LD3, the second electrode EL2, and the fourth electrode EL4. The fourth contact electrode CNE4 may be directly formed or disposed on the fourth electrode EL4 to be electrically connected to the fourth electrode EL4 and to the other end of each of the third light emitting elements LD3. The fourth contact electrode CNE4 may electrically connect the fourth electrode EL4 and the other end of each of the third light emitting elements LD3.

[0332] refer to Figures 1A to 5 , Figures 8 to 15 as well as FIG. 17A to FIG. 17I , a third insulating layer INS3 covering or overlapping the first to fourth contact electrodes CNE1 to CNE4 may be formed or disposed. The third insulating layer INS3 may have a structure in which at least one inorganic layer and at least one organic layer may be alternately stacked.

[0333] According to the present disclosure, a display device can be provided, in which a light-emitting element can be aligned in each pixel by applying a conductive line provided or set in a pixel circuit layer, so that a separation process of the line that can align the light-emitting element can be omitted, thereby simplifying the manufacturing process.

[0334] A method of manufacturing a display device may be provided.

[0335] Embodiments have been disclosed herein, and although specific terms may be employed, those terms used herein are to be interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, unless otherwise specifically indicated, features, characteristics, and / or elements described in conjunction with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with another or other embodiments. Therefore, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. Display equipment, including: Substrate, comprising: A display area including a plurality of pixel areas; and a non-display area adjacent to the display area; and A pixel is provided in each of the plurality of pixel regions, Wherein, the pixels include: The sub-electrode, the first conductive line and the second conductive line are arranged on the substrate, wherein the sub-electrode, the first conductive line and the second conductive line are spaced apart from each other; A first insulating layer is disposed on the sub-electrode and the first conductive line and the second conductive line; A first electrode, a second electrode, a third electrode and a fourth electrode are disposed on the first insulating layer, and the first electrode to the fourth electrode are spaced apart from each other; a second insulating layer, disposed on the first electrode and the second electrode to completely overlap the first electrode and the second electrode, the second insulating layer exposing the third electrode and the fourth electrode; a plurality of light emitting elements, arranged on the second insulating layer between the first electrode and the second electrode; a first contact electrode disposed on the first electrode, wherein the second insulating layer is disposed between the first contact electrode and the first electrode; and The second contact electrode is arranged on the second electrode, wherein the second insulating layer is arranged between the second contact electrode and the second electrode.

2. The display device according to claim 1, wherein: The pixels include: A third conductive line and a fourth conductive line are disposed on the substrate, wherein the third conductive line and the fourth conductive line are disposed between the first conductive line and the second conductive line; and A first intermediate electrode and a second intermediate electrode are disposed on the first insulating layer, and the first intermediate electrode and the second intermediate electrode are disposed between the first electrode and the second electrode.

3. The display device according to claim 2, wherein: The second insulating layer is disposed on the first intermediate electrode and the second intermediate electrode to completely overlap the first intermediate electrode and the second intermediate electrode.

4. The display device according to claim 3, wherein: The first electrode extends on the first insulating layer in the same direction as the first conductive line, The second electrode extends on the first insulating layer in the same direction as the second conductive line, The first intermediate electrode extends on the first insulating layer in the same direction as the third conductive line, and The second intermediate electrode extends on the first insulating layer in the same direction as the fourth conductive line.

5. The display device according to claim 4, wherein: In the plan view, The first electrode overlaps with the first conductive line, The second electrode overlaps with the second conductive line, The first intermediate electrode overlaps the third conductive line, and The second intermediate electrode overlaps the fourth conductive line.

6. The display device according to claim 5, wherein: The first insulating layer includes a plurality of contact holes exposing a portion of the sub-electrode, a portion of each of the first to fourth conductive lines, and another portion of the second conductive line.

7. The display device according to claim 6, wherein: The first electrode is electrically connected to the exposed portion of the first conductive line, The second electrode and the fourth electrode are electrically connected to the exposed portions of the second conductive line, respectively. The first intermediate electrode is electrically connected to the exposed portion of the third conductive line, The second intermediate electrode is electrically connected to the exposed portion of the fourth conductive line, and The third electrode is electrically connected to the exposed portion of the sub-electrode.

8. The display device according to claim 7, wherein: The first conductive line and the first electrode are connected to each other to form a double-layer structure including the first insulating layer disposed between the first conductive line and the first electrode, The second conductive line and the second electrode are connected to each other to form a double-layer structure including the first insulating layer disposed between the second conductive line and the second electrode, The third conductive line and the first intermediate electrode are connected to each other to form a double-layer structure including the first insulating layer disposed between the third conductive line and the first intermediate electrode, and The fourth conductive line and the second intermediate electrode are connected to each other to form a double-layer structure including the first insulating layer disposed between the fourth conductive line and the second intermediate electrode.

9. The display device according to claim 7, wherein: The second conductive line, the second electrode, and the fourth electrode are electrically connected to each other.

10. The display device according to claim 7, wherein: The first contact electrode is directly disposed on the third electrode and on one end portion of each of the plurality of light emitting elements, and The second contact electrode is provided directly on the fourth electrode and on the other end portion of each of the plurality of light emitting elements.

11. The display device according to claim 10, wherein: The first contact electrode electrically connects the third electrode and the one end portion of each of the plurality of light emitting elements, and The second contact electrode electrically connects the fourth electrode and the other end portion of each of the plurality of light emitting elements.

12. The display device according to claim 8, wherein: The pixels include: a third contact electrode spaced apart from the first contact electrode and the second contact electrode and disposed on the first intermediate electrode, the second insulating layer being disposed between the third contact electrode and the first intermediate electrode; and A fourth contact electrode is spaced apart from the first to third contact electrodes and is disposed on the second intermediate electrode, and the second insulating layer is disposed between the fourth contact electrode and the second intermediate electrode.

13. The display device according to claim 12, wherein: The third contact electrode and the first intermediate electrode are electrically isolated from each other, and The fourth contact electrode and the second intermediate electrode are electrically isolated from each other.

14. The display device according to claim 13, wherein: The pixels include: a transistor disposed between the substrate and the first to fourth conductive lines; and A signal line electrically connected to the transistor, Wherein, the transistor is electrically connected to the sub-electrode.

15. The display device according to claim 11, wherein: The pixel includes a third insulating layer disposed on an upper surface of each of the plurality of light emitting elements, and The first contact electrode and the second contact electrode are disposed on the third insulating layer.

16. The display device according to claim 15, wherein: The first contact electrode and the second contact electrode are provided in the same layer.

17. The display device according to claim 15, wherein: The first contact electrode and the second contact electrode are disposed in different layers.

18. The display device according to claim 1, wherein: Each of the plurality of light emitting elements comprises: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and The active layer is disposed between the first semiconductor layer and the second semiconductor layer.

19. A method for manufacturing a display device, the method comprising: Forming a pixel in each pixel region, wherein forming the pixel comprises: forming a sub-electrode and a first conductive line, a second conductive line, a third conductive line and a fourth conductive line on a substrate, wherein the sub-electrode and the first to fourth conductive lines are spaced apart from each other; forming a first insulating layer on the sub-electrode and the first to fourth conductive lines; forming a first electrode, a second electrode, a third electrode, and a fourth electrode and a first intermediate electrode and a second intermediate electrode on the first insulating layer, wherein the first electrode to the fourth electrode and the first intermediate electrode and the second intermediate electrode are spaced apart from each other; Forming a second insulating layer on the first electrode, the second electrode, the first intermediate electrode, and the second intermediate electrode, wherein forming the second insulating layer comprises: forming the second insulating layer completely overlapping the first electrode and the second electrode and each of the first intermediate electrode and the second intermediate electrode and not overlapping the third electrode and the fourth electrode; aligning a plurality of light emitting elements on the second insulating layer between the first electrode and the second electrode and between two adjacent electrodes of the first intermediate electrode and the second intermediate electrode; and A first contact electrode to a fourth contact electrode are formed on the second insulating layer, wherein: The first contact electrode is electrically connected to one of the third electrode and the fourth electrode, and The fourth contact electrode is electrically connected to the other of the third electrode and the fourth electrode.

20. The method according to claim 19, wherein: Forming the first insulating layer includes: applying an insulating material to the sub-electrodes and the first to fourth conductive lines; and A plurality of contact holes exposing a portion of the sub-electrode, a portion of each of the first to fourth conductive lines, and another portion of the second conductive line are formed by removing a portion of the insulating material.

21. The method according to claim 20, wherein: Forming the pixel comprises: connecting the first conductive line and the first electrode to form a double-layer structure including the first insulating layer disposed between the first conductive line and the first electrode, connecting the second conductive line and the second electrode to form a double-layer structure including the first insulating layer disposed between the second conductive line and the second electrode, connecting the third conductive line and the first intermediate electrode to form a double-layer structure including the first insulating layer disposed between the third conductive line and the first intermediate electrode, and The fourth conductive line and the second intermediate electrode are connected to form a double-layer structure including the first insulating layer disposed between the fourth conductive line and the second intermediate electrode.

22. The method according to claim 21, wherein: Forming the pixel includes forming a transistor and a signal line electrically connected to the transistor on the substrate before forming the sub-electrode and the first to fourth conductive lines.

Images