Manufacture of piezoelectric devices with pmnpt layers

Abstract

A piezoelectric device includes a substrate, a thermal oxide layer on the substrate, a metal or metal oxide adhesion layer on the thermal oxide layer, a lower electrode on the metal oxide adhesion layer, a seed layer on the lower electrode, a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer on the seed layer, and an upper electrode on the PMNPT piezoelectric layer.

Description

Technical Field

[0001] The present invention relates to the manufacture of piezoelectric devices, and more particularly to piezoelectric devices comprising PMNPT as a piezoelectric layer. Background Technology

[0002] Piezoelectric materials have been used for decades in various technologies such as inkjet printing, medical ultrasound, and gyroscopes. Traditionally, piezoelectric layers are made by fabricating piezoelectric materials in bulk crystalline form and then processing that material to the desired thickness, or by depositing layers using a sol-gel technique. Lead zirconate titanate (PZT), typically Pb[Zr] x Ti 1-x PZT, in the form of O3, is a commonly used piezoelectric material. Sputtering of PZT has been proposed.

[0003] Recently, relaxor-lead titanate (relaxor-PT) materials, such as lead magnesium niobate-lead titanate (PMNPT), are typically (1-x)[Pb(Mg)] 1 / 3 Nb 2 / 3 (1-X)[Pb(Y)O3]-x[PbTiO3]; and lead yttrium niobate-lead titanate (PYN-PT), such as ... 1 / 3 Nb 2 / 3 (1-X)[PbTiO3]; lead zirconate niobate-lead titanate (PZN-PT), such as (1-X)[Pb(Zr)] 1 / 3 Nb 2 / 3 (1-X)[PbTiO3]; and lead indium niobate-lead titanate (PIN-PT), such as (1-X)[Pb(In3]-X ... 1 / 3 Nb 2 / 3 PMNPT [PbTiO3] has been proposed as a piezoelectric material. Compared to the more commonly used PZT material, PMNPT offers improved piezoelectric properties. However, large-area thin-film deposition of PMNPT layers in a commercially viable manner has not yet been achieved. Summary of the Invention

[0004] In one aspect, a piezoelectric device includes: a substrate; a thermal oxide layer on the substrate; a metal or metal oxide adhesion layer on the thermal oxide layer; a lower electrode on the metal oxide adhesion layer; a seed layer on the lower electrode; a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer on the seed layer; and an upper electrode on the PMNPT piezoelectric layer.

[0005] In another aspect, a method of manufacturing a piezoelectric device includes: forming an adhesion layer on a thermal layer of a substrate; depositing a lower electrode on the adhesion layer; forming a seed layer on the lower electrode; depositing a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer on the seed layer by physical vapor deposition; and depositing an upper electrode on the PMNPT piezoelectric layer.

[0006] Each implementation may have one or more of the following advantages, but is not limited to.

[0007] Devices including PMNPT layers can be fabricated using commercially viable processes. The layer stacking with PMNPT layers allows for good adhesion to the underlying semiconductor wafer. PMNPT layers can be deposited via physical vapor deposition, which provides high purity, good yield, and low cost. The layer stacking allows PMNPT material to be fabricated with highly (001) oriented columnar grains, which provides an excellent d33 coefficient. This process also limits the presence of parasitic phases (such as PbOx and pyrochlore) that could impair piezoelectric properties.

[0008] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the specification, the drawings, and the claims. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of the physical vapor deposition processing chamber.

[0010] Figure 2 This is a schematic cross-sectional view of the stacked layers in a piezoelectric device.

[0011] Similar reference symbols in the various figures indicate similar elements. Detailed Implementation

[0012] Fabricating piezoelectric layers from bulk crystals and depositing them using sol-gel techniques are slow processes, unsuitable for semiconductor manufacturing facilities. Bulk crystals require fabrication in conventional machine shops. This is not only expensive but also limits the ability to integrate piezoelectric layers into devices. Sol-gel processes require multiple rounds of deposition and curing, making them very time-consuming. Therefore, it is desirable to deposit piezoelectric materials using physical vapor deposition processes such as sputtering.

[0013] As mentioned above, PMNPT can provide improved piezoelectric properties compared to traditional PZT-based solutions. However, fabricating PMNPT thin films on large-area semiconductor wafers (such as silicon wafers) via physical vapor deposition has been challenging. It can be difficult to achieve a uniform crystal structure with the desired phase and texture in PMNPT films.

[0014] A technique that can solve these problems involves depositing a layer stack on a semiconductor wafer, comprising silicon oxide, metal oxide, a platinum layer, and a thin seed layer. A PMNPT layer is deposited on this layer stack. The layer stack provides good adhesion to the silicon wafer while also promoting proper crystal orientation of the PMNPT.

[0015] Figure 1 A schematic diagram of a chamber 100 is depicted for an integrated processing system (e.g., an ENDURA system) suitable for implementing the physical vapor deposition processes discussed below. The processing system may include multiple chambers, which may be suitable for PVD or CVD processes. For example, the processing system may include a cluster of interconnected processing chambers (e.g., CVD chambers and PVD chambers).

[0016] The chamber 100 includes a chamber wall 101 surrounding a vacuum chamber 102, a gas source 104, a pumping system 106, and a target power supply 108. Within the vacuum chamber 102 are a target 110 and a base 112 for supporting the substrate 10. A shield may be placed within the chamber to surround the reaction area. The base is vertically movable, and a lifting mechanism 116 may be coupled to the base 112 to position the base 112 relative to the target 110. A heater or cooler 136 (e.g., a resistance heater or thermoelectric cooler) may be embedded in the base 112 to maintain the substrate 10 at the desired processing temperature.

[0017] The target 110 is composed of the material to be deposited, such as lead magnesium niobate-lead titanate used in PMNPT. However, the target may have an excess of PbO relative to the required stoichiometry of the layer to be deposited. x This addresses lead loss due to the volatile nature of lead during deposition or post-treatment processes (such as annealing). For example, the target material may have an excess of 1-20 mol% PbO to address the volatile Pb and PbO in the deposited material. x Loss. The target material itself should have a uniform composition. The target material 110 can be platinum (Pt) or titanium (Ti) used for depositing other layers.

[0018] Gas source 104 may introduce an inert gas (e.g., argon (Ar) or xenon (Xe)) or a mixture of an inert gas and a process gas (e.g., oxygen) into vacuum chamber 102. Chamber pressure is controlled by pumping system 106. Target power supply 108 may include a DC source, a radio frequency (RF) source, or a DC pulse source.

[0019] During operation, the substrate 10 is supported within the chamber 102 by the base 112. Gas from the source 104 flows into the chamber 102, and the target power supply 108 applies power to the target 110 at a frequency and voltage to generate plasma in the chamber 102. The target material is sputtered from the target 110 by the plasma and deposited on the substrate 10.

[0020] If the target power supply 108 is a DC or DC pulse source, the target 110 serves as a negatively biased cathode, and the shield is a grounded anode. For example, plasma is generated by an inert gas by applying a DC bias to the sputtering target 210, sufficient to produce a power density of approximately 1 to 350 watts per square inch, such as 100-38,000 W for a 13-inch diameter target, and more typically approximately 100-10,000 W. If the target power supply 108 is an RF source, the shield is typically grounded, and the voltage at the target 110 varies relative to the shield at RF (typically 13.56 MHz). In this case, electrons in the plasma accumulate at the target 110 to generate a self-bias voltage that gives the target 110 a negative bias.

[0021] Chamber 100 may include additional components for improving the sputtering deposition process. For example, power supply 124 may be coupled to base 112 to apply a bias voltage to substrate 10 in order to control the deposition of a film on substrate 10. Power supply 124 is typically an AC source having a frequency, for example, between about 350 kHz and about 450 kHz. When bias voltage is applied by power supply 124, a negative DC bias is generated at substrate 10 and base 112 (due to electron accumulation). The negative bias voltage at substrate 10 attracts ionized sputtered target material. The target material is typically attracted to substrate 10 in a direction substantially perpendicular to substrate 10. Thus, bias power supply 124 improves the stepped coverage of the deposited material compared to substrate 10 without bias voltage.

[0022] The chamber 100 may also have a magnet 126 or a magnetic subassembly located behind the target 110 for generating a magnetic field in the vicinity of the target 110. In some embodiments, the magnet rotates during the deposition process.

[0023] The operation of the chamber can be controlled by a controller 150 (e.g., a dedicated microprocessor (e.g., an ASIC) or a conventional computer system executing a computer program stored on a non-volatile computer-readable medium). The controller 150 may include a central processing unit (CPU) and memory containing associated control software.

[0024] Figure 2 A cross-section of a portion of a substrate 10 for manufacturing an apparatus including a piezoelectric layer 16 of PMNPT formed on a semiconductor wafer 12 is shown. Specifically, the substrate 10 includes a layer stack 14 located between the semiconductor wafer 12 and the piezoelectric layer 16. The layer stack 14 both enhances the adhesion of the piezoelectric material to the semiconductor wafer 12 and promotes proper crystal orientation of the PMNPT material in the piezoelectric layer 16.

[0025] Semiconductor wafers can be silicon wafers or other semiconductors such as germanium (Ge). Silicon wafers can be single-crystal silicon wafers and can have... <001> Crystallographic orientation, although other orientations can also play a role.

[0026] The layer stack 14 sequentially includes a silicon oxide (SiOx) layer 20, an adhesion layer 22, a first conductive layer 24, and a first seed layer 26, wherein the first seed layer 26 provides a seed layer for the PMNPT layer. The adhesion layer 22 may be a metal oxide, such as titanium oxide, and the seed layer may also be a metal oxide, such as titanium oxide or niobium oxide.

[0027] The silicon oxide layer 20 may include SiO2, SiO, or a combination thereof. The silicon oxide layer 20 may be a thermal oxide and may have a thickness of about 50 nm to 1000 nm. The silicon oxide layer 20 may be an amorphous layer.

[0028] The adhesion layer 22 may be a metal oxide layer. The stoichiometry of the metal oxide layer may be MO2, M2O3, or MO (where M represents a metal element), or another suitable stoichiometry of metal and oxygen. Specifically, the adhesion layer 22 may be formed of titanium oxide (e.g., TiO2, Ti2O3, TiO) or another stoichiometry of titanium and oxygen. In some embodiments, the adhesion layer is a pure metal or metal alloy, rather than a metal oxide layer. Examples of metals (metals relative to metal oxides, or pure metals, or compositions of metal alloys) include titanium, chromium, chromium-nickel, and nickel. The adhesion layer 22 may be thinner than the silicon oxide layer 20. For example, the titanium oxide adhesion layer 22 may have a thickness of 25 nm to 40 nm. The adhesion layer 22 may have a crystallographic orientation to promote a desired crystallographic orientation of the conductive layer 24. For example, the TiO2 layer may have… <001> Orientation to promote Pt <111> orientation.

[0029] The first conductive layer 24 is formed of a conductive material such as platinum, gold, iridium, molybdenum, or SrRuO3. The first conductive layer 24 may be thicker than the adhesion layer 22 and thicker than the silicon oxide layer 20. For example, the first conductive layer 24 may have a thickness of 50-300 nm. The first conductive layer 24 may have a crystallographic orientation to promote the desired crystallographic orientation of the seed layer 26. For example, the platinum layer may have… <111> Crystallographic orientation to promote the formation of titanium oxide seed layers <001> orientation.

[0030] The seed layer 26 can be a metal oxide. Specifically, the seed layer 26 can be an oxide of titanium or niobium. For example, the seed layer 26 can be TiO2, Ti2O3, TiO, or another stoichiometric combination of titanium and oxygen. The seed layer 26 should have a uniform stoichiometry across the entire surface of the substrate 10. The seed layer 26 may have a crystallographic orientation to promote the desired crystallographic orientation of the piezoelectric layer 16. For example, a titanium oxide layer may have... <001> Crystallographic orientation to promote PMNPT piezoelectric layers <001> Orientation. The seed layer 26 is thinner than the adhesion layer 22. For example, the first seed layer 26 can be about 1 nm to 5 nm thick, such as 2 nm.

[0031] A piezoelectric layer 16 is formed on the seed layer 26. Examples of materials used for the piezoelectric layer 16 include PZT and relaxor-PT materials. In particular, the material may be (1-x)[Pb(Mg)] (1-y) Nb y The matrix is ​​∫[O3]-x[PbTiO3], where x is about 0.2 to 0.8 and y is about 0.8 to 0.2, for example, about 2 / 3. Due to the presence of the metal oxide seed layer, PMNPT materials can be primarily, for example, essentially entirely... <001> Crystallographic orientation. Piezoelectric layers can have a thickness of 50 nm to 10 micrometers.

[0032] The second conductive layer 30 is formed on the piezoelectric layer 16. The second conductive layer 30 may have the same material composition as the first conductive layer 24 and may have the same thickness as the first conductive layer 24. For example, the second conductive layer 30 may be platinum and may have a thickness of 50 nm to 300 nm.

[0033] A voltage can be applied between the first conductive layer 24 and the second conductive layer 30 to actuate the piezoelectric layer 16. Thus, the first conductive layer 24 provides the lower electrode, the second conductive layer 30 provides the upper electrode, and the piezoelectric layer 16 is sandwiched between the two.

[0034] To fabricate the layer stack 14, heat treatment can be performed on Si in an oxygen-containing atmosphere. <001> Oxides of SiO2 are grown on single-crystal wafers. Thermal oxides can be grown to thicknesses of 50nm-1000nm (e.g., 100nm). Thermal oxides can be formed on both sides of a silicon wafer.

[0035] Subsequently, a metal layer is deposited via PVD, which will provide the metal for the adhesion layer. For example, a titanium layer can be deposited. The metal layer can be deposited, for example, at a temperature between room temperature and 600°C, with a power density applied to the target of 1 to 350 watts per square inch (e.g., about 1.5 watts per square inch). After depositing the metal layer, it can be annealed in a rapid thermal processing chamber or furnace in the presence of oxygen or air to form an adhesion layer in the form of a metal oxide layer (e.g., TiOx). Annealing can be performed at a temperature of 500°C–800°C for, for example, 2 to 30 minutes. The resulting adhesion layer can have a thickness of 5–400 nm.

[0036] Then, the first conductive layer (e.g., highly oriented platinum) is applied by PVD. <111> A film is deposited on an adhesion layer, such as on a titanium oxide layer. For example, a platinum layer can be deposited at a substrate temperature of room temperature to 500°C and at a power density of 0.5 W to 20 W per square inch (e.g., 4 W to 5 W per square inch) applied to the target. A bottom metal layer can be deposited up to a thickness of 50 nm to 300 nm. In addition to contributing to uniform texturing of the metal layer, the adhesion layer also provides improved adhesion between the metal electrode and the silicon oxide.

[0037] Next, a thin metal layer (e.g., titanium) is deposited on the lower electrode (e.g., a platinum layer) using PVD (e.g., DC sputtering) or CVD (e.g., ALD) techniques. Specifically, the titanium layer can be deposited, for example, by DC sputtering. For instance, a titanium seed layer can be deposited on the substrate at a temperature from room temperature to 500°C at a power density of 0.5 W to 4 W per square inch (e.g., 1 W per square inch) applied to the target. The thin metal layer can have a thickness of 1 nm to 5 nm. The thin metal layer can then be oxidized, for example, by heating in an oxidizing atmosphere, to convert the metal layer into a metal oxide, such as converting Ti to TiOx, to provide a seed layer. Alternatively, the oxidized seed layer can also be deposited directly using PVD or CVD techniques, such as TiOx deposition via RF sputtering or ALD.

[0038] The PMNPT layer is then deposited on the seed layer via PVD. For example, the PMNPT layer can be deposited at a substrate temperature of up to 800°C and a power density of 4 to 40 watts per square inch.

[0039] Finally, a second conductive layer (e.g., a platinum film) is deposited on the PMNPT layer by PVD. For example, the second platinum film can be deposited under the same conditions as the first platinum film.

[0040] Therefore, the final device comprises a stack of the following: 1) wafers, such as <001> 1) A crystallographically oriented single-crystal silicon wafer; 2) A thermal oxide (e.g., silicon oxide) layer; 3) An adhesion layer, e.g., titanium oxide; 4) A first conductive layer, e.g., Pt. <111> Crystallographic orientation, which provides the bottom electrode; 5) Seed layer, such as titanium oxide seed layer; 6) <001> 7) A crystallographically oriented PMNPT layer; and 8) a second conductive layer (e.g., a platinum layer) that provides the top electrode.

[0041] Unrestricted by any particular theory, in the adhesion layer (e.g., TiOx) <001> Favorable lattice matching between the bottom electrode (e.g., Pt) and the base electrode allows for the growth of highly oriented bottom metal electrodes, such as Pt. <111> Grains. And highly oriented bottom metal electrodes (e.g., platinum). <111> The membrane allows for the formation of highly oriented PMNPT. <001> The piezoelectric layer of the grains. This stacking can also limit the presence of parasitic phases (such as PbOx and pyrochlore) that impair piezoelectric properties.

[0042] Several implementations have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of this disclosure. For example,

[0043] · Figure 1 The system 100 shown is suitable for processing planar substrates 10, such as semiconductor substrates, for example, silicon wafers, but the techniques discussed below are applicable to non-planar substrates.

[0044] • PVD processes can utilize self-ionized plasma (SIP). In the SIP process, the plasma is initially ignited using an inert gas (such as argon). After plasma ignition, the inert gas flow is terminated, and the deposited plasma is held in place by ions generated by the sputtering target.

[0045] • The upper electrode can be made of a different conductive material than the lower electrode, such as a conductive material other than platinum.

[0046] Therefore, other embodiments are within the scope of the appended claims.

Claims

1. A piezoelectric device, comprising: substrate; A thermal oxide layer located on the substrate; A metal adhesion layer located on the thermal oxide layer, wherein the metal adhesion layer is composed of metallic chromium, metallic nickel, or a metallic alloy of chromium and nickel; The lower electrode is located on the metal adhesion layer; A seed crystal layer located on the lower electrode, wherein the seed crystal layer is titanium oxide or niobium oxide; A lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer located on the seed crystal layer; and The upper electrode is located on the PMNPT piezoelectric layer.

2. The apparatus of claim 1, wherein the substrate comprises a silicon substrate and the thermal oxide is silicon oxide.

3. The device of claim 1, wherein the lower electrode is made of platinum.

4. The apparatus of claim 1, wherein the PMNPT piezoelectric layer is made of (1-x)[Pb(Mg)] (1-y) Nb y It is composed of [O3]-x[PbTiO3], where x is 0.2 to 0.8 and y is 0.8 to 0.

2.

5. The apparatus of claim 1, wherein the PMNPT piezoelectric layer has <001> Crystallographic orientation.

6. The apparatus of claim 1, wherein the upper electrode has the same composition as the lower electrode.

7. A method for manufacturing a piezoelectric device, comprising: An adhesion layer is formed on a thermal oxide layer of a substrate by depositing metallic chromium, metallic nickel, or a combination of at least two of titanium, chromium, and nickel. A lower electrode is deposited on the adhesion layer; A seed crystal layer is formed on the lower electrode, wherein the seed crystal layer is titanium oxide or niobium oxide; A lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer was deposited on the seed crystal layer by physical vapor deposition; and An upper electrode is deposited on the PMNPT piezoelectric layer.

8. A method for manufacturing a piezoelectric device, comprising: An adhesion layer is formed on the thermal oxide layer of the substrate by depositing a first metal layer on the substrate at 20°C-25°C and annealing the first metal layer to convert at least a portion of the first metal layer into a metal oxide adhesion layer. The first metal layer is titanium, chromium, nickel or a combination of the metals thereof. A lower electrode is deposited on the adhesion layer; A seed crystal layer is formed on the lower electrode, wherein the seed crystal layer is titanium oxide or niobium oxide; A lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer was deposited on the seed crystal layer by physical vapor deposition; and An upper electrode is deposited on the PMNPT piezoelectric layer.

9. The method of claim 7 or 8, wherein forming the seed layer comprises depositing a titanium or niobium layer and annealing the substrate to convert at least a portion of the titanium or niobium layer into the titanium oxide or niobium oxide of the seed layer.

10. The method of claim 9, wherein forming the adhesion layer, depositing the lower electrode, and forming the seed layer comprises physical vapor deposition.

11. The method of claim 7 or 8, wherein the PMNPT piezoelectric layer has <001> Crystallographic orientation.

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