An analog-to-digital conversion encoding circuit

Abstract

An analog-to-digital (ADC) encoding technique is disclosed. This technique, after decoding, eliminates the need for traditional analog power amplifiers to drive power loads such as loudspeakers, and offers high quantization accuracy. A reference power supply provides a basic voltage unit and a reference voltage that is an integer multiple of the basic voltage unit. The quantization result of the analog signal comprises two parts: an integer amplitude and a fractional amplitude. The current analog signal voltage value is divided by the smallest voltage unit; the integer part is the integer amplitude, and the fractional part is the fractional amplitude. Then, the sampling frequency, integer amplitude, fractional amplitude, reference voltage, and signal polarity are concatenated into a single encoded value as the encoding result. Because it employs an integer and fractional amplitude quantization method, its quantization accuracy is high.

Description

Technical Field

[0001] This invention belongs to the technical field of analog-to-digital conversion, specifically implementing the function of encoding analog signals into digital signals. Background Technology

[0002] Most current ADCs employ linear quantization encoding, a mature technology. However, if a power load follows the DAC, the DAC output signal needs to be amplified by an analog power amplifier before driving the load. For high-power loads, pulse amplifiers are necessary to address the efficiency issues of traditional analog amplifiers. Therefore, traditional ADCs / DACs always have to make some sacrifices to drive power loads: either maintain analog signal quality without compromising efficiency—wasting power; or improve efficiency at the expense of some sound quality. Summary of the Invention

[0003] This invention proposes a novel ADC encoding and decoding technology that can directly drive a power load after decoding, without the need for analog signal power amplification through a traditional analog amplifier, thereby improving efficiency while ensuring the quality of the original analog signal.

[0004] The hardware circuit consists of Figures 1-4 The system consists of: an ADC controller, a reference voltage, a sample-and-hold circuit, and a quantization circuit. The function of each circuit is explained below. The encoding system is a single-supply system; only the signal encoding process is described below. The power supply changes according to the needs of the encoding circuit and will not be discussed further.

[0005] Figure 1 It's an ADC controller, consisting of the auxiliary circuitry at the top, the ADC encoder in the middle, and the register set at the bottom. Its main function is to coordinate the entire hardware circuitry to complete the digital quantization and encoding of the analog input signal for output. The following will... Figure 1 The circuit shown, combined with Figures 2-4 The entire hardware circuit Figure 1 The functions are explained.

[0006] The sampling switch driver circuit is a switch driver circuit; its input comes from a fixed-frequency signal from the ADC encoder, and its output drives... Figure 3 The sampling switch S1 is used in the sampling and quantization process. During sampling and quantization, S1 is kept open so that C1 can maintain the analog voltage V_SIN when it is open. At other times, S1 is closed so that the voltage of C1 follows the changes of V_SIN. After sampling and quantization is completed, the ADC encoder converts the voltage to the input voltage. The frequency encoding value is written to register REG[15:14].

[0007] Integer switch driver circuit: This is a set of switch driver circuits; its input comes from the ADC encoder, and its output drives... Figure 2Switches S2 to S6 in the middle; Figure 4 During the integer quantization process of differential amplifier AMP2, the ADC encoder controls the closing or opening of switches S2-S6 based on the differential amplification result between the outputs V_ISET and V_SMP. After integer quantization is complete, the quantized value is maintained so that the input (V_SMP - V_ISET) of differential amplifier AMP2 has a stable difference, thereby maintaining the stability of the differential amplifier's output value V_FOUT. After sampling quantization is completed, the ADC encoder will... Integer encoded values ​​are written to REG[13:11].

[0008] D-value buffer and PWM driver: This is a combined circuit structure. The value of the D-value buffer comes from the ADC encoder. The output of the D-value buffer causes the PWM driver to generate a PWM signal with the current duty cycle of the buffer. The PWM driver uses this PWM signal as its output driver. Figure 2 Switch S7 in the circuit is used to operate the PWM circuit according to the set duty cycle, thereby enabling the output V_FSET of the integrator circuit composed of R13 and C2 to obtain different integrated voltage values; after sampling and quantization, the ADC encoder will... The duty cycle encoded value is written to REG[10:4].

[0009] Reference voltage comparator group: is a group of comparator circuits; its input comes from... Figure 2 The reference power supply V_SREF is set to its voltage value; its output is fed into the ADC encoder; the ADC encoder looks up its own reference voltage setting table based on the results of the comparator group, and outputs the encoded result according to the corresponding voltage value; after sampling and quantization are completed, the ADC encoder will... The reference voltage encoding value is written into REG[3:1].

[0010] Polarity register: is a cache register; its input value is determined by... Figure 3 The polarity comparator CMP1's output V_POUT determines the output voltage. Since it's single-supply powered, output voltage values ​​less than or equal to 0 are 0V (logo 0), and vice versa (logo 1). This is an instantaneous value, changing in real-time based on the analog input signal V_SRC. After sampling and quantization, the ADC encoder will... The polarity encoding value is written to REG[0].

[0011] ADC encoder: controls the auxiliary circuit above, and works with... Figure 4 The quantization result feedback signal V_BACK forms a closed-loop control, completing the quantization of the analog input signal V_SRC; after completing one sampling quantization, the values ​​of the register REG[15:0] are read out and from... The output register REG_OUT[15:0] outputs the quantization result.

[0012] The above Figure 1 The control logic has been explained below. Figure 2 The reference voltage distributor will be explained. Figure 2 Three reference voltage outputs were allocated.

[0013] Route 1: Figure 3 V2_VDIV in the equation serves as the bias voltage for the analog input amplifier AMP1 and also as the reference voltage for the polarity comparison of the polarity comparator CMP1. Figure 2 It can be seen that when the resistances R10 to R14 are equal, the reference voltage V_SREF is divided into four equal-gradient voltage values; each voltage gradient value is Vdiv. V_2_VDIV = 2 * Vdiv, where Vdiv = V_SREF / 4.

[0014] Route 2: Figure 4 V_ISET in the equation serves as the input to the negative terminal of the differential amplifier AMP2, and together with the analog sample-and-hold signal V_SMP, forms the differential input signal. During integer quantization, closing different switches in S2 to S6 can yield the following results: V_ISET = 0V, only S6 is closed, and the integer value is 0; V_ISET = 1 * Vdiv = (1 / 4) * V_SREF, only S5 is closed, integer value is 1; V_ISET = 2 * Vdiv = (2 / 4) * V_SREF, only S4 is closed, and the integer value is 2; V_ISET = 3 * Vdiv = (3 / 4) * V_SREF, only S3 is closed, and the integer value is 3; V_ISET = 4 * Vdiv = (4 / 4) * V_SREF, only S2 is closed, and the integer value is 4.

[0015] Third route: Figure 4 V_FSET in the code serves as the positive input of the small-value comparator CMP2, and is compared with the output V_FOUT of the differential amplifier. Similarly, due to the single power supply, voltages less than or equal to 0V are output as 0V, denoted as logic 0, and vice versa, as logic 1. During small-value quantization, since S7 is driven by PWM with a duty cycle (0%–100%), there is... V_FSET = D * V_1_DIV = (0%~100%) * Vdiv = 0V~Vdiv.

[0016] The above Figure 2The reference voltage function has been explained, and will be described below. Figure 3 The sample-and-hold circuit and Figure 4 The quantization circuit in the diagram describes how it completes a sampling and quantization process for the analog input signal V_SRC.

[0017] Figure 3 The sample-and-hold circuit consists of an analog input amplifier AMP1, a sample-and-hold circuit switch S1 and capacitor C1, and a polarity comparator CMP1.

[0018] AMP1 is an inverting amplifier with a bias signal, a gain of 1, and a bias voltage of V2VDIV. The bias voltage determines the maximum input amplitude of the analog input signal. V_SRC = V_2_VDIV = 2 * Vdiv.

[0019] The function of AMP1 is to convert the analog input signal V_SRC into a positive signal V_SIN by superimposing a bias voltage, in order to adapt to single-supply operation conditions. The output-input voltage relationship of AMP1 is as follows: V_SIN = 1 * (V_2_VDIV - V_SRC) = (2 * Vdiv - V_SRC) When V_SRC = + (2 * Vdiv), V_SIN reaches its minimum value, V_SIN = 0V; When V_SRC = - (2 * Vdiv), V_SIN reaches its maximum value, V_SIN = 4 * Vdiv.

[0020] The main function of the sample-and-hold circuit S1 and C1 is to open S1 during the quantization V_SMP of the subsequent circuit so that C1 holds the inverted voltage value V_SIN of the analog input signal, and close S1 after the subsequent circuit completes the quantization, so that V_SIN is input to C1 through S1 to prepare for the next analog signal.

[0021] The main function of polarity comparator CMP1 is to determine the phase of V_SRC. When S1 is open, the voltage V_SMP held by capacitor C1 is V_SIN before the switch is opened. Since this V_SIN is V_SRC superimposed on V_2_VDIV: When V_SRC > 0, V_SIN < V_2_VDIV, then comparator CMP1 outputs V_POUT = 1, indicating a positive polarity input; When V_SRC < 0, V_SIN > V_2_VDIV, then the comparator CMP1 outputs V_POUT = 0, indicating a negative polarity input.

[0022] Figure 4 The diagram shows the quantization circuit for the analog signal V_SMP. Integer quantization is performed by a differential amplifier AMP2 with a gain of 1, and fractional quantization is performed by a comparator CMP2. Integer values ​​refer to... Figure 2 The smallest unit in the expression is Vdiv, and the output V_ISET is a multiple of the minimum voltage Vdiv. During integer quantization, the positive input signal V_FSET of comparator CMP2 is fixed at Vdiv, that is... Figure 2 The PWM duty cycle of S7 is fixed at 100%, so CMP2 is used only as a comparator, and its output V_BACK reflects the voltage relationship between V_FOUT and V_FSET. Figure 2 middle V_ISET = (0, 1, 2, 3, 4) * Vdiv.

[0023] The score refers to the fact that V_FOUT is less than... Figure 2 The integer unit Vdiv is the value of the second quantization performed by CMP2, and this value is... Figure 1 In this process, after a sampling quantization is completed, the value in the D-value buffer is the duty cycle value. Since this is determined by comparator CMP2, the quantization result is the value of V_FSET, which is... V_FSET = (0%~100%) * Vdiv.

[0024] Therefore, the analog input signal quantization here involves two steps and outputs two quantization result values: The first step is to use V_ISET to quantize the integer part of the analog input signal, and the result is (0, 1, 2, 3, 4); The second step is to use V_FSET to quantize the fractional part of the analog input signal. The result is a continuous value (0% to 100%). When taking the value, remove the percent sign "%", which is the value after being magnified 100 times.

[0025] The specific quantification process will be explained below. The quantification process is as follows: Set V_FSET = 100% * Vdiv, V_ISET = (1 * Vdiv); disconnect Figure 3 Switch S1 in the circuit keeps V_SMP at the analog voltage value; If V_BACK = 1, then V_FOUT < V_FSET, which means (V_SMP - V_ISET) < (1 * Vdiv), and the quantization result is 0 in the integer part; If V_BACK = 0, then V_FOUT > V_FSET, meaning (V_SMP - V_ISET) > (1 * Vdiv). Add a setting so that V_ISET = (2 * Vdiv); If the feedback result changes V_BACK = 1, then V_FOUT < V_FSET, and the quantization result is 1 for the integer part. If the feedback result is still V_BACK = 0, it means V_FOUT > V_FSET. Add a setting so that V_ISET = (3 * Vdiv); If V_BACK = 1, then V_FOUT < V_FSET, and the quantization result has an integer part of 2; ... If quantization still fails when the set value V_ISET is increased to (4 * Vdiv), it means that the analog input signal has exceeded the quantization range.

[0026] Once the integer part is quantized, V_ISET retains the quantized integer value, so the output of the differential amplifier will definitely be... V_FOUT = (V_SMP - V_ISET) < (1 * Vdiv) This provides the basis for the comparator CMP2 to perform secondary quantization on the fractional part of V_SMP.

[0027] when Figure 2 When switch S7 operates in PWM mode, there is V_FSET = D * V_1_VDIV Where D represents the duty cycle value of the drive signal PWM of switch S7, which ranges from 0% to 100%.

[0028] Back Figure 4 In the middle, V_FSET is set to V_FSET = 50% * V_1_VDIV as the starting value: When D = 50%, if the output V_BACK = 1, it means that V_FSET > V_FOUT. D starts to decrease from 50% in 1% increments. If V_BACK = 0 is detected, it means that the critical point has been found. The previous step value is the value of V_FOUT, which is recorded as the decimal part of V_SMP. When D = 50%, if the output V_BACK = 0, it means that V_FSET < V_FOUT. D starts to increase from 50% in 1% increments. If V_BACK = 1 is detected, it means that the critical point has been found. The previous step value is the value of V_FOUT, which is recorded as the decimal part of V_SMP.

[0029] Quantization of V_SMP is complete.

[0030] The above explains the hardware circuit principle and ADC encoding process. The following will output the sampling and quantization results based on the specific input values.

[0031] Operating conditions are set as follows: reference voltage V_SREF = 4V, operating frequency of sampling switch S1 is 40kHz, and amplification factor of AMP1 and AMP2 is 1.

[0032] but Vdiv = V_SREF / 4 = 4V / 4 = 1V; V_1_VDIV = Vdiv = 1V; V_2_VDIV = 2 * Vdiv = 2V; V_ISET = (0V, 1V, 2V, 3V, 4V), and the corresponding quantization integer values ​​are recorded as (0, 1, 2, 3, 4); V_FSET = D * V_1_VDIV = (0%~100%) * 1V = (0V~1V), and the corresponding quantization decimal value is recorded as the value after the duty cycle is amplified by 100; Av1 = 1, the voltage amplification factor of amplifier AMP1; Av2 = 1, the voltage amplification factor of amplifier AMP2; fs1 = 40kHz, the operating frequency of sampling switch S1.

[0033] The voltage swing of the input signal V_SRC is V_SRC = ±V_2_VDIV = ±2V.

[0034] Now, let's assume the input voltage is +1.5V. Then, using the encoding principle described above, we can obtain the binary encoding result when the analog input voltage is +1.5V.

[0035] Preparation phase: S1 is closed; V_SIN = Av1 * (V_2_VDIV - V_SRC) = 1 * (2 – 1.5) = 0.5V; V_SMP = V_SIN = 0.5V; After S1 is disconnected, V_SMP retains the value of V_SIN and begins quantization.

[0036] Polarity determination: The logical result of V_POUT = (V_2_VDIV compared to V_SMP) is (2V > 0.5V) = 1, indicating positive polarity.

[0037] Integer value quantization: Set V_FSET = V_1_VDIV = 1V, and set V_ISET = 0V; V_FOUT = Av2 * (V_SMP - V_ISET) = 1 * (0.5 – 0) = 0.5; V_BACK = (V_FSET compared to V_FOUT) = (1V greater than 0.5V) = 1; The detection of V_BACK = 1 indicates that V_FOUT is less than the minimum voltage unit of 1V, and V_ISET = 0V is the quantization result. The integer value quantization result is 0V, which represents 0 times in (0 * Vdiv).

[0038] Small-value quantization: Set V_ISET to 0V and V_FSET to 0.5V. V_FOUT = Av2 * (V_SMP - V_ISET) = 1 * (0.5 – 0) = 0.5, therefore V_FOUT is fixed at 0.5V. V_BACK = (V_FSET = V_FOUT) = (0.5V = 0.5V) = 0; Increase duty cycle by 1% V_FSET = D * V_1_VDIV = (50% + 1%) * 1V = 0.51V, V_BACK = (V_FSET + V_FOUT) = (0.51V > 0.5V) = 1; A logical change in V_BACK was detected; the previous V_FSET value is the quantization result. The quantization result of the small value is 50%, and the value is 50 after being magnified 100 times.

[0039] Sampling frequency: The operating frequency of switch S1 is set to 40kHz by the ADC encoder frequency setting table, as shown below. Frequency value 20kHz 40kHz 80kHz 160kHz Table 1. Sampling Frequency Setting Table From the frequency setting table of the ADC encoder, the encoding value corresponding to the sampling frequency of 40kHz is found to be F[1:0]=b'01, where “b'” indicates that the following number is binary (the same applies below).

[0040] Reference voltage: V_SREF is determined by the output logic value of the reference voltage comparator group of the ADC encoder, and the corresponding relationship is as follows: voltage value 1V 2V 3V 4V Table 2. Reference Voltage Encoding Table From the reference voltage encoding value table, the encoding value corresponding to the 4V reference voltage is found to be V[1:0]=b'11.

[0041] Based on the above quantification and table lookup results, we can obtain Figure 1 The values ​​of registers REG[15:0]: REG[15:14], the sampling frequency encoding value, the table lookup result is F[1:0] = b'01; REG[13:11], the integer value quantization result, the quantization result is 0, and the binary representation is b'000; REG[10:4], the result of small-value quantization, the quantization result is 50%, and after being magnified by 100 times, the binary representation is b'0110010; REG[3:1], the reference voltage encoding value, the table lookup result is V[2:0] = b'011; REG[0] represents the polarity value of the analog input signal V_SRC in this quantization, with positive polarity represented as b'1.

[0042] Once the +1.5V quantization is complete, the sampling result is output from the output register at the sampling frequency. REG_OUT[15:0] = b'[01 000 0011001 011 1], where the space is only used as a separator to correspond to the above value. Attached Figure Description

[0043] Appendix Figure 1 ADC controller circuit block diagram

[0044] Appendix Figure 2 Reference voltage divider schematic

[0045] Appendix Figure 3 Sample and hold circuit schematic

[0046] Appendix Figure 4 Analog quantization circuit schematic

[0047] Appendix Figure 5 This invention is applied to the schematic diagram of a wireless microphone. Detailed Implementation

[0048] Figure 5 This is a schematic diagram of the present invention applied to a wireless microphone. The functions of each module are explained below.

[0049] Mic is a dynamic audio sensor that converts sound waves into electrical signals, which are then input to the audio amplifier AMP3 via impedance matching through resistor R2. R18 prevents AMP3 from self-oscillating if the sensor is open-circuited.

[0050] The AMP3 audio amplifier is a high-voltage amplifier. Since the maximum amplitude of the sensor is generally less than 5mV, and the subsequent stage requires at least 0.5V for sampling and quantization, the amplification factor is set to 100x. Figure 5 The ratios of R19 and R20 can then be determined.

[0051] R18 is only for preventing self-oscillation and its value is 100k ohms; R17 is an impedance matching resistor, and its value is determined according to the internal resistance of the mic, so no specific value is given here.

[0052] If the current flowing through R19 is set to 12.5uA and the maximum operating amplitude is 0.5V, then... (R19 + R20) = 0.5V / 12.5uA = 40kOhm; R19 / R20 = Av = 100;

[0053] From the above two equations, we can obtain R20 = 0.396 kOhm, with a value of 390 ohms; R19 = 39.6 kOhm, with a value of 39 k ohms.

[0054] When the battery BT is powered by two AAA batteries, it can obtain a 3V power supply voltage, and the AMP circuit, ADC module, and Bluetooth module can all work normally.

[0055] Once the ADC module M2 obtains the input voltage Vsrc, it begins sampling and quantization, and outputs the quantization result to the Bluetooth module from REG_OUT[15:0].

[0056] The main function of the Bluetooth module is to encode the audio digital of REG_OUT[15:0] and then transmit it wirelessly through the Bluetooth antenna ANT after Bluetooth encoding.

[0057] Figure 5 The working principle of wireless microphones is relatively simple: the audio sensor Mic converts audio into an electrical signal, which is then input to the AMP. After being amplified by the voltage of the AMP amplifier and encoded by the ADC module, the digitally encoded audio signal is wirelessly transmitted using the Bluetooth module.

[0058] The encoding principle of the ADC module has been explained in detail in the invention content section; this section only describes the change in operating conditions.

[0059] Since the battery voltage is 3V, but not a constant 3V, after the battery has been working for a period of time, the voltage may drop to as low as 1.2V or even lower. Here, we take the value as 1.2V. Therefore, the lowest voltage of the two batteries is 2.4V, which means that the BT voltage range is 2.4V to 3.0V.

[0060] For ADC module M2, since the minimum battery voltage is 2.4V, the reference voltage should be lower than this value. Therefore, V_SREF = 1.0V is chosen, where V_SREF is... Figure 2 The reference voltage in the diagram. Since the hardware circuitry of the ADC module is the same, the following will reuse the reference voltage. Figure 1 To the attached Figure 4 The encoding process will be explained in conjunction with the specific parameters of this embodiment, except that... Figure 5 middle, Figures 1 to 4 It is represented as module M2.

[0061] Operating conditions are set as follows: reference voltage V_SREF = 1V, operating frequency of sampling switch S1 is 20kHz, and amplification factor of 1 is applied to both AMP1 and AMP2.

[0062] but Vdiv = V_SREF / 4 = 1V / 4 = 0.25V; V_1_VDIV = Vdiv = 0.25V; V_2_VDIV = 2 * Vdiv = 0.5V; V_ISET = (0V, 0.25V, 0.5V, 0.75V, 1V), and the corresponding quantization integer values ​​are recorded as (0, 1, 2, 3, 4); V_FSET = D * V_1_VDIV = (0%~100%) * 0.25V = (0V~0.25V), and the corresponding quantization decimal value is recorded as the value after the duty cycle is amplified by 100; Av1 = 1, the voltage amplification factor of amplifier AMP1; Av2 = 1, the voltage amplification factor of amplifier AMP2; fs1 = 20kHz, the operating frequency of sampling switch S1.

[0063] The voltage swing of the input signal V_SRC is V_SRC = ±V_2_VDIV = ±0.5V This is a unipolar power supply, with Vsrc voltage ranging from 0V to 1V. Figure 3 The effect of capacitor C3 is that the actual voltage amplitude entering AMP1 is still ±0.5V.

[0064] Assuming the output voltage Vsrc of the AMP3 amplifier is 0.12V, then using the above parameters, obtain the binary encoding result when Vsrc is 0.12V (the encoding process is the same for other input voltage values ​​in the range of 0V to 1V).

[0065] Preparation phase: S1 is closed; Due to the DC blocking and AC passing effect of capacitor C3, sinusoidal signals within the voltage range of 0V to 1V are actually positive signals when input to AMP1 with a voltage greater than 0.5V (0V to 0.5V), while signals with a voltage less than 0.5V are actually negative signals when input to AMP1 (0V to -0.5V).

[0066] so V_SIN = Av1 * (V_2_VDIV - V_SRC) = Av1 * (V_2_VDIV - (Vsrc - 0.5V)) = 1 * (0.5V – (0.12V – 0.5V)) = 0.88V; V_SMP = V_SIN = 0.88V; After S1 is disconnected, V_SMP retains the value of V_SIN and begins quantization.

[0067] Polarity determination: The logical result of V_POUT = (V_2_VDIV compared to V_SMP) is (0.5V < 0.88V) = 0, indicating negative polarity.

[0068] Integer value quantization: Fixed V_FSET = V_1_VDIV = 0.25V, set V_ISET = 0V. V_FOUT = Av2 * (V_SMP - V_ISET) = 1 * (0.88 – 0) = 0.88V, V_BACK = (V_FSET compared to V_FOUT) = (0.25V less than 0.88V) = 0; Increase it to V_ISET = 0.25V; V_FOUT = Av2 * (V_SMP - V_ISET) = 1 * (0.88 – 0.25) = 0.63V; V_BACK = (V_FSET compared to V_FOUT) = (0.25V less than 0.63V) = 0; ... Increase it to V_ISET = 0.75V; V_FOUT = Av2 * (V_SMP - V_ISET) = 1 * (0.88 – 0.75) = 0.13V; V_BACK = (V_FSET compared to V_FOUT) = (0.25V is greater than 0.13V) = 1; The logic of V_BACK being 1 was detected, indicating that the V_FTOU value is less than the minimum unit of 0.25V. The value of V_ISET is the quantization result. The integer value quantization result is 0.75V, which represents 3 times in (3 * Vdiv).

[0069] Small-value quantization: Set V_ISET to 0.75V and V_FSET to 0.125V. V_FOUT = Av2 * (V_SMP - V_ISET) = 1 * (0.88 – 0.75) = 0.13V, fixed at 0.13V. V_BACK = (V_FSET compared to V_FOUT) = (0.125V less than 0.13V) = 0; Increase duty cycle by 1% V_FSET = D * V_1_VDIV = (50% + 1%) * 0.25V = 0.1275V, V_BACK = (V_FSET compared to V_FOUT) = (0.1275V is less than 0.13V) = 0; ... A logic change in V_BACK was detected at 53% duty cycle; the previous V_FSET value was the quantization result. The quantization result for the small value is 52%, and the value is 52 after being magnified 100 times.

[0070] Sampling frequency: The operating frequency of switch S1 is found in Table 1 of the ADC encoder frequency setting table. The encoding value at 20kHz is F[1:0]=b'00.

[0071] Reference voltage: Similarly, from the reference voltage encoding value table 2, we can find that the encoding value corresponding to the 1V reference voltage is V[1:0]=b'00.

[0072] Based on the above quantification and table lookup results, we can obtain Figure 1 The binary encoded values ​​of registers REG[15:0]: REG[15:14], the sampling frequency encoding value, the table lookup result is F[1:0] = b'00; REG[13:10], the integer value quantization result, the quantization result is 3, and the binary representation is b'011; REG[9:3], the result of small-value quantization, the quantization result is 52%, and after being magnified by 100 times, the binary representation is b'0110100; REG[2:1], the reference voltage code value, the table lookup result is V[1:0] = b'000; REG[0] represents the polarity value of the analog input signal V_SRC in this quantization, with negative polarity represented as b'0.

[0073] Once the quantization of the 0.12V input to Vsrc is complete, the quantization result of this sampling is output from the output register at the sampling frequency. REG_OUT[15:0] = [00 011 0110100 000 0].

Claims

1. An analog-to-digital converter encoding circuit, comprising an ADC controller, a reference voltage divider, a sample-and-hold circuit, and an analog quantization circuit, characterized in that: The ADC controller consists of an auxiliary circuit, an ADC encoder, and a data register group. The auxiliary circuit comprises a sampling switch driver circuit, an integer switch driver circuit, a PWM switch driver circuit, a reference voltage comparator group, and a polarity buffer. The polarity buffer is a buffer register. The output of the sampling switch driver circuit is connected to the driver terminal (DRV_S1) of switch one (S1), and its input is connected to the ADC encoder. The outputs of the integer switch driver circuit are connected to the driver terminals (DRV_S2), (DRV_S3), (DRV_S4), (DRV_S5), and (DRV_S6) of switches two (S2), three (S3), four (S4), five (S5), and six (S6), respectively, and their inputs are connected to the ADC encoder. The PWM switch driver circuit is a combined circuit consisting of a D-value buffer and a PWM driver. The input of the D-value buffer is connected to the ADC encoder, and the output of the D-value buffer is connected to the PWM driver. The output of the WM driver is connected to the drive terminal (DRV_S7) of switch seven (S7). The value in the D value buffer is the duty cycle value. The input of the reference voltage comparator group is connected to the reference power supply (V_SREF), and its output is connected to the ADC encoder. The input of the polarity buffer is connected to the polarity signal (V_POUT), and its output is connected to the ADC encoder. The first input terminal of the ADC encoder is connected to the feedback signal (V_BACK), and the first output terminal is connected to the internal output register group (REG_OUT[15:0]). The data register group is a 16-bit binary register group (REG[15:0]), which consists of a 2-bit binary frequency encoding value register (REG[15:14]), a 3-bit binary integer encoding value register (REG[13:11]), a 7-bit binary duty cycle encoding value register (REG[10:4]), a 3-bit binary reference voltage encoding value register (REG[3:1]), and a 1-bit binary polarity encoding value register (REG[0]), all of which are connected to the ADC encoder. The reference voltage divider consists of an integer value setting circuit and a fractional value setting circuit. Its key feature is that the positive terminal (V_SREF) of the reference power supply is connected to one end of switch two (S2) and one end of resistor ten (R10); the ground of the reference power supply is connected to system ground (GND); the other end of resistor ten (R10) and one end of switch three (S3) of the integer value setting circuit are connected to one end of resistor eleven (R11); the other end of resistor eleven (R11) and one end of switch four (S4) are connected to one end of resistor twelve (R12); the other end of resistor twelve (R12) and one end of switch five (S5) are connected to one end of resistor fourteen (R14); the other end of resistor fourteen (R14) is connected to system ground (GND); and switch two (S2)... The other end of switch 3 (S3), the other end of switch 4 (S4), the other end of switch 5 (S5), and one end of switch 6 (S6) are connected to the integer value quantization signal (V_ISET). The other end of switch 6 (S6) is connected to system ground (GND). One end of switch 7 (S7) of the fractional value setting circuit is connected to one end of switch 5 (S5). The other end of switch 7 (S7) is connected to one end of resistor 13 (R13). The other end of resistor 13 (R13) and one end of capacitor 2 (C2) are connected to the fractional value quantization signal (V_FSET). The other end of capacitor 2 (C2) is connected to system ground (GND). The bias voltage signal (V_2_VDIV) is connected to one end of switch 4 (S4). The sample-and-hold circuit consists of a bias amplifier circuit, switch one (S1), capacitor one (C1), and a polarity comparator circuit. Its key feature is that the analog input signal (V_SRC) is connected to one end of capacitor three (C3); the other end of capacitor three (C3) in the bias amplifier circuit and one end of resistor five (R5) are connected to one end of resistor one (R1); the other end of resistor five (R5) is connected to system ground (GND); the other end of resistor one (R1) and the negative input terminal (-) of amplifier one (AMP1) are connected to one end of resistor two (R2); the other end of resistor two (R2) and the output terminal (Vo) of amplifier one (AMP1) are connected to one end of switch one (S1); the positive input terminal (+) of amplifier one (AMP1) and one end of resistor sixteen (R16) are connected to one end of resistor fifteen (R15); the other end of resistor fifteen (R15) is connected to... The system ground (GND) is connected to the system ground; the other end of resistor 16 (R16) is connected to the bias voltage signal (V_2_VDIV), the other end of switch 1 (S1) of the sample-and-hold circuit and one end of capacitor 1 (C1) are connected to the sample-and-hold signal (V_SMP), the other end of capacitor 1 (C1) is connected to the system ground (GND), the negative input terminal (-) of comparator 1 (CMP1) of the polarity comparison circuit is connected to the sample-and-hold signal (V_SMP), the positive input terminal (+) of comparator 1 (CMP1) and one end of resistor 9 (R9) are connected to the bias voltage signal (V_2_VDIV), the other end of resistor 9 (R9) is connected to the output terminal (Vo) of comparator 1 (CMP1), the output terminal (Vo) of comparator 1 (CMP1) outputs a polarity signal (V_POUT), and the polarity buffer is used to buffer the polarity signal; The analog quantization circuit consists of an integer quantization circuit and a fractional quantization circuit. The integer quantization circuit comprises resistor 3 (R3), amplifier 2 (AMP2), resistor 4 (R4), resistor 6 (R6), and resistor 7 (R7). The sample-and-hold signal (V_SMP) is connected to one end of resistor 3 (R3). The other end of resistor 3 (R3) and the positive input (+) of amplifier 2 (AMP2) are connected to one end of resistor 4 (R4). The other end of resistor 4 (R4) is connected to system ground (GND). The integer quantization signal (V_ISET) is connected to one end of resistor 6 (R6). The other end of resistor 6 (R6) and the negative input (-) of amplifier 2 (AMP2) are connected to one end of resistor 7 (R7). The other end of resistor 7 (R7) and the output (Vo) of amplifier 2 (AMP2) are connected to the negative input (-) of comparator 2 (CMP2). The fractional quantization circuit consists of comparator 2 (CMP2) and resistor 8 (R8). The fractional quantization signal (V_FSET) is connected to the positive input terminal (+) of comparator 2 (CMP2) and one end of resistor 8 (R8). The other end of resistor 8 (R8) and the output terminal (Vo) of comparator 2 (CMP2) are connected to the feedback signal (V_BACK).

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