Solid-state imaging device and imaging apparatus

Abstract

A solid-state imaging device includes: a first substrate including a photoelectric conversion section and a transfer transistor electrically connected to the photoelectric conversion section; a second substrate arranged to face the first substrate and including an output transistor, the output transistor including a gate electrode, a channel region of a first conductivity type arranged to face the gate electrode, and a source-drain region of the first conductivity type adjacent to the channel region; and a drive circuit that allows signal charges generated by the photoelectric conversion section to be output via the transfer transistor and the output transistor.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device and an imaging apparatus including a photoelectric conversion section. Background Art

[0002] In recent years, image sensors have been used not only in applications for taking images but also in applications such as surveillance and autonomous driving of automobiles. In such an image sensor, for example, solid-state imaging devices such as a charge-coupled device (CCD) and a complementary metal oxide semiconductor (CMOS) are used.

[0003] For example, a solid-state imaging device includes a photoelectric conversion section and an output transistor. The photoelectric conversion section is provided for each pixel. The output transistor outputs signal charges generated in the photoelectric conversion section to a drive circuit (for example, see Patent Document 1).

[0004] Citation List

[0005] Patent Document

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-54876 Summary of the Invention

[0007] In such a solid-state imaging device, it is desirable to suppress noise.

[0008] Therefore, it is desirable to provide a solid-state imaging device capable of suppressing noise and an imaging apparatus including the solid-state imaging device.

[0009] A solid-state imaging device (1) according to an embodiment of the present disclosure includes: a first substrate including a photoelectric conversion section and a transfer transistor electrically connected to the photoelectric conversion section; a second substrate provided opposite to the first substrate and including an output transistor, the output transistor including a gate electrode, a channel region of a first conductivity type arranged opposite to the gate electrode, and a source-drain region of the first conductivity type adjacent to the channel region; and a drive circuit that allows signal charges generated in the photoelectric conversion section to be output via the transfer transistor and the output transistor.

[0010] An imaging apparatus (1) according to an embodiment of the present disclosure includes the solid-state imaging device (1) according to the foregoing embodiment of the present disclosure.

[0011] A solid-state imaging device (2) according to an embodiment of the present disclosure includes: a photoelectric conversion section; a transfer transistor electrically connected to the photoelectric conversion section; an output transistor electrically connected to the transfer transistor and including a channel region of a first conductivity type, a gate electrode covering a plurality of surfaces of the channel region, and a source-drain region of the first conductivity type adjacent to the channel region; and a drive circuit that allows signal charges generated in the photoelectric conversion section to be output via the transfer transistor and the output transistor.

[0012] An imaging device (2) according to an embodiment of the present disclosure includes the solid-state imaging device (2) according to the foregoing embodiment of the present disclosure.

[0013] In the solid-state imaging devices (1) and (2) and the imaging devices (1) and (2) according to embodiments of the present disclosure, the output transistor includes a channel region of the same conductivity type (first conductivity type) as the source-drain region. Therefore, the current path of the channel region is formed away from the interface on the gate electrode side. This makes it less likely that carriers flowing in the channel region are trapped at the interface on the gate electrode side.

[0014] Note that the effects described below are not necessarily restrictive, and any effects described in the present disclosure may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram showing an example of the functional configuration of an imaging element according to a first embodiment of the present disclosure.

[0016] Figure 2 is a diagram showing Figure 1 an example of the circuit configuration of the pixel shown.

[0017] Figure 3 is a diagram showing Figure 1 an example of the configuration of the pixel shown in a schematic plan view.

[0018] Figure 4A is a diagram showing a schematic cross-sectional configuration along the Figure 3 A-A' line shown.

[0019] Figure 4B is a diagram showing a cross-section along the Figure 3 B-B' line shown in a schematic diagram.

[0020] Figure 5 is a diagram showing Figure 4B another example of the configuration of the gate electrode shown in a schematic cross-sectional view.

[0021] Fig. 6Ais a schematic cross-sectional view corresponding to the amplifying transistor of the comparative example Figure 4A

[0022] Figure 6B is a schematic cross-sectional view corresponding to the amplifying transistor of the comparative example Figure 4B

[0023] Figure 7 is a schematic cross-sectional view showing the current path flowing in the amplifying transistor shown in Figure 4B

[0024] Figure 8 is a schematic cross-sectional view showing the configuration of the imaging element according to Modification 1

[0025] Fig. 9 is a schematic cross-sectional view showing the configuration of the imaging element according to Modification 2

[0026] Fig.10 is a diagram showing an example of the circuit configuration of the pixel of the imaging element according to Modification 3

[0027] Fig.11 is a schematic diagram showing an example of the planar configuration of the imaging element shown in Fig.10

[0028] Fig.12 is a schematic diagram showing a schematic configuration of the main part of the imaging element according to the second embodiment of the present disclosure

[0029] Fig.13 is a diagram showing an example of the pixel and the readout circuit in Fig.12

[0030] Fig.14 is a diagram showing an example of the pixel and the readout circuit in Fig.12

[0031] Fig.15 is a diagram showing an example of the pixel and the readout circuit in Fig.12

[0032] Fig.16 is a diagram showing an example of the pixel and the readout circuit in Fig.12

[0033] Fig.17 is a diagram showing an example of the connection mode between a plurality of readout circuits and a plurality of vertical signal lines

[0034] Fig.18 is a diagram showing an example of the cross-sectional configuration of the imaging element in Fig.12 in the vertical direction

[0035] Fig.19 ​​​​​​​​It is a schematic plan view showing the configuration of the main part of the imaging element according to Modification Example 4.

[0036] Fig. 20A It is a schematic diagram showing the cross-sectional configuration along the Fig.19 indicated A-A' line.

[0037] Fig. 20B It is a schematic diagram showing the cross-sectional configuration along the Fig.19 indicated B-B' line.

[0038] Fig.21A It is a schematic cross-sectional view showing the process of the manufacturing method of the imaging element shown in Fig. 20A etc.

[0039] Fig.21B It is a schematic cross-sectional view showing the subsequent process of Fig.21A

[0040] Fig. 21C It is a schematic cross-sectional view showing the subsequent process of Fig.21B

[0041] Fig.22A It is a schematic cross-sectional view showing another example of the subsequent process of Fig. 21C

[0042] Fig. 22B It is a schematic cross-sectional view showing the subsequent process of Fig.22A

[0043] Fig. 22C It is a schematic cross-sectional view showing the subsequent process of Fig. 22B

[0044] Fig.22D It is a schematic cross-sectional view showing the subsequent process of Fig. 22C

[0045] Fig.22E It is a schematic cross-sectional view showing the subsequent process of Fig.22D

[0046] Fig.22F It is a schematic cross-sectional view showing the subsequent process of Fig.22E

[0047] Figure 22G It is a schematic cross-sectional view showing the subsequent process of Fig.22F

[0048] Fig.22H It is a schematic cross-sectional view showing the subsequent process of Figure 22G

[0049] Fig.23It is a schematic cross-sectional view showing the configuration of the main part of the imaging element according to Modification 5.

[0050] Fig.24 It is a view showing Fig.23 an example of the cross-sectional configuration of the imaging element in the horizontal direction in

[0051] Fig.25 It is a view showing Fig.23 an example of the cross-sectional configuration of the imaging element in the horizontal direction in

[0052] Fig.26 It is a view showing Fig.23 an example of the wiring layout in the horizontal plane of the imaging element in

[0053] Fig. 27 It is a view showing Fig.23 an example of the wiring layout in the horizontal plane of the imaging element in

[0054] Fig.28 It is a view showing Fig.23 an example of the wiring layout in the horizontal plane of the imaging element in

[0055] Fig.29 It is a view showing Fig.23 an example of the wiring layout in the horizontal plane of the imaging element in

[0056] Fig.30 It is a view showing an example of the cross-sectional configuration of the imaging element according to Modification 6 in the vertical direction.

[0057] Fig.31 It is a view showing an example of the cross-sectional configuration of the imaging element according to Modification 7 in the horizontal direction.

[0058] Fig.32 It is a view showing Fig.23 another example of the cross-sectional configuration of the imaging element shown in the horizontal direction.

[0059] Fig.33 It is a view showing an example of the cross-sectional configuration of the imaging element according to Modification 8 in the horizontal direction.

[0060] Fig.34 It is a view showing an example of the cross-sectional configuration of the imaging element according to Modification 9 in the horizontal direction.

[0061] Fig.35 It is a view showing an example of the cross-sectional configuration of the imaging element according to Modification 10 in the horizontal direction.

[0062] Fig.36 It is a view showing Fig.35A diagram showing another example (1) of the cross-sectional structure of the imaging element in the horizontal direction.

[0063] Fig.37 It shows Fig.35 A diagram showing another example (2) of the cross-sectional structure of the imaging element in the horizontal direction.

[0064] Fig.38 A diagram showing an example of the circuit structure of the imaging element according to the second embodiment and its modified examples described above.

[0065] Fig.39 It shows where Fig.38 The imaging element in includes an example where three substrates are stacked.

[0066] Fig.40 A diagram showing an example where the logic circuit is separately formed on the substrate provided with the pixel P and the substrate provided with the readout circuit.

[0067] Fig.41 A diagram showing an example where the logic circuit is formed on the third substrate.

[0068] Fig.42 A diagram showing an example of the schematic structure of an imaging device including the imaging element according to the above embodiment and its modified examples.

[0069] Fig.43 It shows Fig.42 An example of the imaging process in the imaging device in.

[0070] Fig.44 A block diagram showing an example of the schematic structure of an in-vivo information acquisition system.

[0071] Fig.45 A diagram showing an example of the schematic structure of an endoscopic surgery system.

[0072] Fig.46 A block diagram showing an example of the functional structure of a camera head and a camera control unit (CCU).

[0073] Fig.47 A block diagram showing an example of the schematic structure of a vehicle control system.

[0074] Fig.48 A diagram assisting in explaining an example of the installation positions of an out-of-vehicle information detection unit and an imaging unit. Detailed Description of the Invention

[0075] Hereinafter, some embodiments of the present technology will be described in detail with reference to the accompanying drawings. Note that the description is given in the following order.

[0076] 1. First Embodiment (Example of a solid-state imaging device provided with an amplifying transistor including a channel region having the same conductivity type as source-drain regions)

[0077] 2. Modification Example 1 (Example in which the amplifying transistor has a Fin FET (Field Effect Transistor) structure)

[0078] 3. Modification Example 2 (Example in which the amplifying transistor has a Gate All Around (GAA) structure)

[0079] 4. Modification Example 3 (Example in which the amplifying transistor is shared by multiple pixels)

[0080] 5. Second Embodiment (Example of a solid-state imaging device having a stacked structure of a first substrate, a second substrate, and a third substrate)

[0081] 6. Modification Example 4 (Example in which the reset transistor, the amplifying transistor, and the selection transistor have a Fin FET structure)

[0082] 7. Modification Example 5 (Example having a Full Trench Isolation (FTI) structure)

[0083] 8. Modification Example 6 (Example in which Cu-Cu bonding is used at the outer edge of the panel)

[0084] 9. Modification Example 7 (Example in which an offset is provided between the pixel and the readout circuit)

[0085] 10. Modification Example 8 (Example in which the silicon substrate provided with the readout circuit has an island shape)

[0086] 11. Modification Example 9 (Example in which the silicon substrate provided with the readout circuit has an island shape)

[0087] 12. Modification Example 10 (Example in which the FD is shared by four pixels P)

[0088] 13. Modification Example 11 (Example in which the signal processing circuit is constituted by a general column ADC circuit)

[0089] 14. Modification Example 12 (Example in which the imaging device is constituted by three stacked substrates)

[0090] 15. Modification Example 13 (Example in which the logic circuit is provided on the first substrate and the second substrate)

[0091] 16. Modification Example 14 (Example in which the logic circuit is provided on the third substrate)

[0092] 17. Application Example (Example of Electronic Device)

[0093] 18. Application Example

[0094] <First Embodiment>

[0095] (Overall Configuration of Imaging Element 10)

[0096] Figure 1 It is a block diagram showing an example of the functional configuration of a solid-state imaging element (imaging element 10) according to the first embodiment of the present disclosure. For example, the imaging element 10 is an amplifying solid-state imaging element such as a CMOS image sensor. The imaging element 10 may be other amplifying solid-state imaging elements, or may be a charge transfer type solid-state imaging element such as a CCD.

[0097] The imaging element 10 includes a semiconductor substrate 11 on which a pixel array unit 12 and a peripheral circuit unit are provided. The pixel array unit 12 is provided, for example, in the central portion of the semiconductor substrate 11, and the peripheral circuit unit is provided outside the pixel array unit 12. For example, the peripheral circuit unit includes a vertical drive circuit 13, a signal processing circuit 14, a horizontal drive circuit 15, and a system control circuit 16.

[0098] In the pixel array unit 12, unit pixels (pixel P) are two-dimensionally arranged in a matrix form. Each unit pixel includes a photoelectric conversion unit that generates a signal charge corresponding to the incident light amount and accumulates the signal charge therein. In other words, a plurality of pixels P are arranged along the Figure 1 X direction (first direction) and Y direction (second direction) in. The "unit pixel" used here is an imaging pixel for acquiring an imaging signal. The specific circuit configuration of the pixel P (imaging pixel) will be described later.

[0099] In the pixel array unit 12, for the pixel arrangement in the matrix, pixel drive lines 17 are wired along the row direction of each pixel row (the arrangement direction of pixels in the pixel row), and vertical signal lines 18 are wired along the column direction of each pixel column (the arrangement direction of pixels in the pixel column). The pixel drive lines 17 transmit drive signals for pixel driving. The drive signals are output from the vertical drive circuit 13 in units of rows. In Figure 1 the pixel drive lines 17 are shown as a single wiring, but are not limited to a single wiring. One end of the pixel drive line 17 is connected to the output terminal corresponding to each row of the vertical drive circuit 13.

[0100] The vertical drive circuit 13 includes, for example, a shift register and an address decoder, and drives each pixel of the pixel array unit 12 in units of rows. Here, the illustration of the specific configuration of the vertical drive circuit 13 is omitted, but generally, the vertical drive circuit 13 has a structure including two scanning systems, namely, a readout scanning system and a discharge scanning system.

[0101] The readout scanning system selectively scans the unit pixels of the pixel array unit 12 in units of rows in order to read out signals from the unit pixels. The signals read out from the unit pixels are analog signals. The discharge scanning system performs a discharge scan on the readout rows to be read out by the readout scanning system at the time of the shutter speed before the readout scan.

[0102] Through the discharge scan of the discharge scanning system, unnecessary charges are discharged from the photoelectric conversion section of the unit pixels in the readout row, thereby resetting the photoelectric conversion section. Therefore, by discharging (resetting) unnecessary charges by the discharge scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding the signal charges in the photoelectric conversion section to restart exposure (start the accumulation of signal charges).

[0103] The signals to be read out through the readout operation of the readout scanning system correspond to the incident light amount immediately after the previous readout operation or electronic shutter operation. In addition, the period from the readout time of the previous readout operation or the discharge time of the electronic shutter operation to the readout time of the current readout operation is used as the accumulation period (exposure period) of the signal charges in the unit pixel.

[0104] The signals to be output from each unit pixel of the pixel row selectively scanned by the vertical drive circuit 13 are supplied to the signal processing circuit 14 via each vertical signal line 18. For each pixel column of the pixel array unit 12, the signal processing circuit 14 performs predetermined signal processing on the signals to be output from each pixel of the selected row via the vertical signal line 18, and temporarily holds the pixel signals after the signal processing.

[0105] Specifically, the signal processing circuit 14 receives the signals of the unit pixels, and performs signal processing such as noise removal on the signals through CDS (correlated double sampling), signal amplification, and AD (analog-to-digital) conversion. Through the noise removal process, reset noise and pixel-specific fixed pattern noise such as threshold variations of amplification transistors are removed. Note that the signal processing illustrated here is only an example, and the signal processing is not limited to these. Here, the signal processing circuit 14 corresponds to a specific example of the drive circuit of the present disclosure.

[0106] The horizontal drive circuit 15 includes, for example, a shift register and an address decoder, and selectively scans in sequence the unit circuits corresponding to the pixel columns of the signal processing circuit 14. Through the selective scanning of the horizontal drive circuit 15, the pixel signals that have been signal-processed by the respective unit circuits of the signal processing circuit 14 are output to the horizontal bus B in sequence and transmitted to the outside of the semiconductor substrate 11 via the horizontal bus B.

[0107] The system control circuit 16 receives, for example, a clock given from the outside of the semiconductor substrate 11 and data giving an operation mode instruction. In addition, the system control circuit 16 outputs data such as internal information of the imaging element 10. Further, the system control circuit 16 includes a timing generator that generates various timing signals. Based on the various timing signals generated in the timing generator, the system control circuit 16 performs drive control of peripheral circuit units such as the vertical drive circuit 13, the signal processing circuit 14, and the horizontal drive circuit 15.

[0108] (Circuit configuration of pixel P)

[0109] Figure 2 It is a circuit diagram showing an example of the readout circuit 20 that outputs a pixel signal based on the charge output from each pixel P.

[0110] Each pixel P includes, for example, a photodiode 21 as a photoelectric conversion section. For example, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 are connected to the photodiode 21 provided for each pixel P. Here, a specific example of the output transistor in the present disclosure is the amplification transistor 24.

[0111] In addition, with respect to the pixel P, as the pixel drive lines 17, for example, three drive wirings of a transmission line 17a, a reset line 17b, and a selection line 17c are commonly provided for each pixel P in the same pixel row. One end of each of the transmission line 17a, the reset line 17b, and the selection line 17c is connected to the output terminal corresponding to each pixel row of the vertical drive circuit 13 in units of pixel rows to transmit a transmission pulse φTRF, a reset pulse φRST, and a selection pulse φSEL as drive signals for driving the pixel P.

[0112] The photodiode 21 includes an anode connected to a negative-side power supply (for example, ground), and photoelectrically converts the received light (incident light) into a signal charge corresponding to the amount of light to accumulate the signal charge. The photodiode 21 includes a cathode electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. The node electrically connected to the gate electrode of the amplification transistor 24 is called an FD (floating diffusion) section 26 (charge accumulation section).

[0113] The transfer transistor 22 is connected between the cathode of the photodiode 21 and the FD section 26. A transfer pulse φTRF, which is at a high level (e.g., Vdd level) and is active (hereinafter referred to as high-active), is supplied to the gate electrode of the transfer transistor 22 via the transfer line 17a. Accordingly, the transfer transistor 22 enters an on state, and the signal charge photoelectrically converted by the photodiode 21 is transferred to the FD section 26.

[0114] The reset transistor 23 includes a drain connected to the pixel power supply Vdd and a source connected to the FD section 26. A high-active reset pulse φRST is supplied to the gate electrode of the reset transistor 23 via the reset line 17b. Accordingly, the reset transistor 23 enters an on state, and the FD section 26 is reset by discharging the charge of the FD section 26 to the pixel power supply Vdd.

[0115] The amplification transistor 24 includes a gate electrode connected to the FD section 26 and a drain connected to the pixel power supply Vdd. Accordingly, the amplification transistor 24 outputs the potential of the FD section 26 after being reset by the reset transistor 23 as a reset signal (reset level) Vrst. Further, after the signal charge is transferred by the transfer transistor 22, the amplification transistor 24 outputs the potential of the FD section 26 as a light integration signal (signal level) Vsig.

[0116] For example, the selection transistor 25 includes a drain connected to the source of the amplification transistor 24 and a source connected to the vertical signal line 18. A high-active selection pulse φSEL is supplied to the gate electrode of the selection transistor 25 via the selection line 17c. Accordingly, the selection transistor 25 enters an on state, causing the unit pixel P to enter a selection state and enabling the signal supplied from the amplification transistor 24 to be output to the vertical signal line 18.

[0117] The vertical signal line 18 is connected to a transistor (not shown) of a constant current source biased at a constant voltage. Accordingly, the amplification transistor 24, the selection transistor 25, and the vertical signal line 18 constitute a so-called source follower circuit.

[0118] In Figure 2 the example, a circuit configuration is given in which the selection transistor 25 is connected between the source of the amplification transistor 24 and the vertical signal line 18. However, a circuit configuration in which the selection transistor 25 is connected between the pixel power supply Vdd and the drain of the amplification transistor 24 may also be employed.

[0119] The circuit configuration of each pixel P is not limited to a circuit configuration of a pixel configuration including the above four transistors. For example, other pixel configurations may also include three transistors, where one transistor serves as both the amplification transistor 24 and the selection transistor 25. The configuration of the pixel circuit is not limited.

[0120] (Specific configuration of pixel P)

[0121] Hereinafter, with reference to Figure 3 , Figure 4A and Figure 4B the specific configuration of pixel P will be described. Figure 3 The planar configuration of pixel P is schematically shown. Figure 4A and Figure 4B respectively schematically show the cross-sectional configuration along the Figure 3 A-A' line shown in Figure 3 and the cross-sectional configuration along the B-B' line shown in

[0122] For example, the imaging element 10 is a back-illuminated imaging element. On the wide area of each pixel P, for example, a photodiode 21 having a substantially rectangular planar shape is provided. For example, near the end of each pixel P, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 are arranged side by side in sequence. The FD section 26 and the transfer transistor 22 are provided between the reset transistor 23 and the photodiode 21 ( Figure 3 ). The amplification transistor 24 is provided on one surface (surface S11B described below) side of the semiconductor substrate 11, and includes a gate electrode 24G, a gate insulating film 24I, a channel region 24C, and a pair of source-drain regions 24A and 24B.

[0123] The semiconductor substrate 11 includes a surface S11A on the light incident side and a surface S11B opposite to the surface S11A. For example, the semiconductor substrate 11 is made of silicon (Si). In the semiconductor substrate 11, a photodiode 21 is provided for each pixel P. The photodiode 21 is, for example, a photodiode having a pn junction, and includes a p-type impurity region 21a and an n-type impurity region 21b formed in a p-type well region 111. For example, the p-type impurity region 21a and the n-type impurity region 21b are provided in sequence from the surface S11B side of the semiconductor substrate 11 along the thickness direction. For example, the p-type impurity region 21a has a size of about 30 nm to 200 nm in the depth direction ( Figure 4B the Z direction in). The n-type impurity region 21b has a size of about 1 μm to 5 μm in the depth direction. For example, the impurity concentration of the p-type impurity region 21a is about 1×10 18 cm -3 ~1×10 19 cm -3 . The impurity concentration of the n-type impurity region 21b is about 1×10 15 cm -3 ~1×10 18 cm -3 . For example, the impurity concentration of the p-type well region 111 is about 1×10 16 cm -3 ~1×10 18cm -3 。

[0124] Near the inner surface S11B of the semiconductor substrate 11, a channel region 24C of the amplification transistor 24 and a pair of source-drain regions 24A and 24B are provided. For example, the pair of source-drain regions 24A and 24B are n-type (first conductivity type) impurity diffusion regions formed in the p-type well region 111 and are disposed adjacent to the channel region 24C. The source-drain region 24A, the channel region 24C, and the source-drain region 24B are arranged in this order along the channel length direction ( Figure 4A the Y direction in). For example, the impurity concentration of the source-drain regions 24A and 24B is about 1×10 19 cm -3 ~1×10 21 cm -3 . In the present embodiment, the channel region 24C of the amplification transistor 24 includes an n-type impurity diffusion region, that is, the same conductivity type as the source-drain regions 24A and 24B. In other words, the amplification transistor 24 has a junctionless structure. Although it will be described in detail later, this makes it less likely that the carriers flowing in the channel region 24C are trapped (captured) at the interface with the gate insulating film 24I. Therefore, the generation of noise in the amplification transistor 24 can be suppressed.

[0125] The channel region 24C disposed between the pair of source-drain regions 24A and 24B is an n-type impurity diffusion region formed in the p-type well region 111. The impurity concentration of the channel region 24C is about 5×10 17 cm -3 ~1×10 19 cm -3 . The channel region 24C is surrounded by the gate electrode 24G. For example, the size of the channel region 24C in the channel length direction is about 200 nm to 3000 nm. For example, the size of the channel region 24C in the channel width direction ( Figure 4B the X direction in) is about 20 nm to 200 nm. For example, the size (size D) of the channel region 24C in the depth direction is larger than the size of the pair of source-drain regions 24A and 24B in the depth direction and is about 50 nm to 500 nm.

[0126] The gate electrode 24G surrounding the channel region 24C includes: a pair of opposite side surfaces 241 and 242 and an upper surface 243 connecting the pair of side surfaces 241 and 242. The pair of side surfaces 241 and 242 and the upper surface 243 are all opposite to the channel region 24C. In other words, the pair of side surfaces 241 and 242 and the upper surface 243 form a concave shape surrounding the channel region 24C.

[0127] A pair of side surfaces 241 and 242 are planes substantially perpendicular to the surface S11B of the semiconductor substrate 11 ( Figure 4B the YZ plane in it), and are opposite to the channel width direction. The channel region 24C is provided between the pair of side surfaces 241 and 242. A part or all of the pair of side surfaces 241 and 242 are buried in the semiconductor substrate 11. In the pair of side surfaces 241 and 242, the dimension of the part buried in the semiconductor substrate 11 in the depth direction is, for example, about 100 nm to 500 nm.

[0128] Figure 5 Another example of the pair of side surfaces 241 and 242 is shown. A part of the channel region 24C may be exposed from the pair of side surfaces 241 and 242. Preferably, more than half of the dimension of the channel region 24C in the depth direction is covered by the pair of side surfaces 241 and 242.

[0129] The upper surface 243 is a plane substantially parallel to the surface S11B of the semiconductor substrate 11 ( Figure 4B the XY plane in it), and is provided outside the semiconductor substrate 11. That is, the upper surface 243 is provided to face the semiconductor substrate 11. The upper surface 243 contacts one end of each of the pair of side surfaces 241 and 242.

[0130] For example, the gate electrode 24G including the pair of side surfaces 241 and 242 and the upper surface 243 is made of p-type (second conductivity type) polysilicon (Poly-Si) or the like. The gate electrode 24G may be made of metals such as tungsten (W), titanium (Ti), titanium nitride (TiN), hafnium (Hf), hafnium silicide (HfSi), ruthenium (Ru), iridium (Ir), and cobalt (Co).

[0131] The gate insulating film 24I is provided between each of the pair of side surfaces 241 and 242 and the upper surface 243 and the channel region 24C. For example, the gate insulating film 24I is made of an insulating film such as silicon oxide (SiO). For example, the thickness of the gate insulating film 24I is about 3 nm to 15 nm.

[0132] The element isolation region (STI: Shallow Trench Isolation) 112 is provided around the side surfaces 241 and 242 buried in the semiconductor substrate 11. For example, the element isolation region 112 is made of an insulating material such as silicon oxide. Inside the semiconductor substrate 11, the element isolation region 112 is provided between the side surface 242 and the photodiode 21.

[0133] (Operation of the imaging element 10)

[0134] In the imaging element 10, light (e.g., light having a wavelength in the visible light region) is incident on the photodiode 21 from the surface S11A of the semiconductor substrate 11. As a result, pairs of holes and electrons are generated in the photodiode 21 (photoelectric conversion is performed). The transfer transistor 22 is turned on, and thus the signal charges accumulated in the photodiode 21 are transferred to the FD section 26. In the FD section 26, the signal charges are converted into voltage signals, and the voltage signals are output to the vertical signal line 18 via the amplification transistor 24 and the selection transistor 25.

[0135] (Function and effect of the imaging element 10)

[0136] In the imaging element 10 of the present embodiment, the amplification transistor 24 is a so-called junctionless transistor and includes a channel region 24C having the same conductivity type as the source-drain regions 24A and 24B (n-type). This causes the current path in the channel region 24C to be formed away from the interface with the gate insulating film 24I, so that the carriers flowing in the channel region 24C are less likely to be trapped at the interface with the gate insulating film 24I. Hereinafter, this function and effect will be described using a comparative example.

[0137] Fig. 6A and Figure 6B Fig. shows a schematic cross-sectional configuration of an amplification transistor (amplification transistor 124) according to a comparative example. Fig. 6A Corresponding to the cross-sectional configuration along Figure 3 the line A-A' in Figure 6B and corresponding to the cross-sectional configuration along Figure 3 the line B-B' in Fig. 6A The gate electrode (gate electrode 124G) of the amplification transistor 124 includes only a single plane provided outside the semiconductor substrate 11. The gate electrode 124G is not buried in the semiconductor substrate 11. For example, the channel region 124C opposite to the gate electrode 124G is formed of an impurity diffusion region having a conductivity type (p-type) opposite to the conductivity type (n-type) of the pair of source-drain regions 24A and 24B. The channel region 124C may be a low-concentration n-type, but it is difficult to increase the size (size D100) of the channel region 124C in the depth direction (

[0138] In such a magnifying transistor 124, the current path in the channel region 124C is formed near the interface with the gate insulating film 24I. Therefore, the presence of trap levels in the gate insulating film 24I causes carriers flowing in the channel region 124C to be captured by the trap levels or released from the trap levels. This causes fluctuations in the current flowing in the channel region 124C. Such fluctuations in the current contribute to the generation of noise.

[0139] A possible method of suppressing noise could be to increase the occupied area of the magnifying transistor. However, in this method, the occupied area of the photodiode provided on the same semiconductor substrate as the magnifying transistor is reduced. For example, this affects the sensitivity and the cumulative saturation amount of the signal charge.

[0140] In contrast, in the imaging element 10, the channel region 24C is formed of an n-type impurity diffusion region with a high impurity concentration. Therefore, a depletion layer is formed near the interface between the channel region 24C and the gate insulating film 24I, causing the current path in the channel region 24C to be formed at a position far from the gate insulating film 24I.

[0141] Figure 7 The current (current C) flowing in the magnifying transistor 24 in the on state is schematically shown. Therefore, in the magnifying transistor 24, most of the current C flows through the central portion of the channel region 24C in the depth direction. In addition, a pair of side surfaces 241 and 242 of the gate electrode 24G are buried in the semiconductor substrate 11. This makes it possible to increase the size D of the channel region 24C in the depth direction ( Figure 4A ).

[0142] Therefore, even when there are trap levels in the gate insulating film 24I, carriers flowing in the channel region 24C of the magnifying transistor 24 are hardly captured by these trap levels. Therefore, the generation of noise caused by fluctuations in the current flowing in the channel region 24C is suppressed.

[0143] In addition, noise is suppressed without increasing the occupied area of the magnifying transistor 24. This makes it possible to maintain the occupied area of the photodiode 21. Therefore, for example, the influence on the sensitivity and the cumulative saturation amount of the signal charge is also suppressed.

[0144] As described above, in the imaging element 10 of the present embodiment, the magnifying transistor 24 includes a channel region 24C having the same conductivity type (n-type) as the source-drain regions 24A and 24B. This makes it possible to reduce the noise caused by carriers captured at the interface on the gate electrode 24G side of the channel region 24C. Therefore, noise can be suppressed.

[0145] In addition, in the imaging element 10, a pair of side surfaces 241 and 242 of the gate electrode 24G are embedded in the semiconductor substrate 11. This makes it easy to increase the size D of the channel region 24C in the depth direction. Therefore, the generation of noise can be suppressed more effectively.

[0146] In the imaging element 10, noise can be suppressed and a high SN ratio can be achieved. Therefore, for example, even in night-time shooting, a clear image can be obtained.

[0147] Hereinafter, modifications of the foregoing first embodiment and other embodiments will be described. However, in the following description, components that are the same as those of the foregoing first embodiment are denoted by the same reference numerals, and their descriptions are appropriately omitted.

[0148] <Modification 1>

[0149] Figure 8 FIG. shows a schematic cross-sectional configuration of a main part of the imaging element 10 ( Figure 1 ) according to Modification 1 of the foregoing first embodiment. Figure 8 Corresponding to the cross-sectional configuration along the Figure 3 B-B' line in. The imaging element 10 includes an amplifying transistor 24 having a Fin FET structure. In other respects, the imaging element 10 according to Modification 1 has a configuration similar to that of the imaging element 10 of the foregoing first embodiment, and also has similar functions and effects.

[0150] The amplifying transistor 24 having a Fin FET structure includes a fin F in which a channel region 24C is provided, a gate electrode 24G provided around the fin F, and a gate insulating film 24I provided between the gate electrode 24G and the fin F.

[0151] For example, the fin F is made of silicon (Si) or the like into which an n-type impurity is diffused. The fin F is provided on the surface S11B of the semiconductor substrate 11 substantially perpendicular to the surface S11B. That is, the amplifying transistor 24 having a Fin FET structure includes an n-type channel region 24C outside the semiconductor substrate 11 in which the photodiode 21 is provided. This makes it possible to increase the occupied area of the amplifying transistor 24 while suppressing the influence on the occupied area of the photodiode 21. For example, the impurity concentration of the channel region 24C is about 5×10 17 cm -3 ~1×10 19 cm -3 . The fin F extends in the channel length direction ( Figure 8 Y direction in). The fin F is provided with source-drain regions 24A and 24B adjacent to the channel region 24C ( Figure 4A)。The source-drain regions 24A and 24B have the same conductivity type (n-type) as the channel region 24C.

[0152] The gate electrode 24G is provided on the surface S11B of the semiconductor substrate 11 together with the fin F. The gate electrode 24G includes a pair of side surfaces 241 and 242 facing the fin F therebetween, and an upper surface 243 connecting the pair of side surfaces 241 and 242. The upper surface 243 faces the surface S11B of the semiconductor substrate 11 via the fin F. For example, the gate electrode 24G is made of p-type polysilicon or the like. The gate insulating film 24I is provided between the fin F and each of the pair of side surfaces 241 and 242 and the upper surface 234. For example, the gate insulating film 24I is made of silicon oxide (SiO) or the like.

[0153] Also in the imaging element 10 according to this modification, as described in the first embodiment above, the amplifying transistor 24 includes a channel region 24C having the same conductivity type (n-type) as the source-drain regions 24A and 24B. Therefore, noise caused by carriers trapped at the interface on the gate electrode 24G side of the channel region 24C can be reduced. In addition, the channel region 24C (fin F) is provided outside the semiconductor substrate 11 in which the photodiode 21 is provided. This makes it possible to increase the occupied area of the amplifying transistor 24. Therefore, noise can be suppressed more effectively.

[0154] <Modification 2>

[0155] Fig. 9 A schematic cross-sectional configuration of the main part of the imaging element 10 ( Figure 1 ) according to Modification 2 of the first embodiment described above is shown. Fig. 9 Corresponding to the cross-sectional configuration along the Figure 3 B-B' line in. The imaging element 10 includes an amplifying transistor 24 having a GAA structure. In other respects, the imaging element 10 according to Modification 2 has a configuration similar to that of the imaging element 10 of the first embodiment described above, and also has similar functions and effects.

[0156] The amplifying transistor 24 having a GAA structure includes a semiconductor portion 24N in which the channel region 24C is provided, a gate electrode 24G surrounding the semiconductor portion 24N, and a gate insulating film 24I provided between the gate electrode 24G and the semiconductor portion 24N.

[0157] For example, the semiconductor portion 24N is made of silicon (Si) or the like into which an n-type impurity is diffused. For example, the semiconductor portion 24N may be made of nanowires. The semiconductor portion 24N is provided on the surface S11B of the semiconductor substrate 11, and in the channel length direction ( Fig. 9extends in the Y direction. In the region surrounded by the gate electrode 24G of the semiconductor portion 24N, an n-type channel region 24C is provided. In the region adjacent to the channel region 24C, n-type source-drain regions 24A and 24B are provided ( Figure 4A ).

[0158] The gate electrode 24G is provided on the surface S11B of the semiconductor substrate 11 together with the semiconductor portion 24N. The gate electrode 24G includes a pair of side surfaces 241 and 242 substantially perpendicular to the semiconductor substrate 11 (surface S11B), and upper surfaces 243 and lower surfaces 244 substantially parallel to the semiconductor substrate 11 (surface S11B). The pair of side surfaces 241 and 242 face each other via the semiconductor portion 24N. The upper surfaces 243 and the lower surfaces 244 connect the pair of side surfaces 241 and 242 and face each other via nanowires. The lower surface 244 of the upper surfaces 243 and the lower surfaces 244 is provided at a position closer to the semiconductor substrate 11. For example, the gate electrode 24G is made of p-type polysilicon or the like.

[0159] Also in the imaging element 10 according to this modification, as described in the foregoing first embodiment, the amplifying transistor 24 includes a channel region 24C having the same conductivity type (n-type) as the source-drain regions 24A and 24B. Therefore, noise caused by carriers trapped at the interface on the gate electrode 24G side of the channel region 24C can be reduced. In addition, the channel region 24C (semiconductor portion 24N) is provided outside the semiconductor substrate 11 in which the photodiode 21 is provided. This makes it possible to increase the occupied area of the amplifying transistor 24. Therefore, noise can be suppressed more effectively.

[0160] <Modification 3>

[0161] Fig.10 Shows an example of the configuration of the equivalent circuit of the imaging element 10 ( Figure 1 ) according to Modification 3 of the foregoing first embodiment. In this imaging element 10, the amplifying transistor 24 and the like are shared by a plurality of pixels P. In other respects, the imaging element 10 according to Modification 3 has a configuration similar to that of the imaging element 10 of the foregoing first embodiment, and also has similar functions and effects.

[0162] In the imaging element 10, for example, the FD section 26, the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 are shared by four pixels P.

[0163] Fig.11 Shows a schematic planar configuration of four pixels P and the FD section 26, the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 shared by the four pixels P. Using Fig.11 And Fig.10The configuration of the imaging element 10 of this modification will be described together.

[0164] A photodiode (any one of photodiodes 21-1, 21-2, 21-3, and 21-4) is provided in a corresponding one of the four pixels P. The photodiode 21-1 is connected to the transfer transistor 22-1. The photodiode 21-2 is connected to the transfer transistor 22-2. The photodiode 21-3 is connected to the transfer transistor 22-3. The photodiode 21-4 is connected to the transfer transistor 22-4. That is, in a single pixel P, a single photodiode (any one of photodiodes 21-1, 21-2, 21-3, and 21-4) and a single transfer transistor (any one of transfer transistors 22-1, 22-2, 22-3, and 22-4) are arranged. The gate electrodes of the transfer transistors 22-1, 22-2, 22-3, and 22-4 are configured to be supplied with transfer pulses φTRF1, φTRF2, φTRF3, and φTRF4 via transfer lines 17a-1, 17a-2, 17a-3, and 17a-4 respectively ( Fig.10 ).

[0165] The FD section 26 is provided in the central portion of the four pixels P ( Fig.11 ). The signal charges photoelectrically converted in each of the photodiodes 21-1, 21-2, 21-3, and 21-4 are transferred to the FD section 26 via the transfer transistors 22-1, 22-2, 22-3, and 22-4.

[0166] For example, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 are arranged side by side along the ends of the four pixels P sharing the transistor (for example, along the Fig.11 ends in the X direction). For example, the configuration of the amplification transistor 24 is similar to the configuration described in the aforementioned first embodiment (see Figure 4A and Figure 4B ). Alternatively, the configuration of the amplification transistor 24 may be similar to the configuration described in Modification 1 ( Figure 8 ) or Modification 2 ( Fig. 9 ).

[0167] Also in the imaging element 10 according to this modification, as described in the aforementioned first embodiment, the amplification transistor 24 includes a channel region 24C having the same conductivity type (n-type) as the source-drain regions 24A and 24B. Therefore, noise caused by carriers trapped at the interface on the gate electrode 24G side of the channel region 24C can be reduced.

[0168] <Second Embodiment>

[0169] Fig.12Shows a schematic configuration of a solid-state imaging device (imaging device 10A) according to a second embodiment of the present disclosure. The imaging device 10A includes a stacked structure of a first substrate 11A, a second substrate 30, and a third substrate 40. On the first substrate 11A, a photodiode 21 and the like are provided. On the second substrate 30, a readout circuit 20 (specifically, an amplification transistor 24 and a selector transistor 25) is provided. On the third substrate 40, a logic circuit (drive circuit) is provided. In other aspects, the imaging device 10A of the second embodiment has a similar configuration to the imaging device 10 of the foregoing first embodiment, and also has similar functions and effects. Here, specific examples of the output transistors of the present disclosure are the amplification transistor 24 and the selection transistor 25.

[0170] In the imaging device 10A, the first substrate 11A, the second substrate 30, and the third substrate 40 are stacked in sequence. The imaging device 10A is configured to allow light to enter from the side where the first substrate 11A is arranged. That is, the imaging device 10A is a back-illuminated type imaging device.

[0171] The first substrate 11A includes a plurality of pixels P that perform photoelectric conversion on a semiconductor substrate 11. The second substrate 30 includes, for example, a readout circuit 20 provided for every four pixels P respectively on a semiconductor layer 30S. The second substrate 30 includes pixel drive lines 17 and vertical signal lines 18. The third substrate 40 includes a logic circuit LC that processes pixel signals in a semiconductor layer 40S. For example, the logic circuit LC includes a vertical drive circuit 13, a signal processing circuit 14, a horizontal drive circuit 15, and a system control circuit 16. The logic circuit LC (specifically, the horizontal drive circuit 15) outputs the output voltage Vout of each pixel P to the outside. In the logic circuit LC, for example, a low-resistance region formed of a silicide such as CoSi 2 or NiSi can be formed on the front surface of the impurity diffusion region in contact with the source and drain. The silicide is formed using a self-aligned silicide (salicide) process.

[0172] Fig.13 Shows an example of the pixel P and the readout circuit 20. Hereinafter, as Fig.13 shown, the case where a single readout circuit 20 is shared by four pixels P is described. Here, "shared" means that the outputs of the four pixels P are input to the common readout circuit 20.

[0173] The pixels P each include common constituent elements. In Fig.13In this case, in order to distinguish the constituent elements of each pixel P from each other, identification numbers (1, 2, 3, and 4) are appended to the end of the reference numerals of the constituent elements of each pixel P. Hereinafter, in cases where it is necessary to distinguish the constituent elements of each pixel P from each other, identification numbers are appended to the end of the reference numerals of the constituent elements of each pixel P, but in cases where it is not necessary to distinguish the constituent elements of each pixel P from each other, the identification numbers at the end of the reference numerals of the constituent elements of each pixel P are omitted.

[0174] For example, each pixel P includes a photodiode 21, a transfer transistor 22, and an FD section 26. The transfer transistor 22 is electrically connected to the photodiode 21. The FD section 26 temporarily holds the charge output from the photodiode 21 via the transfer transistor 22. The photodiode 21 performs photoelectric conversion to generate a charge corresponding to the amount of received light. The cathode of the photodiode 21 is electrically connected to the source of the transfer transistor 22, and the anode of the photodiode 21 is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor 22 is electrically connected to the FD section 26, and the gate of the transfer transistor 22 is electrically connected to the pixel drive line 17. For example, the transfer transistor 22 is a complementary metal oxide semiconductor (CMOS) transistor.

[0175] The FD sections 26 of the respective pixels P sharing a single readout circuit 20 are electrically connected to each other and are electrically connected to the input terminal of the common readout circuit 20. For example, the readout circuit 20 includes a reset transistor 23, a selection transistor 25, and an amplification transistor 24. It should be noted that the selection transistor 25 can be omitted if necessary. The source of the reset transistor 23 (the input terminal of the readout circuit 20) is electrically connected to the FD section 26, and the drain of the reset transistor 23 is electrically connected to the power supply line VDD and the drain of the amplification transistor 24. The gate of the reset transistor 23 is electrically connected to the pixel drive line 17 (see Fig.12 ). The source of the amplification transistor 24 is electrically connected to the drain of the selection transistor 25, and the gate of the amplification transistor 24 is electrically connected to the source of the reset transistor 23. The source of the selection transistor 25 (the output terminal of the readout circuit 20) is electrically connected to the vertical signal line 18, and the gate of the selection transistor 25 is electrically connected to the pixel drive line 17 (see Fig.12 ).

[0176] When the transfer transistor 22 is turned on, the transfer transistor 22 transfers the charge of the photodiode 21 to the FD section 26. The reset transistor 23 resets the potential of the FD section 26 to a predetermined potential. When the reset transistor 23 is turned on, the potential of the FD section 26 is reset to the potential of the power supply line VDD. The selection transistor 25 controls the output timing of the pixel signal from the readout circuit 20. The amplification transistor 24 generates a signal of a voltage corresponding to the level of the charge held in the FD section 26 as a pixel signal. The amplification transistor 24 constitutes a source follower amplifier and outputs a pixel signal of a voltage corresponding to the level of the charge generated by the photodiode 21. When the selection transistor 25 is turned on, the amplification transistor 24 amplifies the potential of the FD section 26 and outputs a voltage corresponding to the relevant potential to the signal processing circuit 14 via the vertical signal line 18. For example, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 are CMOS transistors.

[0177] It should be noted that, as Fig.14 shown, the selection transistor 25 can be provided between the power supply line VDD and the amplification transistor 24. In this case, the drain of the reset transistor 23 is electrically connected to the power supply line VDD and the drain of the selection transistor 25. The source of the selection transistor 25 is electrically connected to the drain of the amplification transistor 24, and the gate of the selection transistor 25 is electrically connected to the pixel drive line 17 (see Fig.12 ). The source (output terminal of the readout circuit 20) of the amplification transistor 24 is electrically connected to the vertical signal line 18, and the gate of the amplification transistor 24 is electrically connected to the source of the reset transistor 23. In addition, as Fig.15 and Fig.16 shown, the FD transfer transistor 27 can be provided between the source of the reset transistor 23 and the gate of the amplification transistor 24.

[0178] The FD transfer transistor 27 is used to switch the conversion efficiency. Usually, the pixel signal is small when shooting in the dark. In the case of performing the conversion from charge to voltage based on Q = CV, when converted to voltage by the amplification transistor 24, the large capacitance (FD capacitance C) of the FD section 26 makes V small. On the contrary, in a bright place, the pixel signal becomes large, so in the case where the FD capacitance C is not large, the FD section 26 cannot receive the charge of the photodiode 21. In addition, in order to prevent V from becoming too large (in other words, making V small) when converted to voltage by the amplification transistor 24, the FD capacitance C needs to become large. Considering these, when the FD transfer transistor 27 is turned on, the gate capacitance of the FD transfer transistor 27 increases, resulting in an increase in the entire FD capacitance C. On the contrary, when the FD transfer transistor 27 is turned off, the entire FD capacitance C becomes small. Therefore, turning on and off the FD transfer transistor 27 can make the FD capacitance C variable and switch the conversion efficiency.

[0179] Fig.17 An example of the connection pattern between a plurality of readout circuits 20 and a plurality of vertical signal lines 18 is shown. When the plurality of readout circuits 20 are arranged side by side in the extending direction of the vertical signal lines 18 (e.g., the column direction), the plurality of vertical signal lines 18 can be assigned to each readout circuit 20 one by one. For example, as Fig.17 shown, when four readout circuits 20 are arranged side by side in the extending direction of the vertical signal lines 18 (e.g., the column direction), the four vertical signal lines 18 can be assigned to each readout circuit 20 one by one. It should be noted that in Fig.17 , in order to distinguish each vertical signal line 18, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of each vertical signal line 18.

[0180] Fig.18 An example of the cross-sectional structure of the imaging element 10A in the vertical direction is shown. The first substrate 11A includes a semiconductor substrate 11 and an interlayer insulating film 19 on the semiconductor substrate 11. The second substrate 30 is disposed opposite to the first substrate 11A, and includes a semiconductor layer 30S, an interlayer insulating film 30I, and a multilayer wiring layer 30W in order from the side where the first substrate 11A (interlayer insulating film 19) is disposed. The third substrate 40 includes a multilayer wiring layer 40W, an interlayer insulating film 40I, and a semiconductor layer 40S in order from the side where the second substrate 30 (multilayer wiring layer 30W) is disposed. The bonding surface S is provided between the multilayer wiring layer 30W of the second substrate 30 and the multilayer wiring layer 40W of the third substrate 40.

[0181] For example, in the semiconductor substrate 11, a photodiode 21 and an FD section 26 are provided. The FD section 26 is provided near the inner surface S11B of the semiconductor substrate 11. For example, the FD section 26 includes an impurity diffusion region in which an n-type impurity is diffused in a p-type well region 111. For example, the concentration of the n-type impurity in the FD section 26 is about 1×10 19 cm -3 ~1×10 20 cm -3 . The surface S11A of the semiconductor substrate 11 serves as a light incident surface.

[0182] The transfer transistor 22 is provided near the surface S11B of the semiconductor substrate 11 together with the FD section 26. For example, the transfer transistor 22 includes a gate electrode 22G and a gate insulating film 22I. The gate electrode 22G is provided outside the semiconductor substrate 11 so as to face the semiconductor substrate 11. For example, the gate electrode 22G is made of p-type polysilicon or the like. The gate electrode 22G may be made of metals such as tungsten (W), titanium (Ti), titanium nitride (TiN), hafnium (Hf), hafnium silicide (HfSi), ruthenium (Ru), iridium (Ir), and cobalt (Co). The gate insulating film 22I is provided between the gate electrode 22G and the semiconductor substrate 11. For example, the gate insulating film 22I is made of a silicon oxide film (SiO) or the like. The gate insulating film 22I may be made of high-k insulating materials such as hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), tantalum oxide (Ta 2 O 5 ), and hafnium aluminate (HfAlO). The gate electrode 22G and the gate insulating film 22I are covered with an interlayer insulating film 19. For example, the interlayer insulating film 19 is made of silicon oxide (SiO) or the like.

[0183] For example, the first substrate 11A may further include a fixed charge film in contact with the surface S11A of the semiconductor substrate 11. The fixed charge film is negatively charged to suppress the generation of dark current caused by the interface level on the light-receiving surface side of the semiconductor substrate 11. For example, the fixed charge film is made of an insulating film containing negative fixed charges. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide. A hole accumulation layer is formed at the interface on the light-receiving surface side of the semiconductor substrate 11 by the electric field induced by the fixed charge film. This hole accumulation layer suppresses the generation of electrons from the interface. For example, the imaging element 10A includes a color filter (e.g., Fig.30 the color filter 55 in Fig.30 ) and a light-receiving lens (e.g.,

[0184] the light-receiving lens 60 in Fig.12 ) on the light incident side of the first substrate 11A. The color filter is provided on the surface S11A side of the semiconductor substrate 11. For example, the color filter is provided in contact with the fixed charge film and is provided at a position facing the pixel P via the fixed charge film. For example, the light-receiving lens is provided in contact with the color filter and is provided at a position facing the pixel P via the color filter and the fixed charge film.

[0185] A pair of source-drain regions 24A and 24B of the amplifying transistor 24 are n-type impurity diffusion regions provided in the semiconductor layer 30S, and are provided, for example, on a part of the semiconductor layer 30S in the thickness direction ( Fig.18 in the Z direction) from the interlayer insulating film 30I side of the semiconductor layer 30S. The channel region 24C is provided between the pair of source-drain regions 24A and 24B. As described in the first embodiment above, the channel region 24C of the amplifying transistor 24 has the same conductivity type (n-type) as the source-drain regions 24A and 24B. For example, the channel region 24C is provided in the entire thickness direction of the semiconductor layer 30S.

[0186] For example, the selection transistor 25 is arranged at a position adjacent to the amplifying transistor 24 in the channel length direction ( Fig.18 in the Y direction). One of the pair of source-drain regions 25A and 25B of the selection transistor 25 (source-drain region 25B) is adjacent to one of the pair of source-drain regions 24A and 24B of the amplifying transistor 24 (source-drain region 24A), and these can be shared. The pair of source-drain regions 25A and 25B of the selection transistor 25 are n-type impurity diffusion regions provided in the semiconductor layer 30S, and are provided, for example, on a part of the semiconductor layer 30S in the thickness direction from the interlayer insulating film 30I side. The channel region 25C is provided between the pair of source-drain regions 25A and 25B. For example, the channel region 25C of the selection transistor 25 has the same conductivity type (n-type) as the source-drain regions 25A and 25B. For example, the channel region 25C is provided in the entire thickness direction of the semiconductor layer 30S.

[0187] In the stacked imaging element 10A, the channel regions 24C and 25C of the amplifying transistor 24 and the selection transistor 25 are provided in a semiconductor layer 30S different from the semiconductor substrate 11 in which the photodiode 21 and the FD section 26 are provided. This makes it possible to increase the occupied area of the amplifying transistor 24 and the selection transistor 25, thereby making it possible to more effectively suppress the generation of noise. In addition, the amplifying transistor 24 and the selection transistor 25 are manufactured separately from the photodiode 21 and the like. This makes it easier to optimize the temperature when manufacturing the amplifying transistor 24 and the selection transistor 25. Therefore, in terms of the manufacturing process, the generation of noise can also be effectively suppressed.

[0188] As long as at least one of the channel region 24C of the amplifying transistor 24 and the channel region 25C of the selection transistor 25 has the same conductivity type as the source-drain regions 24A, 24B, 25A, and 25B. For example, the channel region 25C of the selection transistor 25 can be a p-type impurity diffusion region.

[0189] In the semiconductor layer 30S, an element isolation region 112 is provided. The element isolation region 112 is provided around the channel regions 24C and 25C and a pair of source-drain regions 24A, 24B, 25A, and 25B. Accordingly, a plurality of transistors are electrically isolated.

[0190] In addition to the channel region 24C and a pair of source-drain regions 24A and 24B, the amplifying transistor 24 further includes a gate electrode 24G and a gate insulating film 24I. In addition to the channel region 25C and source-drain regions 25A and 25B, the selecting transistor 25 further includes a gate electrode 25G and a gate insulating film 25I.

[0191] For example, the amplifying transistor 24 and the selecting transistor 25 are planar transistors. The gate electrodes 24G and 25G are provided outside the semiconductor layer 30S and are each constituted by a single plane opposed to each of the channel regions 24C and 25C. That is, both the gate electrodes 24G and 25G have a flat plate shape. For example, in the case where the semiconductor layer 30S is formed using an SOI substrate (the SOI substrate 50 described below Fig.21B ), etc. and the thickness of the semiconductor layer 30S is small, it is easy to constitute a planar junctionless transistor. For example, the gate electrodes 24G and 25G are made of p-type polysilicon or the like. The gate electrodes 24G and 25G may be made of metals such as tungsten (W), titanium (Ti), titanium nitride (TiN), hafnium (Hf), hafnium silicide (HfSi), ruthenium (Ru), iridium (Ir), and cobalt (Co).

[0192] The gate insulating films 24I and 25I are respectively provided between the gate electrodes 24G and 25G and the semiconductor layer 30S. For example, the gate insulating films 24I and 25I are each constituted by a silicon oxide film (SiO), etc. The gate insulating films 24I and 25I may be made of high-k dielectric insulating materials such as hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), tantalum oxide (Ta 2 O 5 ), and hafnium aluminate (HfAlO).

[0193] The gate electrodes 24G and 25G and the gate insulating films 24I and 25I are covered with an interlayer insulating film 30I. For example, the interlayer insulating film 30I is constituted by silicon oxide (SiO), etc. The interlayer insulating film 30I is provided with a connection hole reaching the gate electrode 24G of the amplifying transistor 24 and a connection hole penetrating the interlayer insulating film 30I, the semiconductor layer 30S, and the interlayer insulating film 19 to reach the FD portion 26. An electrode 24E is provided in the connection hole reaching the gate electrode 24G. An electrode 26E is provided in the connection hole reaching the FD portion 26.

[0194] The multilayer wiring layer 30W faces the semiconductor layer 30S via the interlayer insulating film 30I. The multilayer wiring layer 30W includes a plurality of wirings 31, an interlayer insulating film 32, and contact electrodes 33. For example, the wiring 31 is made of a metal material such as copper (Cu) or aluminum (Al). The electrode 24E and the electrode 26E are connected to each other via the wiring 31. That is, the gate electrode 24G of the amplification transistor 24 is connected to the FD section 26 via the wiring 31. For example, the wiring 31 is electrically connected to the reset transistor 23 ( Figure 2 ). The interlayer insulating film 32 is provided between the plurality of wirings 31 for separation and is made of, for example, silicon oxide (SiO). For example, the contact electrode 33 is provided between the wiring 31 of the multilayer wiring layer 30W and the multilayer wiring layer 40W (specifically, the contact electrode 43 described below) for electrical connection. For example, the contact electrode 33 is made of copper (Cu), and one surface is exposed from the bonding surface S.

[0195] For example, in the semiconductor layer 40S of the third substrate 40, a channel region 40SC of a plurality of transistors Tr and a pair of source-drain regions 40SA and 40SB are provided. For example, a plurality of transistors Tr form a logic circuit. Signal charges are output from the photodiode 21 to the logic circuit via the amplification transistor 24 and the selection transistor 25. Therefore, in the imaging element 10A, the logic circuit LC is provided on a different substrate (third substrate 40) from the semiconductor substrate 11 on which the photodiode 21 and the like are provided. The different substrate and the semiconductor substrate 11 are stacked. Therefore, the chip size can be reduced.

[0196] In addition to the channel region 40SC and the pair of source-drain regions 40SA and 40SB, each of the plurality of transistors Tr further includes a gate electrode 40IG and a gate insulating film 40II. For example, the gate electrode 40IG of each of the plurality of transistors Tr is provided outside the semiconductor layer 40S and includes a single plane facing the channel region 40SC, respectively. The gate insulating film 40II is provided between the gate electrode 40IG and the semiconductor layer 40S. The gate electrode 40IG and the gate insulating film 40II are covered with the interlayer insulating film 40I.

[0197] The multilayer wiring layer 40W of the third substrate 40 faces the semiconductor layer 40S via the interlayer insulating film 40I. A bonding surface S is formed between the multilayer wiring layer 40W and the multilayer wiring layer 30W of the second substrate 30. For example, the multilayer wiring layer 40W includes a plurality of wirings 41, an interlayer insulating film 42, and a contact electrode 43. For example, the wiring 41 is made of a metal material such as copper (Cu) or aluminum (Al). The interlayer insulating film 42 is provided between the plurality of wirings 41 for separation and is made of, for example, silicon oxide (SiO). For example, the contact electrode 43 is provided between the wiring 41 of the multilayer wiring layer 40W and the contact electrode 33 of the multilayer wiring layer 30W for electrical connection. For example, the contact electrode 43 is made of copper (Cu), and one surface is exposed from the bonding surface S and contacts the contact electrode 33. That is, the third substrate 40 and the second substrate 30 are connected by Cu-Cu bonding.

[0198] Similarly, in the imaging element 10A of the second embodiment, as described in the foregoing first embodiment, the amplifying transistor 24 includes a channel region 24C having the same conductivity type (n-type) as the source-drain regions 24A and 24B. Therefore, noise caused by carriers trapped at the interface on the gate electrode 24G side of the channel region 24C can be reduced. In addition, the selection transistor 25 also includes a channel region 25C having the same conductivity type (n-type) as the source-drain regions 25A and 25B. Therefore, noise caused by carriers trapped at the interface on the gate electrode 25G side of the channel region 25C can be reduced.

[0199] In addition, the imaging element 10A has a stacked structure of the first substrate 11A, the second substrate 30, and the third substrate 40. Therefore, the amplifying transistor 24 and the selection transistor 25 are formed on a substrate (second substrate 30) different from the first substrate 11A on which the photodiode 21 and the FD section 26 are provided. Therefore, the occupied area of the amplifying transistor 24 and the selection transistor 25 can be increased, and thus noise can be more effectively suppressed. In addition, in terms of the manufacturing process, the manufacturing temperature of the amplifying transistor 24 and the selection transistor 25 can also be optimized, thereby suppressing the generation of noise.

[0200] In addition, the third substrate 40 including the logic circuit LC is stacked on the first substrate 11A on which the photodiode 21 and the like are provided. Therefore, the chip size can be reduced.

[0201] <Modification 4>

[0202] Fig.19 、 Fig. 20A and Fig. 20B shows a schematic configuration of the main part of the imaging element 10A ( Fig.18 ) according to a modification (Modification 4) of the foregoing second embodiment. Fig.19Shows the planar configuration of the reset transistor 23, the amplification transistor 24, and the selection transistor 25. Fig. 20A and Fig. 20B respectively show the cross-sectional configuration along Fig.19 the A-A' line shown, and the cross-sectional configuration along Fig.19 the B-B' line shown. The reset transistor 23, the amplification transistor 24, and the selection transistor 25 of the imaging element 10A have a Fin FET structure. In other respects, the imaging element 10A of the modification 4 has a configuration similar to that of the imaging element 10A of the aforementioned second embodiment, and also has similar functions and effects.

[0203] The reset transistor 23 having a Fin FET structure includes a fin F1 in which a channel region 23C is provided, a gate electrode 23G provided around the fin F1, and a gate insulating film 23I provided between the gate electrode 23G and the fin F1 ( Fig.19 and Fig. 20A ). The amplification transistor 24 having a Fin FET structure includes fins F2 and F3 in which a channel region 24C is provided, a gate electrode 24G provided around the fins F2 and F3, and a gate insulating film 24I provided between the gate electrode 24G and the fins F2 and F3 ( Fig.19 and Fig. 20A ). The selection transistor 25 having a Fin FET structure includes fins F2 and F3 in which a channel region 25C is provided, a gate electrode 25G provided around the fins F2 and F3, and a gate insulating film 25I provided between the gate electrode 25G and the fins F2 and F3 ( Fig.19 and Fig. 20B ).

[0204] For example, the fins F1, F2, and F3 are made of silicon (Si) or the like into which an n-type impurity is diffused. For example, the fins F1, F2, and F3 are made of silicon having an impurity concentration of n-type impurity of about 1×10 17 cm -3 ~1×10 19 cm -3 . The fins F1, F2, and F3 are provided on the interlayer insulating film 19 substantially perpendicular to the surface S11B of the semiconductor substrate 11. The fins F1, F2, and F3 constitute the semiconductor layer 30S of the second substrate 30. For example, the fins F1, F2, and F3 extend parallel to each other. The fins F1, F2, and F3 are separated from each other by the element isolation region 112. The fins F2 and F3 are connected to each other at both ends.

[0205] In the fin F1, source-drain regions 23A and 23B adjacent to the channel region 23C are provided. In the fins F2 and F3, source-drain regions 24A and 25B adjacent to the channel region 24C and source-drain regions 25A and 25B adjacent to the channel region 25C are provided. That is, the reset transistor 23 includes n-type source-drain regions 23A and 23B and a channel region 23C having the same conductivity type (n-type) as that of the source-drain regions 23A and 23B in the fin F1 outside the semiconductor substrate 11. The amplification transistor 24 includes n-type source-drain regions 24A and 24B and a channel region 24C having the same conductivity type (n-type) as that of the source-drain regions 24A and 24B in the fins F2 and F3. For example, the selection transistor 25 includes n-type source-drain regions 25A and 25B and a channel region 25C having the same conductivity type (n-type) as that of the source-drain regions 25A and 25B in the same fins F2 and F3 as the amplification transistor 24. In other words, in the fins F2 and F3, a plurality of channel regions 24C and 25C and source-drain regions 24A, 24B, 25A, and 25B are continuously provided.

[0206] At one end of the fins F2 and F3, a contact portion FC1 is provided. At the other end of the fins F2 and F3, a contact portion FC2 is provided. The contact portion FC1 is a portion that connects one of the pair of source-drain regions 24A and 24B (source-drain region 24B) of the amplification transistor 24 to the pixel power supply Vdd. The contact portion FC2 is a portion that connects one of the pair of source-drain regions 25A and 25B (source-drain region 25A) of the selection transistor 25 to the vertical signal line 18 ( Figure 2 ).

[0207] The gate electrode 23G is provided on the interlayer insulating film 19 together with the fin F1. The gate electrode 23G includes a pair of side surfaces 231 and 232 facing each other via the fin F1 and an upper surface 233 connecting the pair of side surfaces 231 and 232. The upper surface 233 faces the interlayer insulating film 19 via the fin F1. The upper surface 233 is covered with the interlayer insulating film 30I. The gate insulating film 23I is provided between the fin F1 and each of the pair of side surfaces 231 and 232 and the upper surface 233.

[0208] The gate electrode 24G is disposed on the interlayer insulating film 19 together with the fins F2 and F3. The gate electrode 24G includes a pair of side surfaces 241 and 242 that face each other via the fins F2 and F3, an upper surface 243 that connects the pair of side surfaces 241 and 242, and a partition surface 245 between the fins F2 and F3. The pair of side surfaces 241 and 242 and the partition surface 245 are disposed parallel to each other. The upper surface 243 faces the interlayer insulating film 19 via the fins F2 and F3. The upper surface 243 is covered with the interlayer insulating film 30I. The gate insulating film 24I is disposed between each of the fins F2 and F3 and the pair of side surfaces 241 and 242, the upper surface 243, and the partition surface 245.

[0209] The gate electrode 25G is disposed on the interlayer insulating film 19 together with the fins F2 and F3. The gate electrode 25G includes a pair of side surfaces 251 and 252 that face each other via the fins F2 and F3, an upper surface 253 that connects the pair of side surfaces 251 and 252, and a partition surface 255 between the fins F2 and F3. The pair of side surfaces 251 and 252 and the partition surface 255 are disposed parallel to each other. The upper surface 253 faces the interlayer insulating film 19 via the fins F2 and F3. The upper surface 253 is covered with the interlayer insulating film 30I. The gate insulating film 25I is disposed between each of the fins F2 and F3 and the pair of side surfaces 251 and 252, the upper surface 253, and the partition surface 255.

[0210] For example, the gate electrodes 23G, 24G, and 25G as described above are made of p-type polysilicon or the like. For example, the gate insulating films 23I, 24I, and 25I are made of silicon oxide (SiO) or the like.

[0211] The interlayer insulating film 30I faces the interlayer insulating film 19 via the fins F1, F2, and F3. The interlayer insulating film 30I is provided with connection holes that reach the upper surfaces 243 and 253 of the gate electrodes 24G and 25G and a connection hole that reaches the fin F1. The connection hole that reaches the upper surface 243 is provided with the electrode 24E. The connection hole that reaches the upper surface 253 is provided with the electrode 25E. The connection hole that reaches the fin F1 is provided with the electrode 23E.

[0212] For example, as described above, the imaging element 10A including the reset transistor 23, the amplification transistor 24, and the selection transistor 25 can be manufactured as follows ( Figure 21A to Figure 22H ). Although Figure 21A to Figure 22H the reset transistor 23 is shown, the amplification transistor 24 and the selection transistor 25 can also be manufactured similarly.

[0213] First, as Fig.21A shown, the first substrate 11A is formed. For example, the first substrate 11A is formed as follows.

[0214] First, a p-type impurity is prepared at about 1×10 16 cm-3 ~1×10 18 cm -3 The semiconductor substrate 11 with impurity concentration diffusion of -3 ~1×10 18 cm -3 . A semiconductor substrate 11 with a lower p-type impurity concentration can be used, or alternatively, a semiconductor substrate 11 into which n-type impurities are diffused can be used. Next, thermal oxidation is performed to form a silicon oxide film with a thickness of about 3 nm to 10 nm on the surface S11B of the semiconductor substrate 11. Subsequently, for example, a polysilicon film is formed on this silicon oxide film. After that, the polysilicon film and the silicon oxide film are formed into a predetermined shape by photolithography and etching. Thus, the gate electrode 22G and the gate insulating film 22I of the transfer transistor 22 are formed.

[0215] After forming the gate electrode 22G and the gate insulating film 22I, a photodiode 21 is formed inside the semiconductor substrate 11. For example, the photodiode 21 is formed by a p-type impurity region 21a having a size of about 30 nm to 200 nm in the depth direction and an n-type impurity region 21b having a size of about 1 μm to 5 μm in the depth direction. For example, the impurity concentration of the p-type impurity region 21a is about 1×10 18 cm -3 ~1×10 19 cm -3 , and the impurity concentration of the n-type impurity region 21b is about 1×10 15 cm -3 ~1×10 18 cm -3 .

[0216] After forming the photodiode 21, an FD portion 26 is formed inside the semiconductor substrate 11. For example, the FD portion 26 is formed by an n-type impurity diffusion region. For example, the concentration of the FD portion 26 is about 1×10 19 cm -3 ~1×10 20 cm -3 . After forming the FD portion 26, for example, oxidation annealing is performed at about 1000 °C to 1100 °C for 1 second to 10 seconds. Thereafter, an insulating film such as silicon oxide is formed on the semiconductor substrate 11 to cover the gate electrode 22G and the gate insulating film 22I of the transfer transistor 22. The insulating film is subjected to a planarization process such as CMP (chemical mechanical polishing) to form an interlayer insulating film 19. Thus, the first substrate 11A is formed.

[0217] After forming the first substrate 11A, as Fig.21BAs shown, the SOI substrate 50 is bonded to the first substrate 11A. For example, the SOI substrate 50 sequentially includes a first oxide film 52, a semiconductor layer 53F, and a second oxide film 54 on a substrate 51. For example, the substrate 51 is made of a silicon (Si) substrate. For example, the first oxide film 52 and the second oxide film 54 are each made of a silicon oxide (SiO) film. For example, the semiconductor layer 53F is made of a silicon layer into which an n-type impurity is diffused. For example, the concentration of the n-type impurity in the semiconductor layer 53F is about 1×10 17 cm -3 ~1×10 19 cm -3 . The thickness of the semiconductor layer 53F is about 200 nm to 1000 nm. The SOI substrate 50 is bonded to the first substrate 11A such that the second oxide film 54 and the interlayer insulating film 19 are in contact with each other. The bonding surface can be subjected to plasma treatment in advance to increase the bonding strength. The concentration of the n-type impurity in the semiconductor layer 53F can be reduced, or alternatively, a p-type impurity can be diffused into the semiconductor layer 53F. In a subsequent process, an n-type impurity is implanted into the semiconductor layer 53F. Further, instead of the SOI substrate 50, a bulk silicon substrate can be bonded.

[0218] After bonding the SOI substrate 50 to the first substrate 11A, as Fig. 21C shown, the substrate 51 and the first oxide film 52 of the SOI substrate 50 are removed. For example, the removal of the substrate 51 and the first oxide film 52 is performed using CMP or the like. In the case where a bulk silicon substrate is bonded to the first substrate 11A instead of the SOI substrate 50, the silicon substrate is scraped by, for example, CMP or the like to adjust to a desired thickness.

[0219] After removing the substrate 51 and the first oxide film 52, as Fig.22A shown, the semiconductor layer 53F is formed into a desired shape using photolithography and etching to form fins F1 (and F2 and F3). Note that in Figure 22A to Figure 22H , only the layers above the interlayer insulating film 19 are shown.

[0220] After forming the fin F1, as Fig. 22B shown, an element isolation region 112 is formed around the fin F1. For example, the element isolation region 112 is formed as follows. First, an insulating film such as silicon oxide is formed on the interlayer insulating film 19 to cover the fin F1. Thereafter, the insulating film is subjected to a planarization process such as CMP to form the element isolation region 112. Thus, a semiconductor layer 30S including the fin F1 (and fins F2 and F3) and the element isolation region 112 is formed.

[0221] After forming the element isolation region 112, as Fig. 22C As shown, grooves 112M are formed on both sides of fin F1. The grooves 112M penetrate the semiconductor layer 30S and reach the interlayer insulating film 19. The grooves 112M are provided for forming a pair of side surfaces 231 and 232 (as well as side surfaces 241, 242, 251 and 252) of the gate electrode 23G (as well as gate electrodes 24G and 25G). For example, the grooves 112M are formed by etching.

[0222] After the grooves 112M are formed in the semiconductor layer 30S, as Fig.22D shown, a gate insulating film 23I (as well as gate insulating films 24I and 25I) is formed around the fin F1 (as well as fins F2, F3). For example, the gate insulating film 23I is a silicon oxide (SiO) film formed by thermally oxidizing the fin F1, and has a thickness of about 3 nm to 10 nm. The gate insulating film 23I can be formed by a film forming process.

[0223] After the gate insulating film 23I is formed, as Fig.22E shown, the gate electrode 23G (as well as gate electrodes 24G and 25G) is formed. For example, the gate electrode 23G is formed as follows. First, for example, p-type polysilicon is formed on the element isolation region 112 to fill the grooves 112M. Next, a planarization process such as CMP is performed on the polysilicon film. After that, the polysilicon film is formed into a predetermined shape using photolithography and etching. Thus, the gate electrode 23G is formed. After the gate electrode 23G is formed, source-drain regions 23A and 23B (as well as source-drain regions 24A and 24B, 25A and 25B) are formed at positions adjacent to the channel regions 23C (as well as channel regions 24C and 25C). The source-drain regions 23A and 23B are formed by implanting n-type impurities into the fin F1 (as well as fins F2 and F3). After that, for example, activation annealing is performed at about 1000 °C to 1100 °C for 1 second to 10 seconds.

[0224] Subsequently, as Fig.22F shown, an interlayer insulating film 30I is formed on the semiconductor layer 30S. The interlayer insulating film 30I is formed by forming an insulating film to cover the gate electrode 23G, and then performing a planarization process such as CMP on the insulating film.

[0225] After the interlayer insulating film 30I is formed, as Figure 22G shown, the electrode 26E (as well as electrodes 23E, 24E and 25E) is formed. For example, the electrode 26E is formed as follows. First, for example, a connection hole reaching the FD portion 26 is formed by etching. Next, a conductive material such as tungsten (W) is filled in the connection hole. Thus, the electrode 26E is formed.

[0226] After the electrode 26E is formed, as Fig.22H As shown, wiring 31 is formed on the interlayer insulating film 30I. For example, wiring 31 is formed using copper (Cu) or the like.

[0227] Then, a multilayer wiring layer 30W including other wirings 31, an interlayer insulating film 32, and contact electrodes 33 is formed. Thus, the second substrate 30 is formed. Thereafter, the second substrate 30 is bonded to the third substrate 40, for example, by Cu-Cu bonding. In this way, the Fig.19 , Fig. 20A and Fig. 20B shown imaging element 10A is completed.

[0228] Also in the imaging element 10A of this modification, as described in the aforementioned second embodiment, the amplifying transistor 24 includes a channel region 24C having the same conductivity type (n-type) as the source-drain regions 24A and 24B. Therefore, noise caused by carriers trapped at the interface on the gate electrode 24G side of the channel region 24C can be reduced. In addition, the reset transistor 23 and the selection transistor 25 include channel regions 23C and 25C having the same conductivity type (n-type) as the source-drain regions 23A, 23B, 25A, and 25B. Therefore, noise caused by carriers trapped at the interfaces on the gate electrodes 23G and 25G sides of the channel regions 23C and 25C can be reduced.

[0229] In this modification, the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 having a Fin FET structure are described. However, as described in the aforementioned modification 2 ( Fig. 9 ), the reset transistor 23, the amplifying transistor 24, and the selection transistor 25 may have a GAA structure.

[0230] <Modification 5>

[0231] Fig.23 A schematic cross-sectional configuration of the main part of an imaging element 10A ( Fig.18 ) according to a modification (Modification 5) of the aforementioned second embodiment is shown. In the imaging element 10A of this Modification 5, the photodiode 21 is provided at a position deeper than the surface S11B (on the surface S11A side), and the transfer transistor 22 includes a vertical transistor (transfer gate TG). In other respects, the imaging element 10A of Modification 5 has a configuration similar to that of the imaging element 10A of the aforementioned second embodiment and also has similar functions and effects.

[0232] The gate (transfer gate TG) of the transfer transistor 22 penetrates the p-type well region 111 from the front surface of the semiconductor substrate 11 and extends to the depth reaching the photodiode 21.

[0233] The first substrate 11A includes a pixel separation portion 21S that separates each pixel P. The pixel separation portion 21S is formed to extend in the normal direction of the semiconductor substrate 11 (the direction perpendicular to the surface S11B of the semiconductor substrate 11). The pixel separation portion 21S is provided between two adjacent pixels P. The pixel separation portion 21S electrically separates the adjacent pixels P. For example, the pixel separation portion 21S is made of silicon oxide. For example, the pixel separation portion 21S penetrates the semiconductor substrate 11. The p-type impurity region 21a and the n-type impurity region 21b are provided on the side surface side of the pixel separation portion 21S.

[0234] As Fig.23 shown, the first substrate 11A and the second substrate 30 are electrically connected to each other through the electrode 26E. In addition, the first substrate 11A and the second substrate 30 are connected through the electrodes E1 and E2 that penetrate the interlayer insulating films 19 and 30I (see Fig.24 and Fig.25 described below). In the imaging element 10A, for example, the electrodes E1 and E2 are provided for each pixel P. In addition, as Fig.23 shown, the second substrate 30 and the third substrate 40 are electrically connected to each other by the bonding of the contact electrodes 33 and 43. Here, the width of the electrode 26E is narrower than the width of the bonding point of the contact electrodes 33 and 43. That is, the cross-sectional area of the electrode 26E is smaller than the cross-sectional area of the bonding point of the contact electrodes 33 and 43. Therefore, the electrode 26E hardly inhibits the miniaturization of the per-pixel area in the first substrate 11A. In addition, the readout circuit 20 is formed on the second substrate 30, and the logic circuit LC is formed on the third substrate 40. This makes it possible to form a structure that electrically connects the second substrate 30 and the third substrate 40 to each other, which has a higher degree of freedom in layout in terms of the number of contacts for arranging and connecting compared to the structure that electrically connects the first substrate 11A and the second substrate 30 to each other. Therefore, the bonding of the contact electrodes 33 and 43 can be used as the structure for electrically connecting the second substrate 30 and the third substrate 40 to each other.

[0235] Fig.24 and Fig.25 respectively show examples of the cross-sectional configuration of the imaging element 10A in the horizontal direction. Fig.24 and Fig.25 The upper side of each of Fig.23 shows an example of the cross-sectional configuration at the cross-section Sec1 of Fig.24 and Fig.25 The lower side of each of Fig.23 shows an example of the cross-sectional configuration at the cross-section Sec2 of Fig.24 Illustrates the following configuration: Four pixels P arranged in a 2×2 arrangement in two groups are arranged side by side in the second direction H, and Fig.25illustrates the following configuration: Four pixels P arranged in a 2×2 pattern are arranged side by side in a first direction V and a second direction H. It should be noted that in Fig.24 and Fig.25 's upper side sectional view, a diagram showing an example of the front surface configuration of the semiconductor substrate 11 is superimposed on a diagram showing an example of the sectional configuration at the sectional plane Sec1 of Fig.23 , and the interlayer insulating film 19 is omitted. Additionally, in Fig.24 and Fig.25 's lower side sectional view, a diagram showing an example of the front surface configuration of the semiconductor layer 30S is superimposed on a diagram showing an example of the sectional configuration at the sectional plane Sec2 of Fig.23 .

[0236] As Fig.24 and Fig.25 shown, a plurality of electrodes 26E, a plurality of electrodes E2, and a plurality of electrodes E1 are arranged side by side in a strip shape in a first direction V ( Fig.24 's up and down direction or Fig.25 's left and right direction) in the plane of the first substrate 11A. It should be noted that Fig.24 and Fig.25 illustrate a case where a plurality of electrodes 26E, a plurality of electrodes E2, and a plurality of electrodes E1 are arranged side by side in two columns in the first direction V. The first direction V is parallel to one of the two arrangement directions (e.g., row direction and column direction) of the plurality of pixels P arranged in a matrix (e.g., column direction). For example, among the four pixels P sharing the readout circuit 20, the four FD parts 26 are arranged close to each other via the pixel separation part 21S. Among the four pixels P sharing the readout circuit 20, the four transfer gates TG are arranged to surround the four FD parts 26. For example, the four transfer gates TG form a ring shape.

[0237] The element isolation region 112 includes a plurality of blocks extending in the first direction V. The semiconductor layer 30S includes a plurality of island-like blocks 30SA extending in the first direction V and arranged side by side in a second direction H orthogonal to the first direction V via the element isolation region 112. For example, each block 30SA includes a plurality of groups having a reset transistor 23, an amplification transistor 24, and a selection transistor 25. A single readout circuit 20 shared by four pixels P includes, for example, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in a region opposite to the four pixels P. For example, a single readout circuit 20 shared by four pixels P includes an amplification transistor 24 in the block 30SA located on the left side of the element isolation region 112 and a reset transistor 23 and a selection transistor 25 in the block 30SA on the right side of the element isolation region 112.

[0238] Fig.26 , Fig. 27 , Fig.28and Fig.29 illustrate examples of wiring layouts in the horizontal plane of the imaging element 10A, respectively. Figure 26~Figure 29 illustrate an example in which a single readout circuit 20 shared by four pixels P is provided in a region opposite to the four pixels P. For example, Figure 26~Figure 29 the illustrated wirings are provided in different layers of the multilayer wiring layer 30W.

[0239] For example, as Fig.26 illustrated, four electrodes 26E adjacent to each other are electrically connected to the wiring 31. For example, as Fig.26 illustrated, four electrodes 26E adjacent to each other are further electrically connected to the gate of the amplification transistor 24 included in the block 30SA on the left side of the element isolation region 112 and the source of the reset transistor 23 included in the block 30SA on the right side of the element isolation region 112 via the wiring 31 and the electrode 24E.

[0240] For example, as Fig. 27 illustrated, the power supply line VDD is arranged at a position opposite to each readout circuit 20 arranged side by side in the second direction H. For example, as Fig. 27 illustrated, the power supply line VDD is electrically connected to the drains of the amplification transistors 24 and the drains of the reset transistors 23 in each readout circuit 20 arranged side by side in the second direction H via the electrode 24E. For example, as Fig. 27 illustrated, two pixel drive lines 17 are respectively arranged at positions opposite to each readout circuit 20 arranged side by side in the second direction H. For example, as Fig. 27 illustrated, one of the pixel drive lines 17 (the second control line) is a wiring RSTG electrically connected to the gate of the reset transistor 23 of each readout circuit 20 arranged side by side in the second direction H. For example, as Fig. 27 illustrated, the other of the pixel drive lines 17 (the third control line) is a wiring SELG electrically connected to the gate of the selection transistor 25 of each readout circuit 20 arranged side by side in the second direction H. In each readout circuit 20, for example, as Fig. 27 illustrated, the source of the amplification transistor 24 and the drain of the selection transistor 25 are electrically connected to each other via the wiring 31W.

[0241] For example, as Fig.28 illustrated, two power supply lines VSS are respectively arranged at positions opposite to each readout circuit 20 arranged side by side in the second direction H. For example, as Fig.28 illustrated, each power supply line VSS is electrically connected to a plurality of electrodes E1 at positions opposite to the respective pixels P arranged side by side in the second direction H. For example, as Fig.28 illustrated, four pixel drive lines 17 are respectively arranged at positions opposite to each readout circuit 20 arranged side by side in the second direction H. For example, as Fig.28 As shown, each of the four pixel driving lines 17 is a wiring TRG that is electrically connected to an electrode E2 of one of the four pixels P corresponding to each readout circuit 20 arranged side by side in the second direction H. That is, the four pixel driving lines 17 (first control lines) are electrically connected to the gates (transfer gates TG) of the transfer transistors 22 of the respective pixels P arranged side by side in the second direction H. In Fig.28 this case, identification numbers (1, 2, 3, and 4) are given at the ends of the respective wirings TRG to distinguish the respective wirings TRG.

[0242] For example, as Fig.29 shown, the vertical signal lines 18 are arranged at positions opposite to each readout circuit 20 arranged side by side in the first direction V. For example, as Fig.29 shown, the vertical signal lines 18 (output lines) are electrically connected to the output terminals (sources of the amplifying transistors 24) of each readout circuit 20 arranged side by side in the first direction V.

[0243] In this modification example, the pixel P and the readout circuit 20 are formed on different substrates (the first substrate 11A and the second substrate 30) from each other. Therefore, compared with the case where the pixel P and the readout circuit 20 are formed on the same substrate, the areas of the pixel P and the readout circuit 20 can be enlarged. As a result, the photoelectric conversion efficiency can be increased and the transistor noise can be reduced. Further, the first substrate 11A including the pixel P and the second substrate 30 including the readout circuit 20 are electrically connected to each other via the electrode 26E provided in the interlayer insulating films 19 and 30I. This results in a further reduction in chip size compared with the case where the first electrode 11A and the second substrate 30 are electrically connected to each other by bonding of pad electrodes or by through wiring penetrating the semiconductor substrate (e.g., through-silicon via (TSV)). Further, a further miniaturization of the per-pixel area allows for a higher resolution. Further, in the case of the same chip size as before, the formation region of the pixel P can be enlarged. Further, in this modification example, the readout circuit 20 and the logic circuit LC are formed on different substrates from each other (the second substrate 30 and the third substrate 40). This allows the areas of the readout circuit 20 and the logic circuit LC to be enlarged compared with the case where the readout circuit 20 and the logic circuit LC are formed on the same substrate. Further, the areas of the readout circuit 20 and the logic circuit LC are not limited by the pixel separation section 21S. Therefore, the noise characteristics can be enhanced. Further, in this modification example, the second substrate 30 and the third substrate 40 are electrically connected to each other by bonding of the contact electrodes 33 and 43. Here, the readout circuit 20 is formed on the second substrate 30 and the logic circuit LC is formed on the third substrate 40. This enables a structure to be formed that electrically connects the second substrate 30 and the third substrate 40 to each other, which has a higher degree of freedom in terms of the arrangement and the number of connecting contacts compared with the structure that electrically connects the first substrate 11A and the second substrate 30 to each other. Therefore, the bonding of the contact electrodes 33 and 43 can be used for the electrical connection between the second substrate 30 and the third substrate 40. As described above, in this modification example, electrical connection is made between the substrates according to the integration degree of the substrates. This suppresses an increase in chip size caused by the structure for electrically connecting the substrates to each other, or suppresses the miniaturization of the per-pixel area. As a result, an imaging element 10A having a three-layer structure with the same chip size as before and with almost no suppression of the miniaturization of the per-pixel area can be provided.

[0244] In addition, in this modification example, the pixel P including the photodiode 21, transfer transistor 22, and FD section 26 is formed on the first substrate 11A, and the readout circuit 20 including the reset transistor 23, amplification transistor 24, and selection transistor 25 is formed on the second substrate 30. Compared with the case where the pixel P and the readout circuit 20 are formed on the same substrate, this enables the areas of the pixel P and the readout circuit 20 to be enlarged. As a result, using the bonding of the contact electrodes 33 and 43 for the electrical connection between the second substrate 30 and the third substrate 40 hardly causes an increase in the chip size or hardly inhibits the miniaturization of the per-pixel area. As a result, an imaging element 10A having a three-layer structure with the same chip size as before and hardly inhibiting the miniaturization of the per-pixel area can be provided. Specifically, the number of transistors to be provided on the first substrate 11A is reduced, enabling the area of the pixel P, particularly the photodiode 21, to be enlarged. Therefore, the saturation amount of signal charges in the photoelectric conversion can be increased, leading to an improvement in the photoelectric conversion efficiency. In the second substrate 30, the degree of freedom in the layout of each transistor in the readout circuit 20 can be ensured. In addition, the area of each transistor can be enlarged. Therefore, particularly, enlarging the area of the amplification transistor 24 enables the noise affecting the pixel signal to be reduced. Using the bonding of the contact electrodes 33 and 43 for the electrical connection between the second substrate 30 and the third substrate 40 hardly causes an increase in the chip size or hardly inhibits the miniaturization of the per-pixel area. As a result, an imaging element 10A having a three-layer structure with the same chip size as before and hardly inhibiting the miniaturization of the per-pixel area can be provided.

[0245] In addition, in this modification example, the second substrate 30 is bonded to the first substrate 11A with the back surface of the semiconductor layer 30S facing the front surface side of the semiconductor substrate 11. The third substrate 40 is bonded to the second substrate 30 with the front surface side of the semiconductor layer 40S facing the front surface side of the semiconductor layer 30S. Therefore, by using the electrode 26E for the electrical connection between the first substrate 11A and the second substrate 30 and using the bonding of the contact electrodes 33 and 43 for the electrical connection between the second substrate 30 and the third substrate 40, an imaging element 10A having a three-layer structure with the same chip size as before and hardly inhibiting the miniaturization of the per-pixel area can be provided.

[0246] In addition, in this modification example, the cross-sectional area of the electrode 26E is smaller than the cross-sectional area of the bonding point between the contact electrodes 33 and 43. Therefore, an imaging element 10A having a three-layer structure with the same chip size as before and hardly inhibiting the miniaturization of the per-pixel area can be provided.

[0247] In addition, in the logic circuit LC of this modification example, on the front surface of the impurity diffusion region in contact with the source and drain, a material such as CoSi is formed 2A low-resistance region composed of a silicide such as NiSi. The silicide is formed by a Self Aligned Silicide process. The low-resistance region composed of the silicide includes a compound of the material of the semiconductor substrate and a metal. Here, the logic circuit LC is provided on the third substrate 40. Therefore, the logic circuit LC can be formed by a process different from the process of forming the pixel P and the readout circuit 20. As a result, in forming the pixel P and the readout circuit 20, a high-temperature process such as thermal oxidation can be used. In addition, for the logic circuit LC, a material with low heat resistance, the silicide, can also be used. Therefore, when the low-resistance region composed of the silicide is provided on the front surface of the impurity diffusion region in contact with the source and drain of the logic circuit LC, the contact resistance can be reduced. As a result, the calculation speed in the logic circuit LC can be increased.

[0248] In addition, in this modified example, on the first substrate 11A, a pixel separation portion 21S for separating each pixel P is provided. However, in this modified example, the pixel P including the photodiode 21, the transfer transistor 22, and the FD portion 26 is formed on the first substrate 11A. The readout circuit 20 including the reset transistor 23, the amplification transistor 24, and the selection transistor 25 is formed on the second substrate 30. Therefore, even when the area surrounded by the pixel separation portion 21S is reduced due to the miniaturization of each pixel area, the areas of the pixel P and the readout circuit 20 can be enlarged. As a result, the use of the pixel separation portion 21S hardly causes an increase in the chip size or hardly inhibits the miniaturization of each pixel area. Therefore, an imaging element 10A having a three-layer structure with the same chip size as before and hardly inhibiting the miniaturization of each pixel area can be provided.

[0249] In addition, in this modified example, the pixel separation portion 21S penetrates the semiconductor substrate 11. Therefore, even when the distance between adjacent pixels P is reduced due to the miniaturization of each pixel area, signal crosstalk between adjacent pixels P can be suppressed. This can suppress a decrease in the resolution of the reproduced image or deterioration of the image quality due to color mixing.

[0250] In addition, in the modified example, the laminate including the first substrate 11A and the second substrate 30 includes three electrodes 26E, E1, and E2 for each pixel P. The electrode 26E is electrically connected to the gate of the transfer transistor 22 (transfer gate TG). The electrode E1 is electrically connected to the p-type well region 111 of the semiconductor substrate 11. The electrode E2 is electrically connected to the FD section 26. That is, the number of the electrodes 26E, E1, and E2 is greater than the number of pixels P included in the first substrate 11A. However, in this modified example, the electrode 26E with a small cross-sectional area is used for the electrical connection between the first substrate 11A and the second substrate 30. This results in further miniaturization of the chip size and also results in further miniaturization of the area per pixel in the first substrate 11A. As a result, an imaging element 10A having a three-layer structure with the same chip size as before and having almost no inhibition of miniaturization of the area per pixel can be provided.

[0251] <Modified Example 6>

[0252] Fig.30 A modified example of the cross-sectional configuration of the imaging element 10A according to the modified example (modified example 6) of the above-described second embodiment in the vertical direction is shown. In this modified example, the electrical connection between the second substrate 30 and the third substrate 40 is made in a region opposite to the peripheral region 12B of the first substrate 11A. The peripheral region 12B corresponds to the frame region of the first substrate 11A and is provided around the pixel array unit 12. In this modified example, the second substrate 30 includes a plurality of contact electrodes 33 in a region opposite to the peripheral region 12B, and the third substrate 40 includes a plurality of contact electrodes 43 in a region opposite to the peripheral region 12B. The second substrate 30 and the third substrate 40 are electrically connected to each other by the bonding of the contact electrodes 33 and 43 provided in the region opposite to the peripheral region 12B.

[0253] As described above, in this modified example, the second substrate 30 and the third substrate 40 are electrically connected to each other by the bonding of the contact electrodes 33 and 43 provided in the region opposite to the peripheral region 12B. This can reduce the possibility of inhibiting miniaturization of the area per pixel compared to the case where the contact electrodes 33 and 43 are bonded to each other in a region opposite to the pixel array unit 12. Therefore, an imaging element 10A having a three-layer structure with the same chip size as before and having almost no inhibition of miniaturization of the area per pixel can be provided.

[0254] <Modified Example 7>

[0255] Fig.31 and Fig.32 respectively show modified examples of the cross-sectional configuration of the imaging element 10A according to the above-described second embodiment in the horizontal direction. Fig.31 and Fig.32 The upper side views of each of Fig.23A modified example of the cross-section at cross-section Sec1, and Fig.31 and Fig.32 The lower side of each of them shows Fig.23 A modified example of the cross-section at cross-section Sec2. It should be noted that in Fig.31 and Fig.32 In the upper side cross-sectional view, a figure showing a modified example of the front surface configuration of the semiconductor substrate 11 in Fig.23 is superimposed on a figure showing a modified example of the cross-section configuration at cross-section Sec1 of Fig.23 , and the interlayer insulating layer 19 is omitted. Additionally, in Fig.31 and Fig.32 In the lower side cross-sectional view, a figure showing a modified example of the front surface configuration of the semiconductor layer 30S is superimposed on a figure showing a modified example of the cross-section configuration at cross-section Sec2 of Fig.23 .

[0256] As Fig.31 and Fig.32 shown, a plurality of electrodes 26E, a plurality of electrodes E2, and a plurality of electrodes E1 (a plurality of points arranged in rows and columns in the figure) are arranged side by side in a strip shape in the first direction V ( Fig.31 and Fig.32 the left - right direction in Fig.31 and Fig.32 in the plane of the first substrate 11A. It should be noted that

[0257] illustrates a case where a plurality of electrodes 26E, a plurality of electrodes E2, and a plurality of electrodes E1 are arranged side by side in two columns in the first direction V. For example, in four pixels P sharing the readout circuit 20, four FD parts 26 are arranged close to each other via the pixel separation part 21S. In four pixels P sharing the readout circuit 20, for example, four transfer gates TG (TG1, TG2, TG3, and TG4) are arranged to surround the four FD parts 26, and the four transfer gates TG form a ring shape.

[0258] In Fig.31In [the structure], a single readout circuit 20 shared by four pixels P includes a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in a region of the second substrate 30 that is offset in the second direction H from a region opposite to the four pixels P. For example, a single readout circuit 20 shared by four pixels P includes the amplification transistor 24, the reset transistor 23, and the selection transistor 25 in a single block 30SA.

[0259] In Fig.32 [the structure], a single readout circuit 20 shared by four pixels P includes a reset transistor 23, an amplification transistor 24, a selection transistor 25, and an FD transfer transistor 27 in a region of the second substrate 30 that is offset in the second direction H from a region opposite to the four pixels P. For example, a single readout circuit 20 shared by four pixels P includes the amplification transistor 24, the reset transistor 23, the selection transistor 25, and the FD transfer transistor 27 in a single block 30SA.

[0260] In this modification example, for example, a single readout circuit 20 shared by four pixels P is not arranged directly opposite to the four pixels P, but is arranged to be offset in the second direction H from a position directly opposite to the four pixels P. In this case, the wiring 31 can be shortened, or alternatively, the wiring 31 can be omitted, and the source of the amplification transistor 24 and the drain of the selection transistor 25 are formed in a common impurity region. As a result, the size of the readout circuit 20 can be reduced or the size of any other part in the readout circuit 20 can be increased.

[0261] <Modification Example 8>

[0262] Fig.33 A modification example of the cross-sectional configuration of the imaging element 10A in the horizontal direction according to the above-described second embodiment is shown. Fig.33 A cross-sectional configuration of Fig.24 is shown.

[0263] In this modification example, the semiconductor layer 30S includes a plurality of island-shaped blocks 30SA arranged side by side in the first direction V and the second direction H via element isolation regions 112. For example, each block 30SA includes a group having a reset transistor 23, an amplification transistor 24, and a selection transistor 25. In this case, crosstalk between adjacent readout circuits 20 can be suppressed by the element isolation regions 112. This can suppress a decrease in the resolution of the reproduced image and deterioration of the image quality due to color mixing.

[0264] <Modification Example 9>

[0265] Fig.34 A modification example of the cross-sectional configuration of the imaging element 10A in the horizontal direction according to the above-described second embodiment is shown. Fig.34 A cross-sectional configuration of Fig.33 A modified example of the cross-sectional structure in

[0266] In this modified example, a single readout circuit 20 shared by four pixels P is not arranged directly opposite to the four pixels P, but is arranged to be offset in the first direction V. Further, in this modified example, as in Modified Example 8, the semiconductor layer 30S includes a plurality of island-shaped blocks 30SA arranged side by side in the first direction V and the second direction H via the element isolation region 112. For example, each block 30SA includes a group having a reset transistor 23, an amplification transistor 24, and a selection transistor 25. Further, in this modified example, a plurality of electrodes E1 and a plurality of electrodes 26E are also arranged in the second direction H. Specifically, the plurality of electrodes E1 are arranged between the four electrodes 26E sharing the readout circuit 20 and the four electrodes 26E of another readout circuit 20 adjacent to the readout circuit 20 sharing the readout circuit 20 in the second direction H. In this case, crosstalk between adjacent readout circuits 20 can be suppressed by the element isolation region 112 and the electrode E1. This can suppress a decrease in the resolution of the reproduced image and deterioration of the image quality due to color mixing.

[0267] <Modified Example 10>

[0268] Fig.35 An example of the cross-sectional structure of the imaging element 10A in the horizontal direction according to the above-described second embodiment and its modified examples is shown. Fig.35 Shows Fig.24 A modified example of the cross-sectional structure in

[0269] In this modified example, the first substrate 11A includes a photodiode 21 and a transfer transistor 22 for each pixel P, and the FD section 26 is shared by every four pixels P. Therefore, in this modified example, one electrode 26E is provided for every four pixels P.

[0270] Among the plurality of pixels P arranged in a matrix, for convenience, four pixels P are referred to as four pixels PA, and the four pixels PA correspond to a region obtained by shifting a unit region by a single pixel P in the first direction V. The unit region corresponds to four pixels P sharing a single FD section 26. At this time, in this modified example, in the first substrate 11A, the electrode E1 is shared by every four pixels PA. Therefore, in this modified example, one electrode E1 is provided for every four pixels PA.

[0271] In this modification example, the first substrate 11A includes a pixel separation portion 21S that separates the photodiodes 21 and transfer transistors 22 of each pixel P. When viewed from the normal direction of the semiconductor substrate 11, the pixel separation portion 21S does not completely surround the pixel P, but has gaps (unformed regions) near the FD portion 26 (electrode 26E) and near the electrode E1. Therefore, the gaps allow one electrode 26E to be shared by four pixels P and one electrode E1 to be shared by four pixels P. In this modification example, the second substrate 30 includes a readout circuit 20 for every four pixels P that share the FD portion 26.

[0272] Fig.36 An example of the cross-sectional structure of the imaging element 10A according to this modification example in the horizontal direction is shown. Fig.36 Shows Fig.33 A modification example of the cross-sectional structure in. In this modification example, the first substrate 11A includes a photodiode 21 and a transfer transistor 22 for each pixel P, and the FD portion 26 is shared by every four pixels P. In addition, the first substrate 11A includes a pixel separation portion 21S that separates the photodiode 21 and transfer transistor 22 of each pixel P.

[0273] Fig.37 An example of the cross-sectional structure of the imaging element 10A according to this modification example in the horizontal direction is shown. Fig.37 Shows Fig.34 A modification example of the cross-sectional structure in. In this modification example, the first substrate 11A includes a photodiode 21 and a transfer transistor 22 for each pixel P, and the FD portion 26 is shared by every four pixels P. In addition, the first substrate 11A includes a pixel separation portion 21S that separates the photodiode 21 and transfer transistor 22 of each pixel P.

[0274] <Modification Example 11>

[0275] Fig.38 An example of the circuit structure of the imaging element 10A according to the above second embodiment and its modification examples is shown. The imaging element 10A according to this modification example is a CMOS image sensor including a column-parallel ADC.

[0276] As Fig.38 Shown, in addition to including a pixel array unit 12 in which a plurality of pixels P each including a photoelectric conversion element are arranged two-dimensionally in rows and columns (matrix), the imaging element 10A according to this modification example further includes a vertical drive circuit 13, a signal processing circuit 14, a reference voltage supply unit 38, a horizontal drive circuit 15, a horizontal output line 37, and a system control circuit 16.

[0277] In this system configuration, for example, the system control circuit 16 generates clock signals and control signals based on the main clock MCK and uses them as operation references for, for example, the vertical drive circuit 13, the signal processing circuit 14, the reference voltage supply unit 38, and the horizontal drive circuit 15, and supplies the clock signals, control signals, etc. to the vertical drive circuit 13, the signal processing circuit 14, the reference voltage supply unit 38, the horizontal drive circuit 15, etc.

[0278] In addition, the vertical drive circuit 13 is formed together with each pixel P in the pixel array unit 12 in the first substrate 11A, and is also formed in the second substrate 30 in which the readout circuit 20 is formed. The signal processing circuit 14, the reference voltage supply unit 38, the horizontal drive circuit 15, the horizontal output line 37, and the system control circuit 16 are formed in the third substrate 40.

[0279] Although not shown here, for example, a pixel having a configuration including a transfer transistor 22 in addition to the photodiode 21 can be used as the pixel P. The transfer transistor 22 transfers the charge obtained by photoelectric conversion in the photodiode 21 to the FD section 26. In addition, although not shown here, for example, those readout circuits having a three-transistor configuration including a reset transistor 23 that controls the potential of the FD section 26, an amplification transistor 24 that outputs a signal corresponding to the potential of the FD section 26, and a selection transistor 25 for pixel selection can be used as the readout circuit 20.

[0280] In the pixel array unit 12, the pixels P are arranged two-dimensionally. For such an m-row and n-column pixel arrangement, pixel drive lines 17 are wired for each row, and vertical signal lines 18 are wired for each column. One end of each of the plurality of pixel drive lines 17 is connected to a corresponding one of the output ends of the vertical drive circuit 13 corresponding to each row. For example, the vertical drive circuit 13 includes a shift register and controls the row address and row scanning of the pixel array unit 12 via the plurality of pixel drive lines 17.

[0281] For example, the signal processing circuit 14 includes ADCs (analog-digital conversion circuits) 34-1 to 34-m provided for each pixel row of the pixel array unit 12, that is, for each vertical signal line 18, converts the analog signals output column by column from the respective pixels P in the pixel array unit 12 into digital signals, and outputs the digital signals.

[0282] For example, the reference voltage supply unit 38 includes a DAC (digital-analog conversion circuit) 38A as a device for generating a so-called ramp (RAMP) waveform reference voltage Vref whose level changes obliquely with time. It should be noted that the device for generating the ramp waveform reference voltage Vref is not limited to the DAC 38A.

[0283] Under the control of the control signal CS1 provided by the system control circuit 16, the DAC 38A generates a ramp waveform reference voltage Vref based on the clock CK provided by the system control circuit 16, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the signal processing circuit 14.

[0284] It should be noted that each of the ADCs 34-1 to 34-m is configured to selectively perform an AD conversion operation corresponding to each operation mode. The operation modes include a normal frame rate mode in a progressive scanning system in which information of all pixels P is read out, and a high frame rate mode in which the exposure time of the pixel P is set to 1 / N to increase the frame rate by N times, for example, twice the frame rate in the normal frame rate mode. Such switching of the operation mode is performed by using the control of the control signals CS2 and CS3 provided by the system control circuit 16. In addition, the system control circuit 16 is provided with instruction information from an external system controller (not shown) for switching between the respective operation modes, that is, the normal frame rate mode and the high frame rate mode.

[0285] The ADCs 34-1 to 34-m all have the same configuration, and here, the ADC 34-m is taken as an example for description. For example, the ADC 34-m has a configuration including a comparator 34A, an up / down counter (referred to as "U / DCNT" in the figure) 34B serving as a counting device, a transfer switch 34C, and a storage device 34D.

[0286] The comparator 34A compares the signal voltage Vx of the vertical signal line 18 corresponding to the signal output from each pixel P in the nth column of the pixel array unit 12 with the ramp waveform reference voltage Vref supplied from the reference voltage supply unit 38. For example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes the "H" level. When the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco becomes the "L" level.

[0287] The up / down counter 34B includes an asynchronous counter. Under the control of the control signal CS2 provided by the system control circuit 16, the up / down counter 34B receives the clock CK from the system control circuit 16 simultaneously with the DAC 38A, and performs a down (DOWN) count or an up (UP) count synchronously with the clock CK to measure the comparison time from the start to the end of the comparison operation in the comparator 34A.

[0288] Specifically, in the normal frame rate mode, during the readout operation of the signal from a pixel P, a down-count is performed in the first readout operation to measure the comparison time in the first readout. An up-count is performed in the second readout operation to measure the comparison time in the second readout.

[0289] In contrast, in the high frame rate mode, the count result of the pixel P in any row remains as it is. Subsequently, for the pixel P in the next row, a down-count is performed in the first readout operation based on the previous count result to measure the comparison time in the first readout. An up-count is performed in the second readout operation to measure the comparison time in the second readout.

[0290] In the normal frame rate mode, under the control of the control signal CS3 provided by the system control circuit 16, when the up / down counter 34B completes the counting operation of the pixel P in any row, the transfer switch 34C becomes ON (conductive), and the relevant count result of the up / down counter 34B is transferred to the storage device 34D.

[0291] In contrast, at a high frame rate of N = 2, when the up / down counter 34B completes the counting operation of the pixel P in any row, the transfer switch 34C remains in the OFF (non-conductive) state. Subsequently, when the up / down counter 34B completes the counting operation of the pixel P in the next row, the transfer switch 34C becomes conductive, and the count results of two vertical pixels are transferred from the up / down counter 34B to the storage device 34D.

[0292] As described above, the analog signals provided column by column from the respective pixels P in the pixel array unit 12 via the vertical signal lines 18 are converted into N-bit digital signals through the respective operations of the comparators 34A and the up / down counter 34B in the ADCs 34-1 to 34-m, and the digital signals are stored in the storage device 34D.

[0293] For example, the horizontal drive circuit 15 includes a shift register, and the control of the column addresses and column scans of the ADCs 34-1 to 34-m is performed in the signal processing circuit 14. Under the control of the horizontal drive circuit 15, the N-bit digital signals A / D-converted in the respective ADCs 34-1 to 34-m are sequentially read out to the horizontal output lines 37 and output as imaging data via the horizontal output lines 37.

[0294] It should be noted that, in addition to the above-described components, a circuit or the like that performs various types of signal processing on the imaging data to be output via the horizontal output lines 37 may be provided. However, since the circuit or the like is not directly related to the present disclosure, the circuit or the like is not shown.

[0295] In the imaging element 10A including the column parallel ADC having the above-described configuration according to this modification example, the count result of the up-down counter 34B can be selectively transmitted to the storage device 34D through the transfer switch 34C. Therefore, the counting operation of the up-down counter 34B and the readout operation of the count result of the up-down counter 34B to the horizontal output line 37 can be independently controlled.

[0296] <Modification Example 12>

[0297] Fig.39 An example of the imaging element constructed by stacking three substrates (the first substrate 11A, the second substrate 30, and the third substrate 40) is shown. Fig.38 In this modification example, in the first substrate 11A, a pixel array unit 12 including a plurality of pixels P is formed in the central portion, and a vertical drive circuit 13 is formed around the pixel array unit 12. Further, in the second substrate 30, a readout circuit region 20R including a plurality of readout circuits 20 is formed in the central portion, and a vertical drive circuit 13 is formed around the readout circuit region 20R. In the third substrate 40, a signal processing circuit 14, a horizontal drive circuit 15, a system control circuit 16, a horizontal output line 37, and a reference voltage supply unit 38 are formed. Therefore, as in the above-described embodiments and modification examples, the structure of the electrical connection of the substrates hardly causes an increase in the chip size and hardly inhibits the miniaturization of the per-pixel area. As a result, an imaging element 10A having a three-layer structure with the same chip size as before and hardly inhibiting the miniaturization of the per-pixel area can be provided. It should be noted that the vertical drive circuit 13 may be formed only in the first substrate 11A or may be formed only in the second substrate 30.

[0298] <Modification Example 13>

[0299] Fig.40 A modification example of the cross-sectional configuration of the imaging element 10A according to the above-described second embodiment and its modification examples is shown. In the above-described second embodiment and its modification examples, the imaging element 10A is constructed by stacking three substrates (the first substrate 11A, the second substrate 30, and the third substrate 40). However, in the above-described second embodiment and its modification examples, the imaging element 10A may be constructed by stacking two substrates (the first substrate 11A and the second substrate 30). At this time, for example, as Fig.40 shown, the logic circuit LC is separately formed in the first substrate 11A and the second substrate 30. Here, the circuit LCA in the first substrate 11A of the logic circuit LC includes a transistor having the following gate electrode structure: a high dielectric constant (e.g., high-k) film made of a material resistant to high-temperature processes and a metal gate electrode are stacked therein. On the contrary, in the circuit LCB provided in the second substrate 30, by, for example, CoSi 2A low-resistance region 30SL composed of silicides such as CoSi and NiSi is provided on the front surface of the impurity diffusion region in contact with the source and drain. The silicide is formed using a Self Aligned Silicide process. The low-resistance region composed of the silicide is composed of a compound of a material including the semiconductor substrate and a metal. This allows the use of high-temperature processes such as thermal oxidation in forming the pixel P. Further, in the circuit LCB provided in the second electrode 30 of the logic circuit LC, when the low-resistance region 30SL composed of the silicide is provided on the front surface of the impurity diffusion region in contact with the source and drain, the contact resistance can be reduced. As a result, the calculation speed of the logic circuit LC can be increased.

[0300] <Modification Example 14>

[0301] Fig.41 A modification of the cross-sectional configuration of the imaging element 10A according to the above-described second embodiment and its modification examples is shown. In the logic circuit LC of the third substrate 40 according to the above-described second embodiment and its modification examples, a low-resistance region 40SL composed of silicides such as CoSi 2 and NiSi can be provided on the front surface of the impurity diffusion region in contact with the source and drain. The silicide is formed using a Self Aligned Silicide process. This allows the use of high-temperature processes such as thermal oxidation in forming the pixel P. Further, in the logic circuit LC, when the low-resistance region 40SL composed of the silicide is provided on the front surface of the impurity diffusion region in contact with the source and drain, the contact resistance can be reduced. As a result, the calculation speed of the logic circuit LC can be increased.

[0302] <Application Example>

[0303] Fig.42 An example of the schematic configuration of an imaging device 2 including the imaging element 10 or 10A according to the above-described first and second embodiments and their modification examples is shown.

[0304] For example, the imaging device 2 includes an electronic device, which includes an imaging device such as a digital camera or a video camera, or a mobile terminal device such as a smart phone or a tablet terminal. For example, the imaging device 2 includes the imaging element 10 or 10A, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146 according to the above-described first and second embodiments and their modification examples. In the imaging device 2, the imaging element 10 or 10A, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 according to the above-described embodiments and their modification examples are connected to each other via a bus 147.

[0305] The imaging element 10 or 10A according to the foregoing first and second embodiments and their modified examples outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes signals (image data) output from the imaging element 10 or 10A according to the foregoing embodiments and their modified examples. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 in units of frames. For example, the display unit 143 includes a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays a moving image or a still image captured by the imaging element 10 or 10A according to the foregoing embodiments and their modified examples. The storage unit 144 records the image data of the moving image or the still image captured by the imaging element 10 or 10A according to any one of the foregoing first and second embodiments and their modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 outputs operation instructions regarding various functions of the imaging device 2 according to the user's operation. The power supply unit 146 supplies various power supplies used as the operation power supplies for the imaging element 10 or 10A, the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145 according to the foregoing first and second embodiments and their modified examples to these supply targets when necessary.

[0306] Next, an imaging process in the imaging device 2 will be described.

[0307] Fig.43 An example of a flowchart of the imaging operation in the imaging device 2 is shown. The user operates the operation unit 145 to give an instruction for starting imaging (step S101). Then, the operation unit 145 sends an instruction for imaging to the imaging element 10 or 10A (step S102). When receiving the instruction for imaging, the imaging element 10 or 10A (specifically, the system control circuit 16) performs imaging of a predetermined imaging system (step S103).

[0308] The imaging element 10 or 10A outputs the image data captured by imaging to the DSP circuit 141. Here, the image data is data of pixel signals of all pixels generated based on the charges temporarily held in the FD unit 26. The DSP circuit 141 performs predetermined signal processing (for example, noise reduction processing, etc.) based on the image data provided from the imaging element 10 or 10A (step S104). The DSP circuit 141 causes the frame memory 142 to hold the image data that has undergone the predetermined signal processing, and the frame memory 142 stores the image data in the storage unit 144 (step S105). Thus, imaging is performed in the imaging device 2.

[0309] In this application example, the imaging elements 10 and 10A according to the above-described embodiments and their modified examples are applicable to the imaging device 2. This can cause a reduction in the size or higher clarity of the imaging elements 10 and 10A. Therefore, an imaging device 2 with a small size or high clarity can be provided.

[0310] <Application Example of In-Vivo Information Acquisition System>

[0311] Furthermore, the technology according to the present disclosure (this technology) is applicable to various products. For example, the technology according to the present disclosure can be applied to an in-vivo information acquisition system.

[0312] Fig.44 FIG. is a block diagram showing a schematic configuration example of an in-vivo information acquisition system for a patient using a capsule endoscope to which the technology (this technology) according to the embodiments of the present disclosure can be applied.

[0313] The in-vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200.

[0314] During an examination, the patient swallows the capsule endoscope 10100. The capsule endoscope 10100 has an imaging function and a wireless communication function, and while it moves inside an organ such as the stomach or intestine by peristaltic movement for a certain period of time, it sequentially captures images of the inside of the organ (hereinafter referred to as in-vivo images) at predetermined intervals until it is naturally discharged from the patient's body. Then, the capsule endoscope 10100 sequentially transmits the information of the in-vivo images to the external control device 10200 outside the body via wireless transmission.

[0315] The external control device 10200 controls the operation of the in-vivo information acquisition system 10001 as a whole. Further, the external control device 10200 receives the information of the in-vivo images transmitted to it from the capsule endoscope 10100, and generates image data for displaying the in-vivo images on a display device (not shown) based on the received information of the in-vivo images.

[0316] In the in-vivo information acquisition system 10001, in this way, in-vivo images that image the state of the patient's body can be acquired at any time during the period from when the capsule endoscope 10100 is swallowed until it is discharged.

[0317] The configurations and functions of the capsule endoscope 10100 and the external control device 10200 will be described in more detail below.

[0318] The capsule endoscope 10100 includes a capsule-shaped housing 10101, in which a light source unit 10111, an imaging unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power source unit 10116, and a control unit 10117 are accommodated.

[0319] The light source unit 10111 is composed of a light source, such as a light emitting diode (LED), and the light source unit 10111 irradiates light on the imaging field of view of the imaging unit 10112.

[0320] The imaging unit 10112 is composed of an imaging element and an optical system, and the optical system includes a plurality of lenses provided at the previous stage of the imaging element. The reflected light of the light irradiated on the body tissue as the observation target (hereinafter referred to as the observation light) is converged by the optical system and introduced into the imaging element. In the imaging unit 10112, the incident observation light is photoelectrically converted by the imaging element, thereby generating an image signal corresponding to the observation light. The image signal generated by the imaging unit 10112 is provided to the image processing unit 10113.

[0321] The image processing unit 10113 is composed of a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various signal processes on the image signal generated by the imaging unit 10112. Therefore, the image processing unit 10113 provides the image signal on which the signal process has been performed as raw (RAW) data to the wireless communication unit 10114.

[0322] The wireless communication unit 10114 performs predetermined processes such as modulation processing on the image signal on which the signal process has been performed by the image processing unit 10113, and transmits the obtained image signal to the external control device 10200 through the antenna 10114A. In addition, the wireless communication unit 10114 receives a control signal related to the drive control of the capsule endoscope 10100 from the external control device 10200 through the antenna 10114A. The wireless communication unit 10114 provides the control signal received from the external control device 10200 to the control unit 10117.

[0323] The power supply unit 10115 is composed of an antenna coil for power reception, a power regeneration circuit for regenerating power from the current generated in the antenna coil, a voltage booster circuit, etc. The power supply unit 10115 generates power using the non-contact charging principle.

[0324] The power supply unit 10116 is composed of a secondary battery and stores the power generated by the power supply unit 10115. In Fig.44 for the sake of avoiding complicated illustrations, the arrow marks indicating the supply destinations of the power from the power supply unit 10116 etc. are omitted. However, the power stored in the power supply unit 10116 is supplied to the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117, and can be used to drive the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117.

[0325] The control unit 10117 is composed of a processor such as a CPU etc., and appropriately controls the driving of the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the power supply unit 10115 according to the control signal transmitted to it from the external control device 10200.

[0326] The external control device 10200 is composed of a processor (such as a CPU or GPU) or a microcomputer or a control board etc. that is hybridly installed with a processor and a storage element (such as a memory). The external control device 10200 transmits a control signal to the control unit 10117 of the capsule endoscope 10100 through the antenna 10200A to control the operation of the capsule endoscope 10100. In the capsule endoscope 10100, for example, the light irradiation conditions of the light source unit 10111 during observation of the observation target can be changed according to the control signal from the external control device 10200. In addition, the imaging conditions (such as the frame rate or exposure value etc. of the imaging unit 10112) can be changed according to the control signal from the external control device 10200. In addition, the content of the processing by the image processing unit 10113 or the conditions for transmitting the image signal from the wireless communication unit 10114 (such as the transmission interval or the number of transmitted images etc.) can be changed according to the control signal from the external control device 10200.

[0327] In addition, the external control device 10200 performs various image processes on the image signals sent from the capsule endoscope 10100 to generate image data for displaying the captured in-vivo images on the display device. As the image process, various signal processes can be performed, for example, development process (demosaicing process), image quality improvement process (bandwidth enhancement process, super-resolution process, noise reduction (NR) process, and / or image stabilization process), and / or magnification process (electronic zoom process). The external control device 10200 controls the driving of the display device to cause the display device to display the captured in-vivo images based on the generated image data. Alternatively, the external control device 10200 can also control a recording device (not shown) to record the generated image data, or control a printing device (not shown) to output the generated image data by printing.

[0328] In the above, an example of the in-vivo information acquisition system to which the technology according to the present disclosure can be applied has been described. For example, the technology according to the present disclosure can be applied to the imaging unit 10112 in the above configuration. This results in an improvement in detection accuracy.

[0329] <Application Example of Endoscopic Surgery System>

[0330] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0331] Fig.45 FIG. is an example showing a schematic configuration of an endoscopic surgery system to which the technology (this technology) according to the embodiments of the present disclosure can be applied.

[0332] In Fig.45 it, a state is shown in which a surgeon (doctor) 11131 is performing surgery on a patient 11132 on a hospital bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 that supports the endoscope 11100 thereon, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0333] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102. A region of a predetermined length starting from its distal end of the lens barrel is inserted into the body cavity of a patient 11132, and the camera head is connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is shown as a rigid endoscope configured with a rigid lens barrel 11101. However, the endoscope 11100 can also be configured as a flexible endoscope with a flexible lens barrel 11101.

[0334] The lens barrel 11101 has an opening at its distal end in which an objective lens is assembled. A light source device 11203 is connected to the endoscope 11100 so as to introduce the light generated by the light source device 11203 into the distal end of the lens barrel 11101 through an optical fiber extending inside the lens barrel 11101, and irradiate an observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a forward-view endoscope or can be an oblique-view endoscope or a side-view endoscope.

[0335] An optical system and an imaging element are provided inside the camera head 11102 so as to focus the reflected light (observation light) from the observation target on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted as raw data to the CCU 11201.

[0336] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and centrally controls the operations of the endoscope 11100 and the display device 11202. Further, for example, the CCU 11201 receives the image signal from the camera head 11102, and performs various image processes such as development processing (demosaicing processing) on the image signal to display an image based on the image signal.

[0337] The display device 11202 displays, under the control of the CCU 11201, an image based on the image signal that has been subjected to image processing by the CCU 11201 thereon.

[0338] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and provides illumination light for imaging the surgical area to the endoscope 11100.

[0339] The input device 11204 is an input interface of the endoscopic surgical system 11000. A user can input various information or instructions into the endoscopic surgical system 11000 through the input device 11204. For example, the user will input an instruction to change the imaging conditions (type of illumination light, magnification, focal length, etc.) of the endoscope 11100.

[0340] The treatment tool control device 11205 controls the driving of the energy device 11112 to cauterize or incise tissue, seal blood vessels, etc. The pneumoperitoneum device 11206 supplies gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity to ensure the field of view of the endoscope 11100 and ensure the working space for the surgeon. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, image or graph.

[0341] It should be noted that the light source device 11203 that provides the illumination light when photographing the surgical area can be composed of a white light source. For example, the white light source is composed of an LED, a laser light source or a combination thereof. In the case where the white light source is composed of a combination of red, green and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. Further, in this case, if the laser beams from the respective RGB laser light sources are irradiated on the observation target in a time-division manner, the driving of the imaging element of the camera head 11102 is controlled in synchronization with the irradiation timing. Then, images corresponding to the R, G, and B colors can also be captured in a time-division manner. According to this method, a color image can be obtained even without arranging a color filter for the imaging element.

[0342] Further, the driving of the light source device 11203 can be controlled so as to change the intensity of the light to be output at every predetermined time. By controlling the driving of the imaging element of the camera head 11102 in synchronization with the changing timing of the light intensity to obtain and synthesize images in a time-division manner, a high dynamic range image can be created, and there will be no occluding shadows of underexposure and highlights of overexposure in the image.

[0343] Furthermore, the light source device 11203 can be configured to provide light corresponding to a predetermined wavelength band for special light observation. For example, in special light observation, by utilizing the wavelength dependence of light absorption of body tissues, light with a narrower band than the illumination light (i.e., white light) during normal observation is irradiated to perform narrow band observation (narrow band imaging) on predetermined tissues such as blood vessels in the mucosal surface layer part with high contrast. Alternatively, in special light observation, fluorescence observation for obtaining an image from the fluorescence generated by irradiating excitation light can be performed. In fluorescence observation, fluorescence observation of body tissues (autofluorescence observation) can be performed by irradiating excitation light on body tissues, or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissues and irradiating excitation light corresponding to the fluorescence wavelength of the reagent on body tissues. The light source device 11203 can be configured to provide such narrow band light and / or excitation light applicable to the special light observation as described above.

[0344] Fig.46 is a block diagram showing Fig.45 an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in

[0345] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected by a transmission cable 11400 to communicate with each other.

[0346] The lens unit 11401 is an optical system provided at the connection position with the lens barrel 11101. The observation light entering from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focusing lens.

[0347] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). For example, when the imaging unit 11402 is configured as a multi-board type, image signals corresponding to each R, G, and B are generated by the imaging elements, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be configured to have a pair of imaging elements for obtaining a right-eye image signal and a left-eye image signal corresponding to three-dimensional (3D) display. If 3D display is performed, then the surgeon 11131 can more accurately grasp the depth of the living tissue in the surgical area. It should be noted that when the imaging unit 11402 is configured in a stereoscopic manner, multiple lens unit 11401 systems are provided corresponding to each imaging element.

[0348] Furthermore, the imaging unit 11402 may not necessarily be provided on the camera head 11102. For example, the imaging unit 11402 can be provided directly behind the objective lens inside the lens barrel 11101.

[0349] The drive unit 11403 is composed of an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 along the optical axis by a predetermined distance under the control of the camera head control unit 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0350] The communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.

[0351] In addition, the communication unit 11404 receives a control signal for controlling the drive of the camera head 11102 from the CCU 11201 and provides the control signal to the camera head control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value when capturing an image, and / or information specifying the magnification and focus of the captured image.

[0352] It should be noted that imaging conditions such as frame rate, exposure value, magnification, or focus can be specified by the user or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are provided in the endoscope 11100.

[0353] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0354] The communication unit 11411 is composed of a communication device for transmitting various information to and receiving various information from the camera head 11102. The communication unit 11411 receives the image signal transmitted to it from the camera head 11102 through the transmission cable 11400.

[0355] Furthermore, the communication unit 11411 transmits the control signal for controlling the driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0356] The image processing unit 11412 performs various image processing operations on the image signal in the form of RAW data transmitted from the camera head 11102.

[0357] The control unit 11413 performs various controls related to image capturing of the surgical area, etc. through the endoscope 11100 and display of the captured image obtained by image capturing of the surgical area, etc. For example, the control unit 11413 creates a control signal for controlling the driving of the camera head 11102.

[0358] Furthermore, the control unit 11413 controls the display device 11202 to display the captured image in which the surgical area, etc. is imaged, based on the image signal that has been subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition techniques to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as surgical forceps, specific living body areas, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edges of the objects contained in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, it can use the recognition result to display various surgical support information in an overlapping manner with the image of the surgical area. In the case where the surgical support information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can perform the surgery reliably.

[0359] The transmission cable 11400 that interconnects the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable for both electrical communication and optical communication.

[0360] Here, although in the illustrated example, communication is performed via a transmission cable 11400 by wireline communication, communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

[0361] In the above, an example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described. For example, the technology according to the present disclosure can be applied to the imaging unit 11402 in the above configuration. Applying the technology according to the present disclosure to the imaging unit 11402 can improve the detection accuracy.

[0362] Note that here, an endoscopic surgical system is taken as an example for description, but the technology according to the present disclosure can be applied to other systems, such as a microsurgical system and the like.

[0363] <Application Example of a Moving Body>

[0364] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, a robot, a construction machine, and an agricultural machine (tractor).

[0365] Fig.47 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology of the embodiment according to the present disclosure can be applied.

[0366] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.47 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown as functional components of the integrated control unit 12050.

[0367] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for devices such as a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0368] The vehicle body system control unit 12020 controls the operations of various devices provided to the vehicle body according to various programs. For example, the vehicle body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, radio waves transmitted from a portable device that substitutes for a key or signals of various switches can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives these input radio waves or signals and controls the vehicle door lock device, the electric window device, the lights, etc.

[0369] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle having the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a detection process on objects such as a person, a vehicle, an obstacle, a marker, or a symbol on the road surface, or a detection process of the distance to these objects.

[0370] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of the received light. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared light.

[0371] The vehicle interior information detection unit 12040 detects information about the interior of the vehicle. For example, the vehicle interior information detection unit 12040 is connected to the driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0372] The microcomputer 12051 can calculate the control target values of the driving force generating device, the steering mechanism, or the braking device based on information regarding the inside or outside of the vehicle, which is obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), which includes: collision avoidance or impact mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0373] In addition, the microcomputer 12051 can perform cooperative control for autonomous driving, which enables the vehicle to drive autonomously without relying on the driver's operation, etc., by controlling the driving force generating device, the steering mechanism, or the braking device, etc., based on information regarding the inside or outside of the vehicle, which is obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040.

[0374] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information regarding the outside of the vehicle, which is obtained by the out-vehicle information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlamp to change from high beam to low beam according to the positions of the vehicle ahead or the oncoming vehicle detected by the out-vehicle information detection unit 12030.

[0375] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can notify information visually or auditorily to the passengers of the vehicle or the outside of the vehicle. In Fig.47 the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. For example, the display unit 12062 can include at least one of an in-vehicle display and a head-up display.

[0376] Fig.48 is a diagram showing an example of the installation position of the imaging unit 12031.

[0377] In Fig.48 it, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0378] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100 and at a position on the upper part of the windshield inside the vehicle. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield inside the vehicle is mainly used to detect a vehicle ahead, pedestrians, obstacles, signals, traffic signs, or lanes, etc.

[0379] Incidentally, Fig.48 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided on the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided on the rear bumper or rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above is obtained.

[0380] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0381] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thus extract the nearest three-dimensional object as the vehicle ahead. In particular, this three-dimensional object exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, the microcomputer 12051 can preset the inter-vehicle distance to be maintained in front of the vehicle ahead and perform automatic braking control (including following-stop control) or automatic acceleration control (including following-start control), etc. Therefore, cooperative control for autonomous driving can be executed, which enables the vehicle to travel autonomously without relying on the driver's operation, etc.

[0382] For example, the microcomputer 12051 can classify three-dimensional object data on a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 has difficulty visually recognizing. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering through the drive system control unit 12010. The microcomputer 12051 can thus assist driving to avoid collisions.

[0383] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, this identification of a pedestrian is performed by a program for extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras and a program for performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed in a superimposed manner on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon representing the pedestrian or the like is displayed at a desired position.

[0384] In the above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Applying the technology according to the present disclosure to the imaging unit 12031 can obtain an image that is easier to view. Therefore, driver fatigue can be reduced.

[0385] Although the present disclosure has been described above with reference to the embodiments and modification examples, the content of the present disclosure is not limited to the above embodiments and the like, and can be modified in various ways. For example, the layer structure of the imaging element described in the foregoing embodiments is merely exemplary, and may further include other layers. In addition, the materials and thicknesses of each layer are also exemplary and are not limited to those described above.

[0386] In addition, in the foregoing embodiments and the like, the case where the amplification transistor 24 is a junctionless transistor has been described. However, as long as at least one of the reset transistor 23, the amplification transistor 24, and the selection transistor 25 is a junctionless transistor.

[0387] In addition, in the above second embodiment, the case where the amplification transistor 24 and the selection transistor 25 have a single gate electrode structure has been described. However, the amplification transistor 24 and the selection transistor 25 may have a double gate electrode structure.

[0388] In addition, in the above modification example 4, the case where the channel region 23C of the reset transistor 23 is provided on a single fin (fin F1) and the channel regions 24C and 25C of the amplification transistor 24 and the selection transistor 25 are provided on two fins (fins F2 and F3) has been described. However, the number of fins is not limited thereto.

[0389] The effects described in the foregoing embodiments and the like are merely exemplary. Other effects may be produced according to the technology of the present disclosure, or other effects may be further included.

[0390] Note that the present disclosure may have the following configuration. According to the solid-state imaging elements (1) and (2) and the imaging devices (1) and (2) having the following configuration, the output transistor includes a channel region having the same conductivity type (first conductivity type) as the source-drain region. This can reduce the noise caused by the carriers captured at the interface on the gate electrode side of the channel region. Therefore, the noise can be suppressed.

[0391] (1) A solid-state imaging element, comprising:

[0392] A first substrate including a photoelectric conversion portion and a transfer transistor electrically connected to the photoelectric conversion portion;

[0393] A second substrate disposed opposite to the first substrate and including an output transistor, the output transistor including a gate electrode, a channel region of a first conductivity type disposed opposite to the gate electrode, and a source-drain region of the first conductivity type adjacent to the channel region; and

[0394] A driving circuit that allows signal charges generated in the photoelectric conversion section to be output via the transfer transistor and the output transistor.

[0395] (2) The solid-state imaging device according to (1) above, wherein

[0396] the gate electrode has a flat plate shape.

[0397] (3) The solid-state imaging device according to (1) or (2) above, further comprising:

[0398] a third substrate that faces the first substrate, with the second substrate interposed between the third substrate and the first substrate, and the driving circuit is provided on the third substrate.

[0399] (4) A solid-state imaging device, comprising:

[0400] a photoelectric conversion section;

[0401] a transfer transistor electrically connected to the photoelectric conversion section;

[0402] an output transistor electrically connected to the transfer transistor and including a channel region of a first conductivity type, a gate electrode covering a plurality of surfaces of the channel region, and a source-drain region of the first conductivity type adjacent to the channel region; and

[0403] a driving circuit that allows signal charges generated in the photoelectric conversion section to be output via the transfer transistor and the output transistor.

[0404] (5) The solid-state imaging device according to (4) above, further comprising:

[0405] a first substrate including the photoelectric conversion section and the transfer transistor;

[0406] a second substrate provided opposite to the first substrate and including the output transistor; and

[0407] a third substrate that faces the first substrate, with the second substrate interposed between the third substrate and the first substrate, and the driving circuit is provided on the third substrate.

[0408] (6) The solid-state imaging device according to any one of (1) to (5) above, further comprising:

[0409] a gate insulating film between the gate electrode and the channel region.

[0410] (7) The solid-state imaging device according to any one of (1) to (6) above further includes:

[0411] A charge accumulation section to which signal charges generated in the photoelectric conversion section are transferred from the transfer transistor.

[0412] (8) The solid-state imaging device according to (7) above further includes:

[0413] An amplification transistor that outputs a signal according to the magnitude of the potential of the charge accumulation section;

[0414] A reset transistor that resets the potential of the charge accumulation section; and

[0415] A selection transistor that controls the output of the amplification transistor, where

[0416] At least one of the amplification transistor, the reset transistor, and the selection transistor is the output transistor.

[0417] (9) The solid-state imaging device according to any one of (1) to (8) above further includes:

[0418] A fin in which the channel region and the source-drain region are provided.

[0419] (10) In the solid-state imaging device according to (9) above,

[0420] A plurality of the channel regions and a plurality of the source-drain regions are continuously provided in the fin.

[0421] (11) In the solid-state imaging device according to any one of (1) to (4) above,

[0422] The gate electrode includes a first surface and an opposite second surface, and a third surface connecting the first surface and the second surface, and the channel region is between the first surface and the second surface.

[0423] (12) In the solid-state imaging device according to (11) above,

[0424] The gate electrode further includes a fourth surface opposite to the third surface, and the channel region is between the fourth surface and the third surface.

[0425] (13) In the solid-state imaging device according to any one of (1) to (12) above,

[0426] The gate electrode includes polysilicon of a second conductivity type.

[0427] (14) An imaging device, the imaging device including a solid-state imaging element, the solid-state imaging element including:

[0428] A first substrate including a photoelectric conversion portion and a transfer transistor electrically connected to the photoelectric conversion portion;

[0429] A second substrate disposed opposite to the first substrate and including an output transistor, the output transistor including a gate electrode, a channel region of a first conductivity type arranged to face the gate electrode, and a source-drain region of the first conductivity type adjacent to the channel region; and

[0430] A drive circuit that allows signal charges generated in the photoelectric conversion portion to be output via the transfer transistor and the output transistor.

[0431] (15) An imaging device, the imaging device including a solid-state imaging element, the solid-state imaging element including:

[0432] A photoelectric conversion portion;

[0433] A transfer transistor electrically connected to the photoelectric conversion portion;

[0434] An output transistor electrically connected to the transfer transistor and including a channel region of a first conductivity type, a gate electrode covering a plurality of surfaces of the channel region, and a source-drain region of the first conductivity type adjacent to the channel region; and

[0435] A drive circuit that allows signal charges generated in the photoelectric conversion portion to be output via the transfer transistor and the output transistor.

[0436] This application claims the benefit of Japanese Patent Application No. 2018-203704, filed with the Japan Patent Office on October 30, 2018, the entire contents of which are incorporated herein by reference.

[0437] Those skilled in the art should understand that various deformations, combinations, sub-combinations, and changes can be made according to design requirements and other factors, as long as they are within the scope of protection of the appended claims or their equivalents.

Claims

1. A solid-state imaging device, comprising: a first substrate including a photoelectric conversion section and a transfer transistor electrically connected to the photoelectric conversion section; a second substrate disposed opposite to the first substrate and including an output transistor, the output transistor including a gate electrode, a channel region of a first conductivity type disposed opposite to the gate electrode, and a source-drain region of the first conductivity type adjacent to the channel region; and a drive circuit that allows signal charges generated in the photoelectric conversion section to be output via the transfer transistor and the output transistor, wherein the gate electrode includes a first surface and an opposite second surface and a third surface connecting the first surface and the second surface, and the channel region is interposed between the first surface and the second surface, wherein a size of the channel region in a depth direction is larger than a size of the source-drain region in the depth direction, wherein more than half of the size of the channel region in the depth direction is covered by the first surface and the second surface, wherein the impurity concentration of the channel region is 5×10 17 cm -3 ~1×10 19 cm -3 , and wherein the size of the channel region in the depth direction is about 50 nm to 500 nm.

2. The solid-state imaging device according to claim 1, further comprising: a third substrate opposite to the first substrate, the second substrate being interposed between the third substrate and the first substrate, and the drive circuit being provided on the third substrate.

3. The solid-state imaging device according to claim 1, further comprising: a gate insulating film between the gate electrode and the channel region.

4. The solid-state imaging device according to claim 1, further comprising: a charge accumulation section, and signal charges generated in the photoelectric conversion section are transferred from the transfer transistor to the charge accumulation section.

5. The solid-state imaging device according to claim 4, further comprising: an amplification transistor that outputs a signal according to a magnitude of a potential of the charge accumulation section; a reset transistor that resets the potential of the charge accumulation section; and a selection transistor that controls an output of the amplification transistor, wherein at least one of the amplification transistor, the reset transistor, and the selection transistor is the output transistor.

6. The solid-state imaging device according to claim 1, further comprising: a fin in which the channel region and the source-drain region are provided.

7. The solid-state imaging device according to claim 6, wherein in the fin, a plurality of the channel regions and a plurality of source-drain regions are continuously provided.

8. The solid-state imaging device according to claim 1, wherein the gate electrode further includes a fourth surface opposite to the third surface, and the channel region is interposed between the fourth surface and the third surface.

9. The solid-state imaging device according to claim 1, wherein the gate electrode includes polysilicon of a second conductivity type.

10. A solid-state imaging device, comprising: a photoelectric conversion section; a transfer transistor electrically connected to the photoelectric conversion section; An output transistor electrically connected to the transfer transistor and including a channel region of a first conductivity type, a gate electrode covering a plurality of surfaces of the channel region, and a source-drain region of the first conductivity type adjacent to the channel region; and A drive circuit that allows signal charges generated in the photoelectric conversion unit to be output via the transfer transistor and the output transistor, wherein the gate electrode includes a first surface and an opposite second surface and a third surface connecting the first surface and the second surface, and the channel region is interposed between the first surface and the second surface, wherein a size of the channel region in a depth direction is larger than a size of the source-drain region in the depth direction, wherein more than half of the size of the channel region in the depth direction is covered by the first surface and the second surface, wherein the impurity concentration in the channel region is 5×10 17 cm -3 ~1×10 19 cm -3 , and wherein the size of the channel region in the depth direction is about 50 nm to 500 nm.

11. The solid-state imaging device according to claim 10, further comprising: A first substrate including the photoelectric conversion unit and the transfer transistor; A second substrate disposed opposite to the first substrate and including the output transistor; and A third substrate opposite to the first substrate, the second substrate being interposed between the third substrate and the first substrate, and the drive circuit being provided on the third substrate.

12. An imaging device including the solid-state imaging device according to any one of claims 1-11.

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