Solid-state imaging device and imaging device

Abstract

An imaging device includes a photoelectric conversion region that converts incident light into electric charge. The imaging device includes a first readout circuit coupled to the photoelectric conversion region at a first position and a second readout circuit including a portion coupled to the photoelectric conversion region at a second position. The second readout circuit is configured to control the first readout circuit, the first position and the second position being on the same side of the photoelectric conversion region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Japanese Priority Patent Application JP 2018-201132 filed on October 25, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a solid-state imaging device and an imaging device. Background Art

[0004] In the prior art, a synchronous solid-state imaging device that captures image data synchronously with a synchronization signal such as a vertical synchronization signal has been used in an imaging device or the like. In a typical synchronous solid-state imaging device, it is difficult to obtain image data in each synchronization signal cycle (for example, every 1 / 60 second), and therefore, it is difficult to cope with situations requiring relatively high-speed processing in fields related to transportation, robots, and the like. In this regard, an asynchronous solid-state imaging device is proposed, in which a detection circuit is provided for each pixel to detect in real time a situation in which the amount of light received as an address event exceeds a threshold value. An asynchronous solid-state imaging device that detects an address event for each pixel is also referred to as a dynamic vision sensor (DVS).

[0005] Reference List

[0006] Patent Literature

[0007] PTL 1: JP 2016-533140A Summary of the invention

[0008] Technical issues

[0009] However, in DVS, in addition to the circuit configuration for reading the pixel signal whose voltage value corresponds to the light receiving amount, a circuit configuration for detecting the address event must be provided, so the occupancy rate of the light receiving element on the light receiving surface is reduced. As a result, there is a problem that the quantum efficiency of the incident light (hereinafter referred to as "light receiving efficiency") deteriorates.

[0010] Therefore, the present disclosure provides a solid-state imaging apparatus and an imaging apparatus capable of improving light receiving efficiency.

[0011] Solutions to technical problems

[0012] According to one aspect of the present disclosure, there is provided an imaging device, which includes: a photoelectric conversion region that converts incident light into electric charge; a first readout circuit that is coupled to the photoelectric conversion region at a first position; and a second readout circuit that includes a portion coupled to the photoelectric conversion region at a second position, the second readout circuit being configured to control the first readout circuit, and the first position and the second position are at the same side of the photoelectric conversion region. The first position and the second position are at the same distance from the center of the edge of the photoelectric conversion region that defines the side. The first position is at a first corner of the photoelectric conversion region, and the second position is at a second corner of the photoelectric conversion region. The first readout circuit includes a first transistor having a first gate at the first position, and the second readout circuit includes a second transistor having a second gate at the second position. The first readout circuit includes a plurality of third transistors coupled to the first transistor. The second readout circuit includes a plurality of fourth transistors coupled to the second transistor. The number of the plurality of fourth transistors is greater than the number of the plurality of third transistors. The plurality of fourth transistors include a first group of transistors and a second group of transistors arranged along a first direction, and the first group of transistors is adjacent to the second group of transistors in a second direction perpendicular to the first direction. The second group of transistors is further away from the side of the photoelectric conversion region than the first group of transistors. The plurality of third transistors are arranged along the first direction. According to one aspect of the present disclosure, there is provided an imaging device, comprising: a first pixel, comprising: a first photoelectric conversion region, which converts a first incident light into a first charge; a first readout circuit, which is coupled to the first photoelectric conversion region at a first position; and a second readout circuit, which includes a portion coupled to the first photoelectric conversion region at a second position. The second readout circuit is configured to control the first readout circuit. The first position and the second position are on the same first side of the first photoelectric conversion region. The imaging device comprises a second pixel, which is adjacent to the first pixel in the first direction. The second pixel comprises a second photoelectric conversion region, which converts a second incident light into a second charge. The second pixel comprises a third readout circuit, which is coupled to the second photoelectric conversion region at a third position. The second pixel comprises a fourth readout circuit, which includes a portion coupled to the second photoelectric conversion region at a fourth position. The fourth readout circuit is configured to control the third readout circuit. The third position and the fourth position are on the same second side of the second photoelectric conversion region. The first readout circuit and the third readout circuit are located on opposite sides of the second photoelectric conversion region. The first pixel and the second pixel are arranged so that the second photoelectric conversion region is between the first readout circuit and the second readout circuit.The imaging device includes a third pixel adjacent to the first pixel in a second direction perpendicular to the first direction, and the third pixel includes a third photoelectric conversion region that converts a third incident light into a third charge. The third pixel includes a fifth readout circuit that is coupled to the third photoelectric conversion region at a fifth position. The third pixel includes a sixth readout circuit that includes a portion coupled to the third photoelectric conversion region at a sixth position. The sixth readout circuit is configured to control the fifth readout circuit. The fifth position and the sixth position are on the same third side of the third photoelectric conversion region. The imaging device includes a fourth pixel adjacent to the second pixel in the second direction. The fourth pixel includes a fourth photoelectric conversion region that converts a fourth incident light into a fourth charge. The fourth pixel includes a seventh readout circuit that is coupled to the fourth photoelectric conversion region at a seventh position. The fourth pixel includes an eighth readout circuit that includes a portion coupled to the fourth photoelectric conversion region at an eighth position. The eighth readout circuit is configured to control the seventh readout circuit. The seventh position and the eighth position are on the same fourth side of the fourth photoelectric conversion region. The third pixel and the fourth pixel are arranged so that the third photoelectric conversion region is between the seventh readout circuit and the eighth readout circuit. The first pixel, the second pixel, the third pixel and the fourth pixel are arranged so that the second readout circuit and the fifth readout circuit are between the second photoelectric conversion region and the fourth photoelectric conversion region. At least one of the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region and the fourth photoelectric conversion region includes a photogate, which divides the corresponding photoelectric conversion region into a first part and a second part. Wherein, the photogate is located in a central area of ​​the photoelectric conversion region. According to one aspect of the present disclosure, there is provided an imaging device, which includes a photoelectric conversion region, which converts incident light into electric charge. The imaging device includes a first readout circuit, the first readout circuit including a first gate of a first transistor coupled to the photoelectric conversion region at a first position. The imaging device includes a second readout circuit, the second readout circuit including a second gate of a second transistor coupled to the photoelectric conversion region at a second position. The second readout circuit is configured to control the first readout circuit. The first position and the second position are located in the same half of the photoelectric conversion region.According to one aspect of the present disclosure, a solid-state imaging device includes: a photoelectric conversion element that generates an electric charge corresponding to an amount of light received; a first transistor that is connected to the photoelectric conversion element; second to fourth transistors that are connected to the first transistor and are arranged in a straight line; a fifth transistor that is connected to the photoelectric conversion element at a position different from that of the first transistor; sixth and seventh transistors that are connected to the fifth transistor and are arranged in a straight line; and eighth and ninth transistors that are arranged in an array parallel to the sixth transistor and the seventh transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram showing a schematic configuration example of a solid-state imaging apparatus and an imaging apparatus according to the first embodiment.

[0014] Figure 2 is a diagram showing an example of a laminated structure of the solid-state image pickup device according to the first embodiment.

[0015] Figure 3 is a block diagram showing an example of a functional configuration of a solid-state imaging apparatus according to the first embodiment.

[0016] Figure 4 is a schematic diagram showing an array example of unit pixels according to the first embodiment in the case where the Bayer array is adopted in the color filter array.

[0017] Figure 5 is a circuit diagram showing a schematic configuration example of a unit pixel according to the first embodiment.

[0018] Figure 6 is a block diagram showing a schematic configuration example of an address event detection unit according to the first embodiment.

[0019] Figure 7 : is a circuit diagram showing a schematic configuration example of a subtractor and a quantizer according to the first embodiment.

[0020] Figure 8 is a block diagram showing a schematic configuration example of a column ADC according to the first embodiment.

[0021] Fig. 9 is a timing chart showing an example of the operation of the solid-state imaging apparatus according to the first embodiment.

[0022] Fig.10 is a flowchart showing an example of the operation of the solid-state imaging apparatus according to the first embodiment.

[0023] Fig.11 is a top view showing a schematic configuration example of an upper layer circuit according to a first layout example of the first embodiment.

[0024] Fig.12 It is shown along Fig.11 A diagram showing an example of a cross-sectional structure of a unit pixel in the case where the solid-state imaging device is cut along plane AA in FIG.

[0025] Fig.13 1 is a schematic diagram showing an array example of an upper layer circuit in a pixel array unit according to the first layout example of the first embodiment.

[0026] Fig.14 : is a diagram showing a modification of the cross-sectional structure of the unit pixel according to the first layout example of the first embodiment.

[0027] Fig.15 is a top view showing a schematic configuration example of an upper layer circuit according to a second layout example of the first embodiment.

[0028] Fig.16 : is a schematic diagram showing an array example of upper layer circuits in a pixel array unit according to a second layout example of the first embodiment.

[0029] Fig.17 is a top view showing a schematic configuration example of an upper layer circuit according to a third layout example of the first embodiment.

[0030] Fig.18 : is a schematic diagram showing an array example of upper layer circuits in a pixel array unit according to a third layout example of the first embodiment.

[0031] Fig.19 is a top view showing a schematic configuration example of an upper layer circuit according to a fourth layout example of the first embodiment.

[0032] Fig. 20 : is a schematic diagram showing a first array example of upper layer circuits in a pixel array unit according to the fourth layout example of the first embodiment.

[0033] Fig.21 : is a schematic diagram showing a first array example of upper layer circuits in a pixel array unit according to the fourth layout example of the first embodiment.

[0034] Fig. 22 is a top view showing a schematic configuration example of an upper layer circuit according to a fifth layout example of the first embodiment.

[0035] Fig.23 : is a schematic diagram showing an array example of upper layer circuits in a pixel array unit according to a fifth layout example of the first embodiment.

[0036] Fig.24is a top view showing a schematic configuration example of an upper layer circuit according to a sixth layout example of the first embodiment.

[0037] Fig.25 : is a schematic diagram showing an array example of upper layer circuits in a pixel array unit according to a sixth layout example of the first embodiment.

[0038] Fig.26 is a circuit diagram showing a schematic configuration example of a unit pixel according to the second embodiment.

[0039] Fig. 27 is a timing chart showing an example of the operation of the solid-state imaging apparatus according to the second embodiment.

[0040] Fig.28 is a top view showing a schematic configuration example of an upper layer circuit according to a first layout example of the second embodiment.

[0041] Fig.29 It is shown Fig.28 sectional view of a schematic configuration example along plane BB.

[0042] Fig.30 is an energy band diagram showing the potential (off state) of the photoelectric conversion element according to the second embodiment.

[0043] Fig.31 is an energy band diagram showing the potential (monitoring state) of the photoelectric conversion element according to the second embodiment.

[0044] Fig.32 is an energy band diagram showing the potential (accumulation state) of the photoelectric conversion element according to the second embodiment.

[0045] Fig.33 is a top view showing a schematic configuration example of an upper layer circuit according to a second layout example of the second embodiment.

[0046] Fig.34 : is a top view showing a schematic configuration example of an upper layer circuit according to a third layout example of the second embodiment.

[0047] Fig.35 : is a top view showing a schematic configuration example of an upper layer circuit according to a modification example of the third layout example of the second embodiment.

[0048] Fig.36 is a top view showing a schematic configuration example of an upper layer circuit according to a fourth layout example of the second embodiment.

[0049] Fig.37 : is a top view showing a schematic configuration example of an upper layer circuit according to a fifth layout example of the second embodiment.

[0050] Fig.38 : is a top view showing a schematic configuration example of an upper layer circuit according to a sixth layout example of the second embodiment.

[0051] Fig.39 is a circuit diagram showing a schematic configuration example of a unit pixel according to the third embodiment.

[0052] Fig.40 is a top view showing a schematic configuration example of an upper layer circuit according to a first layout example of the third embodiment.

[0053] Fig.41 is a top view of a photoelectric conversion element according to the third embodiment.

[0054] Fig.42 is an energy band diagram showing the potential of the photoelectric conversion element (plane CC) according to the third embodiment.

[0055] Fig.43 is an energy band diagram showing the potential of the photoelectric conversion element (plane DD) according to the third embodiment.

[0056] Fig.44 is an energy band diagram showing the potential of the photoelectric conversion element (plane EE) according to the third embodiment.

[0057] Fig.45 : is a top view showing a schematic configuration example of an upper layer circuit according to a second layout example of the third embodiment.

[0058] Fig.46 : is a top view showing a schematic configuration example of an upper layer circuit according to a third layout example of the third embodiment.

[0059] Fig.47 is a top view showing a schematic configuration example of an upper layer circuit according to a fourth layout example of the third embodiment.

[0060] Fig.48 is a top view showing a schematic configuration example of an upper layer circuit according to a fifth layout example of the third embodiment.

[0061] Fig.49 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0062] Fig.50 2 is a diagram showing an example of installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0063] Hereinafter, embodiments of the present disclosure will be described in detail based on the accompanying drawings. In addition, in the following embodiments, the same reference numerals will be assigned to the same parts, and repeated descriptions thereof will be omitted.

[0064] In addition, the present disclosure will be described according to the following item order.

[0065] 1. Introduction

[0066] 2. First embodiment

[0067] 2.1 Example of the construction of an imaging device

[0068] 2.2 Example of a solid-state imaging device structure

[0069] 2.2.1 Example of laminated structure of solid-state imaging device

[0070] 2.2.2 Example of functional configuration of solid-state imaging device

[0071] 2.3 Example of a pixel array unit

[0072] 2.4 Example of unit pixel construction

[0073] 2.5 Example of Address Event Detection Unit Construction

[0074] 2.5.1 Example of the construction of a current-voltage conversion unit

[0075] 2.5.2 Example of Subtractor and Quantizer Construction

[0076] 2.5.3 Example of Column ADC Construction

[0077] 2.6 Operation Example of Solid-State Image Pickup Device

[0078] 2.6.1 Timing diagram

[0079] 2.6.2 Flowchart

[0080] 2.7 Layout Example of Unit Pixels

[0081] 2.7.1 First layout example

[0082] 2.7.1.1 Array Example

[0083] 2.7.1.2 Variation of the First Layout Example

[0084] 2.7.2 Second layout example

[0085] 2.7.2.1 Array Example

[0086] 2.7.3 Example of the third layout

[0087] 2.7.3.1 Array Example

[0088] 2.7.4 Fourth layout example

[0089] 2.7.4.1 First array example

[0090] 2.7.4.2 Second Array Example

[0091] 2.7.5 Fifth layout example

[0092] 2.7.5.1 Array Example

[0093] 2.7.6 Sixth layout example

[0094] 2.7.6.1 Array Example

[0095] 2.8 Function and Effect

[0096] 3. Second embodiment

[0097] 3.1 Example of unit pixel construction

[0098] 3.2 Operation Example of Solid-State Image Pickup Device

[0099] 3.3 Layout Example of Unit Pixels

[0100] 3.3.1 First layout example

[0101] 3.3.1.1 Regarding the potential of the photoelectric conversion element

[0102] 3.3.2 Second layout example

[0103] 3.3.3 Example of the third layout

[0104] 3.3.3.1 Variations

[0105] 3.3.4 Fourth layout example

[0106] 3.3.5 Fifth layout example

[0107] 3.3.6 Sixth layout example

[0108] 3.4 Function and Effect

[0109] 4. Third embodiment

[0110] 4.1 Example of unit pixel construction

[0111] 4.2 Example of unit pixel layout

[0112] 4.2.1 First layout example

[0113] 4.2.1.1 Regarding the potential of the photoelectric conversion element

[0114] 4.2.2 Second layout example

[0115] 4.2.3 Example of the third layout

[0116] 4.2.4 Fourth layout example

[0117] 4.2.5 Fifth layout example

[0118] 4.3 Function and Effect

[0119] 5. Application examples for mobile objects

[0120] 1. Introduction

[0121] A typical dynamic vision sensor (DVS) adopts a so-called event-driven driving method, in which the presence or absence of an address event is detected for each unit pixel, and when the address event is detected, a pixel signal is read out from the unit pixel where the address event has occurred.

[0122] In addition, the unit pixel in this specification means the minimum unit of a pixel including one photoelectric conversion element (also referred to as a "light receiving element"), and corresponds to each point in the image data read out from the image sensor as an example. In addition, the address event means an event that occurs for each address that can be assigned to each of a plurality of unit pixels arranged in a two-dimensional grid, and examples thereof include an event in which the current value of the photocurrent based on the charge generated in the photoelectric conversion element or the amount of change thereof exceeds an arbitrary constant threshold value.

[0123] 2. First embodiment

[0124] First, a solid-state image pickup apparatus and an image pickup apparatus according to a first embodiment will be described in detail with reference to the drawings.

[0125] 2.1 Example of the construction of an imaging device

[0126] Figure 1 1 is a block diagram showing a schematic configuration example of a solid-state imaging device and an imaging device according to a first embodiment. Figure 1 As shown, for example, the imaging apparatus 100 includes an imaging lens 110, a solid-state imaging apparatus 200, a recording unit 120, and a control unit 130. As the imaging apparatus 100, a camera installed in an industrial robot, a vehicle-mounted camera, or the like is assumed.

[0127] The imaging lens 110 is an example of an optical system that converges incident light and images an image of the incident light onto a light-receiving surface of the solid-state imaging device 200. The light-receiving surface is a surface on which a photoelectric conversion element is arranged in the solid-state imaging device 200. The solid-state imaging device 200 performs photoelectric conversion on the incident light to generate image data. In addition, the solid-state imaging device 200 performs predetermined signal processing such as noise removal and white balance adjustment on the generated image data. The result obtained by the signal processing and the detection signal indicating whether an address event occurs are output to the recording unit 120 through the signal line 209. In addition, a method of generating a detection signal indicating whether an address event occurs will be described later.

[0128] The recording unit 120 is configured by, for example, a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like, and records data input from the solid-state imaging device 200 .

[0129] The control unit 130 is constituted by, for example, a central processing unit (CPU) or the like, and outputs various instructions through a signal line 139 to control the respective units such as the solid-state imaging device 200 in the imaging device 100 .

[0130] 2.2 Example of the construction of a solid-state imaging device

[0131] Next, a configuration example of the solid-state imaging apparatus 200 will be described in detail with reference to the drawings.

[0132] 2.2.1 Example of laminated structure of solid-state imaging device

[0133] Figure 2 1 is a diagram showing an example of a laminated structure of a solid-state imaging device according to the first embodiment. Figure 2 As shown, the solid-state imaging device 200 has a structure in which a light receiving chip 201 and a logic chip 202 are vertically laminated. In the bonding of the light receiving chip 201 and the logic chip 202, for example, so-called direct bonding can be used, in which the bonding surface of the chip is flattened and the chips are laminated using inter-electron force. However, it is not limited to this, and for example, so-called Cu-Cu bonding, bump bonding, etc. can also be used, in which a copper (Cu) electrode pad formed on the bonding surface is bonded.

[0134] In addition, the optical receiving chip 201 and the logic chip 202 are electrically connected to each other through, for example, a connection portion such as a through silicon via (TSV) penetrating a semiconductor substrate. In connection using TSV, for example, a so-called double TSV method in which two TSVs including a TSV formed in the optical receiving chip 201 and a TSV formed from the optical receiving chip 201 to the logic chip 202 are connected to each other on the chip outer surface and a so-called shared TSV method in which the optical receiving chip 201 and the logic chip 202 are connected with a TSV penetrating both chips can be adopted.

[0135] However, when Cu-Cu bonding or bump bonding is used in bonding the light receiving chip 201 and the logic chip 202 , the light receiving chip 201 and the logic chip 202 are electrically connected through the Cu-Cu joint or the bump joint.

[0136] 2.2.2 Example of functional configuration of solid-state imaging device

[0137] Figure 3 1 is a block diagram showing an example of a functional configuration of a solid-state imaging device according to the first embodiment. Figure 3 As shown, the solid-state imaging device 200 includes a driving circuit 211 , a signal processing unit 212 , an arbitrator 213 , a column ADC 220 , and a pixel array unit 300 .

[0138] A plurality of unit cells are arranged in a two-dimensional lattice shape in the pixel array unit 300. The details of the unit pixel will be described later. For example, each unit pixel includes a photoelectric conversion element such as a photodiode and a circuit (hereinafter referred to as a pixel circuit or a pixel signal generating unit) that generates a pixel signal having a voltage value corresponding to the amount of charge generated in the photoelectric conversion element. Here, the pixel circuit can be shared by a plurality of photoelectric conversion elements. In this case, the unit pixel includes a photoelectric conversion element and a shared pixel circuit.

[0139] A plurality of unit pixels are arranged in a two-dimensional lattice in the pixel array unit 300. A plurality of unit pixels may be grouped into a plurality of pixel blocks, each pixel block including a predetermined number of unit pixels. Hereinafter, a set of unit pixels or pixel blocks arranged in a horizontal direction is referred to as a "row", and a set of unit pixels or pixel blocks arranged in a direction orthogonal to a row is referred to as a "column".

[0140] Each unit pixel generates a charge corresponding to the amount of light received by the photoelectric conversion element. In addition, the unit pixel detects whether an address event occurs based on whether the current value of the current generated by the charge generated in the photoelectric conversion element (hereinafter referred to as photocurrent) or the amount of change thereof exceeds a predetermined threshold. In addition, when an address event is triggered, the unit pixel outputs a request to read out a pixel signal of a voltage value corresponding to the amount of light received by the photoelectric conversion element to the arbitrator 213.

[0141] The driving circuit 211 drives each unit pixel and allows each unit pixel to output a pixel signal to the column ADC 220 .

[0142] The arbitrator 213 arbitrates the request from each unit pixel and transmits a predetermined response to the unit pixel that issued the request based on the arbitration result. The unit pixel that receives the response provides a detection signal indicating whether an address event occurs (hereinafter referred to as an "address event detection signal") to the drive circuit 211 and the signal processing unit 212.

[0143] For each unit pixel column, the column ADC 220 converts the analog pixel signal from the column into a digital signal. In addition, the column ADC 220 provides the digital signal generated by the conversion to the signal processing unit 212.

[0144] The signal processing unit 212 performs predetermined signal processing such as correlated double sampling (CDS) processing (noise removal) and white balance adjustment on the digital signal transmitted from the column ADC 220. In addition, the signal processing unit 212 provides the signal processing result and the address event detection signal to the recording unit 120 through the signal line 209.

[0145] 2.3 Example of a pixel array unit

[0146] exist Figure 3 In the illustrated configuration, for example, the pixel array unit 300 is composed of components of unit pixels that receive wavelength components required for reconstructing colors. For example, in the case of reconstructing colors based on three primary colors of RGB, in the pixel array unit 300, unit pixels that receive red (R) light, unit pixels that receive green (G) light, and unit pixels that receive blue (B) light are arranged in a predetermined color filter array.

[0147] Examples of the color filter array include various arrays such as a 2×2 pixel Bayer array, a 3×3 pixel color filter array adopted in an X-Trans (registered trademark) CMOS sensor (hereinafter, also referred to as an “X-Trans (registered trademark) type array”), a 4×4 pixel quad Bayer array (also referred to as a “quad array”), and a 4×4 pixel color filter in which a white RGB color filter is combined with a Bayer array (hereinafter, also referred to as a “white RGB array”). Here, in the following description, a case where a Bayer array is adopted as a color filter array will be taken as an example.

[0148] Figure 4 2 is a schematic diagram showing an example of an array of unit pixels in the case where the Bayer array is used in the color filter array. Figure 4As shown, in the case of adopting the Bayer array as the color filter array, in the pixel array unit 300, a basic pattern 310A is repeatedly arranged in the column direction and the row direction, and the basic pattern 310A includes four unit pixels of a total of 2×2 pixels. For example, the basic pattern 310A is composed of a unit pixel 310R including a red (R) color filter, a unit pixel 310Gr including a green (Gr) color filter, a unit pixel 310Gb including a green (Gb) color filter, and a unit pixel 310B including a blue (B) color filter.

[0149] 2.4 Example of unit pixel construction

[0150] Next, a configuration example of the unit pixel 310 will be described. Figure 5 1 is a circuit diagram showing a schematic configuration example of a unit pixel according to the first embodiment. Figure 5 As shown, the unit pixel 310 includes, for example, a pixel signal generating unit (or readout circuit) 320, a light receiving unit 330, and an address event detecting unit (or readout circuit) 400. According to at least one example embodiment, the readout circuit 400 is configured to control the readout circuit 320 based on the charge generated by the photoelectric conversion element (or photoelectric conversion region) 333. In addition, Figure 5 The logic circuit 210 includes, for example, Figure 3 The driving circuit 211, the signal processing unit 212 and the logic circuit of the arbiter 213 are shown in FIG.

[0151] For example, the light receiving unit 330 includes a transfer transistor (first transistor) 331, an overflow gate (OFG) transistor (fifth transistor) 332, and a photoelectric conversion element 333. The transmission signal TRG transmitted from the drive circuit 211 is supplied to the gate of the transfer transistor 331 of the light receiving unit 330, and the control signal OFG transmitted from the drive circuit 211 is supplied to the gate of the OFG transistor 332. The output through the transfer transistor 331 of the light receiving unit 330 is connected to the pixel signal generating unit 320, and the output through the OFG transistor 332 is connected to the address event detecting unit 400.

[0152] For example, the pixel signal generating unit 320 includes a reset transistor (second transistor) 321 , an amplifying transistor (third transistor) 322 , a selecting transistor (fourth transistor) 323 , and a floating diffusion layer (FD) 324 .

[0153] The transfer transistor 331 and the OFG transistor 332 of the light receiving unit 330 are configured, for example, by using an N-type metal oxide semiconductor (MOS) transistor (hereinafter referred to as an "NMOS transistor"). Similarly, the reset transistor 321, the amplifying transistor 322, and the selecting transistor 323 of the pixel signal generating unit 320 are configured, for example, by using NMOS transistors.

[0154] For example, the address event detection unit 400 includes a current voltage conversion unit 410 and a subtractor 430. However, the address event detection unit 400 is also provided with a buffer, a quantizer, and a transmission unit. Figure 6 etc. to describe the details of the address event detection unit 400.

[0155] In this configuration, the photoelectric conversion element 333 of the light receiving unit 330 performs photoelectric conversion on the incident light to generate charges. The transfer transistor 331 transfers the charges generated in the photoelectric conversion element 333 to the floating diffusion layer 324 according to the transfer signal TRG. The OFG transistor 332 provides an electrical signal (photocurrent) based on the charges generated in the photoelectric conversion element 333 to the address event detection unit 400 according to the control signal OFG.

[0156] The floating diffusion layer 324 accumulates the charge transferred from the photoelectric conversion element 333 through the transfer transistor 331. The reset transistor 321 releases (initializes) the charge accumulated in the floating diffusion layer 324 according to the reset signal transmitted from the drive circuit 211. The amplifier transistor 322 allows a pixel signal having a voltage value corresponding to the charge amount of the charge accumulated in the floating diffusion layer 324 to appear in the vertical signal line VSL. The selection transistor 323 switches the connection between the amplifier transistor 322 and the vertical signal line VSL according to the selection signal SEL sent from the drive circuit 211. In addition, the analog pixel signal appearing in the vertical signal line VSL is read out by the column ADC 220 and converted into a digital pixel signal.

[0157] When the control unit 130 gives an instruction for starting address event detection, the drive circuit 211 in the logic circuit 210 outputs a control signal OFG to set the OFG transistors 332 of all light receiving units 330 in the pixel array unit 300 to a conductive state. With this arrangement, the photocurrent generated in the photoelectric conversion element 333 of the light receiving unit 330 is provided to the address event detection unit 400 of each unit pixel 310 through the OFG transistor 332.

[0158] When the occurrence of an address event is detected based on the photocurrent from the light receiving unit 330, the address event detection unit 400 of each unit pixel 310 outputs a request to the arbitrator 213. In this regard, the arbitrator 213 arbitrates the request transmitted from each unit pixel 310, and transmits a predetermined response to the unit pixel 310 that issued the request based on the arbitration result. The unit pixel 310 that receives the response provides a detection signal indicating whether the address event occurs to the driving circuit 211 and the signal processing unit 212 in the logic circuit 210 (hereinafter referred to as an "address event detection signal").

[0159] The driving circuit 211 sets the OFG transistor 332 in the unit pixel 310 as the supply source of the address event detection signal to an off state. With this arrangement, the photocurrent supply from the light receiving unit 330 to the address event detection unit 400 in the unit pixel 310 is stopped.

[0160] Next, the drive circuit 211 sets the transfer transistor 331 in the light receiving unit 330 of the unit pixel 310 to the on state through the transfer signal TRG. With this arrangement, the charge generated in the photoelectric conversion element 333 of the light receiving unit 330 is transferred to the floating diffusion layer 324 through the transfer transistor 331. In addition, a pixel signal having a voltage value corresponding to the charge amount of the charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL connected to the selection transistor 323 of the pixel signal generating unit 320.

[0161] As described above, in the solid-state imaging device 200 , the pixel signal SIG is output to the column ADC 220 from the unit pixel 310 in which the occurrence of the address event is detected.

[0162] In addition, for example, two logarithmic (LG) transistors (sixth and seventh transistors) 411 and 414 and two amplifying transistors (eighth and ninth transistors) 412 and 413 in the current-voltage conversion unit 410 of the light receiving unit 330, the pixel signal generating unit 320, and the address event detecting unit 400 are arranged, for example, Figure 2 The light receiving chip 201 shown in the figure is provided, and the other structures are arranged in the logic chip 202 bonded to the light receiving chip 201 by, for example, Cu-Cu bonding. Therefore, in the following description, in the unit pixel 310, the structure arranged in the light receiving chip 201 is referred to as an "upper layer circuit", and the two LG transistors 411 and 414 and the two amplifying transistors 412 and 413 in the current voltage conversion unit 410 are referred to as an "upper layer detection circuit 410A".

[0163] 2.5 Example of the construction of the address event detection unit

[0164] Figure 61 is a block diagram showing a schematic configuration example of an address event detection unit according to the first embodiment. Figure 6 As shown, the address event detection unit 400 includes a current-voltage conversion unit 410 , a buffer 420 , a subtractor 430 , a quantizer 440 , and a transmission unit 450 .

[0165] The current-voltage conversion unit 410 converts the photocurrent from the light receiving unit 330 into a logarithmic voltage signal and provides the voltage signal generated by the conversion to the buffer 420 .

[0166] The buffer 420 corrects the voltage signal transmitted from the current-voltage conversion unit 410 and outputs the corrected voltage signal to the subtractor 430 .

[0167] The subtractor 430 reduces the voltage level of the voltage signal transmitted from the buffer 420 according to the row driving signal transmitted from the driving circuit 211 , and provides the reduced voltage signal to the quantizer 440 .

[0168] The quantizer 440 quantizes the voltage signal transmitted from the subtractor 430 into a digital signal, and outputs the digital signal generated by the quantization to the transmission unit 450 as a detection signal.

[0169] The transmission unit 450 transmits the detection signal transmitted from the quantizer 440 to the signal processing unit 212, etc. For example, when the occurrence of an address event is detected, the transmission unit 450 provides a request for transmitting the address event detection signal from the transmission unit 450 to the driving circuit 211 and the signal processing unit 212 to the arbitrator 213. In addition, when a response to the request is received from the arbitrator 213, the transmission unit 450 provides the detection signal to the driving circuit 211 and the signal processing unit 212.

[0170] 2.5.1 Example of the construction of a current-voltage conversion unit

[0171] For example, Figure 6 The current-voltage conversion unit 410 in the configuration shown includes two LG transistors 411 and 414, two amplifying transistors 412 and 413, and a constant current circuit 415. Figure 5 shown.

[0172] For example, the source of the LG transistor 411 and the gate of the amplifying transistor 413 are connected to the drain of the OFG transistor 332 of the light receiving unit 330. In addition, for example, the drain of the LG transistor 411 is connected to the source of the LG transistor 414 and the gate of the amplifying transistor 412. For example, the drain of the LG transistor 414 is connected to the power supply terminal VDD.

[0173] In addition, for example, the source of the amplifier transistor 413 is grounded, and the drain thereof is connected to the gate of the LG transistor 411 and the source of the amplifier transistor 412. For example, the drain of the amplifier transistor 412 is connected to the power supply terminal VDD through the constant current circuit 415. For example, the constant current circuit 415 is composed of a load MOS transistor such as a p-type MOS transistor.

[0174] In this connection relationship, a ring-shaped source follower circuit is formed. Through this arrangement, the photocurrent from the light receiving unit 330 is converted into a voltage signal corresponding to the logarithmic value of its charge amount. In addition, for example, the LG transistors 411 and 414 and the amplifying transistors 412 and 413 can be respectively composed of NMOS transistors.

[0175] 2.5.2 Construction Examples of Subtractors and Quantizers

[0176] Figure 7 1 is a circuit diagram showing a schematic configuration example of a subtractor and a quantizer according to the first embodiment. Figure 7 As shown, the subtractor 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. In addition, the quantizer 440 includes a comparator 441.

[0177] One end of the capacitor 431 is connected to the output terminal of the buffer 420, and the other end is connected to the input terminal of the inverter 432. The capacitor 433 is connected in parallel to the inverter 432. The switch 434 opens or closes a path connecting both ends of the capacitor 433 according to a row driving signal.

[0178] The inverter 432 inverts the voltage signal input through the capacitor 431. The inverter 432 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 441.

[0179] When the switch 434 is turned on, the voltage signal Vinit is input to the buffer 420 side of the capacitor 431. In addition, the opposite side becomes a virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacitance of the capacitor 431 is set to C1, the potential Qinit accumulated in the capacitor 431 is expressed by the following expression (1). On the other hand, both ends of the capacitor 433 are short-circuited, so its accumulated charge becomes zero.

[0180] Qinit=C1×Vinit (1)

[0181] Next, when considering a case where the switch 434 is turned off and the voltage of the capacitor 431 on the buffer 420 side changes and reaches Vafter, the charge Qafter accumulated in the capacitor 431 is expressed by the following expression (2).

[0182] Qafter=C1×Vafter (2)

[0183] On the other hand, when the output voltage is set to Vout, the charge Q2 accumulated in the capacitor 433 is expressed by the following expression (3).

[0184] Q2=-C2×Vout (3)

[0185] At this time, the total amount of charge of the capacitors 431 and 433 does not change, so the following expression (4) is established.

[0186] Qinit=Qafter+Q2 (4)

[0187] When Expression (1) to Expression (3) are substituted for Expression (4), the following Expression (5) is obtained.

[0188] Vout=-(C1 / C2)×(Vafter-Vinit) (5)

[0189] Expression (5) represents the subtraction operation of the voltage signal, and the gain of the subtraction result becomes C1 / C2. Typically, it is desired to maximize (or alternatively, improve) the gain, so it is preferably designed so that C1 becomes larger and C2 becomes smaller. On the other hand, when C2 is too small, kTC noise increases, so there is a concern that the noise characteristics will deteriorate. Therefore, the reduction in the capacitance of C2 is limited to a range that allows noise. In addition, since the address event detection unit 400 including the subtractor 430 is installed for each unit pixel, there is a restriction on the area in the capacitors C1 and C2. The values ​​of the capacitors C1 and C2 are determined in consideration of this restriction.

[0190] The comparator 441 compares the voltage signal transmitted from the subtractor 430 with a predetermined threshold voltage Vth applied to the inverting input terminal (-). The comparator 441 outputs a signal indicating a comparison result to the transmission unit 450 as a detection signal.

[0191] In addition, when the conversion gain of the current-to-voltage conversion unit 410 is set to CG log , and when the gain of the buffer 420 is set to "1", the overall gain A of the address event detection unit 400 is expressed as the following expression (6).

[0192] [Formula 1]

[0193]

[0194] In expression (6), i photo_n represents the photocurrent of the nth unit pixel, and its unit is, for example, ampere (A). N represents the number of unit pixels 310 in the pixel block, and is "1" in the present embodiment.

[0195] 2.5.3 Example of Column ADC Construction

[0196] Figure 8 Column ADC 220 includes a plurality of ADCs 230 provided for each column of unit pixels 310 .

[0197] Each ADC 230 converts the analog pixel signal appearing in the vertical signal line VSL into a digital signal. For example, the pixel signal is converted into a digital signal having a bit length greater than the bit length of the detection signal. For example, when the detection signal is set to two bits, the pixel signal is converted into a digital signal of three or more bits (16 bits, etc.). The ADC 230 provides the generated digital signal to the signal processing unit 212.

[0198] 2.6 Operation Example of Solid-State Image Pickup Device

[0199] Next, the operation of the solid-state imaging device 200 according to this embodiment will be described in detail with reference to the drawings.

[0200] 2.6.1 Timing diagram

[0201] First, an example of the operation of the solid-state imaging device 200 will be described using a timing chart. Fig. 9 is a timing chart showing an example of the operation of the solid-state imaging apparatus according to the first embodiment.

[0202] like Fig. 9 As shown, at time T0, when the control unit 130 gives an instruction for address event detection start, the drive circuit 211 raises the control signal OFG applied to the gate of the OFG transistor 332 of all the light receiving units 330 in the pixel array unit 300 to a high level. With this arrangement, the plurality of OFG transistors 332 of all the light receiving units 330 enter a conductive state, and a photocurrent based on the charge generated in the photoelectric conversion element 333 of each light receiving unit 330 is supplied from each light receiving unit 330 to each of the plurality of address event detection units 400.

[0203] In addition, in the period when the control signal OFG is at a high level, all transmission signals TRG applied to the gate of the transmission transistor 331 in each light receiving unit 330 are maintained at a low level. Therefore, in this period, the plurality of transmission transistors 331 in all light receiving units 330 are in an off state.

[0204] Next, it will be assumed that the address event detection unit 400 of any unit pixel 310 detects the occurrence of an address event during the period when the control signal OFG is at a high level. In this case, the address event detection unit 400 that detects the occurrence of the address event transmits a request to the arbitrator 213. In this regard, the arbitrator 213 arbitrates the request and returns a response to the request to the address event detection unit 400 that issued the request.

[0205] The address event detection unit 400 that receives the response raises the detection signal input to the drive circuit 211 and the signal processing unit 212 to a high level, for example, in the period from time T1 to time T2. In addition, in this specification, it is assumed that the detection signal is a one-bit signal indicating the detection result of the ON event.

[0206] The drive circuit 211 inputting the high level detection signal from the address event detection unit 400 at time T1 lowers all control signals OFG to low level at subsequent time T2. With this arrangement, the photocurrent supply from all light receiving units 330 of the pixel array unit 300 to the address event detection unit 400 is stopped.

[0207] In addition, at time T2, the drive circuit 211 raises the selection signal SEL applied to the gate of the selection transistor 323 in the pixel signal generating unit 320 of the unit pixel 310 (hereinafter referred to as the "readout target unit pixel") that detects the occurrence of the address event to a high level, and raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel signal generating unit 320 to a high level and maintains it for a constant pulse period, thereby releasing (initializing) the charge accumulated in the floating diffusion layer 324 of the pixel signal generating unit 320. In this way, the voltage appearing in the vertical signal line VSL in the state where the floating diffusion layer 324 is initialized is read out by the ADC 230 connected to the vertical signal line VSL in the column ADC 220 as a reset level pixel signal (hereinafter referred to as the "reset level"), and converted into a digital signal.

[0208] Next, at time T3 after the reset level is read out, the drive circuit 211 applies the transmission signal TRG of the constant pulse period to the gate of the transfer transistor 331 of the light receiving unit 330 in the readout target unit pixel 310. With this arrangement, the charge generated in the photoelectric conversion element 333 of the light receiving unit 330 is transferred to the floating diffusion layer 324 in the pixel signal generating unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL. In this way, the voltage appearing in the vertical signal line VSL is read out by the ADC 230 connected to the vertical signal line VSL in the column ADC 220 as a signal level pixel signal of the light receiving unit 330 (hereinafter, simply referred to as "signal level"), and is converted into a digital value.

[0209] The signal processing unit 212 performs CDS processing in which the difference between the reset level and the signal level read out as described above is obtained as a net pixel signal corresponding to the light reception amount of the photoelectric conversion element 333 .

[0210] Next, at time T4, the driving circuit 211 lowers the selection signal SEL applied to the gate of the selection transistor 323 in the pixel signal generating unit 320 of the readout target unit pixel 310 to a low level, and raises the control signal OFG applied to the gate of the OFG transistor 332 of all the light receiving units 330 in the pixel array unit 300 to a high level. With this arrangement, the address event occurrence detection in all the light receiving units 330 in the pixel array unit 300 is restarted.

[0211] 2.6.2 Flowchart

[0212] Next, an example of the operation of the solid-state imaging apparatus 200 will be described using a flowchart. Fig.10 1 is a flowchart showing an example of the operation of the solid-state imaging device according to the first embodiment. For example, when a predetermined application for detecting an address event is executed, the operation is started.

[0213] like Fig.10 As shown, in this operation, first, each unit pixel 310 in the pixel array unit 300 detects whether an address event occurs (step S901). In addition, the driving circuit 211 determines whether an address event occurs in any unit pixel 310 (step S902).

[0214] In the case where the occurrence of an address event is not detected ("No" in step S902), the operation proceeds to step S904. On the other hand, in the case where the occurrence of an address event is detected ("Yes" in step S902), the drive circuit 211 reads out the pixel signal of the unit pixel 310 in which the occurrence of the address event is detected (step S903), and proceeds to step S904.

[0215] In step S904, it is determined whether to terminate the operation. In the case where the operation is not terminated ("No" in step S904), the operation returns to step S901 and the subsequent operation is repeated. On the other hand, in the case where the operation is terminated ("Yes" in step S904), the operation is terminated.

[0216] 2.7 Layout Example of Unit Pixels

[0217] As mentioned above, in Figure 5 In the configuration shown, as an example, an upper circuit 500 including two LG transistors 411 and 414 in the current-voltage conversion unit 410 of the light receiving unit 330, the pixel signal generating unit 320, the address event detecting unit 400, and two amplifying transistors 412 and 413 is provided, for example, in Figure 2 In the light receiving chip 201 shown, other configurations are provided in the logic chip 202 bonded to the light receiving chip 201 by Cu-Cu bonding as an example. Hereinafter, regarding layout examples in the light receiving chip 201 of the upper layer circuit 500, several examples will be described.

[0218] 2.7.1 First layout example

[0219] Fig.11 is a top view showing a schematic configuration example of an upper layer circuit according to the first layout example. Fig.12 It is shown along Fig.11 A diagram showing an example of a cross-sectional structure of a unit pixel in the case where the solid-state imaging device is cut along a plane AA in FIG.

[0220] like Fig.12 As shown, for example, the unit pixel 310 has a back-illuminated structure in which a surface (hereinafter referred to as "back surface") opposite to the element forming surface (lower surface in the figure) of the semiconductor substrate 501 is set as a light incident surface. Here, the unit pixel 310 has a structure in which a light receiving chip 201 including a semiconductor substrate 501 and an interlayer insulating film 503 and a logic chip 202 including a semiconductor substrate 511 and an interlayer insulating film 513 are bonded via a Cu-Cu joint 510.

[0221] As described above, the upper layer circuit 500-1 is formed in the light receiving chip 201. A microlens 502 is provided for each unit pixel 310 on the back surface of the semiconductor substrate 501 in the light receiving chip 201 to focus incident light to the photoelectric conversion element 333. In addition, although not shown in the figure, for example, Figure 4 The color filters shown arranged in a predetermined color filter array are arranged on the back side of the semiconductor substrate 501 .

[0222] In addition, if Fig.11 and Fig.12 As shown, the upper layer circuit 500-1 according to the first layout example includes a photoelectric conversion element 333 formed by injecting an N-type dopant (donor) into a semiconductor substrate 501 diffused with a P-type dopant (acceptor). A transfer gate 3311 of a transfer transistor 331, which is formed in a groove ranging from an element formation surface of the semiconductor substrate 501 to the photoelectric conversion element 333, is arranged at one corner of the photoelectric conversion element 333 whose light receiving surface is rectangular. In addition, an OFG gate 3321 of an OFG transistor 332 formed in a groove ranging from an element formation surface of the semiconductor substrate 501 to the photoelectric conversion element 333 is formed at a corner diagonally positioned relative to the corner where the transfer gate 3311 is provided.

[0223] The reset gate 3211 of the reset transistor 321, the amplification gate 3221 of the amplification transistor 322, and the selection gate 3231 of the selection transistor 323 in the pixel signal generating unit 320 are arranged in a straight line from the corner where the transfer gate 3311 is provided in a direction parallel to the row. In addition, gate insulating films are provided between the reset gate 3211, the amplification gate 3221, the selection gate 3231, and the semiconductor substrate 501, respectively.

[0224] In the semiconductor substrate 501, a diffusion region 325 serving as a connection node is formed in a region between the transfer gate 3311 and the reset gate 3211. In addition, a diffusion region 325 serving as a source and a drain is formed in each region between the reset gate 3211, the amplification gate 3221, and the selection gate 3231.

[0225] The diffusion region 325 between the transfer gate 3311 and the reset gate 3211 and the amplification gate 3221 are connected to each other through an interconnect 3241 formed in the interlayer insulating film 503 and serving as a floating diffusion layer 324. The diffusion region 325 between the reset gate 3211 and the amplification gate 3221 is connected to the power supply terminal VDD.

[0226] On the other hand, in the upper detection circuit 410A, the LG gate 4111 of the LG transistor 411 and the LG gate 4141 of the LG transistor 414 are linearly arranged in a straight line from the corner where the OFG gate 3321 is arranged on the side opposite to the pixel signal generating unit 320 in parallel with the row direction. In addition, the amplification gate 4121 of the amplification transistor 412 and the amplification gate 4131 of the amplification transistor 413 are arranged in parallel with the array of the LG gates 4111 and 4141. In addition, in Fig.12 In FIG. 5 , the amplification transistors 412 and 413 are omitted due to the cross-sectional positional relationship. In addition, a gate insulating film is provided between the LG gates 4111 and 4141 and the semiconductor substrate 501 and between the amplification gates 4121 and 4131 and the semiconductor substrate 501.

[0227] In the semiconductor substrate 501, a diffusion region 416 serving as a connection node is formed in a region between the OFG gate 3321 and the LG gate 4111. In addition, a diffusion region 416 serving as a source and a drain is formed in each of a region between the LG gate 4111 and the LG gate 4141 and a region between the amplification gate 4121 and the amplification gate 4131. In addition, the diffusion region 416 serving as a drain of the LG transistor 414 is connected to the power supply terminal VDD, and the diffusion region 416 serving as a drain of the amplification transistor 413 is grounded.

[0228] In addition, the diffusion region 416 between the OFG gate 3321 and the LG gate 4111 is connected to the amplification gate 4131, the diffusion region 416 between the LG gate 4111 and the LG gate 4141 is connected to the amplification gate 4121, the diffusion region 416 between the amplification gate 4121 and the amplification gate 4131 is connected to the LG gate 4111, and the diffusion region 416 serving as the drain of the amplification transistor 412 is connected to the LG gate 4141.

[0229] In the above configuration, the diffusion region 325 used as the drain of the selection transistor 323 and the diffusion region 416 used as the drain of the amplification transistor 412 are both connected to a copper (Cu) pad 506 in the surface (lower surface in the drawing) of the interlayer insulating film 503 through an interconnection 504 and a pad 505 formed in the interlayer insulating film 503. The Cu pad 506 is bonded to a Cu pad 512 in the surface of the interlayer insulating film 513 formed on the semiconductor substrate 511, thereby forming a Cu-Cu joint 510. The Cu-Cu joint 510 serves as a connection portion for electrically connecting the light receiving chip 201 and the logic chip 202, and also serves as a joint for mechanically laminating the light receiving chip 201 and the logic chip 202. In addition, the Cu pad 512 in the surface of the interlayer insulating film 513 is connected to the semiconductor substrate 511, for example, through an interconnection 514 and a pad 515 formed in the interlayer insulating film 513.

[0230] Therefore, the diffusion region 325 used as the drain of the selection transistor 323 is connected to the vertical signal line VSL on the logic chip 202 side through the interconnection 504 in the interlayer insulation, the pad 505, and the Cu-Cu joint 510. In addition, the diffusion region 416 used as the drain of the amplifier transistor 412 is connected to the remaining circuit configuration of the current-voltage conversion unit 410 arranged on the logic chip 202 side through the interconnection 504 in the interlayer insulation film 503, the pad 505, and the Cu-Cu joint 510.

[0231] In addition, although not shown in the figure, Figure 5 As shown, the transmission gate 3311 and OFG gate 3321 in the light receiving unit 330 and the reset gate 3211 and selection gate 3231 in the pixel signal generating unit 320 are connected to the driving circuit 211 of the logic chip 202 through the interconnection part 504, the pad 505 and the Cu-Cu joint 510 in the interlayer insulating film 503.

[0232] As described above, when the pixel signal generating unit 320 and the upper layer detection circuit 410A are arranged to extend linearly from the corners of the photoelectric conversion element 333, respectively, the interconnection length can be shortened. With this arrangement, the occupancy rate of the pixel signal generating unit 320 and the upper layer detection circuit 410A on the light receiving surface can be reduced, thereby increasing the occupancy rate of the photoelectric conversion element 333. As a result, the light receiving efficiency can be improved.

[0233] In addition, NMOS transistors can be used as each transistor constituting the pixel signal generating unit 320 and each transistor constituting the upper layer detection circuit 410A. Therefore, when the transistors are arranged in the same light receiving chip 201, the manufacturing process of the light receiving chip 201 can be simplified.

[0234] In addition, the layout of the individual transistors constituting the pixel signal generating unit 320 and the layout of the individual transistors constituting the upper detection circuit 410A are similar to each other, so when the structure is set in the same light receiving chip 201, the layout design of the light receiving chip 201 can also be facilitated.

[0235] 2.7.1.1 Array Example

[0236] Fig.13 is a schematic diagram showing an array example of an upper layer circuit according to a first layout example in a pixel array unit. Fig.13 In the figure, for clarity, one of the plurality of upper layer circuits 500-1 is indicated by hatching. Fig.11 The upper circuit 500-1 shown is different. Fig.13It is shown that the transfer gate 3311 of the transfer transistor 331 is provided on the side opposite to the side on which the upper layer detection circuit 410A is provided in the photoelectric conversion element 333 .

[0237] like Fig.13 As shown in the first layout example, for example, a plurality of photoelectric conversion elements 333 are arranged adjacent to each other in the up-down direction (i.e., the column direction) and alternately exist in the left-right direction (i.e., the row direction). When this array is adopted, the pixel value of the region (i.e., the region occupied by the pixel signal generating unit 320 and the upper detection circuit 410A) where the photoelectric conversion element 333 does not exist can be interpolated by the pixel value obtained by the photoelectric conversion element 333 in the periphery of the region.

[0238] In addition, the pixel signal generating unit 320 and the upper layer detection circuit 410A can be integrated in a region corresponding to the photoelectric conversion element 333 between the upper layer circuits 500-1 adjacent to each other, so that the occupancy rate of the pixel signal generating unit 320 and the upper layer detection circuit 410A on the light receiving surface can be further reduced. With this arrangement, the occupancy rate of the photoelectric conversion element 333 is increased, so the light receiving efficiency can be further improved.

[0239] 2.7.1.2 Variation of the First Layout Example

[0240] Furthermore, in the first layout example, the pixel signal generating unit 320 and the upper layer detection circuit 410A are arranged to extend linearly from the corner of the photoelectric conversion element 333. However, for example, Fig.14 In the unit pixel 310-1 shown, the pixel signal generating unit 320 and the upper detection circuit 410A can be arranged to be folded back from the corner of the photoelectric conversion element 333 toward one surface (the lower surface in the figure) of the photoelectric conversion element 333. With this arrangement, the occupancy rate of the pixel signal generating unit 320 and the upper detection circuit 410A on the light receiving surface can be further reduced, and thus the occupancy rate of the photoelectric conversion element 333 is increased. As a result, the light receiving efficiency can be further improved.

[0241] 2.7.2 Second layout example

[0242] Fig.15 1 is a top view showing a schematic configuration example of an upper layer circuit according to a second layout example. Fig.15 As shown, in the upper layer circuit 500 - 2 according to the second layout example, in a manner similar to the first layout example, the transfer gate 3311 and the OFG gate 3321 are respectively provided at the corner portions of the diagonally arranged photoelectric conversion elements 333 .

[0243] The reset gate 3211 , the amplification gate 3221 , and the selection gate 3231 in the pixel signal generating unit 320 are linearly arranged in a straight line from the corner portion of the photoelectric conversion element 333 where the transfer gate 3311 is provided along the side surface of the photoelectric conversion element 333 in parallel with the column direction.

[0244] On the other hand, the LG gates 4111 and 4141 in the upper detection circuit 410A are arranged parallel to the column direction along the side opposite to the side provided with the pixel signal generating unit 320 from the corner portion provided with the OFG gate 3321 of the photoelectric conversion element 333. In addition, the amplification gratings 4121 and 4131 are arranged in an array parallel to the LG gates 4111 and 4141.

[0245] According to this layout, the shape of the outer edge of the upper layer circuit 500-2 can be set to a rectangle, so the layout design of the upper layer circuit 500-2 can be more easily performed in the pixel array unit 300. Other configurations and effects can be similar to those in the first layout example.

[0246] 2.7.2.1 Array Example

[0247] Fig.16 is a schematic diagram showing an array example of an upper layer circuit according to a second layout example in a pixel array unit. Fig.16 In FIG. 5 , for the sake of clarity, one of the plurality of upper layer circuits 500 - 2 is indicated by hatching.

[0248] like Fig.16 As shown, in the second layout example, for example, in a manner similar to the first layout example, the photoelectric conversion elements 333 are arranged to be adjacent to each other in the up-down direction (i.e., the column direction) and to be alternately present in the left-right direction (i.e., the row direction). When this array is adopted, the pixel value of the region (i.e., the region occupied by the pixel signal generating unit 320 and the upper layer detection circuit 410A) where the photoelectric conversion element 333 is not present can be interpolated by the pixel value obtained by the photoelectric conversion element 333 in the periphery of the region.

[0249] In addition, in a manner similar to that in the first layout example, the pixel signal generating unit 320 and the upper layer detection circuit 410A can be integrated in a region corresponding to one photoelectric conversion element 333 between the upper layer circuits 500-2 adjacent to each other, and thus, the occupancy rate of the pixel signal generating unit 320 and the upper layer detection circuit 410A on the light receiving surface can be further reduced. With this arrangement, the occupancy rate of the photoelectric conversion element 333 increases, and thus the light receiving efficiency can be further improved.

[0250] Other configurations and effects may be similar to those in the above-described layout example.

[0251] 2.7.3 Third layout example

[0252] Fig.17 1 is a top view showing a schematic configuration example of an upper layer circuit according to the third layout example. Fig.17 As shown in FIG. 1 , in the upper layer circuit 500 - 3 according to the third layout example, the transfer gate 3311 and the OFG gate 3321 are respectively provided at corner portions adjacent to each other in the photoelectric conversion element 333 (eg, two corner portions on the lower side in the figure).

[0253] In a manner similar to the first embodiment, the reset gate 3211, the amplification gate 3221 and the selection gate 3231 in the pixel signal generating unit 320 are linearly arranged in a straight line parallel to the column direction starting from the corner portion of the photoelectric conversion element 333 where the transfer gate 3311 is provided.

[0254] On the other hand, the LG gates 4111 and 4141 in the upper detection circuit 410A are linearly arranged on a straight line starting from the corner portion of the photoelectric conversion element 333 where the OFG gate 3321 is provided, parallel to the reset gate 3211, the amplification gate 3221 and the selection gate 3231 of the pixel signal generating unit 320.

[0255] In addition, the amplification gates 4121 and 4131 are arranged parallel to the array of LG gates 4111 and 4141 between the reset gate 3211, the amplification gate 3221 and the selection gate 3231 of the pixel signal generating unit 320 and the LG gates 4111 and 4141 of the upper detection circuit 410A.

[0256] The pixel signal generating unit 320 and the upper layer detection circuit 410A are integrated, for example, in a region whose size is equal to or smaller than that of the photoelectric conversion element 333. When such a configuration is adopted, the shape of the outer edge of the upper layer circuit 500-3 can be set to a rectangular shape.

[0257] 2.7.3.1 Array Example

[0258] Fig.18 is a schematic diagram showing an array example of an upper layer circuit according to a third layout example in a pixel array unit. Fig.18 In FIG. 5 , for the sake of clarity, one of the plurality of upper layer circuits 500 - 3 is indicated by hatching.

[0259] like Fig.18As shown, in the third layout example, for example, the photoelectric conversion elements 333 may be arranged to alternately exist in the up-down direction and the left-right direction (i.e., the row direction and the column direction). When this array is adopted, the pixel values ​​of the region where the photoelectric conversion elements 333 do not exist (i.e., the region occupied by the pixel signal generating unit 320 and the upper detection circuit 410A) can be interpolated by the pixel values ​​obtained by the photoelectric conversion elements 333 in the periphery of the region where the photoelectric conversion elements 333 do not exist.

[0260] As described above, when an array is adopted in which the pixel signal generating unit 320 and the upper detection circuit 410A are integrated on one side of the photoelectric conversion element 333, the shape of the outer edge of each upper circuit 500-3 can be set to a rectangle, thereby making the layout design of the upper circuit 500-3 in the pixel array unit 300 easier.

[0261] In addition, when the pixel signal generating unit 320 and the upper detection circuit 410A are integrated on one side of the photoelectric conversion element 333, the area of ​​the upper circuit 500-3 can be reduced. Therefore, the occupancy rate of the pixel signal generating unit 320 and the upper detection circuit 410A on the light receiving surface can be further reduced. With this arrangement, the occupancy rate of the photoelectric conversion element 333 is increased, so the light receiving efficiency can be further improved.

[0262] In addition, when a plurality of upper layer circuits 500-3 are arranged so that the photoelectric conversion elements 333 exist alternately in the up-down direction and the left-right direction, the pixel values ​​of the region where the photoelectric conversion elements 333 do not exist can be interpolated by the pixel values ​​obtained by the photoelectric conversion elements 333 in the periphery of the region where the photoelectric conversion elements 333 do not exist. With this arrangement, an event-driven image sensor can be realized without reducing the resolution of the image data acquired by the solid-state imaging device 200.

[0263] Other configurations and effects may be similar to those in the above-described layout example.

[0264] 2.7.4 Fourth layout example

[0265] Fig.19 1 is a top view showing a schematic configuration example of an upper layer circuit according to a fourth layout example. Fig.19 As shown, in the upper layer circuit 500 - 4 according to the fourth layout example, in a manner similar to the first layout example, the transfer gate 3311 and the OFG gate 3321 are respectively provided at the corner portions of the diagonally arranged photoelectric conversion elements 333 .

[0266] The pixel signal generating unit 320 is disposed in a region facing a corner portion where the transfer gate 3311 is disposed, that is, in Fig.19In the example shown, the reset gate 3211, the amplification gate 3221, and the selection gate 3231 in the pixel signal generating unit 320 are linearly arranged in a straight line parallel to the column direction in the lower left region relative to the region where the photoelectric conversion element 333 is provided.

[0267] On the other hand, the upper layer detection circuit 410A is provided in a region facing the corner portion where the OFG gate 3321 is provided, that is, in Fig.19 In the example shown, the LG gates 4111 and 4141 in the upper detection circuit 410A are arranged linearly in a straight line parallel to the column direction in the upper right oblique area relative to the area where the photoelectric conversion element 333 is provided. In addition, the amplification gates 4121 and 4131 are arranged in an array parallel to the LG gates 4111 and 4141.

[0268] For example, the size of the pixel signal generating unit 320 in the column direction is set to be approximately equal to or smaller than the size of the photoelectric conversion element 333 in the column direction. Similarly, for example, the size of the upper layer detection circuit 410A in the column direction is set to be approximately equal to or smaller than the size of the photoelectric conversion element 333 in the column direction.

[0269] 2.7.4.1 First Array Example

[0270] Fig. 20 is a schematic diagram showing a first array example in a pixel array unit of an upper layer circuit according to a fourth layout example. Fig. 20 In FIG. 5 , for the sake of clarity, one of the plurality of upper-layer circuits 500 - 4 is indicated by hatching.

[0271] like Fig. 20 As shown in, for example, in the first array example, a plurality of upper layer circuits 500-4 according to the fourth layout example are arranged so that the photoelectric conversion elements 333 are linearly arranged in a straight line in the column direction. When this array is adopted, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in an area adjacent to each photoelectric conversion element 333 in the left-right direction (row direction).

[0272] 2.7.4.2 Second Array Example

[0273] Fig.21 is a schematic diagram showing a second array example in the pixel array unit of the upper layer circuit according to the fourth layout example. Fig.21 In FIG. 5 , for the sake of clarity, one of the plurality of upper-layer circuits 500 - 4 is indicated by hatching.

[0274] like Fig.21As shown in the second array example, for example, the upper layer circuit 500-4 according to the fourth layout example is arranged so that the photoelectric conversion elements 333 are arranged linearly in the row direction. When this array is adopted, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in the region adjacent to each photoelectric conversion element 333 in the up-down direction (column direction).

[0275] As described above, according to the fourth layout example, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in the region adjacent to the photoelectric conversion element 333 in the left-right direction (row direction) or the up-down direction (column direction), so the occupancy rate of the pixel signal generating unit 320 and the upper layer detection circuit 410A on the light receiving surface can be further reduced. With this arrangement, the occupancy rate of the photoelectric conversion element 333 increases, so the light receiving efficiency can be further improved.

[0276] In addition, the upper layer circuit 500-4 is arranged so that the photoelectric conversion elements 333 exist alternately in the left-right direction (row direction) or the up-down direction (column direction), and therefore, the pixel values ​​of the region where the photoelectric conversion elements 333 do not exist can be interpolated by the pixel values ​​obtained by the photoelectric conversion elements 333 in the periphery of the region where the photoelectric conversion elements 333 do not exist. With this arrangement, an event-driven image sensor can be realized without reducing the resolution of the image data acquired by the solid-state imaging device 200.

[0277] Other configurations and effects may be similar to those in the above-described layout example.

[0278] 2.7.5 Fifth layout example

[0279] Fig. 22 1 is a top view showing a schematic configuration example of an upper layer circuit according to a fifth layout example. Fig. 22 As shown, in the upper circuit 500-5 according to the fifth layout example, in a manner similar to the third layout example, the transmission gate 3311 and the OFG gate 3321 are respectively arranged at corners adjacent to each other in the photoelectric conversion element 333 (for example, two corners on the right side in the figure).

[0280] The pixel signal generating unit 320 is disposed in a region facing a corner portion where the transfer gate 3311 is disposed, that is, in Fig. 22 In the example shown, the reset gate 3211, the amplification gate 3221, and the selection gate 3231 in the pixel signal generating unit 320 are linearly arranged in a straight line parallel to the column direction in the region diagonally lower right relative to the region where the photoelectric conversion element 333 is provided.

[0281] On the other hand, the upper layer detection circuit 410A is provided in a region facing the corner portion where the OFG gate 3321 is provided, that is, in Fig. 22 In the example shown, the LG gates 4111 and 4141 in the upper detection circuit 410A are arranged linearly in a straight line parallel to the column direction in the region obliquely above and to the right relative to the region where the photoelectric conversion element 333 is provided. In addition, the amplification gates 4121 and 4131 are arranged in an array parallel to the LG gates 4111 and 4141.

[0282] For example, the size of the pixel signal generating unit 320 in the column direction is set to be approximately equal to or smaller than the size of the photoelectric conversion element 333 in the column direction. Similarly, for example, the size of the upper layer detection circuit 410A in the column direction is set to be approximately equal to or smaller than the size of the photoelectric conversion element 333 in the column direction.

[0283] 2.7.5.1 Array Example

[0284] Fig.23 is a schematic diagram showing an array example of an upper layer circuit according to a fifth layout example in a pixel array unit. Fig.23 In FIG. 5 , for the sake of clarity, one of the plurality of upper-layer circuits 500 - 5 is indicated by hatching.

[0285] like Fig.23 As shown, for example, the upper layer circuit 500-5 according to the fifth layout example is arranged so that the photoelectric conversion elements 333 are arranged linearly in the row direction. When this array is adopted, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in the region adjacent to each photoelectric conversion element 333 in the up-down direction (column direction).

[0286] As described above, according to the fifth layout example, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in the region adjacent to each photoelectric conversion element 333 in the up-down direction (column direction), and therefore, the occupancy rate of the pixel signal generating unit 320 and the upper layer detection circuit 410A on the light receiving surface can be further reduced. With this arrangement, the occupancy rate of the photoelectric conversion element 333 increases, and therefore, the light receiving efficiency can be further improved.

[0287] In addition, the upper layer circuit 500-5 is arranged so that the photoelectric conversion elements 333 exist alternately in the up-down direction (column direction), and therefore, the pixel values ​​of the region where the photoelectric conversion elements 333 do not exist can be interpolated by the pixel values ​​obtained by the photoelectric conversion elements 333 in the periphery of the region where the photoelectric conversion elements 333 do not exist. With this arrangement, an event-driven image sensor can be realized without reducing the resolution of the image data acquired by the solid-state imaging device 200.

[0288] Other configurations and effects may be similar to those in the above-described layout example.

[0289] 2.7.6 Sixth layout example

[0290] Fig.24 1 is a top view showing a schematic configuration example of an upper layer circuit according to a sixth layout example. Fig.24 As shown, in the upper circuit 500-6 according to the sixth layout example, in a manner similar to the third layout example, the transmission gate 3311 and the OFG gate 3321 are respectively arranged at the corner portions adjacent to each other in the photoelectric conversion element 333 (for example, the two corner portions on the lower side in the drawing).

[0291] The pixel signal generating unit 320 is disposed in a region facing a corner portion where the transfer gate 3311 is disposed, that is, in Fig.24 In the example shown, the reset gate 3211, the amplification gate 3221, and the selection gate 3231 in the pixel signal generating unit 320 are linearly arranged in a straight line parallel to the column direction in the lower left region relative to the region where the photoelectric conversion element 333 is provided.

[0292] On the other hand, the upper layer detection circuit 410A is provided in a region facing the corner portion where the OFG gate 3321 is provided, that is, in Fig.24 In the example shown, the region is located obliquely to the right of the region where the photoelectric conversion element 333 is provided. In the region obliquely to the right, the LG gates 4111 and 4141 in the upper detection circuit 410A are linearly arranged in a straight line parallel to the column direction. In addition, the amplification gates 4121 and 4131 are arranged in an array parallel to the LG gates 4111 and 4141. In view of the above, it should be understood that Fig.24 A first readout circuit 320 coupled to a photoelectric conversion region at a first position and a second readout circuit 400 including a portion 410A coupled to the photoelectric conversion region at a second position are shown. The second readout circuit 400 is configured to control the first readout circuit 320 according to the operations described herein. Fig.24As shown, the first position and the second position are on the same side (also located in the same half) of the photoelectric conversion region 333. As also shown, the first position and the second position are equidistant from the center of the edge of the photoelectric conversion region 333 defining the side. For example, the first position is at a first corner of the photoelectric conversion region 333, and the second position is at a second corner of the photoelectric conversion region 333. As further shown, the first readout circuit 320 includes a first transistor having a first gate 3311 at a first position, and the second readout circuit 400 includes a second transistor having a second gate 3321 at a second position. The first readout circuit 320 includes a plurality of third transistors (having gates 3211, 3221, 3231) coupled to the first transistor 3311. The second readout circuit 400 includes a plurality of fourth transistors (having gates 4111, 4141, 4131, 4121) coupled to the second transistor 3321. The number of the plurality of fourth transistors is greater than the number of the plurality of third transistors. The plurality of fourth transistors include first and second groups of transistors arranged along a first direction, and the first group of transistors (having gates 4111 and 4141) are arranged in a second direction perpendicular to the first direction to be adjacent to the second group of transistors (having gates 4131 and 4121). The second group of transistors is farther away from the side of the photoelectric conversion region 333 than the first group of transistors. As shown in the figure, the plurality of third transistors (having gates 3211, 3221, 3231) are arranged in the first direction.

[0293] For example, the size of the pixel signal generating unit 320 in the column direction is set to be approximately equal to or smaller than the size of the photoelectric conversion element 333 in the column direction. Similarly, for example, the size of the upper layer detection circuit 410A in the column direction is set to be approximately equal to or smaller than the size of the photoelectric conversion element 333 in the column direction.

[0294] 2.7.6.1 Array Example

[0295] Fig.25 is a schematic diagram showing an array example of an upper layer circuit according to a sixth layout example in a pixel array unit. Fig.25 In FIG. 5 , for the sake of clarity, one of the plurality of upper-layer circuits 500 - 6 is indicated by hatching.

[0296] like Fig.25 As shown, for example, the upper layer circuit 500-6 according to the sixth layout example is arranged so that the photoelectric conversion elements 333 are arranged linearly in the column direction. When this array is adopted, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in the area adjacent to each photoelectric conversion element 333 in the left-right direction (row direction).

[0297] As described above, according to the sixth layout example, one pixel signal generating unit 320 and one upper layer detection circuit 410A can be accommodated in the area adjacent to each photoelectric conversion element 333 in the left-right direction (row direction), and therefore, the occupancy rate of the pixel signal generating unit 320 and the upper layer detection circuit 410A on the light receiving surface can be further reduced. With this arrangement, the occupancy rate of the photoelectric conversion element 333 increases, and therefore, the light receiving efficiency can be further improved.

[0298] In addition, the upper layer circuit 500-6 is arranged so that the photoelectric conversion elements 333 exist alternately in the up-down direction (column direction), and therefore, the pixel values ​​of the region where the photoelectric conversion elements 333 do not exist can be interpolated by the pixel values ​​obtained by the photoelectric conversion elements 333 in the periphery of the region where the photoelectric conversion elements 333 do not exist. With this arrangement, an event-driven image sensor can be realized without reducing the resolution of the image data acquired by the solid-state imaging device 200.

[0299] Other configurations and effects may be similar to those in the above-described layout example.

[0300] 2.8 Function and Effect

[0301] As described above, according to this embodiment, the occupancy rate of the pixel signal generating unit 320 and the upper detection circuit 410A on the light receiving surface can be reduced, thereby increasing the occupancy rate of the photoelectric conversion element 333. As a result, the light receiving efficiency can be improved.

[0302] In addition, NMOS transistors can be used as each transistor constituting the pixel signal generating unit 320 and each transistor constituting the upper layer detection circuit 410A. Therefore, when the transistors are arranged in the same light receiving chip 201, the manufacturing process of the light receiving chip 201 can be simplified.

[0303] In addition, the layout of the individual transistors constituting the pixel signal generating unit 320 and the layout of the individual transistors constituting the upper detection circuit 410A are similar to each other, so when the structure is arranged on the same light receiving chip 201, the layout design of the light receiving chip 201 can also be facilitated.

[0304] In addition, the pixel values ​​of the region where the photoelectric conversion element 333 does not exist can be interpolated by the pixel values ​​obtained by the photoelectric conversion element 333 in the periphery of the region where the photoelectric conversion element 333 does not exist. With this arrangement, an event-driven image sensor can be realized without reducing the resolution of the image data acquired by the solid-state imaging device 200.

[0305] 3. Second embodiment

[0306] Next, a solid-state imaging device and an imaging device according to a second embodiment will be described in detail with reference to the drawings. In addition, in the following description, for the same structure as the above-mentioned embodiment, its structure is cited and repeated description is omitted.

[0307] For example, the capacity of the photoelectric conversion element 333 must be small so that an address event can be sensitively triggered for incident light. On the other hand, the capacity of the photoelectric conversion element 333 must be large to expand the dynamic range of the acquired image. Therefore, in this embodiment, the capacity of the photoelectric conversion element 333 is switched between the period of monitoring the occurrence of the address event and the period of reading out the pixel signal.

[0308] For example, the image pickup apparatus and the solid-state image pickup apparatus according to the present embodiment may be similar to the image pickup apparatus 100 and the solid-state image pickup apparatus 200 described in the first embodiment. However, in the present embodiment, the unit pixel 310 is replaced with a unit pixel 610 as described later.

[0309] 3.1 Example of unit pixel construction

[0310] Fig.26 1 is a circuit diagram showing a schematic configuration example of a unit pixel according to the second embodiment. Fig.26 As shown, for example, the unit pixel 610 has Figure 5 The unit pixel 310 shown is similarly configured, and the light receiving unit 330 is replaced by a light receiving unit 630. In addition, in the present embodiment, the reference numeral of the upper layer circuit is set to 600 for convenience of explanation.

[0311] In the light receiving unit 630 , the photoelectric conversion element 333 includes two photoelectric conversion elements 3331 and 3332 . In addition, cathodes of the two photoelectric conversion elements 3331 and 3332 are connected to each other through the photogate 601 .

[0312] The photo gate 601 is supplied with a control signal PG from the drive circuit 211. The photo gate 601 enters a conducting state when a high-level control signal PG is supplied from the drive circuit 211. With this arrangement, the two photoelectric conversion elements 3331 and 3332 function as two photoelectric conversion elements.

[0313] The other configurations may be similar to those in the unit pixel 310 according to the first embodiment.

[0314] 3.2 Operation examples of solid-state imaging devices

[0315] Next, the operation of the solid-state imaging device 200 according to this embodiment will be described in detail with reference to the drawings. Fig. 27 is a timing chart showing an example of the operation of the solid-state imaging device according to the second embodiment. Fig.10 The flowchart is not shown, so its description will be omitted here.

[0316] like Fig. 27 As shown, in this embodiment, the reference Fig. 9 In a similar manner to the operation described above, at time T0, when the control unit 130 gives an instruction for address event detection start, the drive circuit 211 raises the control signal OFG applied to the gates of the OFG transistors 332 of all the light receiving units 630 in the pixel array unit 300 to a high level. With this arrangement, the plurality of OFG transistors 332 of all the light receiving units 630 enter a conducting state.

[0317] On the other hand, the driving circuit 211 maintains the control signal PG applied to the photogate 601 of all the light receiving units 630 in the pixel array unit 300 at a low level. Therefore, a photocurrent based on the charge generated in one photoelectric conversion element 3332 between the two photoelectric conversion elements 3331 and 3332 is supplied from each light receiving unit 630 to each address event detection unit 400.

[0318] In addition, during the period when the control signal OFG is set to a high level, all transmission signals TRG applied to the gate of the transmission transistor 331 in each light receiving unit 630 are maintained at a low level, and therefore, during this period, multiple transmission transistors 331 of all light receiving units 630 enter a cut-off state.

[0319] Next, it will be assumed that the address event detection unit 400 of any unit pixel 310 detects the occurrence of an address event during the period when the control signal OFG is at a high level. In this case, the address event detection unit 400 that detects the occurrence of the address event sends a request to the arbitrator 213. In this regard, the arbitrator 213 arbitrates the request and returns a response to the request to the address event detection unit 400 that issued the request.

[0320] The address event detection unit 400 receiving the response raises the detection signal input to the drive circuit 211 and the signal processing unit 212 to a high level, for example, in the period from time T1 to time T2. In addition, in this specification, it is assumed that the detection signal is a one-bit signal indicating the detection result of the ON event.

[0321] The drive circuit 211 to which the high level detection signal is input from the address event detection unit 400 at time T1 lowers all control signals OFG to low level at subsequent time T2. By this arrangement, the photocurrent supply from all light receiving units 630 of the pixel array unit 300 to the address event detection unit 400 is stopped.

[0322] On the other hand, at time T2, the drive circuit 211 raises the control signal PG applied to the photogate 601 in the light receiving unit 630 of the unit pixel 610 (hereinafter referred to as the "readout target unit pixel") in which the address event occurs to a high level. With this arrangement, in the light receiving unit 630 in the readout target unit pixel 610, the cathodes of the two photoelectric conversion elements 3331 and 3332 are connected to each other, and therefore, the two photoelectric conversion elements function as one photoelectric conversion element.

[0323] In addition, at time T2, the drive circuit 211 raises the selection signal SEL applied to the gate of the selection transistor 323 in the pixel signal generating unit 320 of the readout target unit pixel 610 to a high level, and raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel signal generating unit 320 to a high level for a constant pulse period, thereby releasing (initializing) the charge accumulated in the floating diffusion layer 324 of the pixel signal generating unit 320. In this way, the voltage appearing in the vertical signal line VSL in the state where the floating diffusion layer 324 is initialized is read out by the ADC 230 connected to the vertical signal line VSL in the column ADC 220 as a reset level pixel signal (hereinafter referred to as "reset level"), and is converted into a digital signal.

[0324] Next, at time T3 after the reset level is read out, the drive circuit 211 applies the transmission signal TRG of the constant pulse period to the gate of the transfer transistor 331 of the light receiving unit 630 in the readout target unit pixel 610. With this arrangement, the charges generated in the photoelectric conversion elements 3331 and 3332 of the light receiving unit 630 are transferred to the floating diffusion layer 324 in the pixel signal generating unit 320, and a voltage corresponding to the charges accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL. In this way, the voltage appearing in the vertical signal line VSL is read out as a signal level pixel signal (hereinafter referred to as "signal level") of the light receiving unit 630 by the ADC 230 connected to the vertical signal line VSL in the column ADC 220, and is converted into a digital value.

[0325] The signal processing unit 212 performs CDS processing in which the difference between the reset level and the signal level read out as described above is obtained as a net pixel signal corresponding to the total light reception amount of the photoelectric conversion elements 3331 and 3332 .

[0326] Next, at time T4, the driving circuit 211 lowers the selection signal SEL applied to the gate of the selection transistor 323 in the pixel signal unit 320 of the readout target unit pixel 610 and the control signal PG applied to the photogate 601 of the light receiving unit 630 to a low level, and raises the control signal OFG applied to the gate of the OFG transistor 332 of all the light receiving units 630 in the pixel array unit 300 to a high level. With this arrangement, the address event occurrence detection in all the light receiving units 630 in the pixel array unit 300 is restarted.

[0327] As described above, during the period in which the control signal OFG applied to the gates of the OFG transistors 332 of all the light receiving units 630 is raised to a high level, the multiple OFG transistors 332 of all the light receiving units 630 enter a conductive state, that is, during the period in which the occurrence of an address event is monitored, the control signal PG applied to the photogate 601 in all the light receiving units 630 in the pixel array unit 300 is maintained at a low level, and the photoelectric conversion element for monitoring the occurrence of an address event is set to, for example, a photoelectric conversion element 3332 having a capacity of about half that of the photoelectric conversion element 333. Therefore, the occurrence of an address event can be detected in a manner that is sensitive to incident light.

[0328] In addition, when a pixel signal is read out from the unit pixel 610 in which the occurrence of the address event is detected, the control signal PG applied to the photogate 601 in the light receiving unit 630 of the readout target unit pixel 610 is raised to a high level, and thus, the incident light can be received by the two photoelectric conversion elements 3331 and 3332. Therefore, the dynamic range of the acquired image can be expanded.

[0329] 3.3 Layout Example of Unit Pixels

[0330] Next, regarding a layout example in the light receiving chip 201 of the upper layer circuit 600 in the unit pixel 610 according to the present embodiment, several examples will be described.

[0331] 3.3.1 First layout example

[0332] Fig.28 is a top view showing a schematic configuration example of an upper layer circuit according to the first layout example. Fig.29 It is shown Fig.28 sectional view of a schematic configuration example along plane BB.

[0333] like Fig.28 and Fig.29 As shown, in the upper layer circuit 600-1 according to the first layout example, for example, in the same manner as in the first embodiment, Fig.11 and Fig.12In a configuration similar to that of the upper circuit 500-1 according to the first layout example described, the transfer gate 3311 is disposed approximately at the center of the side that does not intersect with the photogate 601 among the four sides of the photoelectric conversion element 333, and the OFG gate 3321 is disposed approximately at the center of the side opposite to the side on which the transfer gate 3311 is disposed.

[0334] Furthermore, in the pixel signal generating unit 320 , the reset gate 3211 of the reset transistor 321 , the amplification gate 3221 of the amplification transistor 322 , and the selection gate 3231 of the selection transistor 323 are linearly arranged in a straight line parallel to the row direction from the side where the transfer gate 3311 is provided.

[0335] Similarly, the LG gate 4111 of the LG transistor 411 and the LG gate 4141 of the LG transistor 414 in the upper detection circuit 410A are linearly arranged in a straight line from the side where the OFG gate 3321 is provided in parallel with the row direction on the side opposite to the pixel signal generating unit 320. In addition, the amplification gate 4121 of the amplification transistor 412 and the amplification gate 4131 of the amplification transistor 413 are arranged in an array parallel to the LG gates 4111 and 4141. In addition, in Fig.29 In the figure, the amplifying transistors 412 and 413 are omitted due to the cross-sectional position relationship.

[0336] In this configuration, the photogate 601 is provided in the photoelectric conversion element 333 in such a manner that the region where the N-type dopant is diffused is divided into two regions including a region including a side where the transfer gate 3311 is provided and a region including a side where the OFG gate 3321 is provided.

[0337] The other configurations are the same as in the first embodiment by using Fig.11 and Fig.12 The configuration of the described upper layer circuit 500 - 1 is similar, so a detailed description thereof will be omitted here.

[0338] 3.3.1.1 Potential of Photoelectric Conversion Element

[0339] Figure 30 to Figure 32 : is an energy band diagram showing the potential of the photoelectric conversion element according to the second embodiment. Fig.30 The potential when the transfer transistor 331 and the OFG transistor 332 of the light receiving unit 630 are set to an off state, that is, the potential in a state where the driving circuit 211 does not drive the unit pixel 610 is shown. Fig.31 The potential when the transfer transistor 331 of the light receiving unit 630 is set to the off state and the OFG transistor 332 is set to the on state, that is, in the state where the address event occurrence is monitored, is shown. Fig.32 The potential when the photo gate 601 is set to the on state, that is, in the state where charges are accumulated by using the two photoelectric conversion elements 3331 and 3332 is shown.

[0340] like Fig.30 As shown, when the driving circuit 211 does not drive the unit pixel 610, the photoelectric conversion element 333 is divided into two photoelectric conversion elements 3331 and 3332 by the potential wall under the photogate 601. Fig.31 As shown, when OFG transistor 332 is switched from Fig.30 When the state in is set to the on state, a photocurrent based on the charge generated in the photoelectric conversion element 3332 on the side flows to the LG transistor 411.

[0341] In addition, if Fig.32 As shown, when the photogate 601 is set to the on state, the potential wall that divides the photoelectric conversion element 333 into two photoelectric conversion elements 3331 and 3332 disappears, and thus, one photoelectric conversion element 333 appears. Therefore, when the transfer transistor 331 is set to the on state, the charge generated by the entire photoelectric conversion element 333 is transferred to the floating diffusion layer 324.

[0342] 3.3.2 Second layout example

[0343] Fig.33 is a top view showing a schematic configuration example of an upper layer circuit according to a second layout example. Fig.33 In the upper circuit 600-2 shown in FIG. 1 , the photogate 601 according to this embodiment can also be applied to the photogate 601 according to the first embodiment. Fig.15 An upper layer circuit 500 - 2 of the second layout example is described.

[0344] 3.3.3 Example of the third layout

[0345] Fig.34 is a top view showing a schematic configuration example of an upper layer circuit according to the third layout example. Fig.34 In the upper circuit 600-3 shown in FIG. 1 , the photogate 601 according to this embodiment can also be applied to the photogate 601 according to the first embodiment by using Fig.17 An upper layer circuit 500 - 3 of the third layout example is described.

[0346] 3.3.3.1 Variations

[0347] Furthermore, as in the third layout example, Fig.35In the upper circuit 600-3A shown, when the transmission gate 3311 and the OFG gate 3321 are respectively set at the corner portions adjacent to each other in the photoelectric conversion element 333, the photoelectric conversion element 333 can also be divided into an area where both the transmission gate 3311 and the OFG gate 3321 are set and an area where the transmission gate 3311 and the OFG gate 3321 are not included.

[0348] 3.3.4 Fourth layout example

[0349] Fig.36 is a top view showing a schematic configuration example of an upper layer circuit according to a fourth layout example. Fig.36 In the upper circuit 600-4 shown in FIG. 1 , for example, the photogate 601 according to this embodiment can also be applied to the photogate 601 according to the first embodiment by using Fig.19 An upper layer circuit 500 - 4 of the fourth layout example is described.

[0350] 3.3.5 Fifth layout example

[0351] Fig.37 is a top view showing a schematic configuration example of an upper layer circuit according to a fifth layout example. Fig.37 In the upper circuit 600-5 shown in FIG. 1 , for example, the photogate 601 according to this embodiment can also be applied to the photogate 601 according to the first embodiment by using Fig. 22 An upper layer circuit 500 - 5 of the fifth layout example is described.

[0352] In addition, in the fifth layout example, since the transmission gate 3311 and the OFG gate 3321 are respectively arranged at the corner portions adjacent to each other in the photoelectric conversion element 333, similar to the method in the third layout example, the photoelectric conversion element 333 can also be divided into an area where both the transmission gate 3311 and the OFG gate 3321 are set and an area where the transmission gate 3311 and the OFG gate 3321 are not included.

[0353] 3.3.6 Sixth layout example

[0354] Fig.38 is a top view showing a schematic configuration example of an upper layer circuit according to a sixth layout example. Fig.38 In the upper circuit 600-6 shown in FIG. 1 , the photogate 601 according to this embodiment can also be applied to the photogate 601 according to the first embodiment by using Fig.24 An upper layer circuit 500 - 6 of a sixth layout example is described. Fig.38 The photogate 601 is shown dividing the corresponding photoelectric conversion region 333 into a first portion 3331 and a second portion 3332. In this example, the photogate 601 is located in the central region of the photoelectric conversion region 333.

[0355] In addition, in the sixth layout example, since the transmission gate 3311 and the OFG gate 3321 are respectively arranged at the corner portions adjacent to each other in the photoelectric conversion element 333, similar to the method in the third layout example, the photoelectric conversion element 333 can also be divided into an area where both the transmission gate 3311 and the OFG gate 3321 are set and an area where the transmission gate 3311 and the OFG gate 3321 are not included.

[0356] 3.4 Function and Effect

[0357] As described above, according to the present embodiment, during the period of monitoring the occurrence of an address event, the control signal PG applied to the photogate 601 of all the light receiving units 630 in the pixel array unit 300 is maintained at a low level, and the photoelectric conversion element for monitoring the occurrence of an address event is set to, for example, the photoelectric conversion element 3332 having a capacity approximately half that of the photoelectric conversion element 333. Therefore, the occurrence of an address event can be detected in a manner sensitive to incident light.

[0358] In addition, when a pixel signal is read out from the unit pixel 610 in which the occurrence of an address event is detected, the control signal PG applied to the photogate 601 in the light receiving unit 630 of the readout target unit pixel 610 is raised to a high level, so that incident light can be received by using the two photoelectric conversion elements 3331 and 3332. Therefore, the dynamic range of the acquired image can be expanded.

[0359] Other configurations, operations, and effects are similar to those in the first embodiment, so detailed descriptions thereof will be omitted here.

[0360] 4. Third embodiment

[0361] Next, a solid-state imaging device and an imaging device according to a third embodiment will be described in detail with reference to the accompanying drawings. In addition, in the following description, for a structure similar to that of the above-described embodiment, its structure will be cited and repeated description will be omitted.

[0362] In the second embodiment, the case has been described where the photoelectric conversion element 333 is divided into two photoelectric conversion elements 3331 and 3332 by providing the photogate 601. In contrast, in the third embodiment, a photoelectric conversion element having substantially variable capacity is used instead of the photoelectric conversion element 333 having a fixed capacity.

[0363] The image pickup apparatus and the solid-state image pickup apparatus according to this embodiment may be similar to, for example, the image pickup apparatus 100 and the solid-state image pickup apparatus 200 described in the first embodiment. However, in this embodiment, the unit pixel 310 is replaced with a unit pixel 710 as described later.

[0364] In addition, the operation of the solid-state imaging device 200 according to the present embodiment is similar to that by using, for example, Fig. 9 and Fig.10 Describes the operation.

[0365] 4.1 Example of unit pixel construction

[0366] Fig.39 1 is a circuit diagram showing a schematic configuration example of a unit pixel according to the third embodiment. Fig.39 As shown, for example, the unit pixel 710 has Figure 5 The unit pixel 310 shown is similarly configured, and the light receiving unit 330 is replaced by a light receiving unit 730. In addition, in this embodiment, the reference numeral of the upper layer circuit is set to 700 for convenience of explanation.

[0367] The light receiving unit 730 includes a photoelectric conversion element 733 having a variable capacity, instead of the photoelectric conversion element 333. For example, the photoelectric conversion element 733 supplies a photocurrent based on charges generated by light reception to the OFG transistor 332 at a first capacity, and supplies charges generated by light reception to the transfer transistor 331 at a second capacity greater than the first capacity.

[0368] The other configurations may be similar to those in the unit pixel 310 according to the first embodiment.

[0369] 4.2 Example of unit pixel layout

[0370] Next, regarding a layout example in the light receiving chip 201 of the upper layer circuit 700 in the unit pixel 710 according to this embodiment, several examples will be described.

[0371] 4.2.1 First layout example

[0372] Fig.40 1 is a top view showing a schematic configuration example of an upper layer circuit according to a first layout example. Fig.40 As shown, in the upper layer circuit 700 - 1 according to the first layout example, for example, the photoelectric conversion element 733 is separated into two photoelectric conversion elements 7331 and 7332 by a separation section 701 provided along a diagonal line of the photoelectric conversion element 733 .

[0373] For example, in the separation portion 701, various structures can be used to separate the photoelectric conversion element 733 into two photoelectric conversion elements 7331 and 7332, such as an insulating film that physically separates the photoelectric conversion element 733 into two photoelectric conversion elements 7331 and 7332, a low diffusion region formed by counter-doping with a P-type dopant, and an N diffusion region in which the photoelectric conversion element 733 is formed.

[0374] Regarding the photoelectric conversion element 733, for example, the photoelectric conversion element 733 may be used in the same manner as that used in the first embodiment. Fig.11 In a similar manner to the first layout example described, the OFG gate 3321 is provided in one corner portion of the photoelectric conversion element 733 whose light receiving surface is rectangular in shape. The LG gate 4111 of the LG transistor 411 and the LG gate 4141 of the LG transistor 414 in the upper detection circuit 410A are linearly arranged on a straight line parallel to the row direction from the corner portion provided with the OFG gate 3321. In addition, the amplification gate 4121 of the amplification transistor 412 and the amplification gate 4131 of the amplification transistor 413 are provided in an array parallel to the LG gates 4111 and 4141.

[0375] On the other hand, the transfer gate 3311 is provided at one corner portion of the photoelectric conversion element 733 to be connected to two photoelectric conversion elements 7331 and 7332 separated by the separation portion 701. In addition, the two photoelectric conversion elements 7331 and 7332 are not short-circuited by the transfer transistor 331.

[0376] For example, in the pixel signal generating unit 320 , the reset gate 3211 of the reset transistor 321 , the amplification gate 3221 of the amplification transistor 322 , and the selection gate 3231 of the selection transistor 323 are linearly arranged on a straight line from the corner portion where the transfer gate 3311 is provided toward the lower right.

[0377] Other configurations can be similar to those in the first embodiment by using Fig.11 and Fig.12 The configuration of the upper layer circuit 500 - 1 is described, and thus a detailed description thereof will be omitted here.

[0378] 4.2.1.1 Potential of Photoelectric Conversion Element

[0379] Fig.41 is a top view of a photoelectric conversion element according to the third embodiment. Figure 42 to Figure 44 : is an energy band diagram showing the potential of the photoelectric conversion element according to the third embodiment. Fig.42 Shows Fig.41 The potential on plane CC in Fig.43 Shows Fig.41 The potential on plane DD in Fig.44 Shows Fig.41 The potential on the plane EE in FIG. 7A and 7B is a potential on the plane EE in FIG. 7B. In this specification, the separation portion 701 is set as a low diffusion region.

[0380] like Figure 42 to Figure 44As shown, the potential of the separation portion 701 in the photoelectric conversion element 733 is lower than the potentials of the photoelectric conversion elements 7331 and 7332. When the separation portion 701 having a low potential is provided to separate the photoelectric conversion element 733, the photoelectric conversion element 733 is divided into two photoelectric conversion elements 7331 and 7332.

[0381] Accordingly, when the OFG transistor 332 is set to the on state, a photocurrent based on the charge generated in the photoelectric conversion element 7332 on one side flows to the LG transistor 411 through the OFG transistor 332. On the other hand, when the transfer transistor 331 is set to the on state, the charge generated in the photoelectric conversion elements 7331 and 7332 is transferred to the floating diffusion layer 324 through the transfer transistor 331.

[0382] 4.2.2 Second layout example

[0383] Fig.45 1 is a top view showing a schematic configuration example of an upper layer circuit according to a second layout example. Fig.45 As shown, in the upper layer circuit 700 - 2 according to the second layout example, for example, the separation section 701 is provided to pass through the center of the photoelectric conversion element 733 and to extend in the column direction.

[0384] Regarding the photoelectric conversion element 733, for example, the photoelectric conversion element 733 may be configured as in the second embodiment by using Fig.28 In a similar manner to that in the first layout example described, the OFG gate 3321 is provided at approximately the center of the side not related to the separation portion 701 among the four side surfaces of the photoelectric conversion element 733. The LG gate 4111 of the LG transistor 411 and the LG gate 4141 of the LG transistor 414 in the upper layer detection circuit 410A are linearly arranged on a straight line parallel to the row direction from the side surface provided with the OFG gate 3321. In addition, the amplification gate 4121 of the amplification transistor 412 and the amplification gate 4131 of the amplification transistor 413 are arranged in an array parallel to the LG gates 4111 and 4141.

[0385] On the other hand, for example, the transfer gate 3311 is provided on the side related to the separation section 701 among the four sides of the photoelectric conversion element 733 to be connected to the two photoelectric conversion elements 7331 and 7332. The reset gate 3211 of the reset transistor 321, the amplification gate 3221 of the amplification transistor 322, and the selection gate 3231 of the selection transistor 323 in the pixel signal generating unit 320 are linearly arranged in a straight line parallel to the row direction from the side where the transfer gate 3311 is provided.

[0386] 4.2.3 Example of the third layout

[0387] Fig.46 is a top view showing a schematic configuration example of an upper layer circuit according to the third layout example. Fig.46 In the upper layer circuit 700-3 shown in FIG. 1 , the photoelectric conversion element 733 according to this embodiment can also be applied to the photoelectric conversion element 733 according to the second embodiment by using Fig.34 The upper layer circuit 600 - 3 of the third layout example is described. However, the separation portion 701 is provided along a diagonal line from a corner portion where the transfer gate 3311 in the photoelectric conversion element 733 is provided.

[0388] 4.2.4 Fourth layout example

[0389] Fig.47 is a top view showing a schematic configuration example of an upper layer circuit according to a fourth layout example. Fig.47 In the upper layer circuit 700-4 shown in FIG. 1 , the photoelectric conversion element 733 according to this embodiment can also be applied to the photoelectric conversion element 733 according to the embodiment in the second embodiment by using Fig.36 The upper layer circuit 600 - 4 of the fourth layout example is described. However, the separation portion 701 is provided along a diagonal line from a corner portion where the transfer gate 3311 in the photoelectric conversion element 733 is provided.

[0390] 4.2.5 Fifth layout example

[0391] Fig.48 is a top view showing a schematic configuration example of an upper layer circuit according to a fifth layout example. Fig.48 In the upper layer circuit 700-5 shown in FIG. 1 , the photoelectric conversion element 733 according to this embodiment can also be applied to the upper layer circuit 700-5 according to the second embodiment by using Fig.38 The upper layer circuit 600 - 6 according to the sixth layout example is described. However, the separation portion 701 is provided along a diagonal line from a corner portion where the transfer gate 3311 in the photoelectric conversion element 733 is provided.

[0392] 4.3 Function and Effect

[0393] As described above, according to the present embodiment, the capacity of the photoelectric conversion element 733 can be switched as follows. Specifically, in the case of monitoring the occurrence of an address event, the capacity of the photoelectric conversion element 733 is set to a first capacity according to the photoelectric conversion element 7331, and in the case of reading out a pixel signal, the capacity of the photoelectric conversion element 733 is set to a second capacitance combining the two photoelectric conversion elements 7331 and 7332.

[0394] With this arrangement, in monitoring address event occurrence, the address event occurrence can be detected sensitively relative to the incident light. In addition, when reading out the pixel signal, the dynamic range of the acquired image can be expanded.

[0395] Other configurations, operations, and effects are similar to those in the first or second embodiment, so detailed descriptions thereof will be omitted here.

[0396] 5. Application examples of moving objects

[0397] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device to be installed in any one of a mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile body, an airplane, a drone, a ship, a robot, etc.

[0398] Fig.49 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0399] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig.49 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown in the drawing.

[0400] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor that generates the drive force of the vehicle, a drive force transmitting mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates the braking force of the vehicle, etc.

[0401] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights (such as headlights, reverse lights, brake lights, turn signals, and fog lights, etc.). In this case, an electric wave sent from a portable device that replaces the key or a signal of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives the input electric wave or signal and controls the door lock device, power window device, lights, etc. of the vehicle.

[0402] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 allows the camera unit 12031 to capture an image outside the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing of a person, a vehicle, an obstacle, a sign, characters on the road surface, etc. based on the received image.

[0403] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or invisible light such as infrared light.

[0404] The in-vehicle information detection unit 12040 detects vehicle interior information. For example, a driver state detection unit 12041 that detects a driver state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that photographs the driver, and the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or can determine whether the driver is dozing off.

[0405] The microcomputer 12051 calculates the control target value of the driving force generating device, the steering mechanism or the braking device based on the information inside or outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and outputs a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to realize an advanced driver assistance system (ADAS) function, which includes collision avoidance or impact mitigation of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0406] In addition, the microcomputer 12051 can perform collaborative control for automatic driving, etc., for autonomous driving of the vehicle without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on the information near the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040.

[0407] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare.

[0408] The audio-visual output unit 12052 transmits at least one output signal between sound and image to an output device capable of visually or auditorily notifying passengers in or outside the vehicle of information. Fig.49 In the example of , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are exemplarily shown. For example, the display unit 12062 may include at least one of an in-vehicle display or a head-up display.

[0409] Fig.50 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0410] exist Fig.50 In the figure, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are provided.

[0411] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are installed at the front nose, rearview mirror, rear bumper or rear door, upper part of the windshield in the vehicle 12100, etc. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly obtain the image of the front side of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly obtain the image of the side of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or rear door mainly obtains the image of the rear part of the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, traffic signals, traffic signs or lanes, etc.

[0412] also, Fig.50An example of the photographing range of the camera units 12101 to 12104 is shown. The photographing range 12111 indicates the photographing range of the camera unit 12101 provided at the front nose, the photographing ranges 12112 and 12113 respectively indicate the photographing ranges of the camera units 12102 and 12103 provided at the rearview mirror, and the photographing range 12114 indicates the photographing range of the camera unit 12104 provided at the rear bumper or the rear door. For example, when a plurality of pieces of image data captured by the camera units 12101 to 12104 are superimposed on each other, when the vehicle 12100 is viewed from above, a top-view image can be obtained.

[0413] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element including pixels for phase difference detection.

[0414] For example, the microcomputer 12051 can obtain the distance to each three-dimensional object within the imaging range 12111 to 12114 and the change in the distance over time (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the nearest three-dimensional object that is on the travel path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in the same direction as the traveling vehicle 12100 as the front vehicle. In addition, the microcomputer 12051 can pre-set a safe distance from the front vehicle and perform automatic braking control (also including follow-up stop control) and automatic acceleration control (also including follow-up acceleration control), etc. As described above, cooperative control such as automatic driving in which the vehicle autonomously travels without relying on the driver's operation can be performed.

[0415] For example, the microcomputer 12051 extracts three-dimensional object data related to the three-dimensional object by classifying a plurality of three-dimensional object data into data of a two-wheeled vehicle, data of an ordinary car, data of a large vehicle, data of a pedestrian, and data of other three-dimensional objects such as a utility pole, based on the distance information obtained from the camera units 12101 to 12104, and uses the three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visually recognizable by the driver of the vehicle 12100 and obstacles that are visually difficult for the driver to recognize. In addition, the microcomputer 12051 determines a collision risk indicating the degree of danger of collision with each obstacle. In the case where the collision risk is equal to or greater than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via the audio speaker 12061 or the display unit 12062, or assists driving to avoid collision by performing forced deceleration or evasive steering through the drive system control unit 12010.

[0416] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in an image captured by the camera units 12101 to 12104. For example, pedestrian recognition is performed by extracting specific points in an image captured by the camera units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of specific points representing the contour of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the image captured by the camera units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to superimpose and display a quadrilateral contour line for emphasizing the identified pedestrian. In addition, the audio-visual output unit 12052 may control the display unit 12062 to display an icon representing a pedestrian, etc., at a desired position.

[0417] In the above, a description has been given of an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the camera unit 12031, the driver state detection unit 12041, etc. in the above-mentioned configuration.

[0418] The embodiments of the present disclosure have been described above, but the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made within the scope not departing from the gist of the present disclosure. In addition, the constituent elements in other embodiments and modifications can be appropriately combined.

[0419] In addition, the effects in the embodiments described in this specification are merely illustrative, and other effects may exist without limitation.

[0420] Furthermore, the present technology can adopt the following configurations.

[0421] (1) A solid-state imaging device comprising:

[0422] a photoelectric conversion element that generates electric charge corresponding to the amount of light received;

[0423] a first transistor connected to the photoelectric conversion element;

[0424] second to fourth transistors connected to the first transistor and arranged in a straight line;

[0425] a fifth transistor connected to the photoelectric conversion element at a position different from that of the first transistor;

[0426] sixth and seventh transistors connected to the fifth transistor and arranged in a straight line; and

[0427] Eighth and ninth transistors are arranged in an array parallel to the sixth and seventh transistors.

[0428] (2) The solid-state imaging device according to (1), wherein

[0429] The second and third transistors share a diffusion region serving as a source and a drain,

[0430] The third and fourth transistors share a diffusion region serving as a source and a drain,

[0431] The sixth and seventh transistors share a diffusion region serving as a source and a drain, and

[0432] The eighth and ninth transistors share a diffusion region serving as a source and a drain.

[0433] (3) The solid-state imaging device according to one or more of (1) to (2), wherein:

[0434] The size of the first array formed by the second to fourth transistors along the direction of the first array is equal to or smaller than the size of the photoelectric conversion element along the direction of the first array, and

[0435] A size of a second array formed by the sixth and seventh transistors along a direction of the second array is equal to or smaller than a size of the photoelectric conversion element along the direction of the second array.

[0436] (4) The solid-state imaging device according to one or more of (1) to (3), wherein:

[0437] A total area of ​​the second to fourth transistors and the sixth to ninth transistors is equal to or smaller than an area of ​​the photoelectric conversion element.

[0438] (5) The solid-state imaging device according to one or more of (1) to (4), wherein:

[0439] The light incident surface of the photoelectric conversion element has a rectangular shape,

[0440] The first transistor is disposed in a first corner portion among four corner portions of the rectangle or in a first side portion among four side portions of the rectangle, and

[0441] The fifth transistor is disposed at a second corner portion that is diagonally disposed with respect to the first corner portion or at a second side surface that is opposite to the first side surface.

[0442] (6) The solid-state imaging device according to one or more of (1) to (5), wherein:

[0443] The second to fourth transistors are arranged in a straight line along a first direction from the first transistor, and

[0444] The sixth and seventh transistors are arranged in a straight line along the first direction from the fifth transistor on the side opposite to the second to fourth transistors.

[0445] (7) The solid-state imaging device according to one or more of (1) to (6), wherein:

[0446] The second to fourth transistors are arranged in a straight line from the first transistor along the side of the photoelectric conversion element, and

[0447] The sixth and seventh transistors are arranged in a straight line from the fifth transistor along a side surface of the photoelectric conversion element.

[0448] (8) The solid-state imaging device according to one or more of (1) to (7), wherein:

[0449] The second to fourth transistors are arranged on a straight line along a first direction in a first region adjacent to the photoelectric conversion element in a first oblique direction and have the same area as that of the photoelectric conversion element,

[0450] The sixth and seventh transistors are arranged in a straight line along the first direction from the fifth transistor on the side opposite to the second to fourth transistors in a second region adjacent to the photoelectric conversion element in a second oblique direction opposite to the first oblique direction, and have the same area as that of the photoelectric conversion element, and

[0451] The eighth and ninth transistors are arranged in parallel to the array of the sixth and seventh transistors within the second region.

[0452] (9) The solid-state imaging device according to one or more of (1) to (8), wherein:

[0453] The light incident surface of the photoelectric conversion element has a rectangular shape,

[0454] The first transistor is disposed in a first corner portion among the four corner portions of the rectangle or in a first side portion among the four side portions of the rectangle, and

[0455] The fifth transistor is provided in a second corner portion adjacent to the first corner portion.

[0456] (10) The solid-state imaging device according to one or more of (1) to (9), wherein:

[0457] The second to fourth transistors are arranged in a straight line from the first transistor along a first direction, and

[0458] The sixth and seventh transistors are arranged in a straight line from the fifth transistor along the first direction, and

[0459] The eighth and ninth transistors are arranged in a straight line between the second to fourth transistors and the sixth and seventh transistors along the first direction.

[0460] (11) The solid-state imaging device according to one or more of (1) to (10), wherein:

[0461] The second to fourth transistors are arranged in a straight line along a first direction in a first region adjacent to the photoelectric conversion element along the first oblique direction and have the same area as that of the photoelectric conversion element,

[0462] A second region of the sixth and seventh transistors adjacent to the photoelectric conversion element in a second oblique direction intersecting the first oblique direction is arranged in a straight line along the first direction from the fifth transistor on a side opposite to the second to fourth transistors and has the same area as that of the photoelectric conversion element, and

[0463] The eighth and ninth transistors are arranged in parallel to the array of the sixth and seventh transistors within the second region.

[0464] (12) The solid-state imaging device according to one or more of (1) to (11), wherein:

[0465] The second to fourth transistors are arranged in a straight line along the first direction from the fifth transistor in a first region adjacent to the photoelectric conversion element along the first oblique direction and have the same area as that of the photoelectric conversion element,

[0466] The sixth and seventh transistors are arranged on a straight line along the first direction from the fifth transistor parallel to the second to fourth transistors in a second region adjacent to the photoelectric conversion element along a second oblique direction intersecting the first oblique direction, and have the same area as that of the photoelectric conversion element, and

[0467] The eighth and ninth transistors are arranged in an array parallel to the sixth and seventh transistors within the second region.

[0468] (13) The solid-state imaging device according to one or more of (1) to (12), wherein:

[0469] The light incident surface of the photoelectric conversion element has a rectangular shape,

[0470] The first transistor is disposed in a first side surface of the four sides of the rectangle,

[0471] The fifth transistor is disposed on a second side surface intersecting with the first side surface,

[0472] The second to fourth transistors are arranged in a straight line along a first direction from the first transistor, and

[0473] The sixth and seventh transistors are arranged on a straight line from the fifth transistor along a second direction orthogonal to the first direction.

[0474] (14) The solid-state imaging device according to one or more of (1) to (13), further comprising:

[0475] A photogate divides the photoelectric conversion element into two regions.

[0476] (15) The solid-state imaging device according to one or more of (1) to (14), wherein:

[0477] The photogate divides the photoelectric conversion element into a first region connected to the first transistor and a second region connected to the fifth transistor.

[0478] (16) The solid-state imaging device according to one or more of (1) to (15), wherein:

[0479] The photoelectric conversion element includes a first photoelectric conversion element and a second photoelectric conversion element.

[0480] The first transistor is connected to both the first photoelectric conversion element and the second photoelectric conversion element, and

[0481] The fifth transistor is connected to one of the first photoelectric conversion element and the second photoelectric conversion element.

[0482] (17) The solid-state imaging device according to one or more of (1) to (16), wherein:

[0483] The second to fourth transistors and the sixth to ninth transistors are metal oxide semiconductor (MOS) transistors.

[0484] (18) The solid-state imaging device according to one or more of (1) to (17), wherein:

[0485] The second to fourth transistors constitute a first circuit that generates a pixel signal having a voltage value corresponding to the amount of charge generated in the photoelectric conversion element, and

[0486] The sixth to ninth transistors constitute a second circuit that detects a photocurrent based on charges generated in the photoelectric conversion element.

[0487] (19) The solid-state imaging device according to one or more of (1) to (18), further comprising:

[0488] a first semiconductor chip including the photoelectric conversion element and the first to ninth transistors; and

[0489] a second semiconductor chip bonded to the first semiconductor chip,

[0490] The first semiconductor chip and the second semiconductor chip are electrically and mechanically connected to each other by bonding a copper pad provided in the first semiconductor chip and a copper pad provided in the second semiconductor chip to each other.

[0491] (20) A camera device, comprising:

[0492] Solid-state camera equipment;

[0493] an optical system that images incident light onto a light-receiving surface of the solid-state imaging device; and

[0494] a control unit that controls the solid-state imaging device,

[0495] The solid-state imaging device comprises:

[0496] a photoelectric conversion element that generates electric charge corresponding to the amount of light received;

[0497] a first transistor connected to the photoelectric conversion element;

[0498] second to fourth transistors, which are connected to the first transistor and arranged in a straight line,

[0499] a fifth transistor connected to the photoelectric conversion element at a position different from that of the first transistor,

[0500] sixth and seventh transistors connected to the fifth transistor and arranged in a straight line; and

[0501] Eighth and ninth transistors are arranged in an array parallel to the sixth and seventh transistors.

[0502] (21) A camera device, comprising:

[0503] a photoelectric conversion region, which converts incident light into electric charges;

[0504] a first readout circuit coupled to the photoelectric conversion region at a first position; and

[0505] A second readout circuit includes a portion coupled to the photoelectric conversion region at a second position, the second readout circuit being configured to control the first readout circuit, wherein the first position and the second position are on the same side of the photoelectric conversion region.

[0506] (22) The imaging apparatus according to (21), wherein the first position and the second position are at the same distance from a center of an edge of the photoelectric conversion region defining the side surface.

[0507] (23) The imaging apparatus according to one or more of (21) to (22), wherein the first position is at a first corner of the photoelectric conversion region, and the second position is at a second corner of the photoelectric conversion region.

[0508] (24) An imaging device according to one or more of (21) to (23), wherein the first readout circuit includes a first transistor having a first gate at the first position, and the second readout circuit includes a second transistor having a second gate at the second position.

[0509] (25) The imaging device according to one or more of (21) to (24), wherein the first readout circuit includes a plurality of third transistors coupled to the first transistor.

[0510] (26) The imaging device according to one or more of (21) to (25), wherein the second readout circuit includes a plurality of fourth transistors coupled to the second transistor.

[0511] (27) The imaging device according to one or more of (21) to (26), wherein the number of the plurality of fourth transistors is greater than the number of the plurality of third transistors.

[0512] (28) An imaging device according to one or more of (21) to (27), wherein the plurality of fourth transistors include a first group of transistors and a second group of transistors arranged along a first direction, and the first group of transistors are adjacent to the second group of transistors in a second direction perpendicular to the first direction.

[0513] (29) The imaging device according to one or more of (21) to (28), wherein the second group of transistors is located farther from a side surface of the photoelectric conversion region than the first group of transistors.

[0514] (30) The imaging device according to one or more of (21) to (29), wherein the plurality of third transistors are arranged along the first direction.

[0515] (31) A camera device, comprising:

[0516] A first pixel comprising:

[0517] a first photoelectric conversion region that converts first incident light into first charges;

[0518] a first readout circuit coupled to the first photoelectric conversion region at a first position;

[0519] as well as

[0520] a second readout circuit including a portion coupled to the first photoelectric conversion region at a second position, the second readout circuit being configured to control the first readout circuit, wherein the first position and the second position are on the same first side of the first photoelectric conversion region; and

[0521] A second pixel, which is adjacent to the first pixel in a first direction, comprises:

[0522] a second photoelectric conversion region that converts second incident light into second charges;

[0523] a third readout circuit coupled to the second photoelectric conversion region at a third position;

[0524] as well as

[0525] A fourth readout circuit includes a portion coupled to the second photoelectric conversion region at a fourth position, the fourth readout circuit being configured to control the third readout circuit, wherein the third position and the fourth position are on the same second side of the second photoelectric conversion region.

[0526] (32) The imaging apparatus according to (31), wherein the first readout circuit and the third readout circuit are located on opposite sides of the second photoelectric conversion region.

[0527] (33) An imaging device according to one or more of (31) to (32), wherein the first pixel and the second pixel are arranged so that the second photoelectric conversion region is between the first readout circuit and the second readout circuit.

[0528] (34) The imaging device according to one or more of (31) to (33), further comprising:

[0529] a third pixel, which is adjacent to the first pixel in a second direction perpendicular to the first direction, the third pixel comprising:

[0530] a third photoelectric conversion region that converts third incident light into third charges;

[0531] a fifth readout circuit coupled to the third photoelectric conversion region at a fifth position;

[0532] as well as

[0533] A sixth readout circuit includes a portion coupled to the third photoelectric conversion region at a sixth position, the sixth readout circuit being configured to control the fifth readout circuit, wherein the fifth position and the sixth position are on the same third side of the third photoelectric conversion region.

[0534] (35) The imaging device according to one or more of (31) to (34), further comprising:

[0535] a fourth pixel, which is adjacent to the second pixel in the second direction, the fourth pixel comprising:

[0536] a fourth photoelectric conversion region that converts fourth incident light into fourth charges;

[0537] a seventh readout circuit coupled to the fourth photoelectric conversion region at a seventh position; and

[0538] An eighth readout circuit includes a portion coupled to the fourth photoelectric conversion region at an eighth position, the eighth readout circuit being configured to control the seventh readout circuit, wherein the seventh position and the eighth position are on the same fourth side of the fourth photoelectric conversion region.

[0539] (36) An imaging device according to one or more of (31) to (35), wherein the third pixel and the fourth pixel are arranged so that the third photoelectric conversion region is between the seventh readout circuit and the eighth readout circuit.

[0540] (37) An imaging device according to one or more of (31) to (36), wherein the first pixel, the second pixel, the third pixel and the fourth pixel are arranged so that the second readout circuit and the fifth readout circuit are between the second photoelectric conversion region and the fourth photoelectric conversion region.

[0541] (38) An imaging device according to one or more of (31) to (37), wherein at least one of the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region and the fourth photoelectric conversion region includes a photogate, which divides the corresponding photoelectric conversion region into a first part and a second part.

[0542] (39) The imaging device according to one or more of (31) to (38), wherein the photogate is located in a central region of the photoelectric conversion region.

[0543] (40) Video equipment, including:

[0544] a photoelectric conversion region, which converts incident light into electric charges;

[0545] a first readout circuit including a first gate of a first transistor coupled to the photoelectric conversion region at a first position; and

[0546] A second readout circuit includes a second gate of a second transistor coupled to the photoelectric conversion region at a second position, the second readout circuit being configured to control the first readout circuit, wherein the first position and the second position are located in the same half of the photoelectric conversion region.

[0547] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0548] List of reference numerals

[0549] 100 Camera Equipment

[0550] 110 Camera Lens

[0551] 120 Recording Units

[0552] 130 Control unit

[0553] 200 Solid-state imaging equipment

[0554] 201 Optical Receiver Chip

[0555] 202 Logic Chip

[0556] 210 Logic Circuits

[0557] 211 drive circuit

[0558] 212 Signal Processing Unit

[0559] 213 Arbitrator

[0560] 220 columns ADC

[0561] 230 ADC

[0562] 300 pixel array unit

[0563] 310,310-1,310R,310Gr,310Gb,310B,610,710 unit pixel

[0564] 310A Basic Pattern

[0565] 320 pixel signal generation unit

[0566] 321 Reset transistor

[0567] 322 Amplifier Transistor

[0568] 323 Select transistor

[0569] 325,416 Diffusion Area

[0570] 330,630,730 Light receiving unit

[0571] 331 Pass transistor

[0572] 332 OFG transistor

[0573] 333,3331,3332,733,7331,7332 Photoelectric conversion element

[0574] 400 Address Event Detection Unit

[0575] 410 Current-voltage conversion unit

[0576] 410A Upper detection circuit

[0577] 411,414 LG transistors

[0578] 412,413 Amplifier transistor

[0579] 415 Constant Current Circuit

[0580] 420 Buffer

[0581] 430 Subtractor

[0582] 431,433 Capacitors

[0583] 432 Inverter

[0584] 434 Switch

[0585] 441 Comparator

[0586] 440 Quantizer

[0587] 450 Transmission Unit

[0588] 500,500-1,500-2,500-3,500-4,500-5,500-6,600,600-1,600-2,600-3,600-3A,600-4,600-5,600-6,700,700-1,700-2,700-3,700-4,700-5 Upper circuit

[0589] 501,511 Semiconductor substrate

[0590] 502 Microlens

[0591] 503,513 Interlayer insulation film

[0592] 504,514 Interconnection

[0593] 505,515 pads

[0594] 506,512 Copper pads

[0595] 510 Cu-Cu connector

[0596] 601 Photogate

[0597] 3211 Reset Gate

[0598] 3221 Amplifier Gate

[0599] 3231 Select Gate

[0600] 3311 Transmission Gate

[0601] 3321 OFG Gate

[0602] 4111,4141 LG gate

[0603] 4121,4131 Amplifier gate.

Claims

1. A camera device, comprising: Pixels, which include: a photoelectric conversion region, which converts incident light into electric charges; a first readout circuit coupled to the photoelectric conversion region at a first position; and A second readout circuit includes a portion coupled to the photoelectric conversion region at a second position, the second readout circuit being configured to control the first readout circuit, wherein the first position and the second position are on the same side of the photoelectric conversion region.

2. The imaging device according to claim 1, wherein: The first position and the second position are at the same distance from the center of the edge of the photoelectric conversion region defining the side surface.

3. The imaging device according to claim 2, wherein: The first position is at a first corner of the photoelectric conversion region, and wherein the second position is at a second corner of the photoelectric conversion region.

4. The imaging device according to any one of claims 1 to 3, wherein: The first readout circuit includes a first transistor having a first gate at the first position, and wherein the second readout circuit includes a second transistor having a second gate at the second position.

5. The imaging device according to claim 4, wherein: The first readout circuit includes a plurality of third transistors coupled to the first transistor.

6. The imaging device according to claim 5, wherein: The second readout circuit includes a plurality of fourth transistors coupled to the second transistor.

7. The imaging device according to claim 6, wherein: The number of the plurality of fourth transistors is greater than the number of the plurality of third transistors.

8. The imaging device according to claim 6, wherein: The plurality of fourth transistors include a first group of transistors and a second group of transistors arranged along a first direction, and the first group of transistors are adjacent to the second group of transistors in a second direction perpendicular to the first direction.

9. The imaging device according to claim 8, wherein: The second group of transistors is further away from the side surface of the photoelectric conversion region than the first group of transistors.

10. The imaging device according to claim 9, wherein: The plurality of third transistors are arranged along the first direction.

11. Camera equipment, comprising: A first pixel comprising: a first photoelectric conversion region that converts first incident light into first charges; a first readout circuit coupled to the first photoelectric conversion region at a first position; and a second readout circuit including a portion coupled to the first photoelectric conversion region at a second position, the second readout circuit being configured to control the first readout circuit, wherein the first position and the second position are on the same first side of the first photoelectric conversion region; and A second pixel, which is adjacent to the first pixel in a first direction, comprises: a second photoelectric conversion region that converts second incident light into second charges; a third readout circuit coupled to the second photoelectric conversion region at a third position; and A fourth readout circuit includes a portion coupled to the second photoelectric conversion region at a fourth position, the fourth readout circuit being configured to control the third readout circuit, wherein the third position and the fourth position are on the same second side of the second photoelectric conversion region.

12. The imaging device according to claim 11, wherein: The first readout circuit and the third readout circuit are located on opposite sides of the second photoelectric conversion region.

13. The imaging device according to claim 11 or 12, wherein: The first pixel and the second pixel are arranged so that the second photoelectric conversion region is between the first readout circuit and the second readout circuit.

14. The imaging device according to claim 13, further comprising: a third pixel, which is adjacent to the first pixel in a second direction perpendicular to the first direction, the third pixel comprising: a third photoelectric conversion region that converts third incident light into third charges; a fifth readout circuit coupled to the third photoelectric conversion region at a fifth position; and A sixth readout circuit includes a portion coupled to the third photoelectric conversion region at a sixth position, the sixth readout circuit being configured to control the fifth readout circuit, wherein the fifth position and the sixth position are on the same third side of the third photoelectric conversion region.

15. The imaging device according to claim 14, further comprising: a fourth pixel, which is adjacent to the second pixel in the second direction, the fourth pixel comprising: a fourth photoelectric conversion region that converts fourth incident light into fourth charges; a seventh readout circuit coupled to the fourth photoelectric conversion region at a seventh position; and An eighth readout circuit includes a portion coupled to the fourth photoelectric conversion region at an eighth position, the eighth readout circuit being configured to control the seventh readout circuit, wherein the seventh position and the eighth position are on the same fourth side of the fourth photoelectric conversion region.

16. The imaging device according to claim 15, wherein: The third pixel and the fourth pixel are arranged so that the third photoelectric conversion region is between the seventh readout circuit and the eighth readout circuit.

17. The imaging device according to claim 15, wherein: The first pixel, the second pixel, the third pixel, and the fourth pixel are arranged so that the second readout circuit and the fifth readout circuit are between the second photoelectric conversion region and the fourth photoelectric conversion region.

18. The imaging device according to claim 15, wherein: At least one of the first photoelectric conversion region, the second photoelectric conversion region, the third photoelectric conversion region, and the fourth photoelectric conversion region includes a photogate that divides the corresponding photoelectric conversion region into a first portion and a second portion.

19. The imaging device according to claim 18, wherein: The photogate is located in a central region of the photoelectric conversion region.

20. Camera equipment, comprising: Pixels, which include: a photoelectric conversion region, which converts incident light into electric charges; a first readout circuit including a first gate of a first transistor coupled to the photoelectric conversion region at a first position; and A second readout circuit includes a second gate of a second transistor, the second gate of the second transistor is coupled to the photoelectric conversion region at a second position, and the second readout circuit is configured to control the first readout circuit, wherein the first position and the second position are located in the same half of the photoelectric conversion region.

Images