Semiconductor device, semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device, a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductor. The preparation method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, the semiconductor substrate comprises spaced apart isolation structures and a first active region located between two adjacent isolation structures, and the first active region has a preset epitaxial region; forming a preset semiconductor layer on the preset epitaxial region, the electron affinity energy of the preset semiconductor layer is greater than the electron affinity energy of the semiconductor substrate; forming a gate dielectric layer on the surface formed by the preset semiconductor layer and the semiconductor substrate; and forming a gate layer on the surface of the gate dielectric layer. The semiconductor device, the semiconductor structure and the preparation method thereof can reduce the thickness of the gate layer, improve the gate control ability of the gate layer, reduce the short channel effect, simplify the preparation process and reduce the production cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a semiconductor structure, and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor technology, the size of devices in integrated circuits (ICs) is becoming smaller and smaller. For example, as the size of integrated circuits shrinks, the size of transistors also becomes smaller, their gate control capability weakens, and the short-channel effect becomes more pronounced. Therefore, thinner gate dielectrics are needed to improve gate control capability and reduce the short-channel effect.

[0003] Existing semiconductor devices use materials with high dielectric constants to replace traditional silicon oxide as the gate dielectric layer. However, this requires multiple integrations of the gate dielectric layer with high dielectric constants, making the fabrication process complex and the production cost high.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor device, semiconductor structure and its fabrication method, which can reduce the gate layer thickness, improve the gate control capability of the gate layer, reduce the short-channel effect, simplify the fabrication process and reduce the production cost.

[0006] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0007] A semiconductor substrate is provided, the semiconductor substrate including spaced isolation structures and a first active region located between two adjacent isolation structures, the first active region having a preset epitaxial region;

[0008] A predetermined semiconductor layer is formed in the predetermined epitaxial region, wherein the electron affinity of the predetermined semiconductor layer is greater than that of the semiconductor substrate;

[0009] A gate dielectric layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate;

[0010] A gate layer is formed on the surface of the gate dielectric layer.

[0011] In one exemplary embodiment of this disclosure, the preparation method further includes:

[0012] An inwardly recessed groove is formed within the preset epitaxial region, and the preset semiconductor layer is formed within the groove.

[0013] In one exemplary embodiment of this disclosure, forming an inwardly recessed groove within the predetermined extensional region includes:

[0014] A photoresist layer is formed on the surface of the preset epitaxial region;

[0015] The photoresist layer is exposed and developed to form a developing area, which exposes the surface of the preset epitaxial region;

[0016] The preset epitaxial region is etched in the developing area to a preset depth to form a groove;

[0017] Remove the photoresist layer.

[0018] In one exemplary embodiment of this disclosure, forming a preset semiconductor layer in the preset epitaxial region includes:

[0019] A germanium-silicon layer is formed in the preset epitaxial region using an epitaxial process.

[0020] In one exemplary embodiment of this disclosure, the germanium content in the germanium-silicon layer is 10% to 60%.

[0021] In one exemplary embodiment of this disclosure, forming a preset semiconductor layer in the preset epitaxial region further includes:

[0022] A silicon layer is formed on the side of the germanium-silicon layer away from the semiconductor substrate using an epitaxial process.

[0023] In one exemplary embodiment of this disclosure, the semiconductor substrate further includes a second active region formed on the side of the isolation structure away from the first active region.

[0024] In one exemplary embodiment of this disclosure, forming a gate dielectric layer on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate includes:

[0025] An interface layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate. The interface layer covers the top surface of the first active region and the second active region and is in contact with the surface of the preset semiconductor layer away from the semiconductor substrate.

[0026] A first dielectric layer is formed on the interface layer;

[0027] A second dielectric layer is formed on the side of the first dielectric layer away from the interface layer, and the second dielectric layer is disposed opposite to the second active region.

[0028] In one exemplary embodiment of this disclosure, a second dielectric layer is formed on the side of the first dielectric layer away from the interface layer, and the second dielectric layer is disposed opposite to the second active region, including:

[0029] A reference dielectric layer is formed on the side of the first dielectric layer away from the interface layer using chemical vapor deposition.

[0030] A photoresist layer is formed on the surface of the reference dielectric layer away from the first dielectric layer;

[0031] The photoresist layer is exposed and developed to form a developing area, the developing area exposing the reference dielectric layer disposed opposite to the second active area;

[0032] The reference dielectric layer is etched in the developing area to form a pattern;

[0033] Remove the photoresist layer.

[0034] In one exemplary embodiment of this disclosure, the material of the interface layer is silicon oxide, the material of the first dielectric layer is hafnium oxide, and the material of the second dielectric layer is lanthanum oxide.

[0035] In one exemplary embodiment of this disclosure, the semiconductor substrate is made of silicon, and the fabrication method further includes:

[0036] P-type doping is performed on the first active region and / or n-type doping is performed on the second active region.

[0037] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0038] A semiconductor substrate includes spaced-apart isolation structures and a first active region located between two adjacent isolation structures, the first active region having a predetermined epitaxial region;

[0039] A preset semiconductor layer is formed in the preset epitaxial region, and the electron affinity of the preset semiconductor layer is greater than that of the semiconductor substrate;

[0040] A gate dielectric layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate;

[0041] A gate layer is formed on the surface of the gate dielectric layer.

[0042] In one exemplary embodiment of this disclosure, the preset epitaxial region has an inwardly recessed groove, and the preset semiconductor layer is formed within the groove.

[0043] In one exemplary embodiment of this disclosure, the preset semiconductor layer includes:

[0044] A germanium-silicon layer is located in the preset epitaxial region, and the thickness of the germanium-silicon layer is 2nm to 15nm.

[0045] In one exemplary embodiment of this disclosure, the germanium content in the germanium-silicon layer is 10% to 60%.

[0046] In one exemplary embodiment of this disclosure, the preset semiconductor layer further includes:

[0047] A silicon layer is located on the side of the germanium-silicon layer away from the semiconductor substrate, and the thickness of the silicon layer is 0.1 nm to 2 nm.

[0048] In one exemplary embodiment of this disclosure, the semiconductor substrate further includes a second active region formed on the side of the isolation structure away from the first active region.

[0049] In one exemplary embodiment of this disclosure, the gate dielectric layer includes:

[0050] An interface layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate, and covers the top surface of the first active region and the second active region, and is in contact with the surface of the preset semiconductor layer away from the semiconductor substrate;

[0051] A first dielectric layer is formed on the interface layer;

[0052] The second dielectric layer is formed on the side of the first dielectric layer away from the interface layer and is disposed directly opposite the second active region.

[0053] In one exemplary embodiment of this disclosure, the material of the interface layer is silicon oxide, the material of the first dielectric layer is hafnium oxide, and the material of the second dielectric layer is lanthanum oxide.

[0054] According to one aspect of this disclosure, a semiconductor device is provided, comprising the semiconductor structure described in any of the preceding claims.

[0055] The semiconductor device, semiconductor structure, and fabrication method disclosed herein, on the one hand, can adjust the electron affinity of the first active region by pre-setting the semiconductor layer, thereby independently adjusting the threshold voltage of the semiconductor structure; on the other hand, by placing the pre-setting semiconductor layer between the semiconductor substrate and the gate dielectric layer, the deposition of the pre-setting semiconductor layer in the gate dielectric layer can be avoided, and the gate control capability of the gate dielectric layer can be improved, the short-channel effect can be reduced, and at the same time, multiple integrations of the gate dielectric layer and the gate layer can be avoided, simplifying the fabrication process and reducing production costs.

[0056] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0058] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0059] Figure 2 This is a schematic diagram of the structure of a semiconductor substrate according to an embodiment of the present disclosure.

[0060] Figure 3 for Figure 1 Flowchart of step S110.

[0061] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0062] Figure 5 for Figure 1 Flowchart of step S130.

[0063] Figure 6 For corresponding Figure 5 A schematic diagram of the structure after completing step S1310.

[0064] Figure 7 For corresponding Figure 5 A schematic diagram of the structure after step S1320 is completed.

[0065] Figure 8 For corresponding Figure 5 A schematic diagram of the structure after completing step S1330.

[0066] Figure 9 for Figure 8 Flowchart of step S1330.

[0067] In the figure: 1. Semiconductor substrate; 11. Isolation structure; 12. First active region; 13. Second active region; 2. Preset semiconductor layer; 3. Gate dielectric layer; 31. Interface layer; 32. First dielectric layer; 33. Second dielectric layer; 4. Gate layer. Detailed Implementation

[0068] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0069] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0070] The terms “a,” “one,” “the,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc. The terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0071] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the 1 may include:

[0072] Step S110: A semiconductor substrate is provided, the semiconductor substrate including spaced isolation structures and a first active region located between two adjacent isolation structures, the first active region having a preset epitaxial region;

[0073] Step S120: A preset semiconductor layer is formed in the preset epitaxial region, wherein the electron affinity of the preset semiconductor layer is greater than the electron affinity of the semiconductor substrate;

[0074] Step S130: A gate dielectric layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate;

[0075] Step S140: A gate layer is formed on the surface of the gate dielectric layer.

[0076] The semiconductor structure fabrication method disclosed herein, on the one hand, can adjust the electron affinity of the first active region by pre-setting the semiconductor layer, thereby independently adjusting the threshold voltage of the semiconductor structure; on the other hand, by placing the pre-setting semiconductor layer between the semiconductor substrate and the gate dielectric layer, it is possible to avoid depositing the pre-setting semiconductor layer in the gate dielectric layer, improve the gate control capability of the gate dielectric layer, reduce the short-channel effect, and at the same time avoid multiple integrations of the gate dielectric layer and the gate layer, simplifying the fabrication process and reducing production costs.

[0077] The steps of the method for fabricating the semiconductor structure according to the present disclosure will be described in detail below:

[0078] In step S110, a semiconductor substrate is provided, the semiconductor substrate including spaced isolation structures and a first active region located between two adjacent isolation structures, the first active region having a preset epitaxial region.

[0079] The semiconductor substrate can be a planar structure, and its shape can be circular, rectangular, or other shapes. The material of the semiconductor substrate can be silicon, but is not limited to silicon; it can also be other materials, such as silicon-on-insulator or germanium, etc., without special limitations. Figure 2 As shown, the semiconductor substrate 1 may include spaced-apart isolation structures 11 and a first active region 12 located between two adjacent isolation structures 11. The isolation structure 11 may include a recessed portion extending inward from the surface of the semiconductor substrate 1. This recessed portion may extend from the top surface of the semiconductor substrate 1 to the bottom, but does not extend to the bottom of the semiconductor substrate 1. The cross-sectional shape of the recessed portion may be an inverted trapezoid, a rectangle, or other shapes, without particular limitation. The recessed portion may be filled with an isolation material, which may be silicon oxide. Of course, the isolation material may also be other materials used to isolate the active region, which will not be listed here. The first active region 12 may be P-type doped to form a P-type semiconductor. For example, the first active region 12 may be doped with a P-type dopant material, which may be an element located in Group III of the periodic table, for example, boron or indium. Of course, it may also be other elements, which will not be listed here.

[0080] The first active region 12 may have a preset extension region. The preset extension region may be a pre-defined extension area, the area of ​​which may be less than or equal to the area of ​​the surface of the first active region, and its shape may be a rectangle, a circle, an ellipse, a triangle, a polygon or an irregular shape, without any special limitation.

[0081] In one embodiment, the semiconductor substrate 1 may further include a second active region 13, which may be formed on the side of the isolation structure 11 away from the first active region 12. The second active region 13 may be n-type doped; for example, an n-type dopant material may be doped into the second active region 13 to form an n-type semiconductor. The n-type dopant material may be an element located in Group IV of the periodic table, for example, phosphorus. Of course, it may also be materials of other elements, which will not be listed here.

[0082] It should be noted that the semiconductor substrate 1 may include multiple first active regions 12 and multiple second active regions 13, and each first active region 12 and each second active region 13 may be spaced apart and isolated by an isolation structure 11. No specific limitation is made on the number of first active regions 12 and second active regions 13. Furthermore, each first active region 12 may have a preset epitaxial region, and two adjacent preset epitaxial regions may be interconnected or not interconnected; no specific limitation is made here.

[0083] An inwardly recessed groove can be formed within a preset epitaxial region. The width of the groove can be greater than the width of the semiconductor channel, meaning the orthographic projection of the semiconductor channel can completely fall within the groove. This groove can be filled with material used to control the threshold voltage of the first active region 12, thereby achieving independent control of the threshold voltage. The cross-section in the longitudinal direction can be rectangular, polygonal, semi-circular, or irregular in shape; of course, other shapes are also possible, without special limitations. Figure 3 As shown, in one embodiment, forming an inwardly recessed groove within a predetermined extensional region may include:

[0084] Step S1110: A photoresist layer is formed on the surface of the preset epitaxial region.

[0085] A photoresist layer can be formed on the surface of the semiconductor substrate 1 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the photoresist layer away from the surface of the semiconductor substrate 1 can be the same as the shape of the surface of the semiconductor substrate 1. For example, when the surface of the semiconductor substrate 1 is rectangular, the shape of the photoresist layer can also be rectangular; when the surface of the semiconductor substrate 1 is circular, the shape of the photoresist layer can also be circular, without special limitation.

[0086] Step S1120: Expose the photoresist layer and develop it to form a developing area, the developing area exposing the surface of the preset epitaxial region.

[0087] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the pattern required for the groove. Subsequently, the exposed photoresist layer can be developed to form a developed area, which can expose a portion of the preset epitaxial region, and the pattern of the developed area can be the same as the pattern required for the groove, and the width of the developed area can be the same as the size of the required groove.

[0088] Step S1130: Etch the preset epitaxial region in the developing area to a preset depth to form a groove.

[0089] The pre-defined epitaxial region can be etched in the developing area using processes such as dry etching, wet etching, or plasma etching. The etching depth can be the pre-defined depth of the groove. For example, the pre-defined depth can be 2 to 15 nm. For instance, the depth can be 2 nm, 5 nm, 8 nm, 11 nm, 14 nm, or 15 nm. Of course, other depths are also possible, which can be set according to the actual size of the semiconductor structure. They will not be listed here.

[0090] Step S1140: Remove the photoresist layer.

[0091] After completing the above etching process, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing, so that the surface of the semiconductor substrate 1 is no longer covered by the photoresist layer and the formed groove can be exposed.

[0092] In step S120, a preset semiconductor layer is formed in the preset epitaxial region, wherein the electron affinity of the preset semiconductor layer is greater than that of the semiconductor substrate.

[0093] A predetermined semiconductor layer 2 can be formed in a predetermined epitaxial region of the first active region 12 using an epitaxial process. The electron affinity of the predetermined semiconductor layer 2 can be greater than that of the semiconductor substrate. For example, its material can be germanium-silicon. Of course, other materials that can be used to adjust the electron affinity of the semiconductor structure can also be used, without special limitation. The predetermined semiconductor layer 2 can be a single layer or multiple layers, without special limitation. For example, it can include a germanium-silicon layer, which can be formed in the predetermined epitaxial region using an epitaxial process. The germanium-silicon layer can be a thin film formed in the predetermined epitaxial region. The germanium content in the germanium-silicon layer can be 10% to 60%, for example, it can be 10%, 20%, 30%, 40%, 50%, or 60%. The thickness of the germanium-silicon layer can be 2nm to 15nm, for example, it can be 2nm, 5nm, 8nm, 11nm, 14nm, or 15nm. Of course, the thickness and germanium content of the germanium-silicon layer can also be other, which will not be listed here.

[0094] The pre-defined semiconductor layer 2 may further include a silicon layer, which can be formed on the side of the germanium-silicon layer away from the semiconductor substrate 1 using an epitaxial process. This silicon layer ensures that the silicon content on the surfaces of the first active region 12 and the second active region 13 is the same, preventing uneven growth thickness of other layers when they are formed on the first active region 12 and the second active region 13 due to differences in silicon content on their surfaces. In one embodiment, the silicon layer can completely cover the side of the germanium-silicon layer away from the bottom of the semiconductor substrate 1. The thickness of this silicon layer can be much smaller than the thickness of the germanium-silicon layer. For example, its thickness can be 0.1 nm to 2 nm, such as 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, or 2 nm. Of course, other thicknesses are also possible and are not specifically limited here.

[0095] In one embodiment, a preset semiconductor layer 2 can be formed within a groove, covering the entire groove and flush with the top surface of the first active region 12. It can be used to adjust the threshold voltage within the semiconductor substrate 1, thereby allowing independent adjustment of the threshold voltage of the semiconductor structure. Furthermore, placing the preset semiconductor layer 2 within a groove in the semiconductor substrate 1 avoids the need to form the preset semiconductor layer 2 separately on the semiconductor substrate 1, helping to reduce device thickness, simplify the fabrication process, and lower production costs.

[0096] It should be noted that the preset semiconductor layer 2 can also be formed on the surface of the preset epitaxial region on the top surface of the first active region 12, without any special limitation.

[0097] In step S130, a gate dielectric layer is formed on the surface formed by the preset semiconductor layer and the semiconductor substrate.

[0098] A gate dielectric layer can be formed on the surface jointly formed by the pre-defined semiconductor layer 2 and the semiconductor substrate 1 using methods such as chemical vapor deposition, physical vapor deposition, thermal oxidation, spin coating, coating, inkjet printing, screen printing, or electroplating. The gate dielectric layer may include a multilayer structure. In one embodiment, such as... Figure 4 As shown, the gate dielectric layer 3 may include an interface layer 31, a first dielectric layer 32, and a second dielectric layer 33. Of course, the gate dielectric layer 3 may also include other layers, which are not specifically limited here. In addition, the gate dielectric layer 3 may be in contact with the top surface of the isolation structure 11 and the preset semiconductor layer 2 for gate control.

[0099] In one implementation, such as Figure 5 As shown, step S130 may include:

[0100] Step S1310: An interface layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate. The interface layer covers one side of the top surface of the first active region and the second active region and is in contact with the surface of the preset semiconductor layer away from the semiconductor substrate.

[0101] The surface of the semiconductor substrate 1 may have multiple interface regions arranged side by side and spaced apart. Each interface region may be disposed on the top surface of the first active region 12 and the second active region 13, and may be in contact with the surface of each isolation structure 11. For example Figure 6 As shown, interface layers 31 can be formed on each interface region through a thermal oxidation process. Of course, interface layers 31 can also be formed on each interface region through other methods, without any particular limitation. For example, a reference interface layer 31 covering the semiconductor substrate 1 can be formed on the top surface of the semiconductor substrate 1 through thermal oxidation. The reference interface layer 31 on the top surface of the isolation structure 11 can be removed by photolithography, exposing the top surface of the isolation structure 11, while retaining the reference interface layers 31 of the first active region 12 and the second active region 13. The reference interface layer 31 located on the top surface of the first active region 12 and the second active region 13 is used as the interface layer 31. During the thermal oxidation process, the interface layer 31 can be made to contact the surface of the preset semiconductor layer 2 away from the semiconductor substrate 1 to ensure gate control capability. Of course, the interface region can also be a whole region, which can be the surface jointly composed of the preset semiconductor layer 2, the semiconductor substrate 1, and the isolation structure 11. The interface layer 31 can be formed on the surface jointly composed of the preset semiconductor layer 2, the semiconductor substrate 1, and the isolation structure 11 through a thermal oxidation process.

[0102] The material of the interface layer 31 can be the same as or different from the material of the isolation structure 11, and no special limitation is made here. For example, the material of the interface layer 31 can be silicon oxide, and of course, it can also be other materials, which will not be listed here.

[0103] Step S1320: A first dielectric layer is formed on the interface layer.

[0104] like Figure 7 As shown, the first dielectric layer 32 can be a thin film formed on the surface of the interface layer 31. The first dielectric layer 32 can be formed on the interface layer 31 using processes such as chemical vapor deposition, physical vapor deposition, spin coating, inkjet printing, screen printing, coating, or vacuum evaporation. Of course, other processes can also be used to form the first dielectric layer 32, and no particular limitation is made here. The first dielectric layer 32 can include a material with a high dielectric constant to increase the physical size of the gate layer 3 while ensuring gate control capability. For example, the material can be hafnium oxide, hafnium oxide, silicon oxide, or mixtures thereof. Other materials can also be used, and no particular limitation is made here, as long as they can be used to improve the gate control capability of the gate layer 3.

[0105] Step S1330: A second dielectric layer is formed on the side of the first dielectric layer away from the interface layer, and the second dielectric layer is disposed opposite to the second active region.

[0106] like Figure 8 As shown, the second dielectric layer 33 can be a thin film formed on the first dielectric layer 32. The second dielectric layer 33 can be formed on the first dielectric layer 32 through processes such as chemical vapor deposition, physical vapor deposition, spin coating, inkjet printing, screen printing, coating, or vacuum evaporation. It can also be formed on the first dielectric layer 32 through vacuum evaporation. Of course, other processes can also be used to form the second dielectric layer 33, and no specific limitations are made here.

[0107] The second dielectric layer 33 may be disposed opposite to the second active region 13, and may include a material with a high dielectric constant, which helps to further adjust the threshold voltage. For example, the material of the second dielectric layer 33 may be lanthanum oxide. The diffusion of lanthanum can further change the overall polarization capability of the gate dielectric layer, thereby changing the overall dielectric constant of the gate dielectric. Of course, other materials may also be used, without special limitation here.

[0108] In one implementation, such as Figure 9 As shown, step S1330 may include:

[0109] Step S1331: A reference dielectric layer is formed on the side of the first dielectric layer away from the interface layer by chemical vapor deposition.

[0110] The reference dielectric layer can be a thin film formed on the first dielectric layer 32. It can be formed on the surface of the first dielectric layer 32 away from the interface layer 31 using chemical vapor deposition. This reference dielectric layer can completely or partially cover the first dielectric layer 32; no particular limitation is made here. It can include materials with high dielectric constants, which helps to adjust the threshold voltage. For example, the material of the reference dielectric layer can be lanthanum oxide; of course, other materials can also be used, without particular limitation.

[0111] Step S1332: A photoresist layer is formed on the surface of the reference dielectric layer away from the first dielectric layer.

[0112] A photoresist layer can be formed on the surface of the first dielectric layer 32 by spin coating or other methods. The material of the photoresist layer can be positive or negative photoresist, without special limitation. The shape of the surface of the photoresist layer away from the first dielectric layer 32 can be the same as the shape of the surface of the first dielectric layer 32. For example, when the surface of the first dielectric layer 32 is rectangular, the shape of the photoresist layer can also be rectangular; when the surface of the first dielectric layer 32 is circular, the shape of the photoresist layer can also be circular, without special limitation.

[0113] Step S1333: Expose the photoresist layer and develop it to form a developing area, wherein the developing area exposes the reference dielectric layer disposed opposite to the second active area.

[0114] A photomask can be used to expose the photoresist layer, and the pattern of the photomask can match the required pattern of the reference dielectric layer. Subsequently, the exposed photoresist layer can be developed to form a developed area, which exposes the area other than the area directly opposite the second active region 13, and the pattern of the developed area can be the same as the required pattern of the reference dielectric layer.

[0115] Step S1334: The reference dielectric layer is etched in the developing area to form a pattern.

[0116] The reference dielectric layer can be etched in the developing area by processes such as dry etching, wet etching or plasma etching, thereby removing the portion of the reference dielectric layer that is directly opposite to the first active region 12 to obtain the second dielectric layer 33, and the second dielectric layer 33 can be positioned directly opposite the second active region 13.

[0117] Step S1335: Remove the photoresist layer.

[0118] After the above etching process is completed, the photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes, so that the surface of the first dielectric layer 32 is no longer covered by the photoresist layer.

[0119] Step S140: A gate layer is formed on the surface of the gate dielectric layer.

[0120] The gate layer 4 can be formed on the surface of the gate dielectric layer 3 by processes such as chemical vapor deposition, physical vapor deposition, spin coating, inkjet printing, screen printing, coating or vacuum evaporation. Specifically, the gate layer 4 can be formed on the surface jointly formed by the second dielectric layer 33 and the first dielectric layer 32 by chemical vapor deposition, or on the surface jointly formed by the second dielectric layer 33 and the first dielectric layer 31 by vacuum evaporation. Of course, other processes can also be used to form the gate layer 4, which are not specifically limited here.

[0121] like Figure 4As shown, the gate layer 4 can be a thin film on the surface jointly formed by the second dielectric layer 33 and the first dielectric layer 32. The material of the gate layer 4 can be titanium nitride, but other materials are also possible and not specifically limited here. In one embodiment, a work function layer can also be formed on the second dielectric layer 33 before forming the gate layer 4. This work function layer can be used to adjust the work function of the gate layer 4, thereby facilitating the adjustment of the device's threshold voltage. For example, the gate layer 4 can include a material with a high work function, such as titanium nitride, tungsten, or rubidium. Of course, other materials are also possible, which will not be listed here.

[0122] This disclosure also provides a semiconductor structure, such as Figure 4 As shown, it may include a semiconductor substrate 1, a pre-defined semiconductor layer 2, a gate dielectric layer 3, and a gate layer 4, wherein:

[0123] The semiconductor substrate 1 may include an isolation structure 11 spaced apart and a first active region 12 located between two adjacent isolation structures 11. The first active region 12 may have a preset epitaxial region.

[0124] The preset semiconductor layer 2 can be formed in the preset epitaxial region, and the electron affinity of the preset semiconductor layer 2 is greater than that of the semiconductor substrate;

[0125] A gate dielectric layer 3 is formed on the surface jointly formed by the preset semiconductor layer 2 and the semiconductor substrate 1;

[0126] Gate layer 4 is formed on the surface of gate dielectric layer 3.

[0127] The semiconductor structure disclosed herein allows for the independent adjustment of the threshold voltage of the semiconductor structure by adjusting the electron affinity of the first active region 12 through the preset semiconductor layer 2. Furthermore, by placing the preset semiconductor layer 2 between the semiconductor substrate 1 and the gate dielectric layer 3, the deposition of the preset semiconductor layer 2 in the gate dielectric layer 3 can be avoided, and the gate control capability of the gate dielectric layer 3 can be improved, reducing the short-channel effect. At the same time, it avoids multiple integrations of the gate dielectric layer 3 and the gate layer 4, simplifying the fabrication process and reducing production costs.

[0128] The semiconductor structure of the present disclosure embodiment will be described in detail below:

[0129] The semiconductor substrate 1 can be a flat plate structure, and its shape can be circular, rectangular, or other shapes. The material of the semiconductor substrate 1 can be silicon, but is not limited to silicon; it can also be other materials, such as silicon-on-insulator, germanium, or silicon carbide, etc., without special limitation. The semiconductor substrate 1 can include spaced-apart isolation structures 11 and a first active region 12 located between two adjacent isolation structures 11. The isolation structure 11 can include a recessed portion that extends inward from the surface of the semiconductor substrate 1. The recessed portion can extend from the top surface of the semiconductor substrate 1 to the bottom, but does not extend to the bottom of the semiconductor substrate 1. The cross-sectional shape of the recessed portion can be an inverted trapezoid, a rectangle, or other shapes, without special limitation. The recessed portion can be filled with an isolation material, which can be silicon oxide. Of course, the isolation material can also be other materials used to isolate the active region, which will not be listed here. P-type doping can be performed on the first active region 12 to form a P-type semiconductor. For example, P-type doping material can be doped into the first active region 12. The P-type doping material can be an element located in Group III of the periodic table. For example, it can be boron or indium. Of course, it can also be other elements, which will not be listed here.

[0130] The top surface of the first active region 12 may have a preset extension region. The preset extension region may be a pre-defined extension area, the area of ​​which may be less than or equal to the area of ​​the top surface of the first active region 12, and its shape may be a rectangle, a circle, an ellipse, a triangle, a polygon or an irregular shape, without any special limitation.

[0131] In one embodiment, the semiconductor substrate 1 may further include a second active region 13, which may be formed on the side of the isolation structure 11 away from the first active region 12. The second active region 13 may be n-type doped; for example, an n-type dopant material may be doped into the second active region 13 to form an n-type semiconductor. The n-type dopant material may be an element located in Group IV of the periodic table, for example, phosphorus. Of course, it may also be materials of other elements, which will not be listed here.

[0132] It should be noted that the semiconductor substrate 1 may include multiple first active regions 12 and multiple second active regions 13, and each first active region 12 and each second active region 13 may be spaced apart and isolated by an isolation structure 11. The number of first active regions 12 and second active regions 13 is not specifically limited here. Furthermore, each first active region 12 may have a preset epitaxial region on its top surface, and adjacent preset epitaxial regions may be interconnected or not interconnected; no special limitation is made here.

[0133] The pre-defined epitaxial region may have inwardly recessed grooves to facilitate the filling of material used to control the electron affinity of the first active region 12, thereby achieving independent control of the threshold voltage. The cross-section of the groove in the longitudinal direction may be rectangular, polygonal, semi-circular, or irregular in shape; of course, other shapes are also possible, without special limitation. The groove may have a preset depth, for example, it may be 2–15 nm, such as 2 nm, 5 nm, 8 nm, 11 nm, 14 nm, or 15 nm; of course, other depths are also possible, which can be set according to the actual dimensions of the semiconductor structure, and will not be listed here.

[0134] A predetermined semiconductor layer 2 can be formed in a predetermined epitaxial region of the first active region 12. The electron affinity of the predetermined semiconductor layer 2 can be greater than that of the semiconductor substrate. For example, its material can be germanium-silicon. Of course, other materials that can be used to adjust the electron affinity of the semiconductor structure can also be used, without special limitation. The predetermined semiconductor layer 2 can be a single layer or multiple layers, without special limitation. For example, it can include a germanium-silicon layer, which can be formed in the predetermined epitaxial region using an epitaxial process. The germanium-silicon layer can be a thin film formed in the predetermined epitaxial region. The germanium content in the germanium-silicon layer can be 10% to 60%, for example, it can be 10%, 20%, 30%, 40%, 50%, or 60%. The thickness of the germanium-silicon layer can be 2nm to 15nm, for example, it can be 2nm, 5nm, 8nm, 11nm, 14nm, or 15nm. Of course, the thickness and germanium content of the germanium-silicon layer can also be other, which will not be listed here.

[0135] The pre-defined semiconductor layer 2 may further include a silicon layer, which can be formed on the side of the germanium-silicon layer away from the semiconductor substrate 1 using an epitaxial process. This silicon layer ensures that the silicon content on the surfaces of the first active region 12 and the second active region 13 is the same, preventing uneven growth thickness of other layers when they are formed on the first active region 12 and the second active region 13 due to differences in silicon content on their surfaces. In one embodiment, the silicon layer can completely cover the side of the germanium-silicon layer away from the bottom of the semiconductor substrate 1. The thickness of this silicon layer can be much smaller than the thickness of the germanium-silicon layer. For example, its thickness can be 0.1 nm to 2 nm, such as 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, or 2 nm. Of course, other thicknesses are also possible and are not specifically limited here.

[0136] In one embodiment, a pre-defined semiconductor layer 2 can be formed within a groove. For example, the pre-defined semiconductor layer 2 can be formed within the groove using an epitaxial process. This pre-defined semiconductor layer 2 can cover the entire groove and be flush with the top surface of the first active region 12. It can be used to adjust the electron affinity within the semiconductor substrate 1, thereby independently adjusting the threshold voltage of the semiconductor structure. Furthermore, placing the pre-defined semiconductor layer 2 within a groove in the semiconductor substrate 1 avoids forming the pre-defined semiconductor layer 2 separately on the semiconductor substrate 1, which helps reduce the device thickness. At the same time, it simplifies the fabrication process and reduces production costs.

[0137] It should be noted that the preset semiconductor layer 2 can also be formed on the surface of the preset epitaxial region on the top surface of the first active region 12, without any special limitation.

[0138] The gate dielectric layer 3 may be formed on the surface jointly formed by the pre-defined semiconductor layer 2 and the semiconductor substrate 1, and may include a multilayer structure. In one embodiment, such as... Figure 4 As shown, it may include an interface layer 31, a first dielectric layer 32, and a second dielectric layer 33. Of course, the gate dielectric layer 3 may also include other layers, which are not specifically limited here. In addition, the gate dielectric layer 3 may be in contact with the top surface of the isolation structure 11 and the preset semiconductor layer 2 for gate control.

[0139] like Figure 6 As shown, the interface layer 31 can be formed on the surface jointly formed by the preset semiconductor layer 2 and the semiconductor substrate 1, and can cover the side of the first active region 12 and the second active region 13 away from the semiconductor substrate 1, and can contact the surface of the preset semiconductor layer 2 away from the semiconductor substrate 1. Specifically, the surface of the semiconductor substrate 1 can have multiple interface regions arranged side by side at intervals, each interface region can be respectively disposed on the top surface of the first active region 12 and the second active region 13, and can contact and connect with the surface of each isolation region. The interface layer 31 can be formed on each interface region, and each interface layer 31 can expose the top surface of the isolation structure 11, and can contact the surface of the preset semiconductor layer 2 away from the semiconductor substrate 1, so as to ensure gate control capability. Of course, the interface region can also be a whole region, which can be the surface jointly formed by the preset semiconductor layer 2, the semiconductor substrate 1 and the isolation structure 11, and the interface layer 31 can be formed on the surface jointly formed by the preset semiconductor layer 2, the semiconductor substrate 1 and the isolation structure 11 by thermal oxidation process.

[0140] The material of the interface layer 31 can be the same as or different from the material of the isolation structure 11, and no special limitation is made here. For example, the material of the interface layer 31 can be silicon oxide, and of course, it can also be other materials, which will not be listed here.

[0141] The first dielectric layer 32 may be a thin film formed on the surface jointly formed by the interface layer 31 and the isolation structure 11. It may include a material with a high dielectric constant to increase the physical size of the gate layer 3 while ensuring gate control capability. For example, the material may be hafnium oxide, silicon oxide, silicon oxide or a mixture thereof. Of course, other materials may also be used, without special limitation, as long as they can be used to improve the gate control capability of the gate layer 3.

[0142] The second dielectric layer 33 may be a thin film formed on the side of the first dielectric layer 32 away from the interface layer 31, and may be disposed opposite to the second active region 13. It may include a material with a high dielectric constant, which helps to further adjust the threshold voltage. For example, the material of the second dielectric layer 33 may be lanthanum oxide. The diffusion of lanthanum can further change the polarization capability of the gate dielectric, thereby changing the overall dielectric constant of the gate dielectric. Of course, other materials may also be used, without special limitation here.

[0143] The gate layer 4 can be a thin film formed on the surface jointly formed by the second dielectric layer 33 and the first dielectric layer 32. It can be used to adjust the work function of the gate layer 3, thereby facilitating the adjustment of the threshold voltage of the device. For example, the gate layer 4 can include a material with a high work function, such as titanium nitride, but other materials can also be used, which will not be listed here.

[0144] The semiconductor structure disclosed herein can be a switching component, for example, a PMOS component or a CMOS component, without any particular limitation herein.

[0145] This disclosure also provides a semiconductor device, including the semiconductor structure of any of the above embodiments. The semiconductor device can be a memory chip, such as DRAM (Dynamic Random Access Memory), and of course, other semiconductor devices, which will not be listed here. The beneficial effects of this semiconductor device can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here.

[0146] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including spaced isolation structures and a first active region located between two adjacent isolation structures, the first active region having a preset epitaxial region; A predetermined semiconductor layer is formed in the predetermined epitaxial region, wherein the electron affinity of the predetermined semiconductor layer is greater than that of the semiconductor substrate; A gate dielectric layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate; A gate layer is formed on the surface of the gate dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The preparation method further includes: An inwardly recessed groove is formed within the preset epitaxial region, and the preset semiconductor layer is formed within the groove.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Forming an inwardly recessed groove within the predetermined extensional region includes: A photoresist layer is formed on the surface of the preset epitaxial region; The photoresist layer is exposed and developed to form a developing area, which exposes the surface of the preset epitaxial region; The preset epitaxial region is etched in the developing area to a preset depth to form a groove; Remove the photoresist layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming a predetermined semiconductor layer in the predetermined epitaxial region includes: A germanium-silicon layer is formed in the preset epitaxial region using an epitaxial process.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The germanium content in the germanium-silicon layer is 10% to 60%.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, Forming the preset semiconductor layer in the preset epitaxial region further includes: A silicon layer is formed on the side of the germanium-silicon layer away from the semiconductor substrate using an epitaxial process.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The semiconductor substrate further includes a second active region, which is formed on the side of the isolation structure away from the first active region.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Forming a gate dielectric layer on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate includes: An interface layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate. The interface layer covers the top surface of the first active region and the second active region and is in contact with the surface of the preset semiconductor layer away from the semiconductor substrate. A first dielectric layer is formed on the interface layer; A second dielectric layer is formed on the side of the first dielectric layer away from the interface layer, and the second dielectric layer is disposed opposite to the second active region.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, A second dielectric layer is formed on the side of the first dielectric layer away from the interface layer, and the second dielectric layer is disposed opposite to the second active region, comprising: A reference dielectric layer is formed on the side of the first dielectric layer away from the interface layer using chemical vapor deposition. A photoresist layer is formed on the surface of the reference dielectric layer away from the first dielectric layer; The photoresist layer is exposed and developed to form a developing area, the developing area exposing the reference dielectric layer disposed opposite to the second active area; The reference dielectric layer is etched in the developing area to form a pattern; Remove the photoresist layer.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, The interface layer is made of silicon oxide, the first dielectric layer is made of hafnium oxide, and the second dielectric layer is made of lanthanum oxide.

11. The method for preparing a semiconductor structure according to claim 7, characterized in that, The semiconductor substrate is made of silicon, and the preparation method further includes: P-type doping is performed on the first active region and / or n-type doping is performed on the second active region.

12. A semiconductor structure, characterized in that, include: A semiconductor substrate includes spaced-apart isolation structures and a first active region located between two adjacent isolation structures, the first active region having a predetermined epitaxial region; A preset semiconductor layer is formed in the preset epitaxial region, and the electron affinity of the preset semiconductor layer is greater than that of the semiconductor substrate; A gate dielectric layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate; A gate layer is formed on the surface of the gate dielectric layer.

13. The semiconductor structure according to claim 12, characterized in that, The preset epitaxial region has an inwardly recessed groove, and the preset semiconductor layer is formed in the groove.

14. The semiconductor structure according to claim 12, characterized in that, The preset semiconductor layer includes: A germanium-silicon layer is located in the preset epitaxial region, and the thickness of the germanium-silicon layer is 2nm to 15nm.

15. The semiconductor structure according to claim 14, characterized in that, The germanium content in the germanium-silicon layer is 10% to 60%.

16. The semiconductor structure according to claim 14, characterized in that, The preset semiconductor layer further includes: A silicon layer is located on the side of the germanium-silicon layer away from the semiconductor substrate, and the thickness of the silicon layer is 0.1 nm to 2 nm.

17. The semiconductor structure according to claim 12, characterized in that, The semiconductor substrate further includes a second active region, which is formed on the side of the isolation structure away from the first active region.

18. The semiconductor structure according to claim 17, characterized in that, The gate dielectric layer includes: An interface layer is formed on the surface jointly formed by the preset semiconductor layer and the semiconductor substrate, and covers the top surface of the first active region and the second active region, and is in contact with the surface of the preset semiconductor layer away from the semiconductor substrate; A first dielectric layer is formed on the interface layer; The second dielectric layer is formed on the side of the first dielectric layer away from the interface layer and is disposed directly opposite the second active region.

19. The semiconductor structure according to claim 18, characterized in that, The interface layer is made of silicon oxide, the first dielectric layer is made of hafnium oxide, and the second dielectric layer is made of lanthanum oxide.

20. A semiconductor device, characterized in that, Includes the semiconductor structure described in any one of claims 12-19.

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