Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a semiconductor substrate, a metal pad, a bump, a metal barrier layer and a solder layer. The metal pad is arranged on the semiconductor substrate. The bump is arranged on the metal pad. The metal barrier layer is arranged on a side of the bump away from the metal pad. The metal barrier layer has a receiving cavity. An opening is arranged on a side wall of the metal barrier layer and is in communication with the receiving cavity. The solder layer is arranged in the receiving cavity, and an end of the solder layer away from the bump protrudes out of the receiving cavity. Due to the opening, the solder overflowing out of the soldering process under heat can flow out along the opening, i.e. the opening plays a role of flow guiding. Thus, the flow guiding effect of the solder can be realized by controlling the direction of the opening, so as to improve the problem of solder bridging between the bumps.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As integrated circuits become increasingly powerful, performant, and highly integrated, and with the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, accounting for a larger proportion of the overall value of electronic systems. Bump interconnect technology, with its excellent electrical performance and resistance to electromigration, is becoming a key technology for narrow-pitch interconnects in next-generation chips.

[0003] In the existing technology, during the flip-chip bonding process, the packaging substrate may deform due to heat, resulting in a height difference between the chip and the substrate. This can cause compression of certain semiconductor structures, leading to solder overflow and solder bridging between bumps. Summary of the Invention

[0004] A primary objective of this disclosure is to overcome at least one of the deficiencies of the prior art described above and to provide a semiconductor structure and a method for manufacturing the same.

[0005] According to a first aspect of the present invention, a semiconductor structure is provided, comprising:

[0006] Semiconductor substrate;

[0007] Metal pads are disposed on a semiconductor substrate;

[0008] Bumps are placed on metal pads;

[0009] A metal barrier layer is disposed on the side of the bump away from the metal pad. The metal barrier layer has a receiving cavity and an opening is provided on the side wall of the metal barrier layer, which is connected to the receiving cavity.

[0010] The solder layer is disposed within the receiving cavity, with the end of the solder layer away from the bump protruding out of the receiving cavity.

[0011] In one embodiment of the invention, the receiving cavity is a through hole to allow the solder layer to contact the bump.

[0012] In one embodiment of the present invention, the opening extends along the length of the metal barrier layer and intersects both ends of the metal barrier layer.

[0013] In one embodiment of the present invention, there are multiple openings, which are spaced apart.

[0014] In one embodiment of the present invention, the metal barrier layer includes:

[0015] Side wall segments are arranged in pairs, with two side wall segments spaced apart on the protrusion, and two openings formed between the two opposing side wall segments;

[0016] The connecting section connects to two sidewall sections at each end.

[0017] In one embodiment of the invention, the connecting segment is connected to the middle of the two sidewall segments.

[0018] In one embodiment of the present invention, the solder layer includes:

[0019] The first solder layer is disposed on the bump and located below the connection section;

[0020] The second solder layer is disposed on the first solder layer, and the end of the second solder layer away from the first solder layer protrudes from the receiving cavity;

[0021] The second solder layer is in contact with the first solder layer, and the connection section is located between the first solder layer and the second solder layer.

[0022] In one embodiment of the present invention, a solder layer is provided inside the opening.

[0023] In one embodiment of the present invention, the bump is a copper pillar, and the semiconductor structure further includes:

[0024] The under-bump metal layer is at least partially sandwiched between the metal pad and the bump.

[0025] In one embodiment of the present invention, the semiconductor structure further includes:

[0026] A first protective layer is disposed on a semiconductor substrate. The first protective layer has a first opening that exposes a portion of a metal pad.

[0027] In one embodiment of the present invention, the semiconductor structure further includes:

[0028] A second protective layer is disposed on the first protective layer. The second protective layer has a second opening, the diameter of which is less than or equal to the diameter of the first opening.

[0029] The metal layer under the bump at least covers the bottom surface and sidewall surface of the second opening, and at least a portion of the metal layer under the bump is disposed within the second opening.

[0030] According to a second aspect of the present invention, a method for manufacturing a semiconductor structure is provided, comprising:

[0031] Provide a semiconductor substrate and form metal pads on the semiconductor substrate;

[0032] Form bumps on metal pads;

[0033] A solder layer and a metal barrier layer are formed on the side of the bump away from the metal pad;

[0034] The metal barrier layer has a receiving cavity, and an opening is provided on the side wall of the metal barrier layer. The opening is connected to the receiving cavity. The solder layer is disposed in the receiving cavity, and the end of the solder layer away from the bump protrudes out of the receiving cavity.

[0035] In one embodiment of the present invention, the manufacturing method further includes, prior to forming the bump:

[0036] Form a bump under-metal layer on the metal pads;

[0037] At least a portion of the under-bump metal layer is sandwiched between the metal pad and the bump.

[0038] In one embodiment of the present invention, the manufacturing method further includes, prior to forming the bump:

[0039] A first protective layer is formed on a semiconductor substrate;

[0040] The first protective layer has a first opening, which exposes a portion of the metal pads.

[0041] In one embodiment of the present invention, after forming the first protective layer, the manufacturing method further includes:

[0042] A second protective layer is formed on the upper surface of the first protective layer and the metal pads;

[0043] After the second protective layer is formed, a bump under metal layer is formed on the metal pads and the second protective layer;

[0044] The second protective layer has a second opening, the diameter of which is less than or equal to the diameter of the first opening. The metal layer under the bump at least covers the bottom surface and sidewall surface of the second opening, and at least a portion of the metal layer under the bump is disposed within the second opening.

[0045] In one embodiment of the present invention, the solder layer includes a first solder layer and a second solder layer, and the method for forming the first solder layer and the second solder layer includes:

[0046] A first solder layer is formed on the side of the bump away from the metal pad;

[0047] A metallic barrier layer is formed on the first solder layer and the bump;

[0048] A second solder layer is formed within the cavity.

[0049] In one embodiment of the present invention, the manufacturing method further includes, prior to forming the bump:

[0050] A first photoresist layer is formed on the semiconductor substrate at a location other than the positions corresponding to the bumps and the first solder layer;

[0051] After forming the bumps and the first solder layer, the first photoresist layer is removed.

[0052] In one embodiment of the present invention, the manufacturing method further includes, prior to forming the metal barrier layer:

[0053] A first mask layer is formed on a semiconductor substrate on which a first solder layer is formed;

[0054] The first mask layer is photolithographically etched to expose a portion of the first solder layer.

[0055] The first solder layer is etched using a chemical acid etching process to expose the bump portion, and then the first mask layer is removed;

[0056] Form a second mask layer;

[0057] A second mask layer is formed using photolithography to expose the first solder layer and a portion of the bumps, and a metal barrier layer is formed on the first solder layer, the bumps, and the second mask layer, wherein the metal barrier layer covers a portion of the first solder layer.

[0058] In one embodiment of the present invention, after forming the metal barrier layer, the manufacturing method further includes:

[0059] A second photoresist layer is formed on the metal barrier layer at the position corresponding to the bump;

[0060] Etch the metal barrier layer at the location not covered by the second photoresist layer;

[0061] Remove the second photoresist layer;

[0062] A second solder layer is formed by filling the cavity with solder, wherein the first solder layer is in contact with the second solder layer and a portion of the metal barrier layer is located within the second solder layer;

[0063] Remove the second mask layer.

[0064] In one embodiment of the present invention, after forming the metal barrier layer, the manufacturing method further includes:

[0065] A third photoresist layer is formed on the portion of the metal barrier layer other than the position corresponding to the bump;

[0066] A second solder layer is formed by filling the cavity with solder, wherein the first solder layer is in contact with the second solder layer and a portion of the metal barrier layer is located within the second solder layer;

[0067] Remove the third photoresist layer;

[0068] Etch the metal barrier layer in areas not covered by solder.

[0069] Remove the second mask layer.

[0070] The semiconductor structure of the present invention comprises a semiconductor substrate, metal pads, bumps, a solder layer, and a metal barrier layer. The solder layer is disposed within the receiving cavity, and an opening is provided on the sidewall of the metal barrier layer. Due to the presence of the opening, during the flip chip soldering process, the solder that overflows due to heat will flow out with the opening, that is, the opening plays a guiding role. Thus, by controlling the direction of the opening, the guiding effect of the solder can be achieved, thereby improving the problem of solder bridging between bumps. Attached Figure Description

[0071] The various objectives, features, and advantages of this disclosure will become more apparent from the following detailed description of preferred embodiments of the disclosure taken in conjunction with the accompanying drawings. The drawings are merely illustrative illustrations of the present disclosure and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0072] Figure 1 This is a top view of a first form of a semiconductor structure according to an exemplary embodiment;

[0073] Figure 2 yes Figure 1 A cross-sectional schematic diagram of an exemplary embodiment of a semiconductor structure;

[0074] Figure 3 yes Figure 1 A cross-sectional schematic diagram of another exemplary embodiment of a semiconductor structure;

[0075] Figure 4 This is a top view of a second form of a semiconductor structure according to an exemplary embodiment;

[0076] Figure 5 yes Figure 4 A cross-sectional schematic diagram of an exemplary embodiment of a semiconductor structure;

[0077] Figure 6 yes Figure 4 A cross-sectional schematic diagram of another exemplary embodiment of a semiconductor structure;

[0078] Figure 7 This is a schematic diagram of the arrangement of adjacent semiconductor structures according to an exemplary embodiment;

[0079] Figure 8 This is a schematic diagram of the arrangement of adjacent semiconductor structures according to another exemplary embodiment;

[0080] Figure 9 This is a schematic diagram of a structure formed after a bump under-metal layer is formed using a semiconductor structure fabrication method according to an exemplary embodiment;

[0081] Figure 10 This is a schematic diagram of the structure after forming a first solder layer using a semiconductor structure fabrication method according to an exemplary embodiment;

[0082] Figure 11 This is a schematic diagram of the structure after removing the first photoresist layer according to an exemplary embodiment of a semiconductor structure fabrication method;

[0083] Figure 12 This is a schematic diagram of the structure after forming a first mask layer using a semiconductor structure fabrication method according to an exemplary embodiment;

[0084] Figure 13 This is a schematic diagram of the structure after photolithography of the first mask layer according to an exemplary embodiment of a semiconductor structure fabrication method;

[0085] Figure 14 This is a schematic diagram of the structure after acid etching of the first mask layer according to an exemplary embodiment of a semiconductor structure fabrication method;

[0086] Figure 15 This is a schematic diagram of the structure after removing the first mask layer according to an exemplary embodiment of a semiconductor structure fabrication method;

[0087] Figure 16 This is a schematic diagram of a structure formed by a semiconductor structure fabrication method according to an exemplary embodiment after forming a metal barrier layer;

[0088] Figure 17 This is a schematic diagram of the structure after forming a second photoresist layer using a semiconductor structure fabrication method according to an exemplary embodiment;

[0089] Figure 18 This is a schematic diagram of the structure after etching a metal barrier layer using a semiconductor structure fabrication method according to an exemplary embodiment;

[0090] Figure 19 This is a schematic diagram of the structure after removing the second photoresist layer according to an exemplary embodiment of a semiconductor structure fabrication method;

[0091] Figure 20 This is a schematic diagram of the structure after forming a second solder layer using a semiconductor structure fabrication method according to an exemplary embodiment;

[0092] Figure 21 This is a schematic diagram of the structure after etching the second mask layer according to an exemplary embodiment of a semiconductor structure fabrication method.

[0093] The annotations in the attached figures are explained as follows:

[0094] 1. Solder layer; 10. Metal pad; 11. First photoresist layer; 12. First mask layer; 13. Second mask layer; 14. Second photoresist layer; 20. Semiconductor substrate; 30. Bump; 40. First solder layer; 41. Removal space; 50. Metal barrier layer; 51. Receiving cavity; 52. Opening; 53. Sidewall section; 54. Connecting section; 60. Second solder layer; 70. Under-bump metal layer; 80. First protective layer; 90. Second protective layer. Detailed Implementation

[0095] Typical embodiments embodying the features and advantages of this disclosure will be described in detail in the following description. It should be understood that this disclosure can have various variations in different embodiments without departing from the scope of this disclosure, and the descriptions and drawings therein are illustrative in nature and not intended to limit this disclosure.

[0096] In the following description of various exemplary embodiments of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure, and which illustrate by way of example different exemplary structures, systems, and steps that may implement various aspects of this disclosure. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of this disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of this disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this disclosure.

[0097] One embodiment of the present invention provides a semiconductor structure, please refer to... Figures 1 to 6 The semiconductor structure includes: a semiconductor substrate 20; a metal pad 10 disposed on the semiconductor substrate 20; a bump 30 disposed on the metal pad 10; a metal barrier layer 50 disposed on the side of the bump 30 away from the metal pad 10, the metal barrier layer 50 having a receiving cavity 51, and an opening 52 disposed on the sidewall of the metal barrier layer 50, the opening 52 communicating with the receiving cavity 51; and a solder layer 1 disposed in the receiving cavity 51, with the end of the solder layer 1 away from the bump 30 protruding from the receiving cavity 51.

[0098] In one embodiment of the present invention, the semiconductor structure comprises a semiconductor substrate 20, a metal pad 10, a bump 30, a solder layer 1, and a metal barrier layer 50. The solder layer 1 is disposed in a receiving cavity 51, and an opening 52 is provided on the sidewall of the metal barrier layer 50. Due to the presence of the opening 52, during the flip chip soldering process, the solder that overflows due to heat will flow out with the opening 52, that is, the opening 52 plays a guiding role. Thus, by controlling the direction of the opening 52, the guiding effect of the solder can be achieved, thereby improving the problem of solder bridging between bumps.

[0099] In one embodiment, since the solder layer 1 is disposed in the receiving cavity 51, the outflow of solder is restricted to a certain extent, and the flow direction is controlled by the opening 52, which reduces the problem of solder bridging between bumps caused by the deformation of the packaging substrate after reflow, so as to achieve the goal of improving yield.

[0100] In one embodiment, the receiving cavity 51 is a through hole to allow the solder layer 1 to contact the bump 30. Both ends of the receiving cavity 51 are open ends, and an opening 52 is also provided on its side wall.

[0101] In one embodiment, the opening 52 extends along the length of the metal barrier layer 50 and intersects both ends of the metal barrier layer 50. The opening 52 separates the metal barrier layer 50. For example, when the metal barrier layer 50 is a cylinder, the opening 52 is a notch cut into the cylinder, which passes through both ends of the metal barrier layer 50.

[0102] In one embodiment, there are multiple openings 52, which are spaced apart.

[0103] In one embodiment, opening 52 is one.

[0104] In one embodiment, such as Figure 1 As shown, the metal barrier layer 50 includes: sidewall segments 53, which are arranged in pairs, with the two sidewall segments 53 spaced apart on the protrusion 30, and two openings 52 formed between the two opposing sidewall segments 53; and connecting segments 54, with the two ends of the connecting segments 54 respectively connected to the two sidewall segments 53.

[0105] In one embodiment, the connecting segment 54 connects the middle of the two sidewall segments 53. The connecting segment 54 is provided to enhance the connection stability of the sidewall segments 53.

[0106] like Figure 1 As shown, the metal barrier layer 50 consists of two pairs of sidewall segments 53 and a connecting segment 54. Taking the length direction of the connecting segment 54 as a cross-section (i.e., the direction connecting the two sidewall segments 53), we can obtain... Figure 2 and Figure 3 Two different implementations. Figure 1The diagram mainly illustrates the relationship between the metal barrier layer 50 and the solder layer 1, whereby the solder layer 1 is disposed within the metal barrier layer 50 and fills the receiving cavity 51 and opening 52 of the metal barrier layer 50. For example... Figure 4 As shown, the metal barrier layer 50 consists of two pairs of sidewall segments 53 and a connecting segment 54. The cross-section can be obtained by taking the width direction of the connecting segment 54 as the section line (i.e., the direction of the two opposing openings 52). Figure 5 and Figure 6 Two different implementations, by Figure 5 and Figure 6 It can be seen that the connecting section 54 serves to connect the two side wall sections 53, and the connecting section 54 is located inside the solder layer 1.

[0107] In one embodiment, the solder layer 1 includes: a first solder layer 40 disposed on the bump 30 and located below the connecting section 54; and a second solder layer 60 disposed on the first solder layer 40, with one end of the second solder layer 60 protruding from the receiving cavity 51 away from the first solder layer 40; wherein the second solder layer 60 is in contact with the first solder layer 40, and the connecting section 54 is disposed between the first solder layer 40 and the second solder layer 60.

[0108] In one embodiment, the connector 54 is sealed within the first solder layer 40, or the connector 54 is sealed within the second solder layer 60, or a portion of the connector 54 is located within the first solder layer 40 and another portion is located within the second solder layer 60.

[0109] In one embodiment, a solder layer 1 is provided within the opening 52.

[0110] In one embodiment, the metal barrier layer 50 only includes the sidewall section 53, that is, there is no connecting structure in the middle. It can be understood that the metal barrier layer 50 is a columnar structure with openings at the top and bottom ends and openings 52 on the sidewall.

[0111] In one embodiment, a solder layer 1 is provided inside each of the receiving cavities 51.

[0112] In one embodiment, the first solder layer 40 and the second solder layer 60 may be one of lead, tin, and silver, or an alloy containing any of the aforementioned solder metals. For example, the material of the first solder layer 40 and / or the second solder layer 60 may be an alloy with a tin content of 91.5% to 98.5% and a silver content of 8.5% to 1.5%. Optionally, the material of the first solder layer 40 and / or the second solder layer 60 may be an alloy with a tin content of 93.2% to 96.5% and a silver content of 6.8% to 3.5%, or the material of the first solder layer 40 and / or the second solder layer 60 may be an alloy with a tin content of 98.2% to 98.5% and a silver content of 1.8% to 1.5%.

[0113] In one embodiment, the semiconductor substrate 20 includes a semiconductor substrate, a plurality of IC circuits, and an insulating layer. The material of the metal pads 10 may be aluminum or copper, but is not limited thereto.

[0114] In one embodiment, the metal barrier layer 50 has an H-shaped cross-section. The metal barrier layer 50 consists of two arc-shaped segments and a rectangular segment, with the rectangular segment connecting the two arc-shaped segments, and the second solder layer 60 and the first solder layer 40 within the rectangular segment in contact with each other.

[0115] In one embodiment, the material of the metal barrier layer 50 may include nickel.

[0116] In one embodiment, the bump 30 is a copper pillar, and the semiconductor structure further includes an under-bump metal layer 70, at least a portion of which is sandwiched between the metal pad 10 and the bump 30. The metal material layer of the under-bump metal layer 70 may include a Ti layer, a TiW layer, and a Cu layer. The under-bump metal layer 70 is electrically connected to the metal pad 10. The under-bump metal layer 70 prevents the bump 30 from directly contacting the metal pad 10.

[0117] In one embodiment, the semiconductor structure further includes: a first protective layer 80 disposed on the semiconductor substrate 20, the first protective layer 80 having a first opening that exposes a portion of the metal pad 10, i.e., the first protective layer 80 covers the circumferential outer edge of the metal pad 10. The material of the first protective layer 80 may be one or a combination of silicon dioxide and silicon nitride.

[0118] In one embodiment, the first protective layer 80 covers a portion of the metal pad 10 and the area of ​​the semiconductor substrate 20 outside the metal pad 10.

[0119] In one embodiment, the semiconductor structure further includes: a second protective layer 90 disposed on the first protective layer 80, the second protective layer 90 having a second opening, the diameter of the second opening being smaller than or equal to the diameter of the first opening; wherein, a bump under-metal layer 70 at least covers the bottom surface and sidewall surface of the second opening, and at least a portion of the bump under-metal layer 70 is disposed within the second opening. The material of the second protective layer 90 may be polyimide.

[0120] In one embodiment, the under-bump metal layer 70 is disposed on a portion of the second protective layer 90 and the exposed metal pads 10. In one embodiment, the under-bump metal layer 70 may enclose the bumps 30, that is, the bumps 30 are all located within the opening formed by the under-bump metal layer 70, and the plane of the groove of the under-bump metal layer 70 is on the same plane as the bottom surface of the first solder layer 40.

[0121] In one embodiment, such as Figure 2 and Figure 5As shown, the semiconductor structure comprises a semiconductor substrate 20, metal pads 10, bumps 30, a first solder layer 40, a metal barrier layer 50, a second solder layer 60, a lower bump metal layer 70, a first protective layer 80, and a second protective layer 90. The first protective layer 80 covers the metal pads 10 and partially blocks them. The second protective layer 90 is disposed on the first protective layer 80 and partially covers the metal pads 10. The positions of the second protective layer 90 and the first protective layer 80 covering the metal pads 10 are adjacent, meaning the first protective layer 80 is located below the second protective layer 90. The second protective layer 90 does not cover the center of the metal pads 10. The lower bump metal layer 70 deposits metal material layers such as Ti, TiW, and Cu layers on the second protective layer 90 and the metal pads 10 through physical vapor deposition. The Ti layer enables adhesion and prevents copper from entering the semiconductor substrate 20, while the Cu layer forms the electroplated electrodes. The bump 30 has a T-shaped cross section, meaning that the small end is located inside the lower metal layer 70 of the bump, while the large end is located outside the lower metal layer 70 of the bump.

[0122] In another embodiment, such as Figure 3 and Figure 6 As shown, the semiconductor structure comprises a semiconductor substrate 20, metal pads 10, bumps 30, a first solder layer 40, a metal barrier layer 50, a second solder layer 60, a lower bump metal layer 70, and a first protective layer 80. The first protective layer 80 covers the metal pads 10 and partially blocks them. The lower bump metal layer 70 deposits metal material layers such as Ti, TiW, and Cu layers on the metal pads 10 using physical vapor deposition. The Ti layer allows for adhesion and prevents copper from entering the semiconductor substrate 20, while the Cu layer forms the electroplated electrodes. The bumps 30 have a rectangular cross-section and are located between the lower bump metal layer 70 and the first solder layer 40.

[0123] In one embodiment, such as Figure 7 Semiconductor structures can be designed with a 45-degree tin flow direction. For example... Figure 8 As shown, the solder flow direction of long-distance adjacent bumps can be designed between semiconductor structures. By controlling the solder flow direction, the solder flow can be designed to overflow to the farthest adjacent bump. The distance between bumps can also be reduced by adjusting the direction of opening 52, allowing more semiconductor structures to be accommodated within the same chip area. The solder flow direction can be adjusted according to the specific design and is not limited to... Figure 7 as well as Figure 8 The design scheme in the middle.

[0124] An embodiment of the present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a semiconductor substrate 20 and forming a metal pad 10 on the semiconductor substrate 20; forming a bump 30 on the metal pad 10; forming a solder layer 1 and a metal barrier layer 50 on the side of the bump 30 away from the metal pad 10; wherein the metal barrier layer 50 has a receiving cavity 51, an opening 52 is provided on the sidewall of the metal barrier layer 50, the opening 52 is connected to the receiving cavity 51, the solder layer 1 is disposed in the receiving cavity 51, and the end of the solder layer 1 away from the bump 30 protrudes from the receiving cavity 51.

[0125] In one embodiment, prior to forming the bump 30, the manufacturing method further includes forming a bump under metal layer 70 on the metal pad 10; wherein at least a portion of the bump under metal layer 70 is sandwiched between the metal pad 10 and the bump 30.

[0126] In one embodiment, prior to forming the bump 30, the manufacturing method further includes forming a first protective layer 80 on a semiconductor substrate 20; wherein the first protective layer 80 has a first opening that exposes a portion of the metal pad 10.

[0127] In one embodiment, after forming the first protective layer 80, the manufacturing method further includes: forming a second protective layer 90 on the upper surface of the first protective layer 80 and the metal pad 10; after forming the second protective layer 90, forming a bump under metal layer 70 on the metal pad 10 and the second protective layer 90; wherein the second protective layer 90 has a second opening, the diameter of the second opening is smaller than or equal to the diameter of the first opening, the bump under metal layer 70 at least covers the bottom surface and sidewall surface of the second opening, and at least a portion of the bump under metal layer 70 is disposed within the second opening.

[0128] In one embodiment, solder layer 1 includes a first solder layer 40 and a second solder layer 60. The method of forming the first solder layer 40 and the second solder layer 60 includes: forming the first solder layer 40 on the side of the bump 30 away from the metal pad 10; forming a metal barrier layer 50 on the first solder layer 40 and the bump 30; and forming the second solder layer 60 in the receiving cavity 51.

[0129] In one embodiment, before forming the bump 30, the manufacturing method further includes: forming a first photoresist layer 11 on the semiconductor substrate 20 at a portion other than the location corresponding to the bump 30 and the first solder layer 40; and removing the first photoresist layer 11 after forming the bump 30 and the first solder layer 40.

[0130] In one embodiment, before forming the metal barrier layer 50, the manufacturing method further includes: forming a first mask layer 12 on a semiconductor substrate 20 on which the first solder layer 40 is formed; photolithographically etching the first mask layer 12 to expose a portion of the first solder layer 40; etching the first solder layer 40 using a chemical etching process to expose a portion of the bump 30, and then removing the first mask layer 12; forming a second mask layer 13; photolithographically etching the second mask layer 13 to expose the first solder layer 40 and a portion of the bump 30, and forming a metal barrier layer 50 on the first solder layer 40, the bump 30, and the second mask layer 13, wherein the metal barrier layer 50 covers a portion of the first solder layer 40.

[0131] In one embodiment, after forming the metal barrier layer 50, the manufacturing method further includes: forming a second photoresist layer 14 on the metal barrier layer 50 at a position corresponding to the bump 30; etching the metal barrier layer 50 at a position not covered by the second photoresist layer 14; removing the second photoresist layer 14; filling the receiving cavity 51 with solder to form a second solder layer 60, wherein the first solder layer 40 is in contact with the second solder layer 60 and a portion of the metal barrier layer 50 is located within the second solder layer 60; and removing the second mask layer 13.

[0132] In one embodiment, after forming the metal barrier layer 50, the manufacturing method further includes: forming a third photoresist layer on the metal barrier layer 50 at a portion other than the position corresponding to the bump 30; filling the receiving cavity 51 with solder to form a second solder layer 60, wherein the first solder layer 40 is in contact with the second solder layer 60 and a portion of the metal barrier layer 50 is located within the second solder layer 60; removing the third photoresist layer; etching the metal barrier layer 50 at the position not covered by solder; and removing the second mask layer 13.

[0133] In one embodiment, the specific steps of a method for manufacturing a semiconductor structure include:

[0134] like Figure 9As shown, a first protective layer 80 is formed on the metal pad 10. A second protective layer 90 is formed on the upper surface of the first protective layer 80 and the metal pad 10 using a deposition process. An opening is formed in the second protective layer 90 at the location of a pre-fabricated bump 30 using a photolithography process. A metal material is deposited on the metal pad 10 and the second protective layer 90 to form a bump under-metal layer 70, wherein the bump under-metal layer 70 covers the entire second protective layer 90 and the openings of the second protective layer 90. The material of the first protective layer 80 can be one or a combination of silicon dioxide and silicon nitride, and the material of the second protective layer 90 can be polyimide. The metal material layer of the under-bump metal layer 70 may include a Ti layer, a TiW layer and a Cu layer. The under-bump metal layer 70 is formed on the metal pad 10 and the second protective layer 90 by physical vapor deposition (PVD). The Ti layer of the under-bump metal layer 70 can be used to adhere to and prevent copper metal from entering the semiconductor substrate 20 and the metal pad 10. The Cu layer of the under-bump metal layer 70 can be used as an electrode to form the electroplated copper pillar (bump 30).

[0135] like Figure 10 As shown, a first photoresist layer 11 is formed on the second protective layer 90 at a portion other than the positions corresponding to the bumps 30 and the first solder layer 40. Specifically, a space is reserved in the middle of the first photoresist layer 11 for forming the bumps 30 and the first solder layer 40. Then, the bumps 30 and the first solder layer 40 are electroplated. The first photoresist layer 11 can be a photoresist layer. After coating the photoresist layer, it is exposed and developed to form the space for setting the bumps 30 and the first solder layer 40. The material of the first solder layer 40 can be one of lead, tin, and silver, or an alloy containing any of these solder metals. The material of the first solder layer 40 can be an alloy containing 91.5% to 98.5% tin and 8.5% to 1.5% silver. Optionally, the material of the first solder layer 40 can be an alloy with a tin content of 93.2% to 96.5% and a silver content of 6.8% to 3.5%, or an alloy with a tin content of 98.2% to 98.5% and a silver content of 1.8% to 1.5%, and the bump 30 is a copper pillar.

[0136] like Figure 11 As shown, after forming the electroplated bumps 30 and the first solder layer 40, the first photoresist layer 11 is removed.

[0137] like Figure 12 As shown, a first mask layer 12 is formed on a semiconductor substrate 20 on which a first solder layer 40 is formed. The first mask layer 12 covers the first solder layer 40 and the under-bump metal layer 70. The first mask layer 12 may be a polyimide layer.

[0138] like Figure 13As shown, the first mask layer 12 is photolithographically etched to expose a portion of the top surface of the first solder layer 40.

[0139] like Figure 14 As shown, the first solder layer 40 is etched using chemical acid etching to expose the bumps 30, thereby forming a removal space 41.

[0140] like Figure 15 As shown, the first mask layer 12 is removed.

[0141] like Figure 16 As shown, a second mask layer 13 is formed, covering the first solder layer 40, bumps 30, and under-bump metal layer 70. The second mask layer 13 is photolithographically etched to expose the first solder layer 40 and a portion of the bumps 30. A metal barrier layer 50 is deposited above the second mask layer 13 and the first solder layer 40 using physical vapor deposition (PVD) technology. The metal barrier layer 50 can be a nickel layer; if a thicker metal barrier layer 50 is required, an electroplating process is used to increase the nickel layer thickness. The second mask layer 13 can be a polyimide layer.

[0142] like Figure 17 As shown, a second photoresist layer 14 is formed on the metal barrier layer 50 at a position corresponding to the first solder layer 40. The second photoresist layer 14 covers the top of the first solder layer 40 and serves as a mask when photolithographically ...

[0143] like Figure 18 As shown, the metal material of the metal barrier layer 50 at the location not covered by the second photoresist layer 14 is etched.

[0144] like Figure 19 As shown, the second photoresist layer 14 is removed to expose the receiving cavity 51 on the metal barrier layer 50.

[0145] like Figure 20 As shown, solder is filled into the receiving cavity 51 to form a second solder layer 60. The height of the second solder layer 60 is higher than that of the metal barrier layer 50, and the second solder layer 60 is in contact with the first solder layer 40. The material of the second solder layer 60 can be one of lead, tin, and silver, or an alloy containing any of these solder metals. For example, the material of the second solder layer 60 can be an alloy with a tin content of 91.5% to 98.5% and a silver content of 8.5% to 1.5%. Optionally, the material of the second solder layer 60 can be an alloy with a tin content of 93.2% to 96.5% and a silver content of 6.8% to 3.5%, or an alloy with a tin content of 98.2% to 98.5% and a silver content of 1.8% to 1.5%.

[0146] like Figure 21 As shown, the second mask layer 13 is etched. Then, the under-bump metal layer 70 is etched, and finally, a high-temperature reflow process is used to form solder bumps on the surface of the metal barrier layer 50, thus forming a... Figure 1 The semiconductor structure shown.

[0147] In another embodiment, the specific steps of a method for manufacturing a semiconductor structure include:

[0148] After completion Figures 9 to 16 After the preparation process, the metal barrier layer 50 is deposited on top of the second mask layer 13 and the first solder layer 40 using physical vapor deposition (PVD) technology.

[0149] A third photoresist layer is formed on the metal material of the metal barrier layer 50, excluding the position corresponding to the first solder layer 40. This third photoresist layer may be a photoresist layer.

[0150] A second solder layer 60 is formed by filling the cavity 51 with solder. The height of the second solder layer 60 is higher than the metal barrier layer 50 but lower than the third photoresist layer. The solder layer can be made of one of lead, tin, and silver, or an alloy containing any of these solder metals. For example, the material of the second solder layer 60 can be an alloy with a tin content of 91.5% to 98.5% and a silver content of 8.5% to 1.5%. Optionally, the material of the second solder layer 60 can be an alloy with a tin content of 93.2% to 96.5% and a silver content of 6.8% to 3.5%, or an alloy with a tin content of 98.2% to 98.5% and a silver content of 1.8% to 1.5%.

[0151] Remove the third photoresist layer.

[0152] The second mask layer 13 is etched. Then the under-bump metal layer 70 is etched, and finally, a high-temperature reflow process is used to form solder bumps on the surface of the metal barrier layer 50, thus forming a... Figure 1 The semiconductor structure shown.

[0153] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and exemplary embodiments are to be considered illustrative only, and the true scope and spirit of the invention are indicated by the following claims.

[0154] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate; Metal pads are disposed on the semiconductor substrate; A bump is provided on the metal pad; A metal barrier layer is disposed on the side of the bump away from the metal pad. The metal barrier layer has a receiving cavity, and an opening is provided on the sidewall of the metal barrier layer, which is connected to the receiving cavity. A solder layer is disposed within the receiving cavity, with one end of the solder layer away from the bump protruding from the receiving cavity; The metal barrier layer includes: Sidewall segments, the sidewall segments are arranged in pairs, the two sidewall segments in a pair are spaced apart on the protrusion, and two openings are formed between the two opposing sidewall segments; A connecting segment, wherein both ends of the connecting segment are respectively connected to the two sidewall segments; The solder layer includes: A first solder layer is disposed on the bump and located below the connecting segment; A second solder layer is disposed on the first solder layer, and one end of the second solder layer away from the first solder layer protrudes from the receiving cavity; The second solder layer is in contact with the first solder layer, and the connection segment is located between the first solder layer and the second solder layer.

2. The semiconductor structure according to claim 1, characterized in that, The cavity is a through hole to allow the solder layer to contact the bump.

3. The semiconductor structure according to claim 1, characterized in that, The opening extends along the length of the metal barrier layer and intersects both ends of the metal barrier layer.

4. The semiconductor structure according to claim 1, characterized in that, There are multiple openings, and the multiple openings are spaced apart.

5. The semiconductor structure according to claim 1, characterized in that, The connecting segment is connected to the middle of the two sidewall segments.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The opening contains the solder layer.

7. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The bump is a copper pillar, and the semiconductor structure further includes: A bump under-bump metal layer, at least a portion of which is sandwiched between the metal pad and the bump.

8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure also includes: A first protective layer is disposed on the semiconductor substrate, the first protective layer having a first opening that exposes a portion of the metal pad.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: A second protective layer is disposed on the first protective layer, and the second protective layer has a second opening, the diameter of which is less than or equal to the diameter of the first opening. The metal layer under the bump at least covers the bottom surface and sidewall surface of the second opening, and at least a portion of the metal layer under the bump is disposed within the second opening.

10. A method for manufacturing a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, and metal pads are formed on the semiconductor substrate; A bump is formed on the metal pad; A solder layer and a metal barrier layer are formed on the side of the bump away from the metal pad; The metal barrier layer has a receiving cavity, and an opening is provided on the side wall of the metal barrier layer. The opening is connected to the receiving cavity. The solder layer is disposed in the receiving cavity, and the end of the solder layer away from the bump protrudes out of the receiving cavity. The solder layer includes a first solder layer and a second solder layer, and the method for forming the first solder layer and the second solder layer includes: A first solder layer is formed on the side of the bump away from the metal pad; The metal barrier layer is formed on the first solder layer and the bump; The second solder layer is formed within the receiving cavity; The metal barrier layer includes: Sidewall segments, the sidewall segments are arranged in pairs, the two sidewall segments in a pair are spaced apart on the protrusion, and two openings are formed between the two opposing sidewall segments; A connecting segment, the two ends of which are respectively connected to the two sidewall segments.

11. The manufacturing method according to claim 10, characterized in that, Before forming the bump, the manufacturing method further includes: A bump undermetal layer is formed on the metal pad; Wherein, at least a portion of the metal layer under the bump is sandwiched between the metal pad and the bump.

12. The manufacturing method according to claim 11, characterized in that, Before forming the bump, the manufacturing method further includes: A first protective layer is formed on the semiconductor substrate; The first protective layer has a first opening, which exposes a portion of the metal pad.

13. The manufacturing method according to claim 12, characterized in that, After forming the first protective layer, the manufacturing method further includes: A second protective layer is formed on the upper surface of the first protective layer and the metal pad; After the second protective layer is formed, the bump under metal layer is formed on the metal pads and the second protective layer. The second protective layer has a second opening, the diameter of which is less than or equal to the diameter of the first opening. The metal layer under the bump at least covers the bottom surface and sidewall surface of the second opening, and at least a portion of the metal layer under the bump is disposed within the second opening.

14. The manufacturing method according to claim 10, characterized in that, Before forming the bump, the manufacturing method further includes: A first photoresist layer is formed on the semiconductor substrate at a location other than the positions corresponding to the bumps and the first solder layer. After forming the bump and the first solder layer, the first photoresist layer is removed.

15. The manufacturing method according to claim 10, characterized in that, Prior to forming the metal barrier layer, the manufacturing method further includes: A first mask layer is formed on a semiconductor substrate on which the first solder layer is formed; The first mask layer is photolithographically etched to expose a portion of the first solder layer; The first solder layer is etched using a chemical acid etching process to expose a portion of the bump, and then the first mask layer is removed. Form a second mask layer; The second mask layer is photolithographically etched to expose the first solder layer and a portion of the bumps, and the metal barrier layer is formed on the first solder layer, the bumps, and the second mask layer, wherein the metal barrier layer covers a portion of the first solder layer.

16. The manufacturing method according to claim 15, characterized in that, After forming the metal barrier layer, the manufacturing method further includes: A second photoresist layer is formed on the metal barrier layer at the position corresponding to the bump; Etch the metal barrier layer at locations not covered by the second photoresist layer; Remove the second photoresist layer; The cavity is filled with solder to form the second solder layer, wherein the first solder layer is in contact with the second solder layer and a portion of the metal barrier layer is located within the second solder layer; Remove the second mask layer.

17. The manufacturing method according to claim 15, characterized in that, After forming the metal barrier layer, the manufacturing method further includes: A third photoresist layer is formed on the portion of the metal barrier layer other than the position corresponding to the bump; A second solder layer is formed by filling the cavity with solder, wherein the first solder layer is in contact with the second solder layer and a portion of the metal barrier layer is located within the second solder layer; Remove the third photoresist layer; Etch the metal barrier layer in the areas not covered by solder; Remove the second mask layer.

Images