A digital-to-analog conversion decoding technique

Abstract

A digital-to-analog conversion technology, using power supply stage number, sampling frequency, switch duty cycle to restore the decoding method of analog signal. After traditional digital-to-analog conversion, generally needs the amplification of power amplifier to promote the work of power load, such as audio DAC needs audio power amplifier to drive the loudspeaker to sound. This digital-to-analog conversion technology is similar to pulse power amplifier, but its performance is better than that of pulse power amplifier. Because in the process of analog-to-digital conversion, the integer amplitude and decimal amplitude of the analog signal in the coded information, and the integer amplitude is coarse quantization and the decimal amplitude is fine quantization, here only restores the analog signal. The quality of the restored analog signal on the analog power load is equivalent to the traditional ADC+DAC without power amplifier mode, and the efficiency is higher.

Description

Technical Field

[0001] This invention belongs to the field of digital-to-analog conversion technology, specifically realizing the function of converting digital signals into analog signals. Background Technology

[0002] After a traditional digital-to-analog converter (DAC), a power amplifier is typically needed to amplify the analog signal output from the DAC before it can drive a power load. Driving high-power analog loads, however, employs a pulse amplifier, which sacrifices some signal quality in exchange for increased power amplifier efficiency. Summary of the Invention

[0003] This invention proposes a novel digital-to-analog conversion technology that, after decoding, can directly drive analog power loads without sacrificing the signal quality of the digital-to-analog conversion.

[0004] The data structure of a 16-bit data is as follows Figure 1 As shown, the meaning of each data bit is as follows: DATA[15:14], sampling frequency, symbol Fdac, represents the sampling frequency value during analog-to-digital conversion; DATA[13:11], integer amplitude, symbol Ndac, the integer part of the analog voltage swing value, its value is an integer; DATA[10:4], decimal amplitude, symbol Ddac, the decimal part of the analog voltage swing value, its value is an integer from 0 to 100, representing 0% to 100% of the decimal; DATA[3:1], base voltage multiple, symbol Mdac, the reference voltage multiple for analog-to-digital conversion, whose value is an even positive integer; DATA[0], polarity, symbol Pdac, instantaneous polarity of analog signal during analog-to-digital conversion.

[0005] Analog-to-digital conversion relies on a base voltage (base voltage, hereinafter the same) as a quantization standard. The result of dividing the sampled voltage value of the analog signal by the base voltage value has an integer part as the "integer amplitude" and a fractional part as the "fractional amplitude." The base voltage multiple only indicates how many times the highest reference voltage is compared to the base voltage value. The following will explain how to... Figure 1 The data structure shown contains the key parameters required for decoding.

[0006] Decoding frequency: refers to the operating frequency required to restore the analog signal, denoted by Fsw, and its relationship with Fdac is as follows: Fsw=(Fdac+1)*20kHz.

[0007] Polarity operator: refers to the instantaneous polarity of the signal being restored, symbol Psw, value calculated by Pdac, has... Psw = 2 * Pdac - 1 When Pdac = 0, the negative half-cycle of the analog signal is output, and Psw = -1; When Pdac = 1, the positive half-cycle of the analog signal is output, and Psw = +1.

[0008] The duty cycle of the decoding drive signal: symbol Dsw, the decoding relationship is as follows. Dsw=(Nsw+Ddac)*Psw / (Nsw*Psw+Pdac) Where Nsw=(Ndac–Mdac / 2) represents the midpoint of the integer amplitude value minus the base voltage multiple, i.e., the integer amplitude swing.

[0009] The number of series stages of the isoparametric power supply, Vsw: refers to the number of isoparametric power supplies required to reproduce the analog signal, denoted by Vsw. Its value is equal to the median value of the base voltage multiple, i.e. Vsw = Mdac / 2.

[0010] Switch position: This refers to which switch in the decoder switch group the decoder drive signal should currently drive. The symbol is S[x,y], where x represents an odd-numbered position and y represents an even-numbered position. It is based on the logical relationship values ​​decoded from Ndac, Ddac, and Pdac. The table below illustrates this with a base voltage multiplier of Mdac = 4. Table 1. Switch position decoding table.

[0011] From Table 1, we can see that the relationship between the switch position S[x,y] and Ndac is: When Pdac=1, the output is the positive half-cycle, S[x,y]=S[2*(Ndac-Mdac / 2)+3,2]; When Ndac = Mdac / 2 and Ddac = 0%, S[x,y] = S[1,2]; When Pdac = 0 in the negative half-cycle, S[x,y] = S[1,2*(Mdac / 2-Ndac)+2].

[0012] From the above decoding process, we have obtained the key parameters required for the decoding switch group: The power supply stage number Vsw indicates the number of isoparametric power supplies required. The switching frequency Fsw clarifies the frequency of the decoding drive signal PWM; Duty cycle Dsw specifies the duty cycle of the decoded drive signal PWM. Given the switch position S[x,y], the PWM should drive which switch in the decoder switch group.

[0013] The decoding principle will be explained below using a specific decoding circuit with a base voltage multiplier Mdac = 4.

[0014] Figure 2 This is a block diagram illustrating the principle of decoding the drive signal. Figure 3 This is the schematic diagram of the decoding switch group. The working principle of each switch group will be explained below.

[0015] Figure 2 It consists of three parts: DAC controller, PWM generation, and PWM distribution.

[0016] The DAC controller is a data processing unit with an FPGA device as its core. It performs decoding operations on the input encoded data stream to obtain decoding parameters Fsw, Dsw, and S[x,y].

[0017] The function of the PWM generation circuit is to generate a decoding drive signal PWM by the PWM oscillator according to the requirements of the decoding frequency Fsw and duty cycle Dsw. This PWM is used as the input of the PWM distribution circuit.

[0018] In the PWM distribution circuit, the input switch position signals S[x,y] are split into two paths: S[x] serves as the drive signal for odd-numbered switches, outputting SW_DRV[1,3,5]; S[y] serves as the drive signal for even-numbered switches, outputting SW_DRV[2,4,6]. Each set of S[x,y] position signals selects only one pair of drive signals for output, one for odd-numbered switches and one for even-numbered switches, used to drive the corresponding switches in the decoded switch group.

[0019] For example Figure 2 In the example, if S[x,y] = S[1,4], then SW_DRV1 outputs the drive signal S[x], and SW_DRV4 outputs the drive signal S[y]. The PWM signals distributed by S[x] and S[y] both come from the same PWM generated by the PWM. Similarly, S[3,2] selects SW_DRV3 and SW_DRV2 as a pair of drive signals.

[0020] Figure 3 In the decoding switch group circuit shown, by Odd-numbered switches S1, S3, and S5 Isoparametric power supplies Vdc1 and Vdc2 (C1 and C2 are filter capacitors), The even-numbered position switches S2, S4, and S6 constitute the configuration.

[0021] exist Figure 3The upper end of Vout is set to positive and the lower end to negative. The odd-numbered drive signals drive the odd-numbered switches S[1,3,5], and their outputs are all connected to Vout+, so the potential output of the odd-numbered switches is positive with respect to Vout; while the even-numbered drive signals drive the even-numbered switches S[2,4,6], which are connected to Vout-, so the potential output of the even-numbered switches is negative with respect to Vout.

[0022] Therefore, the output voltage Vout = Dsw * ((Vout+) - (Vout-)) Note: The position numbers in S[x,y] may be odd or even, but they should all follow the above formula, that is, the output voltage Vout is obtained by subtracting the output potential (Vout-) of the even-numbered switch from the output potential (Vout+) of the odd-numbered switch, and then multiplying it by the decoding duty cycle Dsw.

[0023] As described above, after inputting S[1,4], the output of the decoding switch group... Vout = Dsw * ((Vout+) - (Vout-)) =Dsw*((0V)-(Vdc1)) =-(Dsw*Vdc1).

[0024] Since power supplies Vdc1 and Vdc2 are isoparametric power supplies, meaning they have identical power supply characteristics (e.g., equal output internal resistance, equal output voltage, equal ripple voltage), etc., and Vdc represents the voltage of the isoparametric power supply, the above equation becomes... Vout = -(Dsw * Vdc).

[0025] Similarly, when the input is S[3,2], we can get Vout=+(Dsw*Vdc), so we have Vout = 0V ~ ±(Dsw * Vdc).

[0026] The above formula represents the output voltage range of the decoding switch group when there is only one power supply (Vdc). The output range of a two-stage power supply is... Vout = 0V ~ ±2*(Dsw*Vdc), when Dsw = 0% ~ 100%, Vout = 0V ~ ±2*Vdc.

[0027] From the above analysis, it can be seen that when the switching frequency Fsw of the decoding drive signal is fixed, the control of Dsw and S[x,y] can make the output signal of the decoding switch group a sine wave, the value of which varies between 0V and (±2*Vdc). When Fsw, Dsw, and S[x,y] are decoded from the relevant parameters of the ADC encoding circuit, the output signal Vout will also restore the analog signal during encoding.

[0028] The following will reconstruct a complete analog sine wave signal based on a specific set of DAC encoded values. The data table to be decoded is shown below. 1 DATA[00 010 0000000 100 1] DATA[0x1009] 2 DATA[00 010 0110010 100 1] DATA[0x1329] 3 DATA[00 011 0000000 100 1] DATA[0x1809] 4 DATA[00 011 0110010 100 1] DATA[0x1B29] 5 DATA[00 011 0000000 100 1] DATA[0x1809] 6 DATA[00 010 0110010 100 1] DATA[0x1329] 7 DATA[00 010 0000000 100 1] DATA[0x1009] 8 DATA[00 001 0110010 100 0] DATA[0x0B28] 9 DATA[00 001 0000000 100 0] DATA[0x0808] 10 DATA[00 000 0110010 100 0] DATA[0x0328] 11 DATA[00 001 0000000 100 0] DATA[0x0808] 12 DATA[00 001 0110010 100 0] DATA[0x0B28] 13 DATA[00 010 0000000 100 0] DATA[0x1008] Table 2. Raw data from the DAC data table.

[0029] The following analysis and explanation, based on the decoding principle of this invention, will explain how to decode the required parameters from the data in Table 2, thereby ultimately controlling... Figure 3 The decoding switch group in the table restores the analog signal. The decoding process is explained using the first data 0x1009 in Table 2 as an example.

[0030] Decoding frequency Fsw from Figure 1 It can be seen that the sampling frequency Fdac = DATA[15:14] = 2'00 = 0. According to the decoding formula, we have Fsw=(Fdac+1)*20kHz=20kHz.

[0031] Integer swing amplitude Nsw from Figure 1 We know that the base voltage multiple Mdac = DATA[3:1] = 2'100 = 4; the integer amplitude Ndac = DATA[13:11] = 2'010 = 2. Therefore... Nsw = Ndac – Mdac / 2 = 0.

[0032] Polarity operator Psw from Figure 1 It can be seen that the polarity Pdac = DATA[0] = 2'1 = 1, indicating positive polarity output. Based on the decoding relationship, the polarity operator... Psw = 2 * Pdac - 1 = +1.

[0033] Duty cycle Dsw of the decoding drive signal from Figure 1 It can be seen that the decimal amplitude Ddac=DATA[10:4]=2'0000000=0, then Dsw=(Nsw+Ddac)*Psw / (Nsw*Psw+Pdac)=0.

[0034] The number of series stages of an isoparametric power supply, Vsw from Figure 1 Given that the base pressure ratio Mdac = DATA[3:1] = 2'100 = 4, then... Vsw = Mdac / 2 = 2 That is, two isoparametric power supplies are needed in series as the power supply for the decoding switch group.

[0035] Switch position S[x,y] Based on the obtained parameters Ndac=2, Ddac=0%, and Pdac=1, the following can be found in Table 1: S[x,y]=S[1,2].

[0036] Based on the above decoding results, input Dsw=0, Fsw=20kHz to... Figure 2 The PWM generation circuit shown then inputs the switch position signal S[x,y]=S[1,2] to the PWM distribution circuit to switch the position of the drive signal PWM, so that the PWM signal is loaded onto SW_DRV1 and SW_DRV2, driving the PWM signal. Figure 3 The upper half-bridge switch S[x] = S1 and the lower half-bridge switch S[y] = S2 are both turned on.

[0037] When S1 is turned on, the upper half-bridge voltage Vout+ = 0V; when S2 is turned on, the lower half-bridge voltage Vout- = 0V. Vout=Dsw*((Vout+)–(Vout-)) =0%*(0V–0V) =0V.

[0038] Following the decoding process described above, all results for groups 2 through 13 can be obtained and listed in the table below. Let... Figure 3 The isoparametric power supply in the figure is Vdc = Vdc1 = Vdc2 = 12V. 1 0x1009 20 0 0％ +1 2 [1,2] 0% * (0V - 0V) = 0V 2 0x1329 20 0 50％ +1 2 [2,3] 50% * (12V - 0V) = +6V 3 0x1809 20 +1 50％ +1 2 [2,5] 50% * (24V - 0V) = +12V 4 0x1B29 20 +1 75％ +1 2 [2,5] 75% * (24V - 0V) = +18V 5 0x1809 20 +1 50％ +1 2 [2,5] 50% * (24V - 0V) = +12V 6 0x1329 20 0 50％ +1 2 [2,3] 50% * (12V - 0V) = +6V 7 0x1009 20 0 0％ +1 2 [1,2] 0% * (0V - 0V) = 0V 8 0x0B28 20 -1 50％ -1 2 [1,4] 50% * (0V - 12V) = -6V 9 0x0808 20 -1 50％ -1 2 [1,6] 50% * (0V - 24V) = -12V 10 0x0328 20 -2 75％ -1 2 [1,6] 75% * (0V - 24V) = -18V 11 0x0808 20 -1 50％ -1 2 [1,6] 50% * (0V - 24V) = -12V 12 0x0B28 20 -1 50％ -1 2 [1,4] 50% * (0V - 12V) = -6V 13 0x1008 20 0 0％ -1 2 [1,2] 0% * (0V - 0V) = 0V Table 3. Decoding results of data 0x1009 in the first group

[0039] The curve plotted based on the decoding results in the table above is as follows: Figure 4 As shown in the diagram. (For simplicity, the diagram is omitted.) Figure 4 The original data DATA[15:0], Fdac, Mdac, and the decoding results Fsw and Vsw are not shown in the figure.

[0040] Figure 4 The raw data at the top is arranged according to the sequence number in Table 3; the decoded data in the middle is arranged according to the result corresponding to the sequence number in Table 3; and the output results at the bottom are arranged according to the time t0 to t13 based on the driving output of the decoded results.

[0041] from Figure 4It can be seen that regardless of the voltage of the isoparametric power supply, as long as the number of stages corresponds quantitatively to the midpoint of the base voltage multiple in the original data, the correct result can be output, only the amplitude will be different. Furthermore, since it directly outputs the PWM waveform through power switches S1 to S6, it can drive the power load without needing a traditional analog power amplifier circuit.

[0042] This improves the efficiency of the power amplifier, simplifies its structure, and eliminates the high requirements for analog components found in analog amplifiers. This is because the traditional analog signal power amplification process is entirely accomplished using PWM (Pulse Width Modulation) of the power switching transistors.

[0043] Because the analog-to-digital encoding process involves both an integer part and a fractional part, while the decoding process results in an integer swing amplitude plus a duty cycle. Therefore, the integer part during encoding represents the number of power switches activated during decoding, while the fractional part is used to calculate the duty cycle of the decoding switch.

[0044] Compared to pulse power amplifiers, this method, by employing coarse quantization of the integer part and fine quantization of the fractional part, results in superior signal quality compared to a simple single-stage power supply with PWM modulation. Furthermore, it offers even better signal quality than the traditional ADC+DAC+analog power amplifier approach.

[0045] As can be seen from the above analysis, the digital-to-analog conversion accuracy of this invention depends entirely on the quantization accuracy of small values ​​during analog-to-digital conversion. In the example of Vdc = 12V above, Ddac is calculated at 100%, which is the smallest conversion unit. 1LSB=1%*Vdc=1%*12V=0.12V. Attached Figure Description

[0046] Appendix Figure 1 Digital-to-analog conversion data structure

[0047] Appendix Figure 2 Decoding circuit control block diagram

[0048] Appendix Figure 3 Schematic diagram of the decoding switch group

[0049] Appendix Figure 4 A sine wave decoded and restored

[0050] Appendix Figure 5 Audio power amplifier examples Detailed Implementation

[0051] Figure 5 It is an audio decoding circuit whose output load Vout is directly connected to the speaker.

[0052] Figure 5It is an audio decoding circuit with 24-bit data bits, and the input is an audio data stream; the 12V isoparametric power supply consists of 3 series connections; the decoding switch group has a total of 8 switches, with odd-numbered switches S[1, 3, 5, 7] and even-numbered switches S[2, 4, 6, 8].

[0053] Set working parameters If the PWM frequency Fsw = 40kHz = (Fdac + 1) * 20kHz, then... Fdac = 1; The number of series stages of the isoparametric power supply is Vsw = 3 = Mdac / 2, then Mdac = 6; For integer amplitude, the maximum value should be taken, i.e. Nsw_max = Mdac = 6; Polarity operators Psw = 2 * Pdac – 1;

[0054] For PWM duty cycle, if a conversion accuracy of 1mV is required, then... 1LSB = Dsw * Vdc = 1mV, since Vdc = 12V, then Dsw = 1 / 12000, meaning the adjustment range of Dsw is 0 / 12000 to 12000 / 12000. Dsw_max = 12000 Since Dsw = (Nsw + Ddac) * Psw / (Nsw * Psw + Pdac), when Nsw = 0 and Pdac = 1, we have Dsw=(0+Ddac)*1 / (0+1), then Ddac_max = Dsw_max = 12000.

[0055] from Figure 1 From the data structure shown, we can see that the sampling frequency Fdac, integer amplitude Ndac, fractional amplitude Ddac, base voltage multiple Mdac, and polarity Pdac are as follows: Fdac = DATA[15:14] = 2'01; Ndac = DATA[13:11] = 2'110; Ddac=DATA[10:4]=2'10 1110 1110 0000; Mdac = DATA[3:1] = 2'110; Pdac = DATA[0] = 2'x.

[0056] The binary bit lengths of the above Fdac, Ndac, Ddac, Mdac, and Pdac are arranged according to... Figure 1By concatenating the data structures shown, we can obtain... Figure 5 The required data structure for digital-to-analog conversion.

[0057] The total number of binary bits is DATA[Fdac+Ndac+Ddac+Mdac+Pdac] =DATA[2bit+3bit+14bit+3bit+1bit] =DATA[23bit].

[0058] According to the binary data structure that uses 3 bytes of data per 8-bit byte, that is... DATA[MSB:LSB]=[23:0] The results are as follows Figure 5 The audio data stream DATA[23:0] is shown in the figure.

[0059] Working principle

[0060] When DATA[23:0] is encoded according to the above data structure and each field meets the above requirements, it can be input into... Figure 5 The DAC controller performs decoding. The DAC controller outputs according to the decoding method of this invention: Fsw, the frequency of the decoded drive signal PWM; Dsw, the duty cycle of the decoded drive signal PWM; S[x,y] represents the position information of the decoded switch group.

[0061] The input is fed into the PWM generator to generate a PWM signal. After being distributed, the signal is output from DRV[1, 3, 5, 7] and DRV[2, 4, 6, 8] respectively, controlling the output of the isoparametric power supply BT[1, 2, 3] so that it meets the requirements controlled by the PWM and drives the speaker to work, thus restoring the audio signal encoded by DATA[23:0].

Claims

1. A digital-to-analog converter decoding circuit, characterized in that it includes a DAC controller, a PWM generation circuit, a PWM distribution circuit, a decoding switch group, and an isoparametric power supply; The DAC controller is a data processing system consisting of an FPGA and peripheral devices. Its function is to decode the operating frequency Fsw, polarity operator Psw, duty cycle Dsw, power supply stage Vsw, and switch position S[x,y] data required to restore the analog signal from the input data DATA[15:0]. wherein The 16-bit data structure of the input data DATA[15:0] is as follows: DATA[15:14] represents the sampling frequency Fdac; DATA[13:11] represents the integer amplitude value Ndac; DATA[10:4] is the decimal range Ddac, which is an integer from 0 to 100, representing 0% to 100% of the decimal. DATA[3:1] is the base voltage multiple Mdac, whose value is an even positive integer; DATA[0] represents the polarity Pdac; The DAC controller decodes according to the following relationship: Decoding frequency Fsw = (Fdac+1)×20kHz; Polarity operator Psw = 2 × Pdac - 1; Integer amplitude swing Nsw = Ndac - Mdac / 2; Duty cycle Dsw = (Nsw+Ddac)×Psw / (Nsw×Psw+Pdac); Number of power supply stages Vsw = Mdac / 2; The switch position S[x,y] satisfies the following: when Pdac=1, S[x,y]=S[2×(Ndac-Mdac / 2)+3,2]; when Ndac=Mdac / 2 and Ddac=0%, S[x,y]=S[1,2]; when Pdac=0, S[x,y]=S[1,2×(Mdac / 2-Ndac)+2]; The PWM generation circuit consists of a controlled PWM oscillator. The control signals are the operating frequency Fsw and the duty cycle Dsw. The control result is the output signal PWM of the PWM oscillator, whose characteristics are equal to the values ​​of the control signals Fsw and Dsw. The PWM distribution circuit contains two identical one-to-many switching switches: The input signal of the first switching switch is PWM, and the position control signal is S[x]. When the first position is selected, PWM is output from drive signal line one (SW_DRV1). When the third position is selected, PWM is output from drive signal line three (SW_DRV3). When the fifth position is selected, PWM is output from drive signal line five (SW_DRV5). The input signal of the second switch is PWM, and the position control signal is S[y]. When the second position is selected, PWM is output from drive signal line 2 (SW_DRV2). When the fourth position is selected, PWM is output from drive signal line 4 (SW_DRV4). When the sixth position is selected, PWM is output from drive signal line 6 (SW_DRV6). The decoding switch group includes switches 1 (S1), 3 (S3), and 5 (S5) with odd-numbered positions, and switches 2 (S2), 4 (S4), and 6 (S6) with even-numbered positions; wherein: One end of switch one (S1), one end of switch three (S3), and one end of switch five (S5) are connected to the positive terminal (+) of the output Vout; The other end of switch two (S2), the other end of switch four (S4), and the other end of switch six (S6) are connected to the negative terminal (-) of output Vout; The system connects GND to the other end of switch one (S1) and one end of switch two (S2); Power node 1 Vdc1 is connected to the other end of switch 3 (S3) and one end of switch 4 (S4); Power node 2 Vdc2 is connected to the other end of switch 5 (S5) and one end of switch 6 (S6); The negative terminal of power supply BT1 is connected to system ground GND, and the positive terminal is connected to power supply node Vdc1. The negative terminal of power supply BT2 is connected to power node 1 Vdc1, and the positive terminal is connected to power node 2 Vdc2. The driving terminal of switch one (S1) is connected to drive signal line one (SW_DRV1), the driving terminal of switch two (S2) is connected to drive signal line two (SW_DRV2), the driving terminal of switch three (S3) is connected to drive signal line three (SW_DRV3), the driving terminal of switch four (S4) is connected to drive signal line four (SW_DRV4), the driving terminal of switch five (S5) is connected to drive signal line five (SW_DRV5), and the driving terminal of switch six (S6) is connected to drive signal line six (SW_DRV6). The isoparametric power supply refers to the power supply in the decoding switch group in which all the power supplies BT1 and BT2 connected in series have the same parameters, that is, Vdc1=Vdc2.

2. A method of digital-to-analog decoding, applied to the digital-to-analog decoding circuit of claim 1, characterized in that, Includes the following steps: (1) Provide 16-bit input data DATA[15:0], the data structure of which is: DATA[15:14] is the sampling frequency Fdac, DATA[13:11] is the integer amplitude Ndac, DATA[10:4] is the fractional amplitude Ddac, DATA[3:1] is the base voltage multiple Mdac, and DATA[0] is the polarity Pdac; (2) The DAC controller performs decoding operations on the input data to obtain: Decoding frequency Fsw = (Fdac+1)×20kHz; Polarity operator Psw = 2 × Pdac - 1; Integer amplitude swing Nsw = Ndac - Mdac / 2; Duty cycle Dsw = (Nsw+Ddac)×Psw / (Nsw×Psw+Pdac); Number of power supply stages Vsw = Mdac / 2; When Pdac=1, the switch position S[x,y]=S[2×(Ndac-Mdac / 2)+3,2]; when Ndac=Mdac / 2 and Ddac=0%, S[x,y]=S(1,2); when Pdac=0, S[x,y]=S[1,2×(Mdac / 2-Ndac)+2]; (3) The PWM generation circuit generates a PWM signal according to the decoding frequency Fsw and the duty cycle Dsw; (4) The PWM distribution circuit distributes the PWM signal to the corresponding drive signal line according to the switch position S[x,y]. Specifically, the first switch selects one of the drive signal line 1 (SW_DRV1), drive signal line 3 (SW_DRV3), or drive signal line 5 (SW_DRV5) to output PWM according to S[x]; the second switch selects one of the drive signal line 2 (SW_DRV2), drive signal line 4 (SW_DRV4), or drive signal line 6 (SW_DRV6) to output PWM according to S[y]. (5) The corresponding switch pair in the decoding switch group is turned on under PWM drive and is powered by the isoparametric power supply BT1 and BT2 in series. The restored analog signal is obtained at the output Vout terminal. The output voltage Vout = Dsw×((Vout+)-(Vout-)).

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