Semiconductor structure and method for forming the same, and memory

Abstract

A semiconductor structure and a method for forming the same, and a memory, wherein the method for forming the semiconductor structure comprises: providing a substrate, wherein at least one long strip active region is formed in the substrate, wherein the active region is surrounded by an isolation structure; etching the active region and the isolation structures on both sides of the active region to form a gate groove, wherein the length direction of the gate groove intersects with the length direction of the active region, wherein the gate groove comprises a first groove located in the active region and a second groove located in the isolation structure, and the top surface of the active region at the bottom of the first groove is flat and has a smooth edge; and forming a gate structure in the gate groove. The semiconductor structure formed by the above method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a forming method thereof, and a memory. Background Art

[0002] With the continuous development of semiconductor technology, the size of integrated circuits is getting smaller and smaller, and the channel size of transistors, the basic devices in semiconductor structures, is also getting smaller and smaller. Especially in semiconductor memory devices, in order to increase storage density, the size of transistors has been greatly reduced.

[0003] In order to improve the driving capability of the transistor, in the prior art, a groove is formed by etching the active area of ​​the substrate, and then a gate dielectric layer and a gate are formed in the groove to form a buried gate structure, thereby increasing the channel width of the transistor without increasing the line width.

[0004] Since the gate is formed in the groove formed by etching the active area, the morphology of the groove has a great influence on the performance of the transistor. In the prior art, while etching the active area to form the gate groove, the isolation structure on both sides of the active area is also etched. Since the active area and the isolation structure are made of different materials, the etching rates of the two materials are different during the etching process, resulting in a poor morphology of the active area after etching, which is prone to charge accumulation during the operation of the transistor, thereby causing problems such as offset or leakage of the threshold voltage of the transistor, affecting the performance of the transistor.

[0005] How to improve the performance of buried-gate transistors is an urgent problem to be solved. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same, and a memory, so as to improve the performance of the semiconductor structure.

[0007] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein at least one long strip active area is formed in the substrate, and the active area is surrounded by an isolation structure; etching the active area and the isolation structures on both sides of the active area to form a gate groove, wherein the length direction of the gate groove intersects with the length direction of the active area, the gate groove comprises a first groove located in the active area and a second groove located in the isolation structure, and the top surface of the active area at the bottom of the first groove is flat and the edges are smooth; and forming a gate structure in the gate groove.

[0008] Optionally, a depth difference between the first groove and the second groove is less than or equal to 50 nm.

[0009] Optionally, the depth of the first groove is smaller than the depth of the second groove, and the top angle of the top edge of the active area at the bottom of the first groove is rounded.

[0010] Optionally, the first etching process and the second etching process are alternately used to etch the active area and the isolation structure on both sides of the active area to form a gate groove; the first etching process has a greater etching selectivity for the isolation structure than the active area, and the second etching process has a greater etching selectivity for the active area than the isolation structure.

[0011] Optionally, during the process of etching the active area and the isolation structures on both sides of the active area, the height difference between the etched active area and the isolation structure is controlled to be less than or equal to 50 nm.

[0012] Optionally, the etching gas used in the first etching process includes at least carbon- and fluorine-containing gases, the RF power is 800-1600 W, the bias voltage is 150-800 V, and the pressure is 10-30 mTorr; the etching gas used in the second etching process includes at least carbon-, fluorine-, chlorine-, and bromine-containing gases, the RF power is 800-1800 W, the bias voltage is 50-300 V, and the pressure is 15-40 mTorr.

[0013] The technical solution of the present invention also provides a semiconductor structure, including: a substrate, in which at least one long strip active area is formed, and the active area is surrounded by an isolation structure; a gate groove located in the active area and the isolation structure on both sides of the active area, the length direction of the gate groove intersects with the length direction of the active area, the gate groove includes a first groove located in the active area and a second groove located in the isolation structure, and the top surface of the active area at the bottom of the first groove is flat and the edges are smooth; a gate structure located in the gate groove.

[0014] Optionally, a depth difference between the first groove and the second groove is less than or equal to 50 nm.

[0015] Optionally, the depth of the first groove is smaller than the depth of the second groove.

[0016] Optionally, a top corner of a top edge of the active area at the bottom of the first groove is rounded.

[0017] Optionally, the gate structure includes: a gate dielectric layer covering an inner wall of the gate groove; and a gate electrode filling the gate groove on a surface of the gate dielectric layer.

[0018] Optionally, a plurality of active regions arranged in an array are formed in the substrate, including more than two gate grooves, and the gate grooves are arranged in parallel, and each gate groove spans over at least two active regions.

[0019] Optionally, the isolation structure is a shallow trench isolation structure.

[0020] The technical solution of the present invention further provides a memory, comprising any of the semiconductor structures described above.

[0021] The top of the active area at the bottom of the gate trench formed by the semiconductor structure forming method of the present invention is flat, which avoids the accumulation of charges on the top of the active area, thereby effectively preventing the accumulation of charges in the channel area and effectively preventing the device from being turned on prematurely; and the top edge of the active area at the bottom of the gate trench is smooth, which avoids the accumulation of charges at the edge of the active area, avoids device leakage, etc., and improves the effectiveness of the device.

[0022] Furthermore, the isolation structure and the active area always maintain a small height difference during the etching process, which can greatly improve the etching load effect and improve the accuracy of the etching pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1a to 4c It is a structural schematic diagram of a formation process of a semiconductor structure according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0024] The semiconductor structure and the method for forming the semiconductor structure and the memory provided by the present invention are described in detail below with reference to the accompanying drawings.

[0025] Please refer to Figures 1a to 4c , which is a structural schematic diagram of the formation process of a semiconductor structure according to a specific embodiment of the present invention.

[0026] Please refer to Figure 1a-1c , a substrate 100 is provided, in which at least one long strip active region 101 is formed, and the active region 101 is surrounded by an isolation structure 102. Figure 1a A top view diagram is shown. Figure 1b is a schematic cross-sectional view along the A-A' direction, Figure 1c It is a schematic cross-sectional view along the BB' direction.

[0027] The substrate 100 is a semiconductor substrate, including single crystal silicon, polycrystalline silicon, silicon germanium, silicon on insulator, silicon carbide, etc. It can also be a composite structure such as an epitaxial semiconductor layer formed on the surface of a single crystal silicon substrate.

[0028] The active region 101 is formed by etching the substrate 100. In this specific embodiment, a plurality of long active regions 101 arranged in an array are formed in the substrate 100, and each active region 101 is used to form a transistor array, which is used as a transistor of a memory cell of a memory.

[0029] The arrangement of the active area 101 may be set according to the distribution of storage cells of a specific memory, and is not limited here.

[0030] While etching the substrate 100 to form the active area 101, a groove is formed around the active area 101, and an insulating dielectric material is filled in the groove to form the isolation structure 102. Specifically, the isolation structure 102 can be a shallow trench isolation structure, and the isolation structure 102 can include a pad oxide layer covering the inner wall of the groove, and an insulating dielectric layer located on the surface of the pad oxide layer. The pad oxide layer can be a silicon oxide layer formed by a thermal oxidation process, and the insulating dielectric material used in the insulating dielectric layer can be an oxide, a nitride, or an oxide and nitride layer deposited alternately stacked. In this specific embodiment, the insulating dielectric layer is silicon oxide. In other specific embodiments, the material of the insulating dielectric layer can also be silicon nitride, silicon oxynitride, silicon oxycarbide, etc. In other specific embodiments, structures such as air gaps can also be formed in the isolation structure 102 to improve isolation performance.

[0031] Please refer to Figure 2a to Figure 2c A mask structure 200 is formed on the surface of the substrate 100 , and an opening 2041 is provided in the mask structure 200 for defining the position and size of a gate to be formed in the substrate 100 .

[0032] In this specific embodiment, the mask structure 200 includes a first hard mask layer 201 located on the surface of the substrate 100, a second hard mask layer 202 located on the surface of the first hard mask layer 201, a stop layer 203 located on the surface of the second hard mask layer 202, and a patterned mask layer 204 located on the surface of the stop layer 203, wherein an opening 2041 is formed in the patterned mask layer 204.

[0033] The material of the first hard mask layer 201 may be at least one of hard mask materials such as amorphous carbon (DLC), amorphous carbon (ACL), silicon oxycarbide (SiOC), or silicon nitride, and may be a single layer or a multi-layer structure.

[0034] The second hard mask layer 202 may be made of nitride, oxide, carbon or other hard mask materials, and may be a single layer or a multi-layer structure. In this specific implementation, the second hard mask layer 202 and the first hard mask layer 201 are made of different materials.

[0035] The material of the stop layer 203 is amorphous silicon, silicon oxynitride, etc., which has a higher etching selectivity ratio with the material of the patterned mask layer 204 .

[0036] The material of the patterned mask layer 204 can be silicon oxide, silicon oxycarbide or photoresist, etc. The mask layer is etched to the surface of the stop layer 203 by photolithography and etching process to form the patterned mask layer 204 with the opening 2041 .

[0037] In other specific implementations, mask structures with other film layer structures may also be provided, which is not limited here.

[0038] In this specific embodiment, a plurality of parallel arranged long strip openings 2041 are formed in the patterned mask layer 204, and the length direction of the openings 2041 intersects with the length direction of the active area 101. Each opening 2041 intersects with the positions of multiple active areas 101. Since the active area 101 is isolated by the structure 102, the openings 2041 are also located above the isolation structure 102 on both sides of the active area 101.

[0039] Please refer to Figure 3a to Figure 3b , using the mask structure 200 as a mask, etching the substrate 100 to form a gate groove 300 in the substrate 100 .

[0040] During the etching process, etching is performed downward along the opening 2041, and the pattern of the opening 2041 is transferred layer by layer to the first hard mask layer 201, and then the active area 101 and the isolation structure 102 in the substrate 100 are etched simultaneously to form the gate groove 300 located in the active area 101 and the isolation structure 102. In this specific embodiment, more than two gate grooves 300 are formed, and the gate grooves 300 are arranged in parallel, and each gate groove 300 spans at least two active areas 101.

[0041] Since the active region 101 and the isolation structure 102 are made of different materials, etching the active region 101 and the isolation structure 102 has different etching rates. Therefore, the etching depths of the gate groove 300 in the isolation structure 102 and the active region 101 are different.

[0042] The gate groove 300 includes a first groove 301 located in the active region 101 and a second groove 302 located in the isolation structure 102 .

[0043] Preferably, the etching process can be controlled so that the first groove 301 and the second groove 302 have the same depth, so as to help the bottom of the gate groove 300 remain flat, thereby keeping the top plane of the active area 101 at the bottom of the gate groove 300 smooth and flat, thereby improving the performance of the formed transistor.

[0044] However, since the isolation structure 102 and the active area 101 are made of different materials and have different etching ratios, it is difficult to achieve that the depths of the first groove 301 and the second groove 302 are exactly the same. Preferably, in order to increase the area of ​​the channel region between the gate structure and the active area 101 to be formed subsequently, the depth of the first groove 301 is less than the depth of the second groove 302, so that the top of the isolation structure 102' after being etched at the bottom of the second groove 302 is lower than the top of the active area 101' after being etched at the bottom of the first groove 301, thereby exposing part of the sidewall of the active area 101'. In other specific embodiments, the depth of the first groove 301 may also be greater than the depth of the second groove 302.

[0045] Preferably, the etching rate ratio of the isolation structure 102 and the active area 101 during the etching process can be controlled to make the top of the active area 101' flat, avoiding depression or protrusion on the top, thereby avoiding the problem of charge accumulation at the top surface of the active area 101' in the formed transistor, which causes the transistor to be turned on prematurely before the threshold voltage is reached. Furthermore, the top corner of the top edge of the active area 101' can be rounded by controlling the etching process to avoid problems such as leakage caused by charge accumulation at the top corner.

[0046] The height of the substrate 100 is H, and the difference between the depth H1 of the first groove 301 and the depth H2 of the second groove 302 needs to be controlled within a certain range, preferably, H2-H1≤50nm.

[0047] When the depth of the first groove 301 is less than the depth of the second groove 302, the top corner of the top edge of the active area 101' is exposed. In order to effectively avoid the charge accumulation and discharge at the top corner of the active area 101', the top corner of the top edge of the active area 101' at the bottom of the first groove 301 is rounded, for example, in an arc shape, which is conducive to the uniform distribution of charges.

[0048] During the etching of the isolation structure 102 and the active area 101, due to the different etching selectivity of the two, it is easy to have the isolation structure higher than the active area or the active area higher than the isolation structure after etching. In the case where the isolation structure is higher than the top of the active area, if the height difference between the two is too large, since the etching of the active area 101 is mainly chemical etching, the reaction product is discharged faster at the middle position of the active area 101, and the etching rate at the middle position of the active area is faster than the etching rate near the isolation structure 102, resulting in a depression at the top of the active area 101; and in the case where the isolation structure is lower than the top of the active area, if the height difference between the two is too large, since the etching of the isolation structure 102 is mainly physical etching, the etching ions have a high bombardment ability, and during the etching process, the edge of the active area 101 will also be bombarded, resulting in the top of the active area 101 after etching becoming an arc that bulges upward. A depression or a protrusion on the top of the active region 101 will lead to the accumulation of charges. Therefore, during the etching process, the height difference between the active region and the isolation structure at the bottom of the etching groove needs to be controlled.

[0049] In order to overcome the above problems, in a specific embodiment of the present invention, the method for forming the gate groove 300 includes: alternately using a first etching process and a second etching process to etch the active area 101 and the isolation structure 102. The first etching process has a greater etching selectivity for the isolation structure 102 than the active area 101, and the second etching process has a greater etching selectivity for the active area 101 than the isolation structure 102. Both the first etching process and the second etching process are anisotropic etching processes, such as plasma etching process, reactive ion etching process, etc.

[0050] In some specific embodiments, the etching gas used in the first etching process includes at least carbon- and fluorine-containing gases, and has a high etching selectivity for the dielectric material of the isolation structure 102; the etching gas used in the second etching process includes at least carbon-, fluorine-, chlorine-, and bromine-containing gases, and has a high etching selectivity for the material of the active area 101. By adjusting the etching parameters of the first etching process and the second etching process, such as the type of etching gas, flow rate, RF power, bias voltage, etc., the etching depth of the active area and the isolation structure can be better controlled.

[0051] In a specific embodiment, the etching gas used in the first etching process includes CF 4 , CH 2 F 2 , and pass the protective gas He, where CF 4 The flow rate is 30sccm~80sccm, CH 2 F 2The flow rate of is 5sccm~40sccm, the flow rate of He is 50sccm~200sccm, the RF power is 800~1600W, the bias voltage is 150~800V, and the pressure is 10~30mTorr; the etching gas used in the second etching process includes at least CF 4 , CHF 3 , Cl 2 and HBr, and pass the protective gas He, where CF 4 The flow rate is 30sccm~80sccm, CHF 3 The flow rate is 10sccm~150sccm, Cl 2 The flow rate of is 10sccm to 80sccm, the flow rate of HBr is 10sccm to 150sccm, the flow rate of He is 50sccm to 200sccm, the RF power is 800 to 1800W, the bias voltage is 50 to 300V, and the pressure is 15mTorr to 40mTorr. In the actual etching process, according to the requirements for the depth of the first groove and the second groove, it can be reasonably selected to first perform the first etching process or first perform the second etching process.

[0052] In a specific embodiment of the present invention, in order to make the depth of the first groove 301 less than or equal to the depth of the second groove 302, in this specific embodiment, the first stage is firstly performed, and the first etching process with high etching selectivity for the isolation structure 102 is performed, and a higher radio frequency power, for example, 1200W to 1600W, is used, so that the first etching process has a higher etching rate and improves efficiency. After the first stage of etching is completed, the etching depth of the isolation structure 102 is greater than the etching depth of the active area 101, and the height difference between the two after etching is less than 50nm; then the second stage is performed, and the second etching process is used to continue etching, and a higher radio frequency power, for example, 1400W to 1800W, can be used to improve the etching efficiency, and the second etching process reduces the etching efficiency of the active area 101 and the isolation structure. 102, because the etched active area 101 is higher than the top of the isolation structure during the second stage of etching, the etched surface of the top of the active area 101 can be prevented from being concave; in the third stage, the first etching process is continued to be used for etching, and the RF power can be appropriately reduced to reduce the etching rate, for example, the RF power is adjusted to 800W~1300W, so as to better control the etching morphology of the gate groove. Since the height difference between the active area below the etching groove and the top of the isolation structure is small, the ion bombardment effect on the side wall of the active area is small during the etching process of the first etching process, so as to avoid excessive etching of the top edge of the active area, thereby avoiding the generation of a convex morphology on the top surface of the active area. In the fourth stage, the second etching process is continued to be used for etching, and the etching rate of the second etching process is reduced, for example, the RF power is adjusted to 800W~1500W. In this specific implementation, the first etching process and the second etching process are performed in two cycles, so that the top of the active area 101' at the bottom of the first groove is flat and the top angle is smooth.

[0053] In other specific implementations, the first etching process and the second etching process may be alternately cycled multiple times until appropriate gate trench depth and morphology requirements are achieved.

[0054] In the process of alternately performing the first etching process and the second etching process, the height difference between the top of the active area at the bottom of the groove formed by etching and the top of the isolation structure is always maintained to be less than or equal to 50nm. In the etching process, the top of the isolation structure may always be lower than the top of the active area, or the top of the isolation structure may be higher than the top of the active area or the top of the isolation structure may be flush with the top of the active area. According to the state in the etching process, the time of each first etching process and the second etching process is adjusted to adjust the etching amount of the isolation structure and the active area, and the height difference between the two is controlled within 50nm.

[0055] The top of the active area 101' after etching is finally flat, which prevents the charge from gathering at the top of the active area 101', thereby effectively preventing the charge from gathering in the channel area and effectively preventing the device from turning on prematurely. In addition, since the top edge of the active area 101' is bombarded by the ions of the etching isolation structure 102, it is in a smooth state, which prevents the charge from gathering at the top corner of the active area 101', prevents device leakage, etc., and improves the effectiveness of the device.

[0056] Furthermore, the isolation structure 102 ′ and the active area 101 ′ always maintain a small height difference during the etching process, which can greatly improve the etching load effect and improve the accuracy of the etching pattern.

[0057] After etching to form the gate groove 300 , the first hard mask layer 201 is retained to serve as a stop layer for planarization in the subsequent process of forming a gate structure.

[0058] Please refer to Figures 4a to 4c , a gate structure 400 is formed in the gate groove 300 .

[0059] The gate structure 400 includes a gate dielectric layer 401 covering the inner wall of the gate groove 300 and a gate 402 located on the surface of the gate dielectric layer 401 and filling the gate groove 300 .

[0060] The gate dielectric layer 401 may be made of silicon oxide, silicon oxynitride, or a high-K dielectric material such as hafnium oxide, zirconium oxide, or aluminum oxide.

[0061] The material of the gate 402 includes polysilicon, or at least one of metal materials such as Cu, W, Al or Ag. A work function layer may be formed between the gate 402 and the gate dielectric layer 401 to adjust the work function of the gate structure 400. The material of the work function layer may be at least one of TiN, TaN, Ti or Ta.

[0062] In this specific embodiment, the method for forming the gate structure 400 includes: forming a gate dielectric material layer covering the inner wall of the gate groove 300 and the surface of the first hard mask layer 201; forming a gate material filling the gate groove 300 on the surface of the gate dielectric material layer; using the first hard mask layer 201 as a stop layer, planarizing the gate material and the gate dielectric material layer, removing the gate dielectric material layer and the gate material layer on the surface of the first hard mask layer 201, and forming the gate structure 400. After forming the gate structure 400, the first hard mask layer 201 can also be removed.

[0063] Subsequently, the source and drain of the transistor are respectively formed in the active area 101 on both sides of the gate structure.

[0064] In other specific implementations, after the gate groove 300 is formed, the first hard mask layer 201 may be removed, and the top surface of the gate structure formed subsequently is flush with the surface of the substrate 100 .

[0065] A specific embodiment of the present invention further provides a semiconductor structure.

[0066] Please refer to Figures 4a to 4c , which is a schematic diagram of a top view and a cross-sectional structure of a semiconductor structure according to a specific embodiment of the present invention.

[0067] The semiconductor structure includes: a substrate 100, in which at least one long strip active area 101 is formed, and the active area 101 is surrounded by an isolation structure; a gate groove located in the active area 101 and the isolation structure 102 on both sides of the active area 101, the length direction of the gate groove intersects with the length direction of the active area 101, the gate groove includes a first groove located in the active area 101 and a second groove 302 located in the isolation structure 102, and the top surface of the active area 101' at the bottom of the first groove 301 is flat and the edge is smooth; a gate structure 400 located in the gate groove.

[0068] The substrate 100 is a semiconductor substrate, including single crystal silicon, polycrystalline silicon, silicon germanium, silicon on insulator, silicon carbide, etc. It can also be a composite structure such as an epitaxial semiconductor layer formed on the surface of a single crystal silicon substrate.

[0069] The substrate 100 has a plurality of active areas 101 arranged in an array, including two or more gate grooves, each of which is arranged in parallel, and each gate groove spans at least two active areas 101. The arrangement of the active area 101 can be set according to the distribution of the memory cells of the specific memory, and is not limited here.

[0070] The isolation structure 102 is a shallow trench isolation structure, including an insulating dielectric layer filled in the trench. The insulating dielectric material used in the insulating dielectric layer can be an oxide, a nitride, or an oxide and nitride layer deposited alternately stacked. In this specific embodiment, the insulating dielectric layer is silicon oxide. In other specific embodiments, the material of the insulating dielectric layer can also be silicon nitride, silicon oxynitride, silicon oxycarbide, etc. In other specific embodiments, structures such as air gaps can also be formed in the isolation structure 102 to improve the isolation performance. A pad oxide layer can also be formed between the isolation structure 102 and the substrate, and the pad oxide layer can be a silicon oxide layer formed by a thermal oxidation process.

[0071] The depth difference between the first groove 301 and the second groove 302 is less than or equal to 50nm, so as to avoid the formation of concave or convex morphology on the top of the active area 101' during the etching process of forming the gate groove, avoid charge accumulation, and thus improve the reliability of the formed transistor. The depth of the first groove 301 can be greater than or less than the depth of the second groove 302, and can be defined according to requirements. Preferably, the depth of the first groove 301 is the same as the depth of the second groove 302, so that the bottom of the gate groove is flat.

[0072] The top edge of the active area 101 ′ at the bottom of the first groove 301 has a smooth top corner, which may be in the shape of an arc, and the specific arc may be adjusted as needed.

[0073] The gate structure 400 includes: a gate dielectric layer 401 covering the inner wall of the gate groove; and a gate 402 filling the gate groove on the surface of the gate dielectric layer 401. In this specific embodiment, a first hard mask layer 201 is also formed on the surface of the substrate 100, and the gate structure 400 is flush with the first hard mask layer 201. In other specific embodiments, the gate structure 400 is flush with the surface of the substrate 100.

[0074] The top of the active area at the bottom of the gate structure of the semiconductor structure is flat, which prevents charges from gathering at the top of the active area 101', thereby effectively preventing charges from gathering in the channel area and effectively preventing the device from turning on prematurely. In addition, since the top edge of the active area is rounded, charges are prevented from gathering at the top corners of the active area, device leakage is avoided, and the effectiveness of the device is improved.

[0075] The specific embodiment of the present invention also provides a memory having the above semiconductor structure. The active region and the gate structure in the above semiconductor structure constitute a transistor, which is used as a transistor array of a storage unit of the memory.

[0076] In a specific embodiment, the memory is a DRAM memory, and further includes a capacitor array located above the semiconductor structure, each capacitor is respectively connected to a transistor in the semiconductor structure to form a storage unit.

[0077] In other specific implementations, the memory may also be other memories that need to form a transistor array.

[0078] In the above memory, no charge accumulation will occur at the top surface and top corners of the active region, so that the transistor reliability of the memory cell is high, which is beneficial to improving the performance of the memory.

[0079] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein at least one long strip active region is formed in the substrate, and the active region is surrounded by an isolation structure; Etching the active area and the isolation structures on both sides of the active area to form a gate groove, wherein the length direction of the gate groove intersects with the length direction of the active area, the gate groove comprises a first groove located in the active area and a second groove located in the isolation structure, and the top surface of the active area at the bottom of the first groove is flat and has a smooth edge; forming a gate structure in the gate groove; The depth of the first groove is smaller than the depth of the second groove, and the top angle of the top edge of the active area at the bottom of the first groove is rounded.

2. The method for forming a semiconductor structure according to claim 1, wherein: The depth difference between the first groove and the second groove is less than or equal to 50 nm.

3. The method for forming a semiconductor structure according to claim 1, wherein: The active area and the isolation structure on both sides of the active area are etched alternately using the first etching process and the second etching process to form a gate groove; the first etching process has a greater etching selectivity for the isolation structure than the active area, and the second etching process has a greater etching selectivity for the active area than the isolation structure.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: In the process of etching the active area and the isolation structures on both sides of the active area, the height difference between the etched active area and the isolation structure is controlled to be less than or equal to 50 nm.

5. The method for forming a semiconductor structure according to claim 3, wherein: The etching gas used in the first etching process includes at least carbon- and fluorine-containing gases, the RF power is 800-1600W, the bias voltage is 150-800V, and the pressure is 10-30mTorr; the etching gas used in the second etching process includes at least carbon-, fluorine-, chlorine-, and bromine-containing gases, the RF power is 800-1800W, the bias voltage is 50-300V, and the pressure is 15-40mTorr.

6. A semiconductor structure, characterized in that: include: A substrate, wherein at least one long strip active region is formed in the substrate, and the active region is surrounded by an isolation structure; A gate groove located in the active area and the isolation structure on both sides of the active area, wherein the length direction of the gate groove intersects with the length direction of the active area, the gate groove comprises a first groove located in the active area and a second groove located in the isolation structure, and the top surface of the active area at the bottom of the first groove is flat and has a smooth edge; a gate structure located in the gate groove; The depth of the first groove is less than the depth of the second groove, and the top edge of the active area at the bottom of the first groove has a rounded top angle; The substrate includes: single crystal silicon, polycrystalline silicon, silicon germanium, silicon on insulator, silicon carbide, or a single crystal silicon substrate with an epitaxial semiconductor layer formed on its surface.

7. The semiconductor structure according to claim 6, characterized in that: The depth difference between the first groove and the second groove is less than or equal to 50 nm.

8. The semiconductor structure according to claim 6, characterized in that: The gate structure comprises: a gate dielectric layer covering the inner wall of the gate groove; and a gate electrode on the surface of the gate dielectric layer that fills the gate groove.

9. The semiconductor structure according to claim 6, characterized in that: The substrate is provided with a plurality of active regions arranged in an array, including more than two gate grooves, and the gate grooves are arranged in parallel, and each gate groove spans over at least two active regions.

10. The semiconductor structure according to claim 6, characterized in that: The isolation structure is a shallow trench isolation structure.

11. A memory, characterized in that: Comprising the semiconductor structure as claimed in any one of claims 6 to 10.

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