Camera components and electronic devices

Abstract

The present technology relates to an imaging element and an electronic device capable of increasing the amount of saturation charge. The imaging element includes: a substrate; a first photoelectric conversion region, which is arranged in the substrate; a second photoelectric conversion region, which is arranged in the substrate, and the second photoelectric conversion region is adjacent to the first photoelectric conversion region; a pixel separation portion, which is arranged in the substrate and arranged between the first photoelectric conversion region and the second photoelectric conversion region; and a junction region, which is arranged in the side wall of the pixel separation portion, and the junction region has a first impurity region containing a first impurity and a second impurity region containing a second impurity. The length of the side of the first impurity region formed in the side wall of the pixel separation portion is greater than the length between the two parallel sides of the pixel separation portion, and the side of the first impurity region intersects perpendicularly with two parallel sides of the four sides of the pixel separation portion surrounding the first photoelectric conversion region. The present technology is applicable to, for example, an imaging device.

Description

Technical Field

[0001] The present technology relates to an imaging element and an electronic device, and in particular, to an imaging element and an electronic device as follows: a P-type solid diffusion layer and an N-type solid diffusion layer are formed in the side walls of an inter-pixel light-shielding wall formed between each pixel to form a strong electric field region for retaining electric charge, thereby increasing the saturation charge amount Qs of each pixel. Background Art

[0002] In the prior art, the following technology is known: in order to increase the saturation charge amount Qs in each pixel of the imaging element, a P-type diffusion layer and an N-type diffusion layer are formed in the side walls of the grooves formed between pixels to form a strong electric field region for retaining charges (for example, see patent document 1).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1]

[0006] Japanese Patent Laid-Open No. 2015-162603 Summary of the invention

[0007] [Technical issues]

[0008] However, in the structure disclosed in Patent Document 1, the pinning on the light incident side of the Si (silicon) substrate may be weakened, and the generated charge may flow into the photodiode, thereby reducing the dark characteristics. This may, for example, lead to the generation of voids and the generation of dark current. In addition, it is expected to further increase the saturation charge amount.

[0009] In view of the above circumstances, an object of the present technology is to enable suppression of degradation of dark characteristics and to increase the saturation charge amount.

[0010] [Technical solution to the problem]

[0011] An imaging element according to one aspect of the present technology includes: a substrate; a first photoelectric conversion region, which is arranged in the substrate; a second photoelectric conversion region, which is arranged in the substrate, and the second photoelectric conversion region is adjacent to the first photoelectric conversion region; a pixel separation portion, which is arranged in the substrate and arranged between the first photoelectric conversion region and the second photoelectric conversion region; and a bonding region, which is arranged in a side wall of the pixel separation portion, the bonding region having a first impurity region containing a first impurity and a second impurity region containing a second impurity, wherein the length of a side of the first impurity region formed in the side wall of the pixel separation portion is greater than the length between two parallel sides of the pixel separation portion, and the side of the first impurity region perpendicularly intersects with two parallel sides of four sides of the pixel separation portion surrounding the first photoelectric conversion region.

[0012] An electronic device according to one aspect of the present technology is an electronic device including an imaging element, the imaging element including: a substrate; a first photoelectric conversion region provided in the substrate; a second photoelectric conversion region provided in the substrate, the second photoelectric conversion region being adjacent to the first photoelectric conversion region; a pixel separation portion provided in the substrate and provided between the first photoelectric conversion region and the second photoelectric conversion region; and a junction region provided in a side wall of the pixel separation portion, the junction region having a first impurity region containing a first impurity and a second impurity region containing a second impurity. In the electronic device, the length of the side of the first impurity region formed in the side wall of the pixel separation portion is greater than the length between two parallel sides of the pixel separation portion, and the side of the first impurity region perpendicularly intersects two parallel sides of four sides of the pixel separation portion surrounding the first photoelectric conversion region.

[0013] The imaging element of the present technical aspect includes: a substrate; a first photoelectric conversion region, which is provided in the substrate; a second photoelectric conversion region, which is provided in the substrate, and the second photoelectric conversion region is adjacent to the first photoelectric conversion region; a pixel separation portion, which is provided in the substrate and provided between the first photoelectric conversion region and the second photoelectric conversion region; and a junction region, which is provided in the side wall of the pixel separation portion, the junction region having a first impurity region containing a first impurity and a second impurity region containing a second impurity. In addition, the imaging element is configured so that the length of the side of the first impurity region formed in the side wall of the pixel separation portion is greater than the length between two parallel sides of the pixel separation portion, and the side of the first impurity region perpendicularly intersects with two parallel sides of the four sides of the pixel separation portion surrounding the first photoelectric conversion region.

[0014] Note that the above-mentioned electronic device may be an independent device or an internal block constituting one device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 : is a diagram showing a configuration example of an image pickup element.

[0016] Figure 2 : is a diagram showing a configuration example of an image pickup element.

[0017] Figure 3 is a vertical cross-sectional view of assistance in explaining a first configuration example of a pixel to which the present technology is applied.

[0018] Figure 4 It is a plan view of the front side of the first embodiment of the pixel to which the present technology is applied.

[0019] Figure 5 It is the circuit diagram of a pixel.

[0020] Figure 6 A diagram is shown to assist in explaining a method of manufacturing the DTI 82 and the surrounding area.

[0021] Figure 7 is a vertical cross-sectional view showing a second configuration example of a pixel to which the present technology is applied.

[0022] Figure 8 is a vertical cross-sectional view showing a third configuration example of a pixel to which the present technology is applied.

[0023] Fig. 9 is a vertical cross-sectional view showing a fourth configuration example of a pixel to which the present technology is applied.

[0024] Fig.10 is a vertical cross-sectional view showing a fifth configuration example of a pixel to which the present technology is applied.

[0025] Fig.11 is a vertical cross-sectional view showing a sixth configuration example of a pixel to which the present technology is applied.

[0026] Fig.12 is a vertical cross-sectional view showing a seventh configuration example of a pixel to which the present technology is applied.

[0027] Fig.13 is a vertical cross-sectional view showing an eighth configuration example of a pixel to which the present technology is applied.

[0028] Fig.14 is a vertical cross-sectional view showing a ninth configuration example of a pixel to which the present technology is applied.

[0029] Fig.15 is a vertical cross-sectional view showing a tenth configuration example of a pixel to which the present technology is applied.

[0030] Fig.16 are a vertical cross-sectional view and a plan view illustrating an eleventh configuration example of a pixel to which the present technology is applied.

[0031] Fig.17 are a vertical cross-sectional view and a plan view showing a twelfth configuration example of a pixel to which the present technology is applied.

[0032] Fig.18 is a vertical cross-sectional view showing a thirteenth configuration example of a pixel to which the present technology is applied.

[0033] Fig.19 is a vertical cross-sectional view showing a fourteenth configuration example of a pixel to which the present technology is applied.

[0034] Fig. 20 is a plan view showing a configuration example of a pixel to which the present technology is applied.

[0035] Fig.21 is a plan view showing a fifteenth configuration example of a pixel to which the present technology is applied.

[0036] Fig. 22 is a plan view showing another fifteenth configuration example of a pixel to which the present technology is applied.

[0037] Fig.23 A diagram is shown to assist in explaining the dimensions of the protrusion.

[0038] Fig.24 This is a diagram to assist in explaining the manufacture of pixels to which the present technology is applied.

[0039] Fig.25 This is a diagram to assist in explaining the manufacture of pixels to which the present technology is applied.

[0040] Fig.26 A diagram to assist in explaining the shape of a groove produced by etching.

[0041] Fig. 27 It is a diagram for assisting in explaining the shape of an N-type solid phase diffusion layer produced by etching.

[0042] Fig.28 is a plan view showing a sixteenth configuration example of a pixel to which the present technology is applied.

[0043] Fig.29 A diagram to assist in explaining the shape of a groove produced by etching.

[0044] Fig.30 A diagram to assist in explaining the shape of a groove produced by etching.

[0045] Fig.31 It is a diagram for assisting in explaining the shape of an N-type solid phase diffusion layer produced by etching.

[0046] Fig.32 is a plan view showing a seventeenth configuration example of a pixel to which the present technology is applied.

[0047] Fig.33 This is a diagram to assist in explaining the manufacture of pixels to which the present technology is applied.

[0048] Fig.34 is a plan view showing an eighteenth configuration example of a pixel to which the present technology is applied.

[0049] Fig.35 A diagram to assist in explaining the shape of a groove produced by etching.

[0050] Fig.36 is a plan view showing a nineteenth configuration example of a pixel to which the present technology is applied.

[0051] Fig.37 is a plan view showing another nineteenth configuration example of a pixel to which the present technology is applied.

[0052] Fig.38 A diagram to assist in explaining the shape of a groove produced by etching.

[0053] Fig.39 is a plan view showing a twentieth configuration example of a pixel to which the present technology is applied.

[0054] Fig.40 A diagram is shown to assist in explaining the effect.

[0055] Fig.41 is a plan view showing another twentieth configuration example of a pixel to which the present technology is applied.

[0056] Fig.42 is a plan view showing a twenty-first configuration example of a pixel to which the present technology is applied.

[0057] Fig.43 is a cross-sectional view showing a twenty-first configuration example of a pixel to which the present technology is applied.

[0058] Fig.44 : is a block diagram of assistance in explaining the functional configuration of the imaging device according to the embodiment of the present disclosure.

[0059] Fig.45 It is an auxiliary explanation Fig.44 A schematic plan view of the general configuration of an imaging device is shown.

[0060] Fig.46 is shown along Fig.45 A schematic diagram of a cross-sectional structure taken along line III-III' is shown.

[0061] Fig.47 yes Fig.44 The equivalent circuit diagram of the pixel sharing unit is shown.

[0062] Fig.48 is a diagram showing an example of connection aspects of a plurality of pixel sharing units and a plurality of vertical signal lines.

[0063] Fig.49 It is shown Fig.46 A schematic cross-sectional view showing an example of a specific configuration of the imaging device shown.

[0064] Fig.50 It is shown Fig.49 A schematic diagram showing an example of a planar configuration of a main portion of the first substrate is shown.

[0065] Fig.51 It is shown Fig.50 A schematic diagram of the planar structure of the main parts and the pad part of the first substrate is shown.

[0066] Fig.52 It is shown Fig.49 Schematic diagram of an example of a planar structure of the second substrate (semiconductor layer) shown.

[0067] Fig.53 It is shown Fig.49 Schematic diagram of an example of a planar configuration of main parts of the first wiring layer, the pixel circuit, and the first substrate shown.

[0068] Fig.54 It is shown Fig.49 Schematic diagram of an example of a planar configuration of a first wiring layer and a second wiring layer shown.

[0069] Fig.55 It is shown Fig.49 Schematic diagram of an example of a planar configuration of a second wiring layer and a third wiring layer shown.

[0070] Fig.56 It is shown Fig.49 Schematic diagram of an example of a planar configuration of a third wiring layer and a fourth wiring layer shown.

[0071] Fig.57 It is an auxiliary explanation to Fig.46 A schematic diagram of the path of the input signal of the camera device is shown.

[0072] Fig.58 It is an auxiliary explanation to Fig.46 Schematic diagram of the signal path of the pixel signal of the camera device shown.

[0073] Fig.59 It is shown Fig.52 Schematic diagram of a modification of the planar structure of the second substrate (semiconductor layer) shown.

[0074] Fig.60 is a diagram showing the main part of the first wiring layer and the first substrate and Fig.59 Schematic diagram of the planar structure of the pixel circuit shown.

[0075] Fig.61 is a diagram showing the second wiring layer and Fig.60 Schematic diagram of the planar structure of the first wiring layer shown.

[0076] Fig.62 is a diagram showing the third wiring layer and Fig.61 Schematic diagram of the planar structure of the second wiring layer shown.

[0077] Fig.63 is a diagram showing the fourth wiring layer and Fig.62 Schematic diagram of the planar structure of the third wiring layer shown.

[0078] Fig.64 It is shown Fig.50 Schematic diagram of a modified example of the planar structure of the first substrate shown.

[0079] Fig.65 It is shown that the stacking Fig.64 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate shown.

[0080] Fig.66 is a diagram showing the first wiring layer and Fig.65 A schematic diagram of an example of a planar configuration of a pixel circuit is shown.

[0081] Fig.67 is a diagram showing the second wiring layer and Fig.66 Schematic diagram of an example of a planar configuration of a first wiring layer is shown.

[0082] Fig.68 is a diagram showing the third wiring layer and Fig.67 Schematic diagram of an example of a planar configuration of a second wiring layer shown.

[0083] Fig.69 is a diagram showing the fourth wiring layer and Fig.68 Schematic diagram of an example of a planar configuration of a third wiring layer shown.

[0084] Fig.70 It is shown Fig.64 FIG. 4 is a schematic diagram of another example of the planar structure of the first substrate shown.

[0085] Fig.71 It is shown that the stacking Fig.70 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate shown.

[0086] Fig.72 is a diagram showing the first wiring layer and Fig.71 A schematic diagram of an example of a planar configuration of a pixel circuit is shown.

[0087] Fig.73 is a diagram showing the second wiring layer and Fig.72 Schematic diagram of an example of a planar configuration of a first wiring layer is shown.

[0088] Fig.74 is shown as the third wiring layer and Fig.73 Schematic diagram of an example of a planar configuration of a second wiring layer shown.

[0089] Fig.75 is a diagram showing the fourth wiring layer and Fig.74 Schematic diagram of an example of a planar configuration of a third wiring layer shown.

[0090] Fig.76 It is shown Fig.46 A schematic cross-sectional view of another example of the imaging device shown.

[0091] Fig.77 It is an auxiliary explanation to Fig.76 A schematic diagram of the path of the input signal of the camera device is shown.

[0092] Fig.78 It is an auxiliary explanation to Fig.76 Schematic diagram of the signal path of the pixel signal of the camera device shown.

[0093] Fig.79 It is shown Fig.49 A schematic cross-sectional view of another example of the imaging device shown.

[0094] Fig.80 It is shown Figure 4 FIG. 1 is a diagram of another example of an equivalent circuit shown.

[0095] Fig.81 It is shown Fig.50 A schematic plan view of another example of a pixel separation portion shown in FIG.

[0096] Fig.82 : is a diagram showing an example of the overall configuration of an imaging system including the imaging apparatus according to the above-described embodiment and modified examples.

[0097] Fig.83 It is shown Fig.82 A diagram showing an example of an imaging process of the imaging system shown.

[0098] Fig.84 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0099] Fig.85 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU: camera control unit).

[0100] Fig.86 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0101] Fig.87 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0102] Hereinafter, embodiments of the present technology (hereinafter referred to as embodiments) will be described.

[0103] The present technology is applicable to an image pickup device, so the following description takes the case where the present technology is applied to an image pickup device as an example. Note that the description will continue using an image pickup device as an example, but the present technology is not limited to application to an image pickup device, and is applicable to electronic devices that use an image pickup device as an image reading section (photoelectric conversion area), for example, image pickup devices such as digital cameras and video cameras, etc.; portable terminal devices including an image pickup function, such as mobile phones; and copiers that use an image pickup device as an image reading section. Note that a modular structure (i.e., a camera module) installed in an electronic device can be regarded as an image pickup device.

[0104] Figure 1 1 is a block diagram showing a configuration example of an imaging device as an example of an electronic device of the present disclosure. Figure 1 As shown, the camera device 10 includes: an optical system including a lens group 11, etc.; an image pickup element 12; a DSP circuit 13 corresponding to a camera signal processing unit; a frame memory 14; a display unit 15; a recording unit 16; an operating system 17 and a power supply system 18, etc.

[0105] In addition, the image pickup device 10 is configured such that a DSP circuit 13, a frame memory 14, a display section 15, a recording section 16, an operation system 17, and a power supply system 18 are connected together via a bus 19. A CPU 20 controls each section in the image pickup device 10.

[0106] The lens group 11 acquires incident light (image light) from the subject and forms the light into an image on the imaging surface of the imaging element 12. The imaging element 12 converts the amount of incident light formed into an image on the imaging surface by the lens group 11 into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. As the imaging element 12, an imaging element (image sensor) including the following pixels can be used.

[0107] The display section 15 includes a panel type display section such as a liquid crystal display section or an organic EL (electro luminescence) display section, and displays a moving image or a still image captured by the imaging element 12. The recording section 16 records the moving image or the still image captured by the imaging element 12 in a recording medium such as an HDD (Hard Disk Drive) or a memory card.

[0108] The operating system 17 provides operation commands for various functions of the imaging device under user operation. The power supply system 18 appropriately supplies various power supplies used as operation power supplies for the DSP circuit 13, frame memory 14, display unit 15, recording unit 16 and operating system 17 to these power supply targets.

[0109] <Structure of Image Pickup Element>

[0110] Figure 2 2 is a block diagram showing a configuration example of the image pickup element 12. The image pickup element 12 may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0111] The imaging element 12 includes a pixel array section 41, a vertical drive section 42, a column processing section 43, a horizontal drive section 44, and a system control section 45. The pixel array section 41, the vertical drive section 42, the column processing section 43, the horizontal drive section 44, and the system control section 45 are formed on a semiconductor substrate (chip) not shown.

[0112] The pixel array section 41 includes unit pixels (eg, Figure 3 Pixel 50 in the image sensor), each unit pixel includes a photoelectric conversion element that generates a photocharge having a charge amount corresponding to the amount of incident light and stores the photocharge inside. Note that the photocharge having a charge amount corresponding to the amount of incident light will be referred to as a "charge" hereinafter, and the unit pixel may be referred to as a "pixel".

[0113] The pixel array section 41 further includes: pixel drive lines 46, which are formed for each row of the matrix pixel array along the lateral direction of the figure (the direction in which pixels are arranged in pixel rows); and vertical signal lines 47, which are formed for each column of the matrix pixel array along the up-down direction of the figure (the direction in which pixels are arranged in pixel columns). One end of each pixel drive line 46 is connected to an output end of the vertical drive section 42 corresponding to the row corresponding to the pixel drive line 46.

[0114] The imaging element 12 also includes a signal processing unit 48 and a data storage unit 49. The signal processing unit 48 and the data storage unit 49 may include processing performed by an external signal processing unit (e.g., a DSP (Digital Signal Processor) or software), which may be provided in a substrate different from the substrate on which the imaging element 12 is provided, or may be mounted on the same substrate as the substrate on which the imaging element 12 is provided.

[0115] The vertical driving section 42 includes a shift register, an address decoder, etc., and the vertical driving section 42 drives all pixels in the pixel array section 41 at the same time, or drives each pixel in a row, etc. Although a specific configuration of the vertical driving section 42 is not shown, the vertical driving section 42 includes a readout scanning system, a sweep scanning system, or batch sweep and batch transfer.

[0116] In order to read out signals from unit pixels, the readout scanning system selectively scans the unit pixels in the pixel array section 41 sequentially in units of rows. In the case of row driving (rolling shutter operation), for clearing, clearing scanning is performed on the readout row for which the readout scanning is performed by the readout scanning system at a time corresponding to the shutter speed in advance of the readout scanning. In addition, in the case of global exposure (global shutter operation), batch clearing is performed at a time corresponding to the shutter speed in advance of batch transfer.

[0117] By clearing, unnecessary charges are cleared from the photoelectric conversion element in the unit pixel of the readout row (reset). Then, by clearing unnecessary charges (resetting), a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding photocharges from the photoelectric conversion element and restarting exposure (starting accumulation of photocharges).

[0118] The signal read out by the readout operation of the readout scanning system corresponds to the amount of light that has been incident since the last readout operation or the electronic shutter operation. In the case of row driving, the photocharge accumulation period (exposure period) of the unit pixel corresponds to the time period from the readout timing of the last readout operation or the clearing timing of the last electronic shutter operation to the readout timing of the current readout operation. In the case of global exposure, the accumulation period (exposure period) corresponds to the time period from batch clearing to batch transfer.

[0119] The pixel signals output from the unit pixels in the pixel row selectively scanned by the vertical drive section 42 are fed to the column processing section 43 through the vertical signal line 47. The column processing section 43 performs predetermined signal processing on the pixel signals output from the unit pixels in the selected row through the vertical signal line 47 for each pixel column of the pixel array section 41, and temporarily holds the pixel signals subjected to the signal processing.

[0120] Specifically, the column processing section 43 performs at least noise removal processing (e.g., CDS (Correlated Double Sampling)) as signal processing. Fixed pattern noise unique to pixels, such as reset noise and threshold variation of amplifier transistors, is removed by the correlated double sampling of the column processing section 43. Note that the column processing section 43 can have, for example, an AD (Analog-Digital) conversion function in addition to the noise removal processing, and output a signal level using a digital signal.

[0121] The horizontal driving section 44 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to the respective pixel columns in the column processing section 43. Through the selective scanning of the horizontal driving section 44, the pixel signals subjected to the signal processing of the column processing section 43 are sequentially output to the signal processing section 48.

[0122] The system control section 45 includes, for example, a timing generator that generates various timing signals, and drives and controls the vertical drive section 42 , the column processing section 43 , the horizontal drive section 44 , and the like based on the various timing signals generated by the timing generator.

[0123] The signal processing section 48 includes at least an addition processing function to perform various types of signal processing such as addition processing on the pixel signal output from the column processing section 43. For the signal processing in the signal processing section 48, the data storage section 49 temporarily stores data necessary for the processing.

[0124] <Unit Pixel Structure>

[0125] Now, the specific structure of each unit pixel 50 arranged in a matrix form in the pixel array section 41 will be described. The pixel 50 described below can reduce the possibility of the following phenomenon: Figure 3 The pinning of the light incident side of the Si substrate 70 in the example is weakened, and the generated charge flows into the photodiode (in the example of FIG. Figure 3 PD 71 in the display, dark characteristics deteriorate, resulting in, for example, generation of voids or generation of dark current.

[0126] <Configuration Example of Pixel in First Embodiment>

[0127] Figure 3 is a vertical cross-sectional view of a pixel 50a in the first embodiment of the pixel 50 to which the present technology is applied, Figure 4 is a plan view of the front side of pixel 50a. Note that Figure 3 Corresponds to Figure 4 The position of the line segment X-X' in .

[0128] Hereinafter, the pixel 50 will be described taking the structure of the back-illuminated type for the pixel 50 as an example. However, the present technology can also be applied to the front-illuminated type.

[0129] Figure 3 The pixel 50a shown includes a PD (photodiode) 71, and this PD 71 serves as a photoelectric conversion element in each pixel formed inside the Si substrate 70. A P-type region 72 is formed on the light incident side of the PD 71 (in the figure, corresponding to the lower side of the back surface), and a planarization film 73 is further formed below the P-type region 72. The boundary between the P-type region 72 and the planarization film 73 corresponds to the back Si interface 75.

[0130] A light-shielding film 74 is formed in the planarization film 73. The light-shielding film 74 is provided to prevent light leakage into adjacent pixels, and the light-shielding film 74 is formed between adjacent PDs 71. The light-shielding film 74 includes a metal material such as W (tungsten), for example.

[0131] An OCL (On Chip Lens) 76 for focusing incident light on the PD 71 is formed on the planarization film 73, and thus the OCL 76 is also formed on the back surface of the Si substrate 70. The OCL 76 can include an inorganic material and can use, for example, SiN, SiO, or SiO x N y (assuming 0 < x ≤ 1 and 0 < y ≤ 1) as the inorganic material.

[0132] Although Figure 3 is not shown, the pixel can be configured such that a transparent plate such as a cover glass or resin is bonded to the OCL 76. Additionally, although Figure 3 is not shown, the pixel can be configured such that a color filter layer is formed between the OCL 76 and the planarization film 73. Additionally, the pixel can be configured such that in the color filter layer, a plurality of color filters are provided in each pixel, and the colors of the color filters are arranged, for example, according to the Bayer arrangement.

[0133] An active region (P-well) 77 is formed opposite to the light incident side of the PD 71 (in the figure, the upper side corresponding to the front surface). An element isolation region (hereinafter referred to as STI (Shallow Trench Isolation)) 78 for separating pixel transistors and the like is formed in the active region 77.

[0134] A wiring layer 79 is formed on the front side of the Si substrate 70 (in the figure, the upper side), and thus the wiring layer 79 is also formed on the active region 77, and a plurality of transistors are formed in the wiring layer 79. Figure 3An example is shown in which a transfer transistor 80 is formed in the wiring layer 79. The transfer transistor (gate) 80 includes a vertical transistor. Specifically, a vertical transistor trench 81 is formed for the transfer transistor (gate) 80, and then a transfer gate (TG) 80 for reading out the charge from the PD 71 is formed at the vertical transistor trench 81.

[0135] In addition, pixel transistors such as an amplifier (AMP) transistor, a select (SEL) transistor, and a reset (RST) transistor are formed on the front side of the Si substrate 70. Figure 4 The arrangement of transistors will be described and reference will be made to Figure 5 The circuit diagram in Figure 1 is used to illustrate the operation of the transistor.

[0136] A trench is formed between each pixel 50a, and the trench is called DTI (deep trench isolation) 82. The DTI 82 is formed between adjacent pixels 50a and is formed in a shape that penetrates the Si substrate 70 in the depth direction (in the figure, the vertical direction corresponding to the direction from the front surface to the rear surface). In addition, the DTI 82 also serves as a light shielding wall between pixels to prevent unnecessary light from leaking to adjacent pixels 50a.

[0137] Between the PD 71 and the DTI 82, a P-type solid phase diffusion layer 83 and an N-type solid phase diffusion layer 84 are sequentially formed from the DTI 82 side toward the PD 71. The P-type solid phase diffusion layer 83 is formed to extend along the DTI 82 until it contacts the back Si interface 75 of the Si substrate 70. The N-type solid phase diffusion layer 84 is formed to extend along the DTI 82 until it contacts the P-type region 72 of the Si substrate 70.

[0138] Note that the solid phase diffusion layer refers to a layer formed according to the manufacturing method described below and used to form a P-type layer and an N-type layer by impurity doping, but the present technology is not limited to the manufacturing method based on solid phase diffusion, and a P-type layer and an N-type layer produced according to another manufacturing method (e.g., ion implantation) may be respectively provided between the DTI 82 and the PD 71. In addition, the PD 71 in the embodiment includes an N-type region. Photoelectric conversion is performed in part or all of the N-type region.

[0139] The P-type solid phase diffusion layer 83 is formed to extend to contact the back Si interface 75 , while the N-type solid phase diffusion layer 84 is not in contact with the back Si interface 75 with a gap provided therebetween.

[0140] In such a configuration, the PN junction region between the P-type solid diffusion layer 83 and the N-type solid diffusion layer 84 forms a strong electric field region to hold the charge generated by the PD 71. According to the above configuration, the P-type solid diffusion layer 83 and the N-type solid diffusion layer 84 formed along the DTI 82 can form a strong electric field region to hold the charge generated by the PD 71.

[0141] If the N-type solid-phase diffusion layer 84 is formed in such a manner as to extend along the DTI 82 until it contacts the back Si interface 75 of the Si substrate 70, then in the portion where the N-type solid-phase diffusion layer 84 contacts the back Si interface 75 of the Si substrate 70 corresponding to the light incident surface side, the pinning of the charges is weakened, and the generated charges flow into the PD 71 and deteriorate the dark characteristics, thereby causing, for example, the generation of voids and the generation of dark current.

[0142] However, Figure 3 The pixel 50a shown is constructed such that the N-type solid phase diffusion layer 84 is not in contact with the back Si interface 75 of the Si substrate 70, but is in contact with the P-type region 72 of the Si substrate 70 along the DTI 82. Such a construction can prevent the pinning of charges from being weakened, and can prevent charges from flowing into the PD 71 and deteriorating the dark characteristics.

[0143] In addition, Figure 3 In the pixel 50 a shown in the figure, a sidewall film 85 containing SiO 2 is formed on the inner wall of the DTI 82 , and a filler 86 containing polysilicon is embedded inside the sidewall film 85 .

[0144] The pixel 50a in the first embodiment is constructed such that a P-type region 72 is provided on the back surface, thereby preventing the PD 71 and the N-type solid-phase diffusion layer 84 from being present near the back Si interface 75. This prevents the pinning near the back Si interface 75 from being weakened, thereby being able to prevent the generated charge from flowing into the PD 71 and deteriorating the dark characteristics.

[0145] Note that SiN may be used for the DTI 82 instead of SiO2 used for the sidewall film 85. In addition, doped polysilicon may be used instead of polysilicon used for the filler 86. In the case where the DTI 82 is filled with doped polysilicon or the DTI 82 is doped with N-type impurities or P-type impurities after being filled with polysilicon, by applying a negative bias to the DTI 82, pinning of the sidewall of the DTI 82 can be enhanced, and thus the dark characteristics can be further improved.

[0146] refer to Figure 4 and Figure 5 , the arrangement of transistors formed in pixel 50a and the operation of the transistors will be described. Figure 4 From the front (in Figure 3 , arranged in the pixel array section 41 ( Figure 2 ) The plan view of the 3×3 = 9 pixels 50a in Figure 5 is an auxiliary explanation Figure 4 The circuit diagram showing the connection relationship between the transistors shown

[0147] In Figure 4 , a rectangle represents a pixel 50a. As Figure 4 shown, the DTI 82 is formed to surround the pixel 50a (the PD 71 included in the pixel 50a). In addition, a transfer transistor (gate) 80, an FD (floating diffusion section) 91, a reset transistor 92, an amplification transistor 93, and a selection transistor 94 are formed on the front surface of the pixel 50a.

[0148] The PD 71 generates charges corresponding to the received amount of light and stores the charges (signal charges). The PD 71 includes a grounded positive terminal and a negative terminal connected to the FD 91 via a transfer transistor (gate) 80.

[0149] When the transfer transistor 80 is turned on by a transfer signal TR, the transfer transistor 80 reads out the charges generated by the PD 71 and transfers the charges to the FD 91.

[0150] The FD 91 holds the charges read out from the PD 71. When the reset transistor 92 is turned on by a reset signal RST, the charges stored in the FD 91 are discharged to the drain (constant voltage source Vdd), and the potential of the FD 91 is reset.

[0151] The amplification transistor 93 outputs a pixel signal corresponding to the potential of the FD 91. Specifically, the amplification transistor 93 and a load MOS (not shown) connected to the amplification transistor 93 via a vertical signal line 33 and serving as a constant current source together constitute a source follower circuit. The pixel signal representing the level corresponding to the charges accumulated in the FD 91 is output from the amplification transistor 93 to the column processing unit 43 via the selection transistor 94 and the vertical signal line 47 ( Figure 2 ).

[0152] When the pixel 31 is selected by a selection signal SEL, the selection transistor 94 is turned on, and the selection transistor 94 outputs the pixel signal from the pixel 31 to the column processing unit 43 via the vertical signal line 47. The signal lines for transmitting the transfer signal TR, the selection signal SEL, and the reset signal RST correspond to Figure 2 the pixel drive line 46 in

[0153] The pixel 50a can be constructed as described above. However, the pixel 50a is not limited to this construction, and other constructions can be adopted.

[0154] <Manufacturing method of DTI 82 and peripheral area>

[0155] Figure 6 It is a diagram for assisting in explaining the method of manufacturing the DTI 82 and the peripheral region.

[0156] like Figure 6 As shown in A, when DTI 82 is formed in the Si substrate 70, a hard mask containing SiN and SiO2 is used to cover the entire Si substrate 70 except for the position where DTI 82 is to be formed, and the portion not covered by the hard mask is dry etched to form a groove extending downward through the Si substrate 70 to a predetermined depth in the vertical direction.

[0157] Then, a SiO2 film containing P (phosphorus) corresponding to the N-type impurity is formed in the formed groove, and the SiO2 film is heat-treated to dope the P (phosphorus) in the SiO2 film into the Si substrate 70 (hereinafter, this doping is referred to as solid phase diffusion).

[0158] Then, if Figure 6 As shown in B, the SiO2 film including P formed in the formed groove is removed, and heat treatment is performed again to diffuse P (phosphorus) into the Si substrate 70, thereby forming an N-type solid phase diffusion layer 84 that is self-aligned with the current groove shape. Subsequently, the bottom of the groove is etched by dry etching to extend the groove in the depth direction.

[0159] Then, if Figure 6 As shown in FIG. 3 , a SiO2 film containing boron (B) corresponding to a P-type impurity is formed inside the extended trench, and then the SiO2 film is heat-treated for solid-phase diffusion, so that boron (B) diffuses from the SiO2 film toward the Si substrate 70. Thus, a P-type solid-phase diffusion layer 83 is formed that is self-aligned with the shape of the extended trench.

[0160] Subsequently, the SiO2 film containing B (boron) formed on the inner wall of the trench is removed.

[0161] Then, if Figure 6 As shown in D, a sidewall film 85 containing SiO2 is formed on the inner wall of the formed groove, and the groove is filled with polysilicon to form a DTI 82. Subsequently, pixel transistors and wiring are formed. Then, the Si substrate 70 is thinned from the back side. During the thinning process, the bottom of the DTI 82 including the P-type solid-phase diffusion layer 83 is thinned at the same time. The thinning is performed to a depth that has not yet reached the N-type solid-phase diffusion layer 84.

[0162] Through the above process, a strong electric field region including the N-type solid diffusion layer 84 not in contact with the back Si interface 75 and the P-type solid diffusion layer 83 in contact with the back Si interface 75 can be formed adjacent to the PD 71 .

[0163] <Second Embodiment>

[0164] Figure 7 is a vertical cross-sectional view of a pixel 50 b in the second embodiment to which the present technology is applied.

[0165] The second embodiment is different from the first embodiment in that a DTI 82 is formed in the STI 78, but is the same as the first embodiment in other respects. The same components of the embodiments are represented by the same reference numerals, and the description of these components is appropriately omitted. In the following description of the pixel 50, the same components as the pixel 50a in the first embodiment are represented by the same reference numerals, and the description of these components is appropriately omitted.

[0166] exist Figure 7 In the illustrated pixel 50b, the STI 78b formed in the active region 77 is formed to extend to the portion where the DTI 82b is formed (extends to the end of the pixel 50b). In addition, the DTI 82b is formed below the STI 78b.

[0167] In other words, the STI 78 b is formed at a portion where the DTI 82 b is formed, and the STI 78 b and the DTI 82 b are formed at a position where the STI 78 b and the DTI 82 b are in contact with each other.

[0168] The structure in which the STI 78b and the DTI 82b are formed at different positions (for example, the pixel 50a in the first embodiment ( Figure 3 ))Compared with FIG. 5A , this formation can make pixel 50b smaller.

[0169] In addition, the pixel 50 b in the second embodiment can also produce an effect similar to that of the pixel 50 a , that is, an effect capable of preventing deterioration of dark characteristics.

[0170] <Third Embodiment>

[0171] Figure 8 is a vertical cross-sectional view of a pixel 50 c in the third embodiment to which the present technology is applied.

[0172] The pixel in the third embodiment is different from the pixel 50a and the pixel 50b in the first and second embodiments in that a film 101 having a negative fixed charge is formed on the side wall of the DTI 82c and the inside of the film 101 is filled with SiO2 as a filler 86c.

[0173] The pixel 50a in the first embodiment is structured so that a sidewall film 85 of SiO2 is formed on the sidewall of the DTI 82 filled with polysilicon, while in the pixel 50c of the third embodiment, a film 101 having a negative fixed charge is formed on the sidewall of the DTI 82c, wherein the inside of the film 101 is filled with SiO2.

[0174] The film 101 formed on the side wall of the DTI 82c and having a negative fixed charge may include, for example, a hafnium oxide (HfO2) film, an aluminum oxide (Al2O3) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a titanium oxide (TiO2) film. The above-mentioned types of films have been successfully used as gate insulating films in insulated gate field effect transistors. Therefore, since the film formation method has been established, the film can be easily formed.

[0175] Examples of the film formation method include chemical vapor deposition, sputtering, and atomic layer deposition, and atomic layer deposition is suitable because it can simultaneously form a SiO 2 layer for reducing the interface state to a thickness of about 1 nm during film formation.

[0176] In addition, materials other than the materials listed above include: lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3) and yttrium oxide (Y2O3), etc.

[0177] Furthermore, the film 101 having a negative fixed charge may include a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film.

[0178] The film 101 having a negative fixed charge may include silicon (Si) or nitrogen (N) added to the film as long as the insulation is not impaired. The concentration of silicon or nitrogen is appropriately determined within a range that does not impair the insulation. However, in order to prevent image defects such as voids, additives such as the above-mentioned silicon and nitrogen are preferably added to the front surface of the film 101 having a negative fixed charge, that is, the surface of the film 101 opposite to the PD 71 side. As described above, by adding silicon (Si) or nitrogen (N), the heat resistance of the film and the ability to prevent ion implantation in the process can be improved.

[0179] In the third embodiment, it is possible to enhance the pinning of the trench sidewalls of the DTI 82. Therefore, for example, the pixel 50c can reliably prevent the degradation of the dark characteristic compared with the pixel 50a in the first embodiment.

[0180] In order to form the DTI 82 in the third embodiment, Figure 6 In the state shown in D of , the back side can be polished until the polysilicon as the filler 86 is exposed. Then, the filler 86 (polysilicon) and the sidewall film 85 (SiO2) inside the trench can be removed using photoresist and wet etching, the film 101 can be formed, and the trench can be filled with SiO2.

[0181] Note that, instead of SiO 2 , a metal material such as W (tungsten) may be used to fill the inside of the groove. Therefore, light transmission of incident light propagating in an oblique direction through the DTI 82 is reduced, so that color mixing can be reduced.

[0182] <Fourth Embodiment>

[0183] Fig. 9 is a vertical cross-sectional view of a pixel 50 d in a fourth embodiment to which the present technology is applied.

[0184] The fourth embodiment differs from the first embodiment in that the N-type solid diffusion layer 84 d formed along the DTI 82 has a concentration gradient in the depth direction of the Si substrate 70 , but the other aspects of the pixel in the fourth embodiment are similar to the pixel 50 a in the first embodiment.

[0185] The N-type impurity in the N-type solid phase diffusion layer 84 in the pixel 50a of the first embodiment has a constant concentration regardless of the depth direction, whereas the N-type impurity in the N-type solid phase diffusion layer 84d in the pixel 50d of the fourth embodiment has a concentration depending on the depth direction.

[0186] Specifically, the N-type solid phase diffusion layer 84d-1 near the front of the N-type solid phase diffusion layer 84d in the pixel 50d has a high concentration of N-type impurities, while the N-type solid phase diffusion layer 84d-2 near the back of the N-type solid phase diffusion layer 84d has a low concentration of N-type impurities.

[0187] The pixel 50d in the fourth embodiment can produce a new effect, in addition to the effects similar to those of the pixel 50a in the first embodiment: the concentration gradient provided in the N-type solid-phase diffusion layer 84d makes the potential on the back surface shallow, thereby making it easy to read out charges.

[0188] The concentration gradient can be provided in the N-type solid phase diffusion layer 84d as follows: For example, when forming the trench of the DTI 82, etching damage is caused to the sidewall of the trench, and thus, a change in the solid phase diffusion doping level according to the damage amount can be used to provide the concentration gradient.

[0189] Note that, instead of providing a concentration gradient in the N-type solid-phase diffusion layer 84d, the P-type solid-phase diffusion layer 83d near the front side may have a reduced P-type impurity concentration, while the P-type solid-phase diffusion layer 83d near the back side may have an increased P-type impurity concentration. Even in this case, an effect similar to that of providing a concentration gradient in the N-type solid-phase diffusion layer 84d can be produced.

[0190] In addition, each of the N-type solid-phase diffusion layer 84d and the P-type solid-phase diffusion layer 83d may be provided with respective concentration gradients.

[0191] <Fifth Embodiment>

[0192] Fig.10 is a vertical cross-sectional view of a pixel 50 e in a fifth embodiment to which the present technology is applied.

[0193] The pixel 50e in the fifth embodiment is different from the pixel 50a in the first embodiment in that the sidewall film 85e formed on the inner wall of the DTI82e and containing SiO2 is thicker than the sidewall film 85 in the pixel 50a of the first embodiment, but other aspects of the pixel 50e in the fifth embodiment are similar to the pixel 50a in the first embodiment.

[0194] Since the refractive index of SiO2 is lower than that of Si, incident light entering the Si substrate 70 is reflected according to Snell's law, thereby reducing the transmittance of light to the adjacent pixel 50. However, reducing the thickness of the sidewall film 85 may make it impossible to fully establish Snell's law, resulting in an increase in the amount of transmitted light.

[0195] Increasing the film thickness of the sidewall film 85e formed in the pixel 50e in the fifth embodiment can reduce the deviation from Snell's law, thereby increasing the reflection of the incident light at the sidewall film 85e and reducing the transmission of light to the adjacent pixel 50e. Therefore, the pixel 50e in the fifth embodiment can produce an effect that can suppress color mixing with the adjacent pixel 50e due to oblique incident light in addition to producing an effect similar to that of the pixel 50a in the first embodiment.

[0196] <Sixth Embodiment>

[0197] Fig.11 is a vertical cross-sectional view of a pixel 50 f in a sixth embodiment to which the present technology is applied.

[0198] The pixel 50f in the sixth embodiment is different from the pixel 50a in the first embodiment in that the region 111 located between the PD 71 and the back Si interface 75 is doped with P-type impurities to provide a concentration gradient so that in the Si substrate 70, the P-type impurity concentration on the back side is higher than the P-type impurity concentration on the front side, but other aspects of the pixel 50f in the sixth embodiment are similar to the pixel 50a in the first embodiment.

[0199] Return to reference Figure 3 , the pixel 50a of the first embodiment has no concentration gradient in the Si substrate 70, and the pixel 50a of the first embodiment includes a P-type region 72 located between the Si substrate 70 and the back Si interface 75. In the pixel 50f of the sixth embodiment, the Si substrate 70 is provided with a concentration gradient. The concentration gradient is such that the P-type impurity concentration on the back side (the P-type region 111 side) is higher than the P-type impurity concentration on the front side.

[0200] Compared with the pixel 50a in the first embodiment, the pixel 50f in the sixth embodiment having the concentration gradient as described above can produce an effect of being able to read out charges more easily in addition to effects similar to those of the pixel 50a in the first embodiment.

[0201] <Seventh Embodiment>

[0202] Fig.12 is a vertical cross-sectional view of a pixel 50g in the seventh embodiment to which the present technology is applied.

[0203] The difference between pixel 50g in the seventh embodiment and pixel 50a in the first embodiment is that the Si substrate 70 in pixel 50g is thicker than the Si substrate 70 in pixel 50a, and the increased thickness of the Si substrate 70 increases the depth of the DTI 82 etc. formed in pixel 50g.

[0204] In the seventh embodiment, the Si substrate 70g formed in the pixel 50g has an increased thickness. The increased thickness of the Si substrate 70g increases the area (volume) of the PD 71g and the depth of the DTI 82g. In addition, the DTI 82g is formed with an increased depth, thereby forming a P-type solid-phase diffusion layer 83g and an N-type solid-phase diffusion layer 84g with increased depth (increased area).

[0205] The areas of the P-type solid phase diffusion layer 83g and the N-type solid phase diffusion layer 84g are increased, and the area of ​​the PN junction region including the P-type solid phase diffusion layer 83g and the N-type solid phase diffusion layer 84g is increased. Therefore, compared with the pixel 50a in the first embodiment, the pixel 50g in the seventh embodiment can further increase the saturation charge amount Qs in addition to producing an effect similar to that of the pixel 50a in the first embodiment.

[0206] <Eighth Embodiment>

[0207] Fig.13 is a vertical cross-sectional view of a pixel 50h in the eighth embodiment to which the present technology is applied.

[0208] In the pixel 50h of the eighth embodiment, Fig.12 Like the pixel 50g of the seventh embodiment shown, the Si substrate 70g has an extended length in the depth direction.

[0209] In pixel 50g, P-type region 121-1, N-type region 122, and P-type region 121-2 are formed by ion implantation on the back surface of PD 71. The PN junction defined by P-type region 121-1, N-type region 122, and P-type region 122-2 is subjected to a strong electric field and can therefore hold charges.

[0210] Therefore, the pixel 50h in the eighth embodiment can further increase the saturation charge amount Qs in addition to producing the same effects as those of the pixel 50g in the seventh embodiment.

[0211] <Ninth Embodiment>

[0212] Fig.14 is a vertical cross-sectional view of a pixel 50i in a ninth embodiment to which the present technology is applied.

[0213] The pixel 50i in the ninth embodiment is different from the pixel 50a in the first embodiment in that a MOS capacitor 131 and a pixel transistor (not shown) are formed on the front side of the Si substrate 70, but other aspects of the pixel 50i in the ninth embodiment are similar to the pixel 50a in the first embodiment.

[0214] Generally, even if the saturation charge amount Qs of the PD 71 increases, unless the conversion efficiency decreases, the vertical signal line VSL ( Figure 2 The amplitude limitation of the vertical signal line 47 shown will also limit the output, making it difficult to fully utilize the increased saturation charge amount Qs.

[0215] To reduce the conversion efficiency of PD 71, it is necessary to reduce the conversion efficiency of FD 91 ( Figure 4 ) added capacitance. Therefore, the pixel 50i in the ninth embodiment is configured to add the MOS capacitor 131 as a capacitance to be added to the FD 91 ( Fig.11 not shown).

[0216] The pixel 50i in the ninth embodiment can not only be configured to produce effects similar to those of the pixel 50a in the first embodiment, but can also reduce the conversion efficiency of the PD 71 by adding a MOS capacitor 131 to the FD 91, thereby making full use of the increased saturation charge amount Qs.

[0217] <Tenth Embodiment>

[0218] Fig.15 is a vertical cross-sectional view of a pixel 50j in a tenth embodiment to which the present technology is applied.

[0219] The pixel 50j in the tenth embodiment is different from the pixel 50a in the first embodiment in that two contacts 152 are formed on the well contact portion 151 formed in the active area 77, and the contacts 152 are connected to the Cu wiring 153, but other aspects of the pixel 50j in the tenth embodiment are similar to the pixel 50a in the first embodiment.

[0220] As described above, it is possible to provide a structure including the well contact portion 151. Note that although Fig.15 An example is shown in which two contacts 152 are formed, but more than two contacts 152 may be formed on the well contact 151 .

[0221] The pixel 50j in the tenth embodiment can improve the yield of severe defects in addition to producing effects similar to those of the pixel 50a in the first embodiment.

[0222] <Eleventh Embodiment>

[0223] Fig.16 A vertical cross-sectional view and a plan view of a pixel 50 k in an eleventh embodiment to which the present technology is applied are shown.

[0224] The pixel 50k in the eleventh embodiment differs from the pixel 50a in the first embodiment in that a vertical transistor trench 81k is formed in the center of the pixel 50k to form a transfer transistor (gate) 80k, but other aspects of the pixel 50k in the eleventh embodiment are similar to the pixel 50a in the first embodiment.

[0225] Fig.16 The pixel 50k shown is formed so that the transfer transistor (gate) 80k is located equidistant from each periphery of the PD 71. Therefore, in addition to producing an effect similar to that of the pixel 50a in the first embodiment, the pixel 50k in the eleventh embodiment includes a transfer transistor (gate) equidistant from each periphery of the PD 71, thereby enabling improved transfer of charge.

[0226] <Twelfth Embodiment>

[0227] Fig.17 A vertical cross-sectional view and a plan view of a pixel 50 m in a twelfth embodiment to which the present technology is applied are shown.

[0228] The pixel 50m in the twelfth embodiment is different from the pixel 50a in the first embodiment in that the transfer transistor 80m includes two vertical transistor trenches 81-1 and 81-2, but the other aspects of the pixel 50m in the twelfth embodiment are similar to the pixel 50a in the first embodiment.

[0229] The pixel 50a ( Figure 3 ) is constructed so that the transfer transistor 80 includes one vertical transistor trench 81, while in the pixel 50m of the twelfth embodiment, the transfer transistor 80m includes two vertical transistor trenches 81-1 and 81-2.

[0230] The configuration having two vertical transistor trenches 81-1 and 81-2 as described above improves the followability of the potential of the region sandwiched between the two vertical transistor trenches 81-1 and 81-2 observed when the potential of the transfer transistor 80k changes. Therefore, the modulation factor can be increased. As a result, the charge transfer efficiency can be improved.

[0231] In addition, effects similar to those of the pixel 50 a in the first embodiment are obtained.

[0232] Note that although the transfer transistor 80 k including two vertical transistor trenches 81 - 1 and 81 - 2 is described as an example, more than two vertical transistor trenches 81 may be formed in each pixel region.

[0233] In addition, in the example shown, the two vertical transistor trenches 81-1 and 81-2 are formed to have the same size (length and thickness). However, in the case of forming a plurality of vertical transistor trenches 81, the sizes of the vertical transistor trenches 81 formed may be different from each other. For example, the two vertical transistor trenches 81-1 and 81-2 may be formed so that one of the vertical transistor trenches 81-1 and 81-2 is longer or thicker than the other.

[0234] <Thirteenth Embodiment>

[0235] Fig.18 is a vertical cross-sectional view of a pixel 50n in a thirteenth embodiment to which the present technology is applied.

[0236] The pixel 50 n in the thirteenth embodiment is different from the pixel 50 a in the first embodiment in the configuration of the light shielding film 74 , but is similar to the pixel 50 a in other respects.

[0237] In the pixel 50n of the thirteenth embodiment, a light shielding film 74n-1 and a light shielding film 74n-2 are formed above and below the DTI 82n, respectively. Figure 3), the light shielding film 74 is formed on the back side (on the lower side of the figure) of the DTI 82 and covers the back side. However, in the pixel 50n ( Fig.18 ), the interior of the DTI 82n is filled with the same metal material (eg, tungsten) as the light shielding film 74, and the front side (on the upper side in the figure) of the Si substrate 70 is also covered with the metal material.

[0238] In other words, the pixel 50n is constructed so that each pixel area except the back side (except the light incident side) is surrounded by a metal material. However, in the case where the pixel 50n is constructed so that the entire pixel 50n except the back side is surrounded by a metal material, an opening portion is appropriately formed at a desired position, for example, a portion of the light shielding film 74n-2 where the transfer transistor 80n is located is opened, and a terminal for connecting to the outside is formed in the opening.

[0239] Note that a metal material other than tungsten (W) may be used for the light shielding film 74 or the like.

[0240] The pixel 50n in the thirteenth embodiment can prevent incident light from leaking to the adjacent pixel 50n, thereby preventing color mixing.

[0241] In addition, the pixel 50n can be constructed so that light that reaches the front side without undergoing photoelectric conversion after being incident from the back side is reflected on the metal material (light shielding film 74n-2) and is incident again on the PD 71. Therefore, the pixel 50n in the thirteenth embodiment can improve the sensitivity of the PD 71 in addition to producing the same effect as the pixel 50a in the first embodiment.

[0242] <Fourteenth Embodiment>

[0243] Fig.19 is a vertical cross-sectional view of a pixel 50 p in a fourteenth embodiment to which the present technology is applied.

[0244] The pixel 50p in the fourteenth embodiment is different from the pixel 50a in the first embodiment in the shapes of the P-type solid-phase diffusion layer 83p and the side wall film 85p formed on the back surface, but is similar to the pixel 50a in the first embodiment in other respects.

[0245] The P-type solid phase diffusion layer 83p on the back side of the pixel 50p is formed in a shape protruding toward the area below the N-type solid phase diffusion layer 84p. The pixel 50p includes a P-type solid phase diffusion layer 83p formed at the end of the P-type region 72p and formed in a shape protruding into the P-type region 72p. In addition, the side wall film 85p formed in the P-type solid phase diffusion layer 83p is also formed in a shape protruding toward the P-type region 72p. In addition, the filler 86p formed in the side wall film 85p is formed in a shape protruding toward the P-type region 72p.

[0246] The above shape provides a configuration that more reliably prevents the N-type solid phase diffusion layer 84p from contacting the back Si interface 75 of the Si substrate 70. Therefore, it is possible to prevent the pinning of charges from being weakened, and prevent the charges from flowing into the PD 71 to deteriorate the dark characteristics.

[0247] When the N-type solid phase diffusion layer 84p is formed, the depth or concentration of the N-type solid phase diffusion layer 84p may vary. For example, it may vary so that the N-type solid phase diffusion layer 84 formed in the A pixel 50 is deeper than the N-type solid phase diffusion layer 84 formed in the B pixel 50. In this case, the deeper N-type solid phase diffusion layer 84 may extend through the P-type region 72 or penetrate the P-type region 72 and reach the back Si interface 75 of the Si substrate 70.

[0248] In addition, a change may occur such that the concentration of the N-type impurity in the N-type solid diffusion layer 84 formed in the A pixel 50 is higher than the concentration of the N-type impurity in the N-type solid diffusion layer 84 formed in the B pixel 50. In this case, the N-type solid diffusion layer 84 having the higher concentration may extend through the P-type region 72 or penetrate the P-type region 72 and reach the back Si interface 75 of the Si substrate 70.

[0249] In the pixel 50p, on the back Si interface 75 side of the N-type solid phase diffusion layer 84p, not only the P-type region 72p is formed in a shape protruding toward the region below the N-type solid phase diffusion layer 84p, but also the P-type solid phase diffusion layer 83p is formed in a shape protruding toward the region below the N-type solid phase diffusion layer 84p. Therefore, as described above, as long as the depth or concentration of the N-type solid phase diffusion layer 84 is changed, the change can be absorbed, and the P-type solid phase diffusion layer 83p can reliably prevent the N-type solid phase diffusion layer 84p from contacting the back Si interface 75 of the Si substrate 70.

[0250] The pixel 50 p in the fourteenth embodiment can produce effects similar to those of the pixel 50 a in the first embodiment.

[0251] <Shape of the Strong Electric Field Region>

[0252] The pixel 50 in the first to fourteenth embodiments is formed to be surrounded by the DTI 82 in a plan view, for example, as shown in FIG. Fig. 20 As shown. On the sidewall of the DTI 82, a PN junction region including a P-type solid diffusion layer 83 and an N-type solid diffusion layer 84 is formed to provide a strong electric field region. Note that the above description and the following description include a configuration in which a depletion layer exists between the P-type solid diffusion layer 83 and the N-type solid diffusion layer 84 and a configuration in which the PN junction region includes only the P-type solid diffusion layer 83 and the N-type solid diffusion layer 84.

[0253] like Fig. 20As shown, the PD 71 is surrounded by an N-type solid phase diffusion layer 84 . The N-type solid phase diffusion layer 84 is surrounded by a P-type solid phase diffusion layer 83 . Furthermore, the P-type solid phase diffusion layer 83 is surrounded by a DTI 82 .

[0254] As described above, since the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84 form a PN junction region, a strong electric field region is formed around the PD 71. Therefore, the saturation charge amount can be increased. Fig. 20 As shown, a description will be given of the shape of a PN junction region in a plan view that further increases the saturation charge amount Qs compared to a linearly shaped PN junction region.

[0255] The shapes of the strong electric field regions will be described below in fifteenth to nineteenth embodiments, and any of the fifteenth to nineteenth embodiments can be combined with any of the first to fourteenth embodiments described above.

[0256] In addition, the above description and the following description take the PN junction region including the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 arranged in sequence from the DTI 82 side toward the PD 71 side as an example. However, depending on the configuration of the PD 71, the PN junction region may include the N-type solid-phase diffusion layer 84 and the P-type solid-phase diffusion layer 83 arranged in sequence from the DTI 82 side toward the PD 71 side. The present technology is applicable to the case where the PN junction region provided in the sidewall of the DTI 82 has a first impurity region including a first impurity and a second impurity region including a second impurity, and the first impurity is an N-type impurity and the second impurity is a P-type impurity, or the first impurity is a P-type impurity and the second impurity is an N-type impurity.

[0257] In addition, the P type and N type described above and below represent the function of P type or N type with respect to a predetermined material. The description here takes the pixel using the Si substrate 70 as an example, so the following description takes the following structure as an example, in which the impurity that functions as P type with respect to Si (silicon) is regarded as a P type impurity, and the impurity that functions as N type with respect to Si (silicon) is regarded as an N type impurity.

[0258] <Fifteenth Embodiment>

[0259] Fig.21 : is a horizontal cross-sectional view (plan view) of a pixel 50q in a fifteenth embodiment to which the present technology is applied.

[0260] The shape of the pixel 50q in the fifteenth embodiment is such that the strong electric field region surrounding the PD 71q includes a concave portion and a convex portion. Fig.21 In the illustrated pixel 50q, when attention is paid to the PD 71q-1 included in the pixel 50q, the DTI 82q corresponding to the side surface surrounding the PD 71q-1 is formed in a shape having a protrusion (a recess).

[0261] The description will be continued with the protruding portion. However, whether the portion is protruding or recessed relative to the side used as a reference depends on which side is used as a reference. Here, by placing a portion of the DTI 82q having a linear shape and formed continuously (at Fig. 20 In the description, a portion referred to as DTI 82q is defined as a reference and a portion protruding relative to DTI 82q defined as a reference is referred to as a protrusion, and the description is continued.

[0262] According to the shape of DTI 82q, P-type solid-phase diffusion layer 83q is formed to include a protrusion. In addition, according to the shape of P-type solid-phase diffusion layer 83q, N-type solid-phase diffusion layer 84q is also formed to include a protrusion (the protrusion of P-type solid-phase diffusion layer 83q corresponds to the recessed portion of N-type solid-phase diffusion layer 84q).

[0263] The P-type solid phase diffusion layer 83q is provided with a protrusion, so that the area where the P-type solid phase diffusion layer 83q contacts the N-type solid phase diffusion layer 84q can be increased. Therefore, the PN junction region including the P-type solid phase diffusion layer 83q and the N-type solid phase diffusion layer 84q is expanded, thereby expanding the strong electric field region. The expanded strong electric field region increases the amount of charge that can be maintained in the strong electric field region, thereby increasing the saturation charge amount.

[0264] exist Fig.21 In the pixel 50q shown, for example, the DTI 82q-1 included in the four sides surrounding the PD 71q-1 and formed on the left side of the PD 71q-1 is provided with three protrusions. The number of protrusions is exemplary, and it is sufficient as long as more than one protrusion is formed. In addition, instead of a rectangle, other shapes can be used. Other shapes may be a triangle as described in the sixteenth embodiment below.

[0265] in addition, Fig.21 The pixel 50q shown is an example in which three protrusions are provided on each of the four sides surrounding the PD 71q-1. However, at least one of the four sides may be provided with a protrusion. Fig. 22 As shown in the illustrated pixel 50q, one of the four sides surrounding the PD 71q may be provided with a protrusion.

[0266] exist Fig. 22In the pixel 50q shown, when the PD 71q-1 included in the pixel 50q is focused, a protrusion is formed on the DTI 82q-1 on the left side, and no protrusion is formed on the DTI 82q-2 on the right side, the DTI 82q-11 on the upper side, and the DTI 82q-12 on the lower side. As described above, it is possible to provide a configuration in which a protrusion is formed on one of the four sides surrounding the PD 71q and a strong electric field region larger than other strong electric field regions is formed.

[0267] In addition, although not shown, a configuration may be provided in which protrusions are provided on two or three of the four sides.

[0268] By providing a protrusion, the strong electric field region can be expanded. However, the light receiving area of ​​PD 71q may be reduced. The size of the protrusion can be set in association with the size of PD 71q. In addition, as described above, the size of the protrusion can be adjusted by setting the side on which the protrusion is provided (how many sides are provided with the protrusion among one to four sides). In addition, the size of the strong electric field region can also be adjusted by adjusting the size of the protrusion itself.

[0269] refer to Fig.23 , the dimensions of the protrusion will be described. Fig.23 , taking one side of the PD 71 as an example for explanation. Fig.23 In the figure, A shows Fig. 20 One side of the structure shown without forming a protrusion. Fig.23 In the figure, B shows the Fig.21 or Fig. 22 One side of the protrusion structure shown. Note that Fig.23 The description does not take into account the thickness of the layer.

[0270] refer to Fig.23 In the case where the protrusion is not formed, the DTI 82 is in a linear shape, and the P-type solid-phase diffusion layer 83 is formed along the DTI 82. Therefore, the P-type solid-phase diffusion layer 83 is also in a linear shape. The P-type solid-phase diffusion layer 83 has a length L1. The length L1 corresponds to the distance between the upper side and the lower side of the DTI 82 formed around the PD 71.

[0271] refer to Fig.23 B is described by taking a structure having a protruding portion as an example. Fig.23 B is described by taking a structure in which a protrusion is formed on one side as an example. Fig.23 In B, the DTI 82q is formed to include one protrusion on a straight line, and a P-type solid-phase diffusion layer 83q is formed along the DTI 82q. Therefore, the P-type solid-phase diffusion layer 83q is also formed to include a combination of a straight line and one protrusion.

[0272] The portion of the P-type solid-phase diffusion layer 83q corresponding to the height of the protrusion has a length L2. The length L2 corresponds to the length from the linear shape portion of the P-type solid-phase diffusion layer 83q to the end portion of the protrusion. Fig.23 As shown in B, the length of the P-type solid-phase diffusion layer 83q having the protrusion is (L1+2×L2).

[0273] In the case of comparing a structure in which the P-type solid phase diffusion layer 83 is provided with no protrusion and a structure in which the P-type solid phase diffusion layer 83 is provided with one protrusion, the length of the P-type solid phase diffusion layer 83 is increased by (2×L2) by providing one protrusion. The length of the P-type solid phase diffusion layer 83 is equal to the length of the P-type solid phase diffusion layer 83 and the length of the N-type solid phase diffusion layer 84q ( Fig.23 Therefore, by providing a protrusion, the portion of the P-type solid phase diffusion layer 83 in contact with the N-type solid phase diffusion layer 84 is increased by (2×L2), thereby increasing the PN junction area and being able to expand the strong electric field region.

[0274] By providing a plurality of protrusions, the junction region between the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 can be expanded, and thus the strong electric field region can be expanded.

[0275] The length L2 of the protrusion can be set to, for example, 10 nm or more, although the length L2 can be changed according to the size of the pixel 50q. In addition, in the case where the length L1 of the P-type solid-phase diffusion layer 83 without the protrusion is 1, the length L3 of the P-type solid-phase diffusion layer 83 with the protrusion is set to a predetermined value or, for example, greater than or equal to 1.3 times. The length L3 can be adjusted by the length L2 of one protrusion or the number of protrusions.

[0276] When the length L3 of the P-type solid-phase diffusion layer 83q is greater than the length between two parallel sides (e.g., the upper side and the lower side of the DTI 82) of the four sides surrounding the PD 71q, as described above, the PN junction area can be increased, thereby expanding the strong electric field region. Since the P-type solid-phase diffusion layer 83q is formed along the DTI 82q, the length L3 of the P-type solid-phase diffusion layer 83q depends on the length of the side wall of the DTI 82q. Therefore, the DTI 82q is formed so that the length of the side wall of the DTI 82q is greater than the length between the parallel arrangement parts of the DTI 82q surrounding the PD 71q, thereby increasing the PN junction area and expanding the strong electric field region.

[0277] The protrusion thus formed on the P type solid phase diffusion layer 83 enables the bonding area between the P type solid phase diffusion layer 83 and the N type solid phase diffusion layer 84 to be increased, thereby enabling the saturation charge amount to be increased.

[0278] refer to Fig.24 and Fig.25 , a method for manufacturing a strong electric field region in the case where a protrusion is formed as described above will be described. Fig.21 The description will continue with the structure in which each of the four sides surrounding the PD 71 includes a protrusion as an example.

[0279] In step S51( Fig.24 ), a substrate in which DTI 82 is formed is prepared. In this substrate, a silicon oxide film 200 is formed, and an insulating film (insulating material) 201 is embedded in a pre-formed groove. As the silicon oxide film 200, LP-TEOS is deposited, for example.

[0280] In step S52, a portion of the silicon oxide film 200, a portion of the insulating film 201, a portion of the SiN, and a portion of the Si substrate 70 are dug out by dry etching. In step S52, a deep trench is formed. Fig.26 As shown, the shape of the deep trench in a planar shape is, for example, a combination of a lattice shape and a protrusion, and the depth of the deep trench reaches the lower end of a region where an N-type region will be formed by solid phase diffusion in a subsequent step.

[0281] In step S53, a silicon oxide film (PSG) 202 containing phosphorus (P) is deposited on the entire surface of the wafer using an atomic layer deposition (ALD) method. Through the process in step S53, the PSG film 202 is formed on the front surface of the wafer where no deep trenches are formed, the side surfaces of the deep trenches, and the bottom surface of the deep trenches. Here, the PSG film 202 is formed as an N-type film using phosphorus (P).

[0282] In step S54, a thermal diffusion process is performed. In step S54, the wafer is annealed to cause solid phase diffusion in the region where the PSG film 202 contacts the Si substrate 70, and phosphorus (P) is diffused from the PSG film 202 to the Si substrate 70. As a result, Fig.24 As shown in step S54 in FIG. 8 , an N-type impurity region 203 is formed. The N-type impurity region 203 is a region corresponding to the N-type solid-phase diffusion layer 84q.

[0283] In step S55, the PSG film 202 on the wafer is removed. The removal of the PSG film 202 is performed by, for example, wet etching using hydrofluoric acid.

[0284] In step S56, the silicon on the bottom surface of the deep trench in the wafer is dug deeper by dry etching. Fig.26 The lattice string portion and the groove portion of the protrusion shown are both dug deeper. Fig. 27As shown, a region corresponding to the N-type solid-phase diffusion layer 84q has been formed. Fig. 27 The illustrated N-type solid-phase diffusion layer 84 q has a substantially linear shape on the PD 71 side.

[0285] In step S54, when phosphorus is diffused into the Si substrate 70, according to the shape and number of the protruding portions of the trench (DTI 82q), as shown in FIG. Fig. 27 As shown, the diffusion is performed to the extent that the PD 71 side has a substantially linear shape. The N-type solid-phase diffusion layer 84q does not need to be formed in the same shape as the groove. The N-type solid-phase diffusion layer 84q may be as follows: Fig. 27 The shape shown or Fig.21 The shapes shown are both within the scope of the present technology. Either shape will produce the same effect.

[0286] In step S57 ( Fig.25 ), a silicon oxide film (BSG) 205 containing boron (B) is deposited using an atomic layer deposition (ALD: Atomic Layer Deposition) method. Through the process in step S57, the BSG film 205 is formed on the front surface of the wafer where no deep trench is formed, the side surface of the deep trench, and the bottom surface of the deep trench. Here, the BSG film 205 is formed as a P-type film using boron (B).

[0287] In step S58, a thermal diffusion process is performed. In step S58, the wafer is annealed to cause solid phase diffusion in the region where the BSG film 205 contacts the Si substrate 70, and to diffuse boron (B) from the BSG film 205 to the Si substrate 70. As a result, Fig.25 As shown in step S58 in the above, a P-type impurity region 206 is formed. The P-type impurity region 206 is connected to the P-type solid phase diffusion layer 83q ( Fig.21 ) corresponding to the area.

[0288] In step S59, the BSG film 205 is removed. The removal of the BSG film 205 is performed by, for example, wet etching using hydrofluoric acid.

[0289] In step S60, polysilicon is embedded in the groove as filler 86p, and unnecessary polysilicon deposited on the upper surface of the wafer is removed. In addition, pixel transistors and wiring are formed. Subsequently, the Si substrate 70 is thinned from the back. The thinning is performed until the bottom of the deep groove is exposed.

[0290] This formed the Fig.21 or Fig. 22 The P-type solid-phase diffusion layer 83q having a protrusion is shown, thereby forming a pixel 50q having an expanded strong electric field region.

[0291] <Sixteenth Embodiment>

[0292] Fig.28 is a plan view of a pixel 50r in a sixteenth embodiment to which the present technology is applied.

[0293] The shape of the pixel 50 r in the sixteenth embodiment is such that a strong electric field region surrounding the PD 71 r includes a protruding portion and a depressed portion as in the case of the pixel 50 q in the fifteenth embodiment. Fig.28 The pixel 50r shown is Fig.21 The pixel 50q shown is different in that the protrusion of the pixel 50r is triangular, but the other aspects of the pixel 50r are basically similar to the pixel 50q. Therefore, repeated description is omitted.

[0294] for Fig.28 The pixel 50r shown shows an example in which protrusions are formed on two of the four sides surrounding the PD 71. The pixel 50r can be configured such that a protrusion is formed on at least one of the four sides surrounding the PD 71, or a protrusion is formed on one, two, three, or four of the four sides.

[0295] for Fig.28 The pixel 50r shown shows an example in which, for example, two triangular protrusions are formed on the side of the DTI 82r-1 that is included in the four sides surrounding the PD 71r-1 and formed on the left side of the PD 71r-1. The number of protrusions is exemplary, and it is sufficient as long as the number is greater than 1. In addition, the shape of the protrusion may be such that the protrusion is triangular; or includes a circular vertex; or the sides constituting the triangle are curved lines instead of straight lines. Alternatively, the protrusion may have a shape close to a semicircle or an ellipse instead of a triangle, or the protrusion may be polygonal.

[0296] When a triangular protrusion is formed, although the height of the protrusion depends on the size of the pixel 50q, the height can be set to, for example, 10 nm or more. Fig.23 As described above, the length of the P-type solid phase diffusion layer 83r provided with the protrusion is set to be at least a predetermined value multiple, for example, at least 1.3 times the length of the P-type solid phase diffusion layer 83 without the protrusion. The length can be adjusted based on the height of one protrusion or the number of protrusions.

[0297] Similar to the pixel 50q in the fifteenth embodiment, the pixel 50r in the sixteenth embodiment can be formed such that the length of the P-type solid-phase diffusion layer 83q is greater than the length between two parallel-arranged sides of the four sides surrounding the PD 71q. Therefore, the PN junction area can be increased and the strong electric field region can be expanded. In other words, when the DTI 82r is formed so that the length of the side wall of the DTI 82r is greater than the length between the parallel-arranged portions of the DTI 82r surrounding the PD 71r, the PN junction area can be increased and the strong electric field region can be expanded.

[0298] A manner of manufacturing a strong electric field region in the case where the protrusions as described above are formed will be described. Fig.28 The pixel 50r shown is manufactured in the same manner as Fig.21 The manufacturing method of the pixel 50q shown in FIG. Fig.24 and Fig.25 The manufacturing method described is substantially similar. Therefore, the description of the similar parts is omitted, and the different parts will be described.

[0299] When a triangular protrusion is formed as in the case of the pixel 50r, the manufacturing steps of the pixel 50r are the same as those of the pixel 50q ( Fig.21 ) is different from the manufacturing steps of S52 ( Fig.24 ) is divided into two steps.

[0300] First, in step S52-1, a portion of the silicon oxide film 200, a portion of the insulating film 201, a portion of the SiN, and a portion of the Si substrate 70 are dug out by dry etching. Step S52 forms a deep trench. In the planar shape, as shown in FIG. Fig.29 As shown, the deep trench is, for example, a combination of a lattice shape and a protrusion, and the depth of the deep trench reaches the lower end of a region where an N-type region will be formed by solid phase diffusion in a subsequent step.

[0301] In step S52-2, a portion of the silicon oxide film 200, a portion of the insulating film 201, a portion of the SiN, and a portion of the Si substrate 70 are further dug out by wet etching. Specifically, wet etching is performed so that the shape of the protrusion on the crystal plane is uniform. Fig.30 As shown, the deep trench includes, for example, a protrusion shaped like a triangle, and the depth of the deep trench reaches the lower end of a region where an N-type region will be formed by solid phase diffusion in a subsequent step.

[0302] The combination of dry etching and wet etching as described above forms the desired shape, in this case, a deep trench with a triangular protrusion. Fig.24 and Fig.25The subsequent steps of forming the region corresponding to the N-type solid-phase diffusion layer 84r and the region corresponding to the P-type solid-phase diffusion layer 83r are similarly performed as described in the corresponding steps.

[0303] Fig.31 FIG. 5 shows the structure of the pixel 50r obtained by further digging out the silicon on the bottom surface of the deep trench by dry etching in step S56. Fig.30 The lattice string portion and the groove portion of the triangular protrusion shown are both dug deeper. Fig.31 As shown, a region corresponding to the N-type solid-phase diffusion layer 84r has been formed.

[0304] In step S54, when phosphorus diffuses into the Si substrate 70, as shown in FIG. Fig.31 As shown, according to the shape and number of the protruding portions of the trench (DTI 82r), an N-type solid phase diffusion layer 84r having a shape substantially the same as that of the trench is formed. Fig. 27 As described, depending on the shape and number of the protruding portions of the groove, diffusion may proceed to such an extent that the PD 71 side has a substantially linear shape instead of a groove shape.

[0305] Therefore, the N-type solid-phase diffusion layer 84r does not have to be formed in the same shape as the trench. The shape of the N-type solid-phase diffusion layer 84r may or may not be equal to the shape of the trench, and both shapes are within the scope of the present technology.

[0306] This formed the Fig.28 The P-type solid-phase diffusion layer 83r shown has a triangular protrusion, thereby forming a pixel 50r with an expanded strong electric field area.

[0307] <Seventeenth Embodiment>

[0308] Fig.32 is a plan view of a pixel 50 s in the seventeenth embodiment to which the present technology is applied.

[0309] The shape of the pixel 50 s in the seventeenth embodiment is formed such that the strong electric field region surrounding the PD 71 r includes concave portions and convex portions as in the case of the pixel 50 q in the fifteenth embodiment. Fig.32 The pixel 50s shown is different from the pixel 50q in that minute concave and convex portions are formed.

[0310] refer to Fig.32 , in the structural plan view of pixel 50s, as Fig. 20 As shown in the structural plan view of the pixel 50, the PD 71s is formed so as to be surrounded by the DTI 82s, and a PN junction region including a P-type solid-phase diffusion layer 83s and an N-type solid-phase diffusion layer 84s is formed in the side wall of the DTI 82s.

[0311] The enlarged view of the portion including the DTI 82s is shown in FIG. Fig.32 As shown in the figure on the right. Fig.32 , the side of the PD 71s-1 of the DTI 82s-1 is formed to include convex portions and concave portions. As in the case of the shape of the DTI 82s-1 including convex portions and concave portions, the side of the DTI 82s-1 and the side of the PD 71s-1 of the P-type solid phase diffusion layer 83s-1 are formed to include convex portions and concave portions. In addition, as in the case of the shape of the P-type solid phase diffusion layer 83s-1 including convex portions and concave portions, the side of the P-type solid phase diffusion layer 83s-1 of the N-type solid phase diffusion layer 84s-1 is formed to include convex portions and concave portions.

[0312] By forming the P-type solid phase diffusion layer 83s to include tiny protrusions and recesses, the bonding area where the P-type solid phase diffusion layer 83s and the N-type solid phase diffusion layer 84s contact each other can be increased. Therefore, the strong electric field region including the P-type solid phase diffusion layer 83s and the N-type solid phase diffusion layer 84s can be expanded, thereby increasing the saturation charge amount.

[0313] Similar to the pixel 50q in the fifteenth embodiment, the pixel 50s in the seventeenth embodiment can be formed such that the length of the P-type solid-phase diffusion layer 83s is greater than the length between two parallel-arranged sides of the four sides surrounding the PD 71s, thereby increasing the PN junction area and expanding the strong electric field region. In other words, the DTI 82s is formed such that the length of the side wall of the DTI 82s is greater than the length between the parallel-arranged portions of the DTI 82s surrounding the PD 71s, thereby increasing the PN junction area and expanding the strong electric field region.

[0314] A method of manufacturing a strong electric field region while forming minute recesses and projections as described above will be described. Fig.32 The manufacturing method of the pixel 50s shown in FIG. Fig.21 The manufacturing method of the pixel 50q shown in FIG. 5 is the same as that of the pixel 50q shown in FIG. Fig.24 ) to step S56, the manufacturing process of the pixel 50s similarly includes executing the steps from the beginning to forming a region corresponding to the N-type solid-phase diffusion layer 84s in the side wall of the deep trench.

[0315] refer to Fig.33 , the process after forming the region corresponding to the N type solid phase diffusion layer 84s in the side wall of the deep trench will be described.

[0316] A method of forming concave and convex portions on the front surface of polysilicon to increase the surface area has been proposed. Considering the state of the front surface, the polysilicon obtained in this case can be called rough polysilicon. Here, a configuration in which rough polysilicon is formed to form a concave-convex shape on DTI 82s, thereby also forming a concave-convex shape on P-type solid-phase diffusion layer 83s and N-type solid-phase diffusion layer 84s is described as an example.

[0317] In step S101( Fig.33 ), in the Si substrate 70 in which a region corresponding to the N-type solid phase diffusion layer 84s is formed in the sidewall of the deep trench, a concavo-convex shape (rough polysilicon film) is formed on the sidewall of the trench. The rough polysilicon film is referred to as an RP film 301. The RP film 301 can be formed, for example, by forming a doped polysilicon film and an amorphous silicon film on a silicon oxide film and performing a predetermined roughening treatment on the amorphous silicon film.

[0318] Step S102 and step S57 ( Fig.25 ) and deposits a silicon oxide film (BSG) 205 containing boron (B) using an ALD method. Through the process in step S102, a BSG film 205 is formed on the front surface of the wafer where no deep trench is formed, the RP film 301 corresponding to the side surface of the deep trench, and the bottom surface of the deep trench. Here, the BSG film 205 is formed as a P-type film using boron (B).

[0319] Step S103 and Step S58 and Step S59 ( Fig.25 ) is the same, and thermal diffusion treatment is first performed. The wafer is annealed to perform solid phase diffusion in the region where the BSG film 205 contacts the Si substrate 70, and boron (B) diffuses from the BSG film 205 to the Si substrate 70. As a result, Fig.33 As shown in step S103 in the above, a P-type impurity region 206 is formed. The P-type impurity region 206 corresponds to the P-type solid phase diffusion layer 83s ( Fig.32 ) area.

[0320] In the solid phase diffusion of boron, the RP film 301 serves as a diffusion suppression layer, and therefore, the boron diffused through the sidewall of the trench side is not uniform. Fig.33 As shown in step S103 in FIG. 1 , the non-uniform diffusion of boron results in the formation of concave and convex portions in the P-type impurity region 206. The P-type impurity region 206 is formed to include concave and convex portions, so the portion in contact with the previously formed N-type impurity region 203 is formed to include concave and convex portions. Therefore, compared with the uniform diffusion of boron, the bonding area where the P-type solid phase diffusion layer 83s contacts the N-type solid phase diffusion layer 84s can be increased.

[0321] After the heat treatment, the BSG film 205 is removed. The removal of the BSG film 205 can be performed by wet etching using hydrofluoric acid, for example.

[0322] Step S104 and step S60 ( Fig.25 ) is the same as that of the wafer, and polysilicon is embedded in the groove as filler 86p. And unnecessary polysilicon deposited on the upper surface of the wafer is removed. In addition, pixel transistors and wiring, etc. are formed. Subsequently, the Si substrate 70 is thinned from the back. Thinning is performed until the bottom of the deep groove is exposed.

[0323] This formed the Fig.32 The P-type solid-phase diffusion layer 83s shown includes minute concave and convex portions, thereby forming a pixel 50s having an expanded strong electric field region.

[0324] <Eighteenth Embodiment>

[0325] Fig.34 is a plan view of a pixel 50 t in the eighteenth embodiment to which the present technology is applied.

[0326] In the pixel 50t of the eighteenth embodiment, for the expanded strong electric field region, a strong electric field expansion region is formed in a part of the PD 71. The strong electric field expansion region is a PN junction region for expanding the strong electric field region. Fig.34 An example is shown in which a rectangular strong electric field region is formed in each of the four corners of the region of the PD 71 t - 1 and a cross-shaped strong electric field region is formed in the center of the region of the PD 71 t - 2 .

[0327] The rectangular strong electric field region formed in each of the four corners of the region of the PD 71t-1 includes a DTI 82t-21 formed in the central portion and a P-type solid-phase diffusion layer 83t-21 formed around the DTI 82t-21. In addition, an N-type solid-phase diffusion layer 84t-21 is formed around the P-type solid-phase diffusion layer 83t-21. Such a configuration is the same as the configuration of the strong electric field region formed in the DTI 82t surrounding the PD 71t.

[0328] A portion of the N-type solid phase diffusion layer 84t-21 is shared with the N-type solid phase diffusion layer 84t-1 formed in the sidewall of the DTI 82t-1. In addition, a portion of the N-type solid phase diffusion layer 84t-21 is shared with the N-type solid phase diffusion layer 84t-11 formed in the sidewall of the DTI 82t-11.

[0329] The cross-shaped strong electric field region formed in the region of the PD 71t-2 is provided with a cross-shaped DTI 82t-22, and a P-type solid-phase diffusion layer 83t-22 is formed around the cross-shaped DTI 82t-22. In addition, an N-type solid-phase diffusion layer 84t-22 is formed around the P-type solid-phase diffusion layer 83t-22. Such a structure is the same as the structure of the strong electric field region formed in the DTI 82t surrounding the PD 71t.

[0330] A portion of the N-type solid phase diffusion layer 84t-22, in other words, the N-type solid phase diffusion layer 84t-22 corresponding to the tip portion of the cross is shared with each of the N-type solid phase diffusion layer 84t-3 formed in the side wall of the DTI 82t-2, the N-type solid phase diffusion layer 84t-4 formed in the side wall of the DTI 82t-3, the N-type solid phase diffusion layer 84t-11 formed in the side wall of the DTI 82t-11, and the N-type solid phase diffusion layer 84t-12 formed in the side wall of the DTI82t-12.

[0331] Fig.34 The example shown shows a rectangular strong electric field region and a cross-shaped strong electric field region. However, other shapes may also be used. In addition, in the example shown, a rectangular strong electric field region and a cross-shaped strong electric field region are formed in a pixel 50t. The strong electric field region formed in the pixel 50t need not have different shapes, and may all be rectangular or cross-shaped.

[0332] in addition, Fig.34 The case where rectangular strong electric field regions are formed in the four corners of the PD 71 t - 1 is shown. However, instead of four strong electric field regions, one, two, or three strong electric field regions may be formed in any one of the four corners of the PD 71 .

[0333] also, Fig.34 The case where a cross-shaped strong electric field region is formed in PD 71t-2 is shown. However, the cross-shaped strong electric field region is not necessarily a cross-shaped region, and a strong electric field region shaped like a portion of a cross (for example, an L-shaped strong electric field region or a strong electric field region including only vertical strips (or horizontal strips)) can also be formed.

[0334] In addition, this example can be combined with the pixel 50q to the pixel 50s in the fifteenth to seventeenth embodiments to form concave portions and convex portions in a strong electric field region formed on the side wall of the DTI 82t surrounding the PD 71t.

[0335] By forming a strong electric field region including a P-type solid phase diffusion layer 83t and an N-type solid phase diffusion layer 84t in a region other than the DTI 82t surrounding the PD 71t, the strong electric field region provided in one pixel 50t can be expanded, thereby increasing the saturation charge amount.

[0336] Similar to the pixel 50q in the fifteenth embodiment, the pixel 50t in the eighteenth embodiment can be formed such that the length of the P-type solid-phase diffusion layer 83t is greater than the length between two parallel sides of the four sides surrounding the PD 71t, thereby increasing the PN junction area and expanding the strong electric field region.

[0337] In the pixel 50t of the eighteenth embodiment, the length of the P-type solid-phase diffusion layer 83t includes the length of the P-type solid-phase diffusion layer 83t included in the rectangular strong electric field region formed in each of the four corners of the PD 71t and the length of the P-type solid-phase diffusion layer 83t included in the cross-shaped strong electric field region formed in the PD 71t, and the length of the side wall of the DTI 82t. Therefore, as described above, the pixel 50t can be formed so that the length of the P-type solid-phase diffusion layer 83t is greater than the length between two parallel-arranged sides of the four sides surrounding the PD 71t.

[0338] Therefore, in other words, the DTI 82t can be formed such that the length of the side wall of the DTI 82t is greater than the length between the parallel arranged portions of the DTI 82t surrounding the PD 71t, thereby increasing the PN junction area and expanding the strong electric field region.

[0339] A method of manufacturing the pixel 50 t including the strong electric field region formed in the region of the PD 71 t as described above will be described. Fig.34 The manufacturing method of the pixel 50t shown can be carried out by referring to Fig.25 The Fig.21 The same steps as those for the pixel 50q shown in FIG. 5 are used to implement the method, and thus the description of the method is omitted. However, in step S52 ( Fig.24 ) has a different shape, so this will be explained below.

[0340] In step S52, a portion of the silicon oxide film 200, a portion of the insulating film 201, a portion of the SiN, and a portion of the Si substrate 70 are dug out by dry etching to form a deep trench. The shape of the deep trench is such that in a planar shape, the deep trench is provided with, for example, a lattice-shaped DTI 82t, a DTI 82t-21 corresponding to a portion where a rectangular strong electric field region is formed, and a DTI 82t-22 corresponding to a portion where a rectangular strong electric field region is formed. Fig.35 The cross-shaped strong electric field region shown corresponds to the DTI 82t-22. The depth of the formed trench reaches the lower end of the region where an N-type region will be formed by solid phase diffusion in a subsequent step.

[0341] As described above, a deep trench is formed in a desired shape in a portion where a strong electric field region is formed by dry etching. Fig.24 and Fig.25 As described above, the subsequent steps of forming the region corresponding to the N-type solid-phase diffusion layer 84r and the region corresponding to the P-type solid-phase diffusion layer 83r are performed.

[0342] like Fig.34 As shown, by forming the strong electric field region including the rectangular or cross-shaped strong electric field region in this way, a pixel 50t having an expanded strong electric field region is formed.

[0343] <Nineteenth Embodiment>

[0344] Fig.36 is a plan view of a pixel 50u in the nineteenth embodiment to which the present technology is applied.

[0345] The pixel 50u in the nineteenth embodiment is formed in such a manner that the DTI 82u portion surrounding the PD 71u is discontinuous. Fig.36 , the DTI 82u-11 portion formed in the left-right direction (lateral direction) of the figure is discontinuous. Other DTIs 82u, such as DTI 82u-12, are formed continuously.

[0346] The enlarged view of the part including DTI 82u-11 is shown in FIG. Fig.36 As shown in the figure on the right. Fig.36 In the right figure of FIG. 71 , DTI 82u-11 is formed in a manner including a discontinuous portion. The discontinuous portion is formed between DTI 82u-11 and DTI 82u-2 included in DTI 82u surrounding PD 71u-1. In other words, Fig.36 In the example shown, the discontinuous portion of the DTI 82u is disposed above and to the right of the PD 71-1.

[0347] The discontinuous portion of the DTI 82 - 11 is covered with a P-type solid-phase diffusion layer 83 u .

[0348] The P-type solid-phase diffusion layer 83u-10 formed above the DTI 82u-11 in the figure and the P-type solid-phase diffusion layer 83u-11 formed below the DTI 82-11 in the figure are in contact with each other in the discontinuous portion of the DTI 82u-11. Fig.36 As shown, the DTI 82u-11 is formed such that a discontinuous portion of the DTI 82u-11 is covered by the P-type solid-phase diffusion layer 83u.

[0349] Referring to the portion of the P-type solid-phase diffusion layer 83u-10 formed above the DTI 82u-11 in the figure, the shape of the P-type solid-phase diffusion layer 83u-10 in the discontinuous portion of the DTI 82u-11 is like an arc (like a curved surface). In addition, referring to the portion of the P-type solid-phase diffusion layer 83u-11 formed below the DTI 82u-11 in the figure, the shape of the P-type solid-phase diffusion layer 83u-11 in the discontinuous portion of the DTI 82u-11 is like an arc (like a curved surface).

[0350] The curved surface shape of the P-type solid diffusion layer 83u expands the portion (joining surface) where the P-type solid diffusion layer 83u contacts the N-type solid diffusion layer 84u, thereby expanding the strong electric field region and increasing the saturation charge amount.

[0351] exist Fig.36 In the example shown, for example, when focusing on the PD 71u-1, the discontinuous portion of the DTI 82u is formed at a position on the upper right of the PD 71u-1. The position and number of the discontinuous portions are not limited to Fig.36 Location and quantity shown.

[0352] For example, the discontinuous portion of the DTI 82u may be formed at each of the four corners relative to the PD 71u. Also, for example, the discontinuous portion of the DTI 82u may be formed in the center of the side. Also, for example, the discontinuous portion of the DTI 82u may be formed at a plurality of locations on one side. Fig.37 An example in which a plurality of discontinuous portions are formed on one side is shown.

[0353] Fig.37 1 is a plan view showing another configuration of a pixel 50u in the nineteenth embodiment to which the present technology is applied. Fig.37 In the illustrated pixel 50u, a plurality of discontinuities are formed on one side of the DTI 82u.

[0354] The enlarged view of the part including DTI 82u-2 is shown in Fig.37 As shown in the figure on the right. Fig.37 In the right figure of FIG. 82 , DTI 82u-2 is formed discontinuously and includes a discontinuous portion. DTI 82u-2 includes a plurality of DTI 82u-2 portions, and each DTI82u-2 portion is surrounded by a P-type solid-phase diffusion layer 83u. The P-type solid-phase diffusion layer 83u-2 formed on the left side of DTI 82u-2 in the figure and the P-type solid-phase diffusion layer 83u-11 formed below DTI 82u-2 in the figure are in contact with each other in the discontinuous portion of DTI 82-11.

[0355] Therefore, if Fig.37As shown, the DTI 82-2 is formed such that discontinuous portions of the DTI 82-2 are covered by the P-type solid-phase diffusion layer 83u, and is shaped such that respective portions of the DTI 82u-2 are surrounded by the P-type solid-phase diffusion layer 83u.

[0356] By forming the P-type solid diffusion layer 83u surrounding each portion of the DTI 82u, the contact portion (joint surface) between the P-type solid diffusion layer 83u and the N-type solid diffusion layer 84u is expanded, thereby expanding the strong electric field region and increasing the saturation charge amount.

[0357] exist Fig.37 In the left figure of FIG. 8 , the various parts of the DTI 82u are represented by rectangles, while Fig.37 In the right figure of FIG. , each portion of the DTI 82u is represented by an ellipse. Each portion of the DTI 82u may have a rectangular or elliptical shape or any other shape. By forming each portion of the DTI 82u so that its shape includes a curve such as an ellipse, the portion (joining surface) in contact with the N-type solid phase diffusion layer 84u can be enlarged.

[0358] This structure can be combined with the pixels 50q to 50t in the above-mentioned fifteenth to eighteenth embodiments so that recesses and protrusions can be formed in the strong electric field region formed in the side wall of the DTI 82u surrounding the PD 71u, or a strong electric field region can be formed in the region of the PD 71u.

[0359] Similar to the pixel 50q in the fifteenth embodiment, the pixel 50u in the nineteenth embodiment can be formed so that the length of the P-type solid-phase diffusion layer 83u is greater than the length between two parallel sides of the four sides surrounding the PD 71u, thereby increasing the PN junction area and expanding the strong electric field region.

[0360] A method of manufacturing the strong electric field region in the case where the DTI 82u is discontinuously formed as described above will be described. Fig.36 or Fig.37 The manufacturing method of the pixel 50u shown can be carried out by referring to Fig.24 and Fig.25 The Fig.21 The same steps as those for the pixel 50q shown in FIG. 5A are implemented, and the description of the method is omitted here. However, in step S52 ( Fig.24 ) have different shapes, so they will be described below.

[0361] In step S52, a portion of the silicon oxide film 200, a portion of the insulating film 201, a portion of the SiN film, and a portion of the Si substrate 70 are dug out by dry etching to form a deep trench. The shape of the deep trench is such that, in a planar shape, for example, Fig.37In the case of the discontinuous DTI 82u shown, the formation is as follows Fig.38 The shape shown is a grid-like but discontinuous DTI 82u. The depth of the formed trench reaches the lower end of a region where an N-type region will be formed by solid phase diffusion in a subsequent step.

[0362] As described above, in the portion where the strong electric field region is formed by dry etching, a deep trench is formed into a desired shape. In the subsequent steps S53 and S54 ( Fig.24 ), a region corresponding to the N-type solid-phase diffusion layer 84u is formed. In these steps, the N-type solid-phase diffusion layer 84u is formed so that each portion of the N-type solid-phase diffusion layer 84u is joined at each discontinuous portion of the DTI 82u.

[0363] In addition, in step S57 and step S58 ( Fig.25 ), a region corresponding to the P-type solid-phase diffusion layer 83u is formed. In these steps, the P-type solid-phase diffusion layer 83u is formed so that each portion of the P-type solid-phase diffusion layer 83u is joined at each discontinuous portion of the DTI 82u.

[0364] As mentioned above, Fig.36 or Fig.37 As shown, a pixel 50u is formed in which the DTI 82u includes a discontinuous portion for expanding a strong electric field region.

[0365] According to the fifteenth to nineteenth embodiments, the PN junction area of ​​the solid phase diffusion layer can be increased, so that the saturation charge amount can be increased.

[0366] <20th Embodiment>

[0367] Fig.39 It is a plan view of a pixel 50v in the 20th embodiment to which the present technology is applied.

[0368] The pixel 50v in the 20th embodiment is formed so that the strong electric field region surrounding the PD 71v includes concave portions and convex portions. Fig.21 The pixel 50q in the fifteenth embodiment shown is similar in configuration except that the protrusions are formed radially.

[0369] exist Fig.39 In the pixel 50v shown, when focusing on the PD 71v-1 included in the pixel 50v, the DTI 82v surrounding the PD 71v-1 is formed so that each side of the DTI 82v includes a protrusion. When a linearly continuously formed portion of the DTI 82v is used as a reference and a portion protruding relative to the DTI 82v used as a reference is designated as a protrusion, the protrusion is formed radially.

[0370] exist Fig.39In the example shown, the transfer transistor 80 (the gate of the transfer transistor 80 ) is formed approximately in the center of the pixel 50 v. Therefore, as described above, in the case where the transfer transistor 80 is formed in the center portion, the tip of the protrusion faces the transfer transistor 80 .

[0371] In accordance with the shape of the DTI 82v including such a protrusion, the P-type solid-phase diffusion layer 83v is also shaped to include a protrusion. In addition, in accordance with the shape of the P-type solid-phase diffusion layer 83v, the N-type solid-phase diffusion layer 84v is also shaped to include a protrusion.

[0372] The P-type solid phase diffusion layer 83v provided with the protrusion can increase the area where the P-type solid phase diffusion layer 83v contacts the N-type solid phase diffusion layer 84v. Therefore, the PN junction region including the P-type solid phase diffusion layer 83v and the N-type solid phase diffusion layer 84v is expanded, thereby expanding the strong electric field region. By expanding the strong electric field region, the amount of charge that can be maintained in the strong electric field region is increased, thereby increasing the saturation charge amount.

[0373] Here, reference Fig.40 , the effect of forming the protrusions radially, in other words, the effect of forming the protrusions so that the tips of the protrusions face the transfer transistor 80, will be described.

[0374] For comparison, Fig.40 A shows Fig.21 A portion of PD 71q is shown. Fig.40 In the above table, B is Fig.39 A partial enlarged view of PD 71v is shown. Fig.40 In the case where a protrusion is formed perpendicularly to the DTI 82q formed linearly and continuously, the electrons accumulated in the corner portion of the PD 71q reach the transfer transistor 80 in a manner avoiding the protrusion and are then read out. When the protrusion is enlarged (lengthened), the electrons accumulated in the corner portion will not reach the transfer transistor 80 unless they take a detour. The enlarged protrusion prevents the electrons accumulated in the corner portion of the PD 71q from being read out.

[0375] refer to Fig.40 B, also in the case where the protrusion is formed obliquely relative to the DTI 82v formed linearly and continuously and the protrusion points to the transfer transistor 80, Fig.40 As in the case of PD 71q shown in FIG. 1A , the electrons accumulated in the corner portion of PD 71v reach the transfer transistor 80 in a manner avoiding the protrusions and are then read out. However, in PD 71v, each protrusion formed obliquely expands the portion of the corner of PD 71v that opens toward the transfer transistor 80, thereby forming a path for electrons to flow smoothly.

[0376] Therefore, in the case of PD 71v, the electrons accumulated in the corner portion of PD 71v smoothly migrate to the transfer transistor 80, and thus it is possible to prevent the electrons from being difficult to read out. In addition, although not shown in the figure, a path toward the transfer transistor 80v is also formed in the portion other than the corner portion of PD 71v, thereby providing a structure that makes it easy to read out electrons.

[0377] By forming the protrusion so that the tip of the protrusion faces the transfer transistor 80 (the gate of the transfer transistor 80), the reading efficiency of the transfer transistor 80 can be improved. Therefore, depending on the position where the gate of the transfer transistor 80 is formed, for example, Fig.41 The structure shown.

[0378] exist Fig.41 PD 71v' shown (indicated by a prime symbol to distinguish PD 71v' from Fig.39 In the PD 71v shown in FIG. 1 , the gate of the transfer transistor 80v' is formed near one of the four corners of the PD 71v'. Even in the case where the transfer transistor 80v' is formed at such a position, the protrusion is formed to face the transfer transistor 80v'.

[0379] exist Fig.41 In the illustrated example, the PD 71 v ′ is formed such that a protrusion is formed on each of two sides opposite to a corner where the transfer transistor 80 v ′ is formed, and the tip of the protrusion faces the transfer transistor 80 v ′.

[0380] The twentieth embodiment can be combined with any of the first to nineteenth embodiments described above.

[0381] <Example 21>

[0382] Fig.42 and Fig.43 : is a diagram showing a configuration example of a pixel 50w in a 21st embodiment to which the present technology is applied.

[0383] Compared with the pixel 50q ( Fig.21 ) is the same as in Fig.42 In the pixel 50w in the embodiment of FIG. 1 , the PD 71w is shaped so that the strong electric field region surrounding the PD 71w includes a protrusion. Fig.42 As shown, a configuration in which a protrusion is provided at one position on each of four sides surrounding the PD 71w and a configuration in which the protrusion is vertically formed are described as examples.

[0384] Fig.42 The structure of PD 71w shown is similar to Fig.21The illustrated PD 71q is similarly constructed except that a protrusion is formed on one side. Fig.43 Shows a section taken along line segment A-A' Fig.42 A cross-sectional view of PD 71w is shown.

[0385] A protrusion is formed in the portion of line segment AA'. Here, in order to distinguish from DTI 82w, P-type solid-phase diffusion layer 83w, and N-type solid-phase diffusion layer 84w constituting the remaining portion, prime marks are used to describe DTI 82w', P-type solid-phase diffusion layer 83w', and N-type solid-phase diffusion layer 84w' constituting the protrusion.

[0386] refer to Fig.43 , penetrating DTI 82w is formed on both sides of PD 71w. In contrast, in the protrusion, non-penetrating DTI 82w' is formed instead of penetrating DTI 82w. In other words, DTI 82w' formed in the protrusion is formed with a portion constituting PD 71w remaining on the on-chip lens 76w side.

[0387] Now, refer again Fig. 20 and Fig.21 . Fig. 20 is a plan view of the PD 71 in the case where the protrusion is not formed, Fig.21 71q is a plan view of the PD 71q in which the protrusion is formed. Fig.21 As described above, by providing the protrusion, the strong electric field region can be expanded, but the light receiving area of ​​the PD 71q may be reduced.

[0388] When the general Fig. 20 The area of ​​PD 71 shown is Fig.21 When compared with the region of PD 71q shown, the lack of a protrusion makes Fig. 20 The area of ​​PD 71 shown is larger than Fig.21 The region of PD 71q is shown.

[0389] Fig. 20 For example, corresponding to Fig.43 The plane diagram is a partial intercept of the line segment B-B', and Fig.21 For example, corresponding to Fig.43 Therefore, even in the case of forming a protrusion, such as Fig.42 As shown in FIG. 1 , since the area of ​​PD 71w becomes larger on the light incident surface side, it is also possible to prevent the sensitivity from being reduced due to the formation of the protrusion. On the other hand, in the area away from the light incident surface side, as shown in FIG. Fig.21 The protrusion formed as shown expands the PN junction region, thereby being able to expand the strong electric field region.

[0390] Therefore, the saturation charge amount can be increased without reducing the sensitivity.

[0391] It is possible to combine the 50q( Fig.21 ), 50r in the sixteenth embodiment ( Fig.28 ), 50t in the eighteenth embodiment and 50v in the twentieth embodiment ( Fig.39 ) combination. Specifically, when the above-mentioned structure includes a protrusion, the protrusion can be formed in a non-penetrating manner.

[0392] As described above, in the case where the portion corresponding to the protrusion is formed in a non-penetrating manner and the portion other than the protrusion is formed in a penetrating manner, the penetrating portion and the non-penetrating portion can be formed by making the width of the DTI 82 different during the manufacturing process. Fig.43 The width of the DTI 82w' in the protruding portion is assumed to be a width L1, and the width of the DTI 82w corresponding to the portion other than the protruding portion is assumed to be a width L2. The width L1 is assumed to be smaller than the width L2.

[0393] When the width is varied in this way, in the step of forming the groove, the loading effect makes the narrower part of the groove shallower and the wider part of the groove deeper. In this case, the part of the groove having a width of L1 is shallower, while the part of the groove having a width of L2 is deeper.

[0394] For example, reference Figure 24 to Figure 27 , the method for manufacturing the strong electric field region including the protrusion has been described, and in step S52, the silicon substrate is dug out by dry etching. As dry etching, for example, RIE (Reactive Ion Etching) can be used. When the groove is formed by dry etching, the loading effect makes the narrower part of the groove shallower than the wider part of the groove.

[0395] By adjusting the width L1, the depth of the DTI 82w' in the protrusion can be set to a desired value. Therefore, even when the portion corresponding to the protrusion is formed in a non-penetrating manner and the portion other than the protrusion is formed in a penetrating manner, DTI 82 having different widths can be formed without increasing the process.

[0396] The first to 21st embodiments can be applied to the image pickup device 1 described below. The image pickup device 1 will be described below.

[0397] [Functional Configuration of Image Capture Device 1]

[0398] Fig.44 : is a block diagram showing an example of a functional configuration of an image pickup apparatus (image pickup apparatus 1 ) according to an embodiment of the present disclosure.

[0399] Fig.44 The imaging device 1 in the embodiment includes, for example, an input section 510A, a row driving section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0400] The pixel array section 540 includes pixels 541 that are repeatedly arranged in an array. More specifically, pixel sharing units 539 each including a plurality of pixels are used as a repeating unit, and these pixel sharing units 539 are repeatedly arranged in an array including a row direction and a column direction. Note that in this specification, for ease of explanation, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction may be referred to as the V direction. Fig.44 In the example of FIG. 5 , one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Pixels 541A, 541B, 541C, and 541D each include a photodiode PD (described below). Fig.49 The pixel sharing unit 539 is a pixel sharing circuit (described below). Fig.46 210 in the pixel sharing unit 539). In other words, the pixel sharing unit 539 includes one pixel circuit (the pixel circuit 210 described below) for every four pixels (pixels 541A, 541B, 541C, and 541D). By operating the pixel circuit in a time-sharing manner, pixel signals are sequentially read out from pixels 541A, 541B, 541C, and 541D. Pixels 541A, 541B, 541C, and 541D are arranged, for example, in 2 rows × 2 columns. The pixel array section 540 is provided with pixels 541A, 541B, 541C, and 541D, as well as a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543. The row drive signal line 542 drives the pixels 541 included in each of the plurality of pixel sharing units 539 arranged in parallel along the row direction in the pixel array section 540. Therefore, the pixels arranged in parallel along the row direction in the pixel sharing unit 539 are driven. Fig.44 As described in detail, the pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of the plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to each vertical signal line (column readout line) 543. Pixel signals are read out from the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal line (column readout line) 543.

[0401] The row driving section 520 includes a row address control section, in other words, a row decoder section for determining the position of a row of pixels to be driven, and a row driving circuit section for generating signals for driving the pixels 541A, 541B, 541C, and 541D.

[0402] The column signal processing section 550 includes, for example, a load circuit section that is connected to the vertical signal line 543 and constitutes a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539). The column signal processing section 550 may include an amplifier circuit section that amplifies the signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing section 550 may include a noise processing section. For example, as a result of photoelectric conversion, the noise processing section removes the noise level of the system from the signal read out from the pixel sharing unit 539.

[0403] The column signal processing section 550 includes, for example, an analog digital converter (ADC). The analog digital converter converts the signal read out from the pixel sharing unit 539 or the analog signal that has undergone the above-mentioned noise processing into a digital signal. The ADC includes, for example, a comparator section and a counter section. The comparator section compares the analog signal to be converted with a reference signal to be compared with the analog signal. The counter section is suitable for measuring the time before the comparison result of the comparator section is inverted. The column signal processing section 550 may include a horizontal scanning circuit section that performs control for scanning the readout row.

[0404] The timing control section 530 feeds a signal for controlling the timing to the row driving section 520 and the column signal processing section 550 based on the reference clock signal and the timing control signal input to the device.

[0405] The image signal processing section 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, on data obtained as a result of an image pickup operation in the image pickup device 1. The image signal processing section 560 includes, for example, an image signal processing circuit section and a data storage section. The image signal processing section 560 may include a processor section.

[0406] An example of the signal processing performed in the image signal processing section 560 is a tone curve correction process in which, in the case of obtaining image data by imaging a dark subject, many gray levels are set for the image data obtained from AD conversion, and in the case of obtaining image data by imaging a bright subject, fewer gray levels are set for the image data obtained from AD conversion. In this case, in order to determine based on which tone curve the gray level of the image data is corrected, it is desirable to store characteristic data related to the tone curve in advance in the data storage section of the image signal processing section 560.

[0407] The input section 510A is used, for example, to input a reference clock signal, a timing control signal, and feature data from outside the device to the camera 1. The timing control signal includes, for example, a vertical synchronization signal and a horizontal synchronization signal. The feature data is stored, for example, in a data storage section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0408] The input terminal 511 is an external terminal for input data. The input circuit section 512 is used to load the signal input to the input terminal 511 into the image pickup device 1. The input amplitude change section 513 changes the amplitude of the signal loaded by the input circuit section 512 to an amplitude that is easy to use inside the image pickup device 1. The input data conversion circuit section 514 changes the arrangement of the data sequence of the input data. The input data conversion circuit section 514 includes, for example, a serial-parallel conversion circuit. The serial-parallel conversion circuit converts a serial signal received as input data into a parallel signal. Note that in the input section 510A, the input amplitude change section 513 and the input data conversion circuit section 514 can be omitted. Based on the power supply supplied from the outside to the image pickup device 1, the power supply section supplies power that is set to various voltages required inside the image pickup device 1.

[0409] When the camera apparatus 1 is connected to an external storage device, the input unit 510A may be provided with a storage interface circuit for receiving data from the external storage device, such as a flash memory, SRAM, or DRAM.

[0410] The output unit 510B outputs image data to the outside of the device. The image data is, for example, image data obtained by the camera 1 and image data subjected to signal processing by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0411] The output data conversion circuit section 515 includes, for example, a parallel-serial conversion circuit, and the output data conversion circuit section 515 converts a parallel signal used inside the image pickup device 1 into a serial signal. The output amplitude change section 516 changes the amplitude of the signal used inside the image pickup device 1. The signal after the amplitude change is easy to be used by an external device connected to the outside of the image pickup device 1. The output circuit section 517 is a circuit that outputs data from the inside of the image pickup device 1 to the outside, and the output circuit section 517 drives the external wiring of the image pickup device 1 connected to the output terminal 518. The image pickup device 1 outputs the data to the outside of the device through the output terminal 518. In the output section 510B, the output data conversion circuit section 515 and the output amplitude change section 516 can be omitted.

[0412] When the camera apparatus 1 is connected to an external storage device, the output unit 510B may be provided with a storage interface circuit for outputting data to the external storage device, such as a flash memory, SRAM, or DRAM.

[0413] [Overall Configuration of Image Capture Device 1]

[0414] Fig.45 and Fig.46 There is shown an example of the overall configuration of the image pickup device 1. The image pickup device 1 includes three substrates (a first substrate 100, a second substrate 260, and a third substrate 300). Fig.45 The planar configurations of the first substrate 100 , the second substrate 260 , and the third substrate 300 are schematically shown. Fig.46 The cross-sectional configuration of the first substrate 100 , the second substrate 200 , and the third substrate 300 stacked together is schematically shown. Fig.46 Corresponding to along Fig.45The cross-sectional structure of the line III-III' shown. The camera device 1 is a camera device having a three-dimensional structure, which includes three substrates (a first substrate 100, a second substrate 260, and a third substrate 300) stacked together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 260 includes a semiconductor layer 260S and a wiring layer 260T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. In this regard, for the sake of convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 260, and the third substrate 300 and the surrounding interlayer insulating film is referred to as the wiring layer (100T, 260T, 300T) provided in each substrate (the first substrate 100, the second substrate 260, and the third substrate 300). The first substrate 100, the second substrate 260 and the third substrate 300 are sequentially stacked together and include a semiconductor layer 100S, a wiring layer 100T, a semiconductor layer 260S, a wiring layer 260T, a wiring layer 300T and a semiconductor layer 300S sequentially arranged in a stacking direction. The specific configurations of the first substrate 100, the second substrate 260 and the third substrate 300 will be described below. Fig.46 The arrow shown indicates the incident direction of the light L entering the imaging device 1. In this specification, for the sake of convenience of explanation, in the following cross-sectional views, the light incident side in the imaging device 1 may be referred to as "lower", "below", or "downward", and the side opposite to the light incident side may be referred to as "upper", "above", or "upward". In addition, in this specification, for the sake of convenience of explanation, for each substrate including a semiconductor layer and a wiring layer, the side of the wiring layer may be referred to as the front surface, and the side of the semiconductor layer may be referred to as the rear surface. Note that the description here is not limited to the above designation. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident on the imaging device from the back side of the first substrate 100 including a photodiode.

[0415] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both constructed using the first substrate 100 and the second substrate 260. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C and 541D included in the pixel sharing unit 539. Each pixel 541 includes a photodiode (photodiode PD described below) and a transfer transistor (transfer transistor TR described below). The second substrate 260 is provided with a pixel circuit (pixel circuit 210 described below) included in the pixel sharing unit 539. The pixel circuit reads out the pixel signal transmitted from the photodiode of each of the pixels 541A, 541B, 541C and 541D via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 260 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 260 also includes a power supply line 544 extending in the row direction. The third substrate 300 includes, for example, an input section 510A, a row driving section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driving section 520 is, for example, disposed in a region where the row driving section 520 partially overlaps with the pixel array section 540 along the stacking direction of the first substrate 100, the second substrate 260, and the third substrate 300 (hereinafter referred to as the stacking direction). More specifically, the row driving section 520 is disposed in a region where the row driving section 520 overlaps with the vicinity of the end of the pixel array section 540 in the H direction along the stacking direction ( Fig.45 ). The column signal processing unit 550 is, for example, disposed in a region where the column signal processing unit 550 partially overlaps with the pixel array unit 540 along the stacking direction. More specifically, the column signal processing unit 550 is disposed in a region where the column signal processing unit 550 overlaps with the vicinity of the end portion of the pixel array unit 540 in the V direction along the stacking direction ( Fig.45 ). Although not shown, the input section 510A and the output section 510B may be provided in a portion other than the third substrate 300 or, for example, in the second substrate 260. Alternatively, the input section 510A and the output section 510B may be provided on the back side (light incident) of the first substrate 100. Note that the pixel circuit provided in the second substrate 260 has different names, and the pixel circuit may be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. The name "pixel circuit" is used here.

[0416] The first substrate 100 and the second substrate 260 are connected to each other by, for example, through electrodes (described below) Fig.49The through electrodes 120E and 121E in the second substrate 260 are electrically connected. The second substrate 260 and the third substrate 300 are electrically connected, for example, via the contact portions 261, 262, 305 and 302. The contact portions 261 and 262 are provided in the second substrate 260, and the contact portions 305 and 302 are provided in the third substrate 300. The contact portion 261 of the second substrate 260 contacts the contact portion 305 of the third substrate 300, and the contact portion 262 of the second substrate 260 contacts the contact portion 302 of the third substrate 300. The second substrate 260 includes a contact region 261R provided with a plurality of contact portions 261 and a contact region 262R provided with a plurality of contact portions 262. The third substrate 300 includes a contact region 305R provided with a plurality of contact portions 305 and a contact region 302R provided with a plurality of contact portions 302. The contact regions 261R and 305R are provided between the pixel array section 540 and the row drive section 520 in the stacking direction ( Fig.46 ). In other words, the contact regions 261R and 305R are provided, for example, in a region where the row drive section 520 (third substrate 300) overlaps with the pixel array section 540 (second substrate 260) in the stacking direction or in the vicinity of the region. The contact regions 261R and 305R are provided, for example, at the ends of the regions in the H direction as described above ( Fig.45 ). On the third substrate 300, for example, the contact region 305R is provided at a position where the contact region 305R overlaps with a portion of the row drive unit 520, specifically, at a position where the contact region 305R overlaps with an end portion of the row drive unit 520 in the H direction ( Fig.45 and Fig.46 ). The contact portions 261 and 305 are intended, for example, to connect the row drive portion 520 provided in the third substrate 300 to the row drive line 542 provided in the second substrate 260. The contact portions 261 and 305 can, for example, connect the input portion 510A provided in the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS described below). The contact regions 262R and 302R are provided between the pixel array portion 540 and the column signal processing portion 550 in the stacking direction ( Fig.46 ). In other words, the contact regions 262R and 302R are provided, for example, in a region where the column signal processing section 550 (third substrate 300) and the pixel array section 540 (second substrate 260) overlap in the stacking direction or in the vicinity of the region. The contact regions 262R and 302R are provided, for example, at the V-direction ends of such a region as described above ( Fig.45 ). On the third substrate 300, for example, the contact region 305R is provided at a position where the contact region 305R overlaps with a portion of the column signal processing unit 550, specifically, at a position where the contact region 305R overlaps with an end portion of the column signal processing unit 550 in the V direction ( Fig.45 and Fig.46). The contact portions 262 and 302 are intended, for example, to connect a pixel signal (corresponding to the amount of charge generated by photoelectric conversion of a photodiode) output from each of the plurality of pixel sharing units 539 included in the pixel array portion 540 to a column signal processing portion 550 provided in the third substrate 300. The pixel signal is transmitted from the second substrate 260 to the third substrate 300.

[0417] As mentioned above, Fig.46 is an example of a cross-sectional view of the image pickup device 1. The first substrate 100, the second substrate 260, and the third substrate 300 are electrically connected via wiring layers 100T, 260T, and 300T. For example, the image pickup device 1 includes an electrical connection portion that electrically connects the second substrate 260 and the third substrate 300. Specifically, the contact portions 261, 262, 305, and 302 are formed by electrodes including a conductive material. The conductive material includes, for example, a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 261R, 262R, 305R, and 302R are, for example, directly bonded to wiring formed as electrodes to electrically connect the second substrate and the third substrate, thereby enabling input and / or output of signals between the second substrate 260 and the third substrate 300.

[0418] The electrical connection portion that electrically connects the second substrate 260 and the third substrate 300 can be disposed at a desired position. For example, the electrical connection portion can be disposed in a region where the electrical connection portion overlaps with the pixel array portion 540 in the stacking direction, and with reference to Fig.46 , which has been described as the contact region 261R, 262R, 305R or 302R. In addition, the electrical connection portion may be provided in an area in which the electrical connection portion does not overlap with the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portion may be provided in an area that overlaps with a peripheral portion provided outside the pixel array portion 540 in the stacking direction.

[0419] The first substrate 100 and the second substrate 260 are provided with connection holes H1 and H2, for example. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 260 ( Fig.46 The connection hole portions H1 and H2 are provided outside the pixel array portion 540 (or outside the portion overlapping with the pixel array portion 540) ( Fig.45). For example, the connection hole portion H1 is disposed on the outside of the pixel array portion 540 in the H direction, and the connection hole portion H2 is disposed on the outside of the pixel array portion 540 in the V direction. For example, the connection hole portion H1 reaches the input portion 510A disposed in the third substrate 300, and the connection hole portion H2 reaches the output portion 510B disposed in the third substrate 300. The connection hole portions H1 and H2 may be cavities, or at least a portion thereof may contain a conductive material. For example, in a certain configuration, a bonding wire is connected to an electrode formed as the input portion 510A and / or the output portion 510B. Alternatively, in a certain configuration, an electrode formed as the input portion 510A and / or the output portion 510B is connected to a conductive material disposed in the connection hole portion H1 or H2. The conductive material disposed in the connection hole portion H1 or H2 may be embedded in a portion or all of the connection hole portion H1 or H2, or may be formed in the sidewall of the connection hole portion H1 or H2.

[0420] Note that Fig.46 In the structure of the third substrate 300, the input portion 510A and the output portion 510B are provided, but the present disclosure is not limited to this structure. For example, a signal from the third substrate 300 is transmitted to the second substrate 260 via the wiring layers 260T and 300T, so that the input portion 510A and / or the output portion 510B can be provided in the second substrate 260. Similarly, a signal from the second substrate 260 is transmitted to the first substrate 100 via the wiring layers 100T and 260T, so that the input portion 510A and / or the output portion 510B can be provided in the first substrate 100.

[0421] Fig.47 5 is an equivalent circuit diagram showing a configuration example of a pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (in Fig.47 , four pixels 541 including pixels 541A, 541B, 541C, and 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210 are represented. The pixel circuit 210 includes, for example, four transistors, specifically, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 is adapted to operate one pixel circuit 210 in a time-sharing manner so that pixel signals respectively from four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 are sequentially output to the vertical signal line 543. The following aspect is represented as "a plurality of pixels 541 share one pixel circuit 210": one pixel circuit 210 is connected to the plurality of pixels 541, and the one pixel circuit 210 outputs the pixel signals of the plurality of pixels 541 in a time-sharing manner.

[0422] Pixels 541A, 541B, 541C, and 541D include common components. In order to distinguish the components of pixels 541A, 541B, 541C, and 541D, the reference numerals of the components of pixel 541A include the identification number 1 as the last digit, the reference numerals of the components of pixel 541B include the identification number 2 as the last digit, the reference numerals of the components of pixel 541C include the identification number 3 as the last digit, and the reference numerals of the components of pixel 541D include the identification number 4 as the last digit. In the case where it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D, the last identification numbers of the reference numerals of the components of pixels 541A, 541B, 541C, and 541D are omitted.

[0423] Pixels 541A, 541B, 541C, and 541D respectively include, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. The photodiode PD (PD1, PD2, PD3, and PD4) includes a cathode electrically connected to the source of the transfer transistor TR and an anode electrically connected to a reference potential line (e.g., ground). The photodiode PD performs photoelectric conversion on incident light and generates charges corresponding to the amount of light received. The transfer transistor TR (transfer transistors TR1, TR2, TR3, and TR4) is, for example, an N-type CMOS (Complementary Metal Oxide Semiconductor) transistor. The transfer transistor TR includes a drain electrically connected to the floating diffusion FD and a gate electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 542 (see FIG. 5 ) connected to one pixel sharing unit 539. Fig.44 ). The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, and FD4) is an N-type diffusion layer region formed in a P-type semiconductor layer. The floating diffusion FD is a charge holding device for temporarily holding the charge transferred from the photodiode PD and a charge-voltage conversion device for generating a voltage corresponding to the amount of charge.

[0424] The four floating diffusions FD (each floating diffusion FD1, FD2, FD3, and FD4) included in one pixel sharing unit 539 are electrically connected to each other and are electrically connected together to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The FD conversion gain switching transistor FDG includes a drain connected to the source of the reset transistor RST and a gate connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The reset transistor RST includes a drain connected to the power supply line VDD and a gate connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The amplifier transistor AMP includes a gate connected to the floating diffusion FD, a drain connected to the power supply line VDD, and a source connected to the drain of the selection transistor SEL. The selection transistor SEL includes a source connected to the vertical signal line 543 and a gate connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539.

[0425] By turning on the transfer transistor TR, the transfer transistor TR transfers the charge in the photodiode PD to the floating diffusion FD. Fig.49 As shown, the gate electrode (transmission gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and extends from the semiconductor layer (described below) to the gate electrode. Fig.49 The front surface of the semiconductor layer 100S in the floating diffusion FD is extended to a depth that reaches the PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. By setting the reset transistor RST to an on state, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a signal having a voltage corresponding to the level of the charge stored in the floating diffusion FD as a pixel signal. The amplifier transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplifier transistor AMP is connected to the load circuit unit (see Fig.44 ) together constitute a source follower. By setting the selection transistor SEL to an on state, the amplifier transistor AMP outputs the voltage of the floating diffusion portion FD to the column signal processing portion 550 via the vertical signal line 543. The reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are, for example, N-type CMOS transistors.

[0426] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion of the floating diffusion FD. Generally, when photographing in a dark place, the pixel signal is very small. Based on Q=CV, if the capacitance (FD capacitance C) of the floating diffusion FD is large during the charge-voltage conversion process, the V obtained by the amplifier transistor AMP converted into a voltage becomes smaller. On the other hand, bright places involve large pixel signals, so unless the FD capacitance C of the floating diffusion FD is large, the floating diffusion FD cannot receive the charge from the photodiode PD. In addition, the FD capacitance C must be appropriately large to prevent the V generated by the conversion of the amplifier transistor AMP into a voltage from being too large (in other words, making V smaller). Based on this, by turning on the FD conversion gain switching transistor FDG, the gate capacitance will increase by an amount corresponding to the FD conversion gain switching transistor FDG, thereby increasing the FD capacitance C of the entire pixel. On the other hand, by turning off the FD conversion gain switching transistor FDG, the FD capacitance C of the entire pixel is reduced. Therefore, by turning on and off the FD conversion gain switching transistor FDG, the FD capacitance C can be changed, thereby switching the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0427] Note that in a possible configuration, the FD conversion gain switching transistor FDG is omitted. In this case, for example, the pixel circuit 210 has three transistors including an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 includes at least one of the pixel transistors such as the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0428] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see Fig.44 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Note that although not shown, the number of pixels 541 that share one pixel circuit 210 may not be four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0429] Fig.48543. For example, four pixel sharing units 539 arranged in parallel in the column direction are divided into four groups, each of which is connected to a vertical signal line 543. Fig.48 An example is shown in which each of the four groups includes one pixel sharing unit 539. However, each of the four groups may include a plurality of pixel sharing units 539. As described above, in the image pickup device 1, a plurality of pixel sharing units 539 arranged in parallel in the column direction may be divided into a plurality of groups, each group including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each of the plurality of groups, and pixel signals can be read out simultaneously from the respective groups. Alternatively, in the image pickup device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in parallel in the column direction. At this time, pixel signals are sequentially read out in a time-division manner from the plurality of pixel sharing units 539 connected to one vertical signal line 543.

[0430] [Specific Structure of the Image Capture Device 1]

[0431] Fig.49 An example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100 , the second substrate 260 , and the third substrate 300 of the image pickup device 1 is shown. Fig.49 A cross-sectional structure is schematically shown to help understand the positional relationship of each component, and may be different from the actual cross-section. The camera device 1 includes a first substrate 100, a second substrate 260, and a third substrate 300 stacked in sequence. The camera device 1 also includes a light receiving lens 401 located on the back side (light incident side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. For example, a light receiving lens 401 is provided in each of the pixels 541A, 541B, 541C, and 541D. The camera device 1 is, for example, a back-illuminated camera device. The camera device 1 includes a pixel array portion 540 arranged in a central portion and a peripheral portion 540B arranged outside the pixel array portion 540.

[0432] The first substrate 100 includes an insulating film 110, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T arranged in order from the light receiving lens 401 side. The semiconductor layer 100S includes, for example, a silicon substrate. The semiconductor layer 100S includes, for example, a p-well layer 115 in a portion of the front surface (side surface of the wiring layer 100T) and near the portion, and the semiconductor layer 100S includes an N-type semiconductor region 114 as another region (a region deeper than the p-well layer 115). For example, the N-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a P-type semiconductor region.

[0433] Fig.50 An example of a planar configuration of the first substrate 100 is shown. Fig.50 The planar structure of the pixel separation unit 117, the photodiode PD, the floating diffusion unit FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100 is mainly shown. Fig.50 and Fig.49 The structure of the first substrate 100 will be described.

[0434] The floating diffusion FD and the VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion FD includes an N-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (each floating diffusion FD1, FD2, FD3, and FD4) of each of the pixels 541A, 541B, 541C, and 541D are provided, for example, close to each other in the central portion of the pixel sharing unit 539 ( Fig.50 ). Although described in detail below, the four floating diffusions (floating diffusions FD1, FD2, FD3, and FD4) included in the pixel sharing unit 539 are electrically connected together in the first substrate 100 (more specifically, in the wiring layer 100T) by an electrical connection device (the pad portion 120 described below). In addition, the floating diffusion FD is connected from the first substrate 100 to the second substrate 260 (more specifically, from the wiring layer 100T to the wiring layer 260T) via an electrical device (a through electrode 120E described below). In the second substrate 260 (more specifically, inside the wiring layer 260T), the floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG by the electrical device.

[0435] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is spaced apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is provided at one end of the V direction of each pixel, and the VSS contact region 118 is provided at the other end ( Fig.50 ). The VSS contact region 118 includes, for example, a P-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Therefore, a reference potential is provided to the semiconductor layer 100S.

[0436] The first substrate 100 is provided with a transfer transistor TR as well as a photodiode PD, a floating diffusion portion FD, and a VSS contact region 118. A photodiode PD, a floating diffusion portion FD, a VSS contact region 118, and a transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite to the light incident side, the second substrate 260 side). The transfer transistor TR includes a transfer gate TG. The transfer gate TG, for example, includes a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa contacts the horizontal portion TGb, and the other end of the vertical portion TGa is provided in the N-type semiconductor region 114. When the transfer transistor TR includes such a vertical transistor, erroneous transmission of the pixel signal is less likely to occur, thereby being able to improve the readout efficiency of the pixel signal.

[0437] The horizontal portion TGb of the transfer gate TG extends from a position facing the vertical portion TGa, for example, along the H direction toward the central portion of the pixel sharing unit 539 ( Fig.50 ). Therefore, the position of the through electrode (the through electrode TGV described below) reaching the transfer gate TG can be made closer in the H direction to the position of the through electrode (the through electrode 120E or 121E described below) connected to the VSS contact region 118 in the H direction. For example, the plurality of pixel sharing units 539 provided in the first substrate 100 have the same configuration ( Fig.50 ).

[0438] The semiconductor layer 100S is provided with a pixel separation portion 117 that separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the front surface of the semiconductor layer 100S). The pixel separation portion 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from each other, and the pixel separation portion 117 has, for example, a grid-like planar shape ( Fig.50 and Fig.51). The pixel separation unit 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation unit 117 includes, for example, a light shielding film 117A and an insulating film 117B. As the light shielding film 117A, for example, tungsten (W) or the like is used. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the N-type semiconductor region 114. The insulating film 117B includes, for example, silicon oxide (SiO). The pixel separation unit 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation unit 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, the pixel separation unit 117 may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S, and is formed in a partial region of the semiconductor layer 100S.

[0439] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and between the N-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided in the side of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or between the pixel separation portion 117 and the N-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 each include, for example, a P-type semiconductor region.

[0440] A fixed charge film 112 containing negative fixed charges is provided between the semiconductor layer 100S and the insulating film 110. The electric field caused by the fixed charge film 112 forms a first pinning region 113 for a Hall storage layer at the light receiving surface (back side) side interface of the semiconductor layer 100S. This reduces the generation of dark current caused by the interface state on the light receiving surface side of the semiconductor layer 100S. The fixed charge film 112 includes, for example, an insulating film containing negative fixed charges. Examples of materials for the insulating film containing negative fixed charges include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide.

[0441] A light shielding film 117A is provided between the fixed charge film 112 and the insulating film 110. The light shielding film 117A may be provided continuously with the light shielding film 117A constituting the pixel separation portion 117. The light shielding film 117A between the fixed charge film 112 and the insulating film 110 is selectively provided, for example, at a position facing the pixel separation portion 117 in the semiconductor layer 100S. The insulating film 110 is provided on the light shielding film 117A. The insulating film 110 includes, for example, silicon oxide.

[0442] Starting from the semiconductor layer 100S side, the wiring layer 100T provided between the semiconductor layer 100S and the second substrate 260 includes an interlayer insulating film 119, pad portions 120 and 121, a passivation film 126, an interlayer insulating film 123, and a bonding film 124. The horizontal portion TGb of the transfer gate TG is provided in the wiring layer 100T, for example. The interlayer insulating film 119 is provided on the entire front surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 includes, for example, a silicon oxide film. Note that the wiring layer 100T is not limited to the above-described configuration, and any configuration may be employed as long as the wiring layer 100T includes wiring and an insulating film.

[0443] Fig.51 The configuration of the pad portions 120 and 121 and Fig.50 The pad portions 120 and 121 are provided in a selected area on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the respective pixels 541A, 541B, 541C, and 541D to each other. In the plan view, the pad portion 120 of each pixel sharing unit 539 is provided, for example, in the central portion ( Fig.51 The pad portion 120 is provided to cross the pixel separation portion 117 and is provided to be aligned with the floating diffusion portions FD1, FD2, FD3, and FD4 ( Fig.49 and Fig.51 ) overlap at least a portion of each. Specifically, the pad portion 120 is formed in a region overlapping with at least a portion of each of the plurality of floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection through hole 120C for electrically connecting the pad portion 120 to the floating diffusion portions FD1, FD2, FD3, and FD4. The connection through hole 120C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 120 is embedded in the connection through hole 120C to electrically connect the pad portion 120 to each of the floating diffusion portions FD1, FD2, FD3, and FD4.

[0444] The pad portion 121 is used to connect a plurality of VSS contact regions 118 together. For example, the pad portion 121 electrically connects together the VSS contact regions 118 provided for the pixels 541C and 541D in one of the pixel sharing units 539 adjacent to each other in the V direction and the VSS contact regions 118 provided for the pixels 541A and 541B in the other pixel sharing unit 539. The pad portion 121 is provided, for example, to cross the pixel separation portion 117, and is arranged to overlap with at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region overlapping with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection through hole 121C for electrically connecting the pad portion 121 to the VSS contact region 118. A connection through hole 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 121 is embedded in the connection through hole 121C to electrically connect the pad portion 121 to each of the VSS contact regions 118. For example, the pad portions 120 and 121 in each of the plurality of pixel sharing units 539 arranged in the V direction are located at approximately the same position in the H direction ( Fig.51 ).

[0445] By providing the pad portion 120, the wiring for connecting each floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifier transistor AMP) can be reduced in the entire chip. Similarly, by providing the pad portion 121, the wiring for providing a potential to each VSS contact area 118 can be reduced in the entire chip. Therefore, it is possible to reduce the area of ​​the entire chip, reduce electrical interference between wirings in micro pixels, and / or reduce costs by reducing the number of components.

[0446] The pad portions 120 and 121 can be arranged at desired positions in the first substrate 100 and the second substrate 260. Specifically, the pad portions 120 and 121 can be arranged in any one of the insulating region 212 of the wiring layer 100T or the semiconductor layer 260S. In the case where the pad portions 120 and 121 are arranged in the wiring layer 100T, the pad portions 120 and 121 can be arranged to contact the semiconductor layer 100S. Specifically, in a certain configuration, the pad portions 120 and 121 can be directly connected to at least a portion of each of the floating diffusion portion FD and / or the VSS contact region 118. In addition, in a certain configuration, the connecting through holes 120C and 121C can be arranged to extend from each of the floating diffusion portion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 can be arranged at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 260S.

[0447] In particular, by providing the pad portions 120 and 121 in the wiring layer 100T, the wiring connected to the floating diffusion portion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 260S can be reduced. This in turn can reduce the area of ​​the insulating region 212 of the second substrate 260 where the pixel circuit 210 is formed, and the insulating region 212 is configured so that the through wiring for connecting the floating diffusion portion FD to the pixel circuit 210 is formed in the insulating region 212. Therefore, the area of ​​the portion of the second substrate 260 where the pixel circuit 210 is formed can be increased. By providing a large area for the pixel circuit 210, a large pixel transistor can be formed, so that image quality can be improved by reducing noise and the like.

[0448] In particular, when the FTI structure is used for the pixel separation portion 117, it is preferable to provide a floating diffusion portion FD and / or a VSS contact region 118 in each pixel 541. Therefore, by using the configuration of the pad portions 120 and 121, the wiring connecting the first substrate 100 and the second substrate 260 can be greatly reduced.

[0449] In addition, if Fig.51As in, for example, the pad portion 120 connected to the plurality of floating diffusions FD and the pad portion 121 connected to the plurality of VSS contact regions 118 are linearly arranged alternately in the V direction. In addition, the pad portions 120 and 121 are formed at positions surrounded by the plurality of photodiodes PD, the plurality of transfer gates TG, or the plurality of floating diffusions FD. Therefore, in the first substrate 100 in which the plurality of elements are formed, elements other than the floating diffusion FD and the VSS contact region 118 can be freely arranged, thereby enabling the layout of the entire chip to be more efficient. In addition, the layout of the elements formed in each pixel sharing unit 539 can be reliably made symmetrical, thereby enabling the characteristic variation of each pixel 541 to be reduced.

[0450] The pad portions 120 and 121 include, for example, polysilicon (Poly Si), more specifically, doped polysilicon doped with impurities. The pad portions 120 and 121 preferably include a conductive material with high heat resistance such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride. Therefore, after the semiconductor layer 260S of the second substrate 260 is stacked on the first substrate 100, the pixel circuit 210 can be formed. The reason will be described below. Note that in the following description, the first manufacturing method refers to a method of forming the pixel circuit 210 after the semiconductor layer 260S of the second substrate 260 is stacked on the first substrate 100.

[0451] In this regard, it is also possible that after the pixel circuit 210 is formed in the second substrate 260, the second substrate 260 is laminated on the first substrate 100 (this is hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on each of the front surface of the first substrate 100 (the front surface of the wiring layer 100T) and the front surface of the second substrate 260 (the front surface of the wiring layer 260T). When the first substrate 100 and the second substrate 260 are laminated to each other, the electrodes for electrical connection formed on the front surface of the first substrate 100 are simultaneously in contact with the electrodes for electrical connection formed on the front surface of the second substrate 260. In this way, electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 260. Therefore, when the second manufacturing method is used to construct the imaging device 1, for example, the imaging device 1 can be manufactured using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 260. Therefore, an imaging device with high quality and high performance can be manufactured.

[0452] In the above-mentioned second manufacturing method, when the first substrate 100 and the second substrate 260 are stacked, an alignment error may occur due to the manufacturing equipment used for stacking. In addition, the first substrate 100 and the second substrate 260 have a diameter of about tens of centimeters, for example, and when the first substrate 100 and the second substrate 260 are stacked, in the microscopic area of ​​each part of the first substrate 100 and the second substrate 260, expansion and contraction of the substrate may occur. The expansion and contraction of the substrate is caused by a small time deviation generated when the substrates are in contact with each other. Due to this expansion and contraction of the first substrate 100 and the second substrate 260, an error may be generated in the position of the electrode for electrical connection formed on each front surface of the first substrate 100 and the second substrate 260. Preferably, even if there is such an error, the second manufacturing method is able to make the electrodes of the first substrate 100 and the second substrate 260 contact each other. Specifically, in consideration of the error, at least one of the electrodes of the first substrate 100 and the second substrate 260 and preferably both are enlarged. Therefore, by using the second manufacturing method, for example, the size of the electrode formed on the front surface of the first substrate 100 or the second substrate 260 (the size in the substrate plane direction) is made larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 260 along the thickness direction to the front surface.

[0453] On the other hand, in the case where the pad portions 120 and 121 include a heat-resistant conductive material, the above-mentioned first manufacturing method can be used. In the first manufacturing method, a first substrate 100 including a photodiode PD and a transfer transistor TR, etc. is formed, and then the first substrate 100 and the second substrate 260 (semiconductor layer 260S) are stacked. At this time, a pattern of an active element and a wiring layer, etc. constituting the pixel circuit 210 has not yet been formed in the second substrate 260. Since a pattern has not yet been formed in the second substrate 260, when the first substrate 100 and the second substrate 260 are stacked, even if an error occurs in the stacking position, no error occurs in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 260. This is because the pattern of the second substrate 260 is formed after the first substrate 100 and the second substrate 260 are stacked. Note that when a pattern is formed in the second substrate, for example, an exposure device for pattern formation is used to form a pattern by using the pattern formed in the first substrate 100 as an alignment target. For the reasons described above, with the first manufacturing method, an error in the stacking position between the first substrate 100 and the second substrate 260 does not constitute a problem in the manufacture of the image pickup device 1. For the same reasons, with the first manufacturing method, an error due to expansion and contraction of the substrate in the second manufacturing method does not constitute a problem in the manufacture of the image pickup device 1.

[0454] In the first manufacturing method, after the first substrate 100 and the second substrate 260 (semiconductor layer 260S) are stacked in this manner, an active element is formed in the second substrate 260. Subsequently, the through electrodes 120E and 121E and the through electrode TGV ( Fig.49 ). When forming the through electrodes 120E, 121E and TGV, for example, by using reduced projection exposure of an exposure device, a pattern of the through electrodes is formed from above the second substrate 260. Since a reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 260 and the exposure device, the magnitude of the error in the second substrate 260 is a portion of the error in the second manufacturing method (the inverse of the reduced exposure projection magnification). Therefore, in the case of constructing the imaging device 1 using the first manufacturing method, the elements formed in the first substrate 100 are easily aligned with the elements formed in the second substrate 260, so that a high-quality and high-performance imaging device can be manufactured.

[0455] The image pickup device 1 manufactured using the first manufacturing method as described above has features different from those of the image pickup device manufactured using the second manufacturing method. Specifically, in the image pickup device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E and TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 260 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E and TGV have a tapered shape, the tapered shape has a certain inclination. The image pickup device 1 having such through electrodes 120E, 121E and TGV promotes the miniaturization of the pixel 541.

[0456] In this regard, when the image pickup device 1 is manufactured using the first manufacturing method, since the active element is formed in the second substrate 260 after the first substrate 100 and the second substrate 260 (semiconductor layer 260S) are stacked, the first substrate 100 is affected by the heat treatment required during the formation of the active element. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided in the first substrate 100. For example, for the pad portions 120 and 121, it is preferable to use a material having a higher melting point than at least a part of the wiring material contained in the wiring layer 260T of the second substrate 260 (i.e., providing higher heat resistance). For example, for the pad portions 120 and 121, a conductive material with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, is used. Therefore, the image pickup device 1 can be manufactured using the above-mentioned first manufacturing method.

[0457] The passivation film 126 is provided on the entire front surface of the semiconductor layer 100S in a manner covering the pad portions 120 and 121, for example. Fig.49). The passivation film 126 includes, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 via the passivation film 126. The interlayer insulating film 123 is, for example, disposed on the entire front surface of the semiconductor layer 100S. The interlayer insulating film 123 includes, for example, a silicon oxide (SiO) film. The bonding film 124 is disposed at a bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 260. Specifically, the bonding film 124 contacts the second substrate 260. The bonding film 124 is disposed on the entire main surface of the first substrate 100. The bonding film 124 includes, for example, a silicon nitride film.

[0458] The light receiving lens 401 faces the semiconductor layer 100S ( Fig.49 ). The light receiving lens 401 is provided at a position facing, for example, each photodiode PD of the pixels 541A, 541B, 541C, and 541D.

[0459] The second substrate 260 includes a semiconductor layer 260S and a wiring layer 260T arranged in sequence from the first substrate 100 side. The semiconductor layer 260S includes a silicon substrate. In the semiconductor layer 260S, a well region 211 is provided in a manner extending in the thickness direction. The well region 211 is, for example, a P-type semiconductor region. The second substrate 20 is provided with a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is, for example, provided on the front side (wiring layer 260T side) of the semiconductor layer 260S. In the imaging device 1, the second substrate 260 is stacked on the first substrate 100 in such a manner that the front side (wiring layer 100T side) of the first substrate 100 faces the back side (semiconductor layer 260S side) of the second substrate 260. In other words, the second substrate 260 is stacked on the first substrate 100 face to back.

[0460] Figure 52 to Figure 56 An example of a planar configuration of the second substrate 260 is schematically shown. Fig.52 The configuration of the pixel circuit 210 provided near the front surface of the semiconductor layer 260S is shown. Fig.53 The configurations of the wiring layer 260T (specifically, a first wiring layer W1 described below), the semiconductor layer 260S connected to the wiring layer 260T, and the respective parts of the first substrate 100 are schematically shown. Figure 54 to Figure 56 An example of a planar structure of the wiring layer 260T is shown. Figure 52 to Figure 56 as well as Fig.49 The structure of the second substrate 260 will be described together. Fig.52 and Fig.53The outline of the photodiode PD (the boundary between the pixel separation portion 117 and the photodiode PD) is shown by a dotted line, and the boundary between the element separation region 213 or the insulating region 212 and the portion of the semiconductor layer 260S overlapping with the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dashed line. On one side in the channel width direction, the portion of the second substrate 260 overlapping with the gate electrode of the amplification transistor AMP is provided with the boundary between the semiconductor layer 260S and the element separation region 213 and the boundary between the element separation region 213 and the insulating region 212.

[0461] The second substrate 260 is provided with an insulating region 212 for dividing the semiconductor layer 260S into pieces and an element separation region 213 ( Fig.49 ). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, through electrodes 120E and 121E of two pixel sharing units 539 connected to the two pixel circuits 210 and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) are arranged ( Fig.53 ).

[0462] The insulating region 212 has a thickness substantially the same as that of the semiconductor layer 260S ( Fig.49 ). The semiconductor layer 260S is divided into several pieces by the insulating region 212. The through electrodes 120E and 121E and the through electrode TGV are arranged in the insulating region 212. The insulating region 212 includes, for example, silicon oxide.

[0463] The through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings (the first wiring W1, the second wiring W2, the third wiring W3, and the fourth wiring W4 described below) in the wiring layer 260T. The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 126, and the lower ends of the through electrodes 120E and 121E are connected to the pad portions 120 and 121 ( Fig.49 ). The through electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210. Specifically, the through electrode 120E electrically connects the floating diffusion portion FD of the first substrate 100 and the pixel circuit 210 of the second substrate 260. The through electrode 121E is used to electrically connect the pad portion 121 and the reference potential line VSS in the wiring layer 260T. Specifically, the through electrode 121E electrically connects the VSS contact area 118 of the first substrate 100 and the reference potential line VSS in the second substrate 260.

[0464] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 260T. The through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 126, and the interlayer insulating film 119, and the lower end of the through electrode TGV is connected to the transmission gate TG ( Fig.49 The through-electrode TGV as described above is used to electrically connect the transfer gates TG (transfer gates TG1, TG2, TG3, and TG4) of the respective pixels 541A, 541B, 541C, and 541D to the wiring (a portion of the row drive signal line 542, in particular, the following Fig.55 Specifically, the through electrode TGV electrically connects the transfer gate TG of the first substrate 100 to the wiring TRG of the second substrate 260 to transmit the driving signal to each transfer transistor TR (transmission transistors TR1, TR2, TR3 and TR4).

[0465] The insulating region 212 is a region insulated from the semiconductor layer 260S and provided with through electrodes 120E and 121E and through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 260. For example, in the insulating region 212 provided between two pixel circuits 210 (pixel sharing unit 539) adjacent to each other in the H direction, through electrodes 120E and 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel circuits 210 are provided. The insulating region 212 is provided, for example, to extend in the V direction ( Fig.52 and Fig.53 In this regard, the arrangement of the horizontal portion TGb of the transfer gate TG is designed so that the position of the through electrode TGV in the H direction is closer to the position of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGa ( Fig.50 and Fig.53). For example, the through electrode TGV is arranged at approximately the same position as each of the through electrodes 120E and 121E in the H direction. Therefore, the through electrodes 120E and 121E and the through electrode TGV can be arranged together in the insulating region 212 extending along the V direction. In another arrangement example, the horizontal portion TGb can be arranged only in the area overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, and, for example, the through electrode TGV is arranged approximately in the central part of each pixel 541 in the H direction and the V direction. At this time, the position of the through electrode TGV in the H direction is significantly misaligned with the position of each of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is arranged around the through electrode TGV and the through electrodes 120E and 121E for electrical insulation from the nearby semiconductor layer 260S. In the case where the position of the through electrode TGV in the H direction is significantly away from the positions of the through electrodes 120E and 121E in the H direction, it is necessary to independently provide the insulating region 212 around each of the through electrodes 120E, 121E and TGV. Therefore, the semiconductor layer 260S is divided into small pieces. In contrast, by arranging the through electrodes 120E and 121E and the through electrode TGV together in the insulating region 212 extending in the V direction, the size of the semiconductor layer 260S in the H direction can be increased. Therefore, a large area can be provided for the semiconductor element formation region in the semiconductor layer 260S. Therefore, for example, the size of the amplifier transistor AMP can be increased, so that noise can be reduced.

[0466] As reference Fig.49 As described above, the pixel sharing unit 539 has the following structure: wherein the pixel sharing unit 539 electrically connects each floating diffusion portion FD provided in each of the plurality of pixels 541, and the plurality of pixels 541 share one pixel circuit 210. In addition, each floating diffusion portion FD is electrically connected by a pad portion 120 provided in the first substrate 100 ( Fig.49 and Fig.51 ). The electrical connection portion (pad portion 120) provided in the first substrate 100 is electrically connected to the pixel circuit 210 provided in the second substrate 260 via a through electrode 120E. In another structural example, an electrical connection portion between each floating diffusion portion FD may be provided in the second substrate 260. In this case, the pixel sharing unit 539 is provided with four through electrodes respectively connected to the floating diffusion portions FD1, FD2, FD3 and FD4. Therefore, in the second substrate 260, more through electrodes penetrate the semiconductor layer 260S, thereby expanding the insulating region 212 that insulates the periphery of the through electrodes. In contrast, the structure having the pad portion 120 provided in the first substrate 100 ( Fig.49 and Fig.51) can reduce the number of through electrodes and can reduce the size of the insulating region 212. Therefore, a large area can be provided for the semiconductor element formation region in the semiconductor layer 260S. This can increase the size of the amplifier transistor AMP, for example, thereby reducing possible noise.

[0467] An element separation region 213 is provided on the front side of the semiconductor layer 260S. The element separation region 213 has an STI (Shallow Trench Isolation) structure. In the element separation region 213, the semiconductor layer 260S is dug out in the thickness direction (perpendicular to the main surface of the second substrate 260), and an insulating film is embedded in the dug-out portion. The insulating film includes, for example, silicon oxide. The element separation region 213 separates a plurality of transistors constituting the pixel circuit 210 into a plurality of elements according to the layout of the pixel circuit 210. The semiconductor layer 260S (specifically, the well region 211) extends below the element separation region 213 (deep part of the semiconductor layer 260S).

[0468] Now, refer to Fig.50 , Fig.51 and Fig.52 , the difference in outer shape (outer shape in the substrate plane direction) between the pixel sharing unit 539 in the first substrate 100 and the pixel sharing unit 539 in the second substrate 260 will be described.

[0469] In the image pickup device 1, the pixel sharing unit 539 is provided across both the first substrate 100 and the second substrate 260. For example, the outer shape of the pixel sharing unit 539 provided in the first substrate 100 is different from the outer shape of the pixel sharing unit 539 provided in the second substrate 260.

[0470] exist Fig.50 and Fig.51 , the outlines of pixels 541A, 541B, 541C, and 541D are shown with alternating long dashed lines and short dashed lines, and the outer shape of the pixel sharing unit 539 is shown with a bold line. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to the pixels 541A and 541B in the V direction. Specifically, the pixel sharing unit 539 of the first substrate 100 includes four pixels 541 in two adjacent rows and two adjacent columns, and has a substantially square outer shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a spacing of two pixels in the H direction (corresponding to the spacing of the two pixels 541) and at a spacing of two pixels in the V direction (corresponding to the spacing of the two pixels 541).

[0471] exist Fig.52 and Fig.53 , the outlines of the pixels 541A, 541B, 541C, and 541D are shown with alternating long dashed lines and short dashed lines, and the outer shape of the pixel sharing unit 539 is shown with a bold line. For example, compared with the outer shape of the pixel sharing unit 539 of the first substrate 100, the outer shape of the pixel sharing unit 539 of the second substrate 260 is smaller in the H direction but larger in the V direction. For example, the size (area) of the pixel sharing unit 539 of the second substrate 260 is formed to correspond to one pixel in the H direction and four pixels in the V direction. Specifically, the size of the pixel sharing unit 539 of the second substrate 260 is formed to correspond to pixels arranged in an adjacent row and adjacent four columns, and the pixel sharing unit 539 of the second substrate 260 has a substantially rectangular outer shape.

[0472] For example, each pixel circuit 210 includes a selection transistor SEL, an amplifier transistor AMP, a reset transistor RST, and an FD conversion gain switching transistor FDG ( Fig.52 As described above, when each pixel circuit 210 has a substantially rectangular shape, it is possible to Fig.52 Four transistors (select transistor SEL, amplifier transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) are arranged in parallel in the diffusion region (V direction in the center). Therefore, the drain of the amplifier transistor AMP and the drain of the reset transistor RST can be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, a substantially square formation region can be provided for each pixel circuit 210 (see the following Fig.65 ). In this case, two transistors are arranged in one direction, so that it is difficult to share the drain of the amplifier transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by providing a substantially rectangular formation area for the pixel circuit 210, it is easy to arrange the four transistors adjacent to each other, so that the formation area of ​​the pixel circuit 210 can be made smaller. In other words, the pixel can be miniaturized. In addition, when it is not necessary to make the formation area of ​​the pixel circuit 210 smaller, the formation area of ​​the amplifier transistor AMP can be expanded to reduce noise.

[0473] For example, in addition to the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the front surface of the semiconductor layer 260S. The VSS contact region 218 includes, for example, a P-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring in the wiring layer 260T and the through electrode 121E. The VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG across the element separation region 213 ( Fig.52 ).

[0474] Now, refer to Fig.51 and Fig.52 , the positional relationship between the pixel sharing unit 539 provided in the first substrate 100 and the pixel sharing unit 539 provided in the second substrate 260 will be described. For example, one of the two pixel sharing units 539 arranged side by side in the V direction of the first substrate 100 (for example, Fig.51 The upper pixel sharing unit 539 in the page of FIG. 260 is connected to one of the two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 (for example, Fig.52 For example, the other of the two pixel sharing units 539 arranged in parallel in the V direction of the first substrate 100 (for example, Fig.51 The lower pixel sharing unit 539 in the page of FIG. 260 is connected to the other of the two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 (for example, Fig.52 The right pixel sharing unit 539 in the page).

[0475] For example, for two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout in which the internal layout of the other pixel sharing unit 539 is reversed in the V direction and the H direction. The effect of this layout will be described below.

[0476] In the two pixel sharing units 539 arranged in parallel in the V direction of the first substrate 100, each pad portion 120 is disposed in the central portion of the outer shape of the pixel sharing unit 539, that is, in the central portion of the pixel sharing unit 539 in the V direction and the H direction ( Fig.51). On the other hand, since the pixel sharing unit 539 of the second substrate 260 has a generally rectangular shape that is long in the V direction, for example, the amplifier transistor AMP connected to the pad portion 120 is set at a position that is deviated toward the upper side of the page of the figure relative to the center of the pixel sharing unit 539 in the V direction. For example, when two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260 have the same internal layout, the amplifier transistor AMP of one pixel sharing unit 539 and the pad portion 120 (for example, Figure 7 The distance between the pad portion 120 of the upper pixel sharing unit 539 in the page is relatively short. However, the amplifying transistor AMP of another pixel sharing unit 539 and the pad portion 120 (for example, Figure 7 The distance between the pad portion 120 of the lower pixel sharing unit 539 in the page is longer. Therefore, the area of ​​the wiring required to connect the amplifier transistor AMP and the pad portion 120 is increased, and the increased area may complicate the wiring layout of the pixel sharing unit 539. This in turn may affect the miniaturization of the camera device 1.

[0477] On the contrary, in the case where the internal layout of one of the two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260 is reversed at least in the V direction relative to the internal layout of the other pixel sharing unit 539, the distance between the amplifier transistor AMP and the pad portion 120 can be reduced in both pixel sharing units 539. Therefore, compared with a configuration in which the two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260 have the same layout, this configuration is conducive to miniaturization of the image pickup device 1. Note that the planar layout of each pixel sharing unit 539 in the second substrate 260 is Fig.52 The range shown is laterally symmetrical, but the following includes Fig.53 The planar layout of the illustrated layout of the first wiring layer W1 is laterally asymmetric.

[0478] In addition, preferably, the internal layout of one of the two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 is also reversed in the H direction relative to the internal layout of the other pixel sharing unit 539. The reason for this will be described below. Fig.53As shown, two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 are respectively connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged in the H direction at the central portion of the two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 (arranged between the two pixel sharing units 539 arranged in parallel along the H direction). Therefore, in the case where the internal layout of one of the two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 is also reversed in the H direction relative to the internal layout of the other pixel sharing unit 539, the distance between each of the plurality of pixel sharing units 539 of the second substrate 260 and each of the pad portions 120 and 121 can be reduced. In other words, the miniaturization of the image pickup device 1 is further promoted.

[0479] In addition, the outline of the pixel sharing unit 539 of the second substrate 260 does not need to be aligned with any outline of the pixel sharing unit 539 of the first substrate 100. For example, one of the two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260 (e.g., Fig.53 A contour line (for example, Fig.53 The upper side contour line in the page of the first substrate 100 is arranged on the corresponding contour line in the V direction of the pixel sharing unit 539 (for example, Fig.51 In addition, the other of the two pixel sharing units 539 arranged in parallel in the H direction of the second substrate 260 (for example, Fig.53 Another contour line in the V direction of the contour line (for example, Fig.53 The lower side contour line in the page of the first substrate 100 is arranged in the V direction of the pixel sharing unit 539 of the first substrate 100. The corresponding other contour line (for example, Fig.51 By arranging the pixel sharing unit 539 of the second substrate 260 and the pixel sharing unit 539 of the first substrate 100 opposite to each other in this way, the distance between the amplifying transistor AMP and the pad portion 120 can be reduced. Therefore, it is conducive to the miniaturization of the camera device 1.

[0480] In addition, the contour lines of the plurality of pixel sharing units 539 of the second substrate 260 do not need to be aligned with each other. For example, the contour lines in the V direction of two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260 are not aligned with each other. This can reduce the distance between the amplifier transistor AMP and the pad portion 120. Therefore, it is conducive to the miniaturization of the camera device 1.

[0481] refer to Fig.51and Fig.53 , the repeated arrangement of the pixel sharing unit 539 in the pixel array section 540 will be described. The pixel sharing unit 539 of the first substrate 100 has a size corresponding to two pixels 541 in the H direction and a size corresponding to two pixels 541 in the V direction ( Fig.51 ). For example, in the pixel array portion 540 of the first substrate 100, the pixel sharing units 539 having the above-mentioned sizes corresponding to the four pixels 541 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch corresponding to the two pixels 541) and at a pitch of two pixels in the V direction (a pitch corresponding to the two pixels 541). Alternatively, in the pixel array portion 540 of the first substrate 100, a pair of pixel sharing units 539 may be provided, the pair of pixel sharing units 539 including two pixel sharing units 539 arranged adjacent to each other in the V direction. In the pixel array portion 540 of the first substrate 100, for example, the paired pixel sharing units 539 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch corresponding to the two pixels 541) and at a pitch of four pixels in the V direction (a pitch corresponding to the four pixels 541). The pixel sharing unit 539 of the second substrate 260 has a size corresponding to one pixel 541 in the H direction and a size corresponding to four pixels 541 in the V direction ( Fig.53 ). For example, the pixel array portion 540 of the second substrate 260 is provided with a pair of pixel sharing units 539, which includes two pixel sharing units 539 having the above-mentioned size corresponding to the four pixels 541. Such pixel sharing units 539 are arranged adjacent to each other in the H direction, but are not aligned with each other in the V direction. In the pixel array portion 540 of the second substrate 260, for example, the paired pixel sharing units 539 are repeatedly arranged adjacent to each other without gaps in the H direction at a spacing of two pixels (a spacing corresponding to the two pixels 541) and in the V direction at a spacing of four pixels (a spacing corresponding to the four pixels 541). By repeatedly arranging such pixel sharing units 539, the pixel sharing units 539 can be arranged without gaps. Therefore, it is conducive to the miniaturization of the camera device 1.

[0482] Preferably, the amplifying transistor AMP has a three-dimensional structure such as a Fin structure, for example. Fig.49 ). This increases the size of the effective gate width, thereby being able to reduce possible noise. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG each have a planar structure, for example. The amplifier transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0483] The wiring layer 260T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221, for example, contacts the front surface of the semiconductor layer 260S and covers the entire front surface of the semiconductor layer 260S. The passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. An interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The interlayer insulating film 222 separates the plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4) from each other. The interlayer insulating film 222 includes, for example, silicon oxide.

[0484] The wiring layer 260T is provided with a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 261 and 261 in order from the semiconductor layer 260S side, and the above components are insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 is provided with a plurality of connection portions for connecting the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the lower layer of the wiring layer. The connection portion includes a connection hole, which is provided in the interlayer insulating film 222, and a conductive material is embedded in the connection hole. For example, the interlayer insulating film 222 is provided with a connection portion 218V, which connects the first wiring layer W1 and the VSS contact area 218 of the semiconductor layer 260S. For example, the hole diameter of the connection portion of the element connecting the second substrate 260 is different from the hole diameter of each of the through electrodes 120E and 121E and the through electrode TGV. Specifically, the aperture of the connection hole of the element connecting the second substrate 260 is preferably smaller than the aperture of each of the through electrodes 120E and 121E and the through electrode TGV. The reason will be explained below. The depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 260T is smaller than the depth of the through electrodes 120E and 121E and the through electrode TGV. Therefore, it is easier to embed the conductive material in the connection hole of the connection portion than in the through electrodes 120E and 121E and the through electrode TGV. By making the aperture of the connection portion smaller than the aperture of each of the through electrodes 120E and 121E and the through electrode TGV, it is beneficial to miniaturize the camera device 1.

[0485] For example, the first wiring layer W1 connects the through-electrode 120E to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1, for example, connects the through-electrode 121E and the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 260S to the VSS contact region 118 of the semiconductor layer 100S.

[0486] Now, we will use Figure 54 to Figure 56 The planar structure of the wiring layer 260T will be described. Fig.54 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Fig.55 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Fig.56 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0487] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction). Fig.55 ). The above wiring corresponds to the reference Fig.47 The plurality of row drive signal lines 542. Wirings TRG1, TRG2, TRG3 and TRG4 are used to transmit drive signals to transmission gates TG1, TG2, TG3 and TG4, respectively. Wirings TRG1, TRG2, TRG3 and TRG4 are connected to transmission gates TG1, TG2, TG3 and TG4, respectively, via the second wiring layer W2, the first wiring layer W1 and the through-electrode 120E. Wiring SELL is used to transmit the drive signal to the gate of the selection transistor SEL, wiring RSTL is used to transmit the drive signal to the gate of the reset transistor RST, and wiring FDGL is used to transmit the drive signal to the gate of the FD conversion gain switching transistor FDG. Wirings SELL, RSTL and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0488] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 ( Fig.56 ). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0489] In a plan view, the contact portions 261 and 262 may be disposed at positions where the contact portions 261 and 262 overlap with the pixel array portion 540 (eg, Fig.46 ) or disposed in a peripheral portion 540B outside the pixel array section 540 (for example, Fig.49 ). Contact portions 261 and 262 are provided on the front surface of the second substrate 260 (side surface of the wiring layer 260T). The contact portions 261 and 262 include, for example, metals such as Cu (copper) and Al (aluminum). The contact portions 261 and 262 are exposed on the front surface of the wiring layer 260T (side surface of the third substrate 300). The contact portions 261 and 262 are used to electrically connect the second substrate 260 and the third substrate 300, and are used to laminate the second substrate 260 onto the third substrate 300.

[0490] Fig.49 2 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 260. The peripheral circuit may include a portion of the row driving unit 520 or a portion of the column signal processing unit 550, etc. Alternatively, as Fig.46 As shown, in the case where no peripheral circuit is provided in the peripheral portion 540B of the second substrate 260 , the connection hole portions H1 and H2 may be provided near the pixel array portion 540 .

[0491] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in sequence starting from the second substrate 260 side. For example, the front surface of the semiconductor layer 300S is provided on the second substrate 260 side. The semiconductor layer 300S includes a silicon substrate. A circuit is provided in the front side portion of the semiconductor layer 300S. Specifically, the front side portion of the semiconductor layer 300S is provided with, for example, at least some of the input portion 510A, the row drive portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 260 includes, for example, an interlayer insulating film, a plurality of wiring layers separated from each other by the interlayer insulating film, and contact portions 305 and 302. The contact portions 305 and 302 are exposed on the front surface (side surface of the second substrate 260) of the wiring layer 300T, the contact portion 305 contacts the contact portion 261 of the second substrate 260, and the contact portion 302 contacts the contact portion 262 of the second substrate 260. The contact portions 305 and 302 are electrically connected to a circuit (for example, at least one of the input portion 510A, the row driving portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, or the output portion 510B) formed in the semiconductor layer 300S. The contact portions 305 and 302 include, for example, any metal such as Cu (copper) and aluminum (Al). For example, the external terminal TA is connected to the input portion 510A via the connection hole portion H1, and the external terminal TB is connected to the output portion 510B via the connection hole portion H2.

[0492] Now, features of the image pickup device 1 will be described.

[0493] Typically, an image pickup device includes a photodiode and a pixel circuit as main components. In this regard, by increasing the area of ​​the photodiode, the amount of charge generated by photoelectric conversion is increased, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal. Therefore, the image pickup device is enabled to output better image data (image information). On the other hand, by increasing the size of the transistor included in the pixel circuit (particularly, the size of the amplifying transistor), the noise that may occur in the pixel circuit is reduced, thereby improving the S / N ratio of the pixel signal. Therefore, the image pickup device is enabled to output better image data (image information).

[0494] However, in an imaging device in which a photodiode and a pixel circuit are provided in the same semiconductor substrate, if the area of ​​the photodiode is increased within a limited area of ​​the semiconductor substrate, the size of the transistor included in the pixel circuit may be reduced. In addition, increasing the size of the transistor included in the pixel circuit may reduce the area of ​​the photodiode.

[0495] In order to solve these problems, for example, the image pickup device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to overlap with the photodiode PD. Therefore, it is possible to maximize the area of ​​the photodiode PD within a limited area of ​​the semiconductor substrate, and maximize the size of the transistor included in the pixel circuit 210. Therefore, the S / N ratio of the pixel signal can be improved, and the image pickup device 1 can output better image data (image information).

[0496] When a structure is implemented in which a plurality of pixels 541 share one pixel circuit 210 and the pixel circuit 210 is arranged to overlap the photodiode PD, a plurality of wirings connected to the pixel circuit 210 extend from the floating diffusion FD of the corresponding plurality of pixels 541. In order to ensure that the area of ​​the semiconductor substrate 260 for forming the pixel circuit 210 is large, for example, a plurality of extended wirings can be connected together and formed into one integral connection wiring. For a plurality of wirings extending from the VSS contact region 118, a plurality of extended wirings can also be connected together and formed into one integral connection wiring.

[0497] For example, in the case where the connection wiring is formed in the semiconductor substrate 260 for forming the pixel circuit 210, the connection wiring connects and integrates a plurality of wirings extending from the floating diffusion portions FD of the corresponding plurality of pixels 541, and the area in which the transistors included in the pixel circuit 210 are formed may be reduced. Similarly, in the case where the connection wiring is formed in the semiconductor substrate 260 for forming the pixel circuit 210, the above-mentioned connection wiring connects and integrates a plurality of wirings extending from the VSS contact regions 118 of the corresponding plurality of pixels 541 into one wiring, and the area in which the transistors included in the pixel circuit 210 are formed may be reduced.

[0498] In order to solve these problems, for example, the camera device 1 of the present embodiment has a structure in which a plurality of pixels 541 share a pixel circuit 210, the shared pixel circuit 210 is arranged to overlap with the photodiode PD, and the first substrate 100 is provided with two types of connecting wiring, one of which connects the floating diffusion portions FD of the corresponding plurality of pixels 541 together and integrates them into a floating diffusion portion FD, and the other of which connects the VSS contact areas 118 included in the corresponding plurality of pixels 541 together and integrates them into one VSS contact area 118.

[0499] In this regard, when the second manufacturing method described above is used as a manufacturing method for providing the first substrate 100 with two kinds of connection wiring, for example, one of the connection wirings connects the floating diffusions FD of the corresponding plurality of pixels 541 together and integrates them into one floating diffusion FD, and the other of the connection wirings connects the VSS contact regions 118 included in the corresponding plurality of pixels 541 together and integrates them into one VSS contact region 118, and can be manufactured using an appropriate process corresponding to the configuration of the first substrate 100 and the second substrate 260. Then, an image pickup device with high quality and high performance can be manufactured. In addition, the connection wirings for the first substrate 100 and the second substrate 260 can be formed using a simple process. Specifically, in the case of using the second manufacturing method described above, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact region 118 are respectively provided on the front surface of the first substrate 100 and the front surface of the second substrate 260 constituting the stacking interface between the first substrate 100 and the second substrate 260. Furthermore, when the first substrate 100 and the second substrate 260 are stacked, misalignment may occur between the electrodes provided on the front surfaces of the two substrates, in which case, in order to allow the electrodes formed on the front surfaces of the two substrates to contact each other despite the misalignment, the electrodes formed on the front surfaces of the two substrates are preferably enlarged. This may make it difficult to provide the electrodes in a limited area of ​​each pixel included in the image pickup device 1.

[0500] In order to eliminate the disadvantage of requiring a large electrode at the stacking interface between the first substrate 100 and the second substrate 260, for example, the camera device 1 of the present embodiment can use the above-mentioned first manufacturing method as a manufacturing method, wherein a plurality of pixels 541 share a pixel circuit 210 and the shared pixel circuit 210 is arranged to overlap with the photodiode PD. This facilitates alignment between the elements formed in the first substrate 100 and the elements formed in the second substrate 260, thereby enabling the manufacture of a high-quality and high-performance camera device. In addition, a specific structure resulting from the use of the manufacturing method can be provided. Specifically, a structure is provided in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 260S and the wiring layer 260T of the second substrate 260 are stacked in sequence, in other words, a structure is provided in which the first substrate 100 and the second substrate 260 are stacked face to face. Furthermore, through electrodes 120E and 121E extending from the front surface of the semiconductor layer 260S of the second substrate 260 through the semiconductor layer 260S and the wiring layer 100T of the first substrate 100 to the front surface of the semiconductor layer 100S of the first substrate 100 are provided.

[0501] Regarding the structure in which the first substrate 100 is provided with connecting wiring that connects the floating diffusion portions FD of the corresponding multiple pixels 541 together and integrates them into one floating diffusion portion FD, and connecting wiring that connects the VSS contact areas 118 included in the corresponding multiple pixels 541 together and integrates them into one VSS contact area 118, when the structure and the second substrate 260 are stacked using the first manufacturing method and the pixel circuit 210 is formed in the second substrate 260, the heat treatment required during the formation of the active elements included in the pixel circuit 210 may have an adverse effect on the connecting wiring formed in the first substrate 100.

[0502] Therefore, in order to solve the problem of adverse effects of heat treatment on the connection wiring during the formation of the active element, ideally, the image pickup device 1 of the present embodiment is desirably configured so that a conductive material having high heat resistance is used for both the connection wirings, one connecting wiring that connects the floating diffusions FD of the corresponding plurality of pixels 541 together and integrates into one floating diffusion FD, and the other connecting wiring that connects the VSS contact regions 118 included in the corresponding plurality of pixels 541 together and integrates into one VSS contact region 118. Specifically, as the conductive material having high heat resistance, a material having a higher melting point than at least a part of the wiring material included in the wiring layer 260T of the second substrate 260 can be used.

[0503] As described above, for example, the image pickup device 1 of the present embodiment includes: (1) a structure in which the first substrate 100 and the second substrate 260 are stacked facing each other (specifically, the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 260S and the wiring layer 260T of the second substrate 260 are stacked in this order); and (2) a structure in which the through electrodes 120E and 125E are provided, the through electrodes 120E and 125E extending from the front side of the semiconductor layer 260S of the second substrate 260 through the semiconductor layer 260T. 60S and the wiring layer 100T of the first substrate 100 to the front surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which a conductive material having high heat resistance is used to form two types of connection wirings, one of which connects the floating diffusions FD included in the corresponding plurality of pixels 541 together and integrates into one floating diffusion FD, and the other of which connects the VSS contact areas 118 included in the corresponding plurality of pixels 541 together and integrates into one VSS contact area 118. Therefore, it is possible to provide the first substrate 100 with two types of connection wirings, one of which connects the floating diffusions FD included in the corresponding plurality of pixels 541 together and integrates into one floating diffusion FD, and the other of which connects the VSS contact areas 118 included in the corresponding plurality of pixels 541 together and integrates into one VSS contact area 118, without providing a large electrode at the interface between the first substrate 100 and the second substrate 260.

[0504] [Operation of the Image Capture Device 1]

[0505] Now, refer to Fig.57 and Fig.58 The operation of the imaging device 1 will be described. Fig.57 and Fig.58 Corresponds to the addition of an arrow indicating the signal path Fig.46 . Fig.57 The paths of input signals input from the outside to the image pickup device 1 and power supply potential and reference potential are shown by arrows. Fig.58The signal path of the pixel signal output from the image pickup device 1 to the outside is shown by the arrow. For example, the input signal (e.g., pixel clock and synchronization signal) input to the image pickup device 1 via the input portion 510A is transmitted to the row drive portion 520 (which generates a row drive signal) of the third substrate 300. The row drive signal is transmitted to the second substrate 260 via the contact portions 305 and 261. In addition, the row drive signal reaches the respective pixel sharing units 539 of the pixel array portion 540 via the row drive signal line 542 in the wiring layer 260T. For the row drive signal that has reached the respective pixel sharing units 539 of the second substrate 260, a drive signal other than the drive signal for the transmission gate TG is input to the pixel circuit 210 to drive the transistor included in the pixel circuit 210. The drive signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV to drive the pixels 541A, 541B, 541C, and 541D ( Fig.57 ). In addition, the power supply potential and the reference potential provided to the input portion 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 260 via the contacts 305 and 261, and are provided to the pixel circuit 210 of each pixel sharing unit 539 via the wiring in the wiring layer 260T. The reference potential is also provided to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 125E. On the other hand, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 260 for each pixel sharing unit 539 via the through electrode 120E. A pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 262 and 302. The pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300 and then output to the outside via the output section 510B.

[0506] [Effect]

[0507] In the present embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are arranged in different substrates (first substrate 100 and second substrate 260). Compared with the configuration in which pixels 541A, 541B, 541C, and 541D and pixel circuit 210 are formed in the same substrate, this configuration can increase the area of ​​pixels 541A, 541B, 541C, and 541D and pixel circuit 210. As a result, the amount of pixel signals generated by photoelectric conversion can be increased, and possible transistor noise from pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information). In addition, miniaturization of the image pickup device 1 can be achieved (in other words, the pixel size and the size of the image pickup device 1 are reduced). By reducing the pixel size, the image pickup device 1 can increase the number of pixels per unit area and output high-quality images.

[0508] In addition, in the image pickup device 1, the first substrate 100 and the second substrate 260 are electrically connected to each other through the through electrodes 120E and 125E provided in the insulating region 212. For example, the following method is also possible: the first substrate 100 and the second substrate 260 are connected to each other by bonding pad electrodes, or by using through electrodes (for example, TSV (Through Si Vias: through silicon vias)) that penetrate the semiconductor layer. Compared with this method, by providing the through electrodes 120E and 125E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 260 can be reduced. Therefore, the pixel size and the size of the image pickup device 1 can be reduced. In addition, by further reducing the area of ​​each pixel, the resolution can be improved. When it is not necessary to reduce the chip size, the formation area of ​​the pixels 541A, 541B, 541C and 541D and the pixel circuit 210 can be expanded. As a result, the amount of pixel signals generated by photoelectric conversion can be increased, and possible transistor noise from the transistors included in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information).

[0509] In addition, in the image pickup device 1, the pixel circuit 210 and the column signal processing section 550 and the image signal processing section 560 are both provided in different substrates (the second substrate 260 and the third substrate 300). Compared with a configuration in which the pixel circuit 210 and the column signal processing section 550 and the image signal processing section 560 are both formed in the same substrate, this configuration can increase the area of ​​the pixel circuit 210 and the area of ​​the column signal processing section 550 and the image signal processing section 560. Therefore, possible noise from the column signal processing section 550 can be reduced, and a more advanced image processing circuit can be installed in the image signal processing section 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information).

[0510] In addition, in the image pickup device 1, a pixel array section 540 is provided in the first substrate 100 and the second substrate 260, and a column signal processing section 550 and an image signal processing section 560 are provided in the third substrate 300. In addition, contact sections 261, 262, 305, and 302 for connecting the second substrate 260 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 261, 262, 305, and 302 can be freely arranged without being interfered by various wirings included in the pixel array. Therefore, the contact sections 261, 262, 305, and 302 can be used to electrically connect the second substrate 260 and the third substrate 300. By using the contact sections 261, 262, 305, and 302, for example, the column signal processing section 550 and the image signal processing section 560 can be arranged more freely. Therefore, possible noise from the column signal processing section 550 can be reduced, and a more advanced image processing circuit can be installed in the image signal processing section 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information).

[0511] In addition, in the image pickup device 1, the pixel separation unit 117 penetrates the semiconductor layer 100S. Therefore, even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is reduced by reducing the area of ​​each pixel, color mixing between the pixels 541A, 541B, 541C, and 541D can be reduced. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information).

[0512] In addition, in the image pickup device 1, a pixel circuit 210 is provided in each pixel sharing unit 539. Compared with a configuration in which a pixel circuit 210 is provided in each of the pixels 541A, 541B, 541C, and 541D, this configuration can expand the formation area of ​​transistors (amplifier transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switching transistor FDG) used to constitute the pixel circuit 210. For example, by expanding the formation area of ​​the amplifier transistor AMP, possible noise can be reduced. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the image pickup device 1 can output better pixel data (image information).

[0513] In addition, in the image pickup device 1, the first substrate 100 is provided with a pad portion 120, which electrically connects the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the four pixels 541A, 541B, 541C, and 541D. Compared with the configuration in which the pad portion 120 as described above is provided in the second substrate 260, this configuration can reduce the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 260. Therefore, the insulating region 212 can be minimized, thereby providing a formation region (semiconductor layer 260S) of a sufficient size for the transistor constituting the pixel circuit 210. Therefore, the noise from the transistor included in the pixel circuit 210 can be reduced, and the signal-to-noise ratio of the pixel signal can be improved, while enabling the image pickup device 1 to output better pixel data (image information).

[0514] A modification of the image pickup device 1 according to the above-described embodiment will be described below. In the modification described below, the same components as those of the above-described embodiment are denoted by the same reference numerals for description.

[0515] <Modification 1>

[0516] Figure 59 to Figure 63 A modification example of the planar configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.59 The planar configuration near the front surface of the semiconductor layer 260S of the second substrate 260 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.52 . Fig.60 The configurations of the first wiring layer W1, the semiconductor layer 260S connected to the first wiring layer W1, and the respective parts of the first substrate 100 are schematically shown, and correspond to those described in the above embodiments. Fig.53 . Fig.61 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.54 . Fig.62An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.55 . Fig.63 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the example described in the above embodiment. Fig.56 .

[0517] like Fig.60 As shown, this modification shows a configuration in which the internal layout of one of the two pixel sharing units 539 arranged side by side in the H direction of the second substrate 260 (for example, the right pixel sharing unit 539 in the page of the figure) is reversed only in the H direction relative to the internal layout of the other pixel sharing unit 539 (for example, the left pixel sharing unit 539 in the page of the figure). In addition, the misalignment of the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 in the V direction is more obvious than the misalignment described in the above embodiment ( Fig.53 ). A more significant misalignment in the V direction can reduce the amplification transistor AMP of another pixel sharing unit 539 and the pad portion 120 connected to the amplification transistor AMP (arranged in parallel in the V direction) Figure 7 The distance between the pad portion 120 of the other of the two pixel sharing units 539 (the lower pixel sharing unit 539 in the page of the figure). With such a layout, Figure 59 to Figure 63 The modified example 1 of the camera device 1 shown in FIG. 1 makes it possible to make the area of ​​the pixel sharing unit 539 equal to the area of ​​the pixel sharing unit 539 of the second substrate 260 described in the above embodiment without inverting the plane layout of the two pixel sharing units 539 arranged in parallel along the H direction in the V direction. Note that the plane layout of the pixel sharing unit 539 of the first substrate 100 is different from the plane layout in the above embodiment ( Fig.50 and Fig.51 ) are the same. Therefore, the image pickup device 1 of this modification can produce the same effect as the image pickup device 1 in the above-mentioned embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 260 is not limited to the arrangement in the above-mentioned embodiment or this modification.

[0518] <Modification 2>

[0519] Figure 64 to Figure 69 A modification example of the planar configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.64 The planar structure of the first substrate 100 is schematically shown and corresponds to the planar structure of the first substrate 100 described in the above embodiment. Fig.50 . Fig.65 The planar configuration near the front surface of the semiconductor layer 260S of the second substrate 260 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.52 . Fig.66 The configurations of the first wiring layer W1, the semiconductor layer 260S connected to the first wiring layer W1, and the respective parts of the first substrate 100 are schematically shown, and correspond to those described in the above embodiments. Fig.53 . Fig.67 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.54 . Fig.68 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.55 . Fig.69 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the example described in the above embodiment. Fig.56 .

[0520] In this modification, the outer shape of each pixel circuit 210 has a substantially square planar shape ( Fig.65 In this respect, the planar configuration of the imaging device 1 in the present modification example is different from the planar configuration of the imaging device 1 in the above-described embodiment.

[0521] For example, as described in the above embodiment ( Fig.64 ), each pixel sharing unit 539 of the first substrate 100 is formed on a pixel region of two rows and two columns, and has a substantially square planar shape. For example, in each pixel sharing unit 539, the horizontal portion TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C in one pixel column extends from the position where the horizontal portion TGb overlaps with the vertical portion TGa in the H direction (more specifically, the direction toward the outer edges of the pixels 541A and 541C and the direction toward the central portion of the pixel sharing unit 539) toward the central portion of the pixel sharing unit 539, and the horizontal portion TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D in another pixel column extends from the position where the horizontal portion TGb overlaps with the vertical portion TGa in the H direction (more specifically, the direction toward the outer edges of the pixels 541B and 541D and the direction toward the outside of the pixel sharing unit 539) toward the outside of the pixel sharing unit 539. A pad portion 120 connected to the floating diffusion portion FD is provided in the central portion of the pixel sharing unit 539 (the central portion in the H direction and the V direction of the pixel sharing unit 539). The pad portion 125 connected to the VSS contact region 118 is at least in the H direction (in the V direction). Fig.64 H direction and V direction) are set at the end of the pixel sharing unit 539.

[0522] In another arrangement example, the horizontal portion TGb of the transfer gates TG1, TG2, TG3 and TG4 may be provided only in the region facing the vertical portion TGa. At this time, as described in the above embodiment, the semiconductor layer 260S may be divided into small pieces. Therefore, it becomes difficult to form a large transistor in the pixel circuit 210. On the other hand, as described in the above embodiment, when the horizontal portion TGb of the transfer gates TG1, TG2, TG3 and TG4 extends along the H direction from the position where the horizontal portion TGb overlaps with the vertical portion TGa, the width of the semiconductor layer 260S can be increased. Specifically, the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 can be arranged so that the H-direction positions of the through electrodes TGV1 and TGV3 are closely adjacent to the H-direction position of the through electrode 120E, and the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 can be arranged so that the H-direction positions of the through electrodes TGV2 and TGV4 are closely adjacent to the H-direction position of the through electrode 125E ( Fig.66 ). As described in the above embodiment, this can increase the width of the semiconductor layer 260S extending in the V direction (the size in the H direction). Therefore, the size of each transistor in the pixel circuit 210, especially the size of the amplifier transistor AMP, can be increased. As a result, the signal-to-noise ratio of the pixel signal can be improved, and the camera device 1 can output better pixel data (image information).

[0523] Each pixel sharing unit 539 of the second substrate 260 has, for example, substantially the same size as each pixel sharing unit 539 of the first substrate 100 in the H direction and the V direction, and each pixel sharing unit 539 of the second substrate 260 is, for example, disposed on an area corresponding to a pixel area of ​​approximately 2 rows × 2 columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the V direction in a semiconductor layer 260S extending along the V direction, and the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the V direction in a semiconductor layer 260S extending along the V direction. A semiconductor layer 260S in which the selection transistor SEL and the amplifier transistor AMP are disposed is adjacent to a semiconductor layer 260S in which the FD conversion gain switching transistor FDG and the reset transistor RST are disposed in the H direction across the insulating region 212. The insulating region 212 extends in the V direction ( Fig.65 ).

[0524] Now, refer to Fig.65 and Fig.66 The appearance of each pixel sharing unit 539 of the second substrate 260 is described. For example, Fig.64 The pixel sharing unit 539 of the first substrate 100 shown in FIG. 1 is arranged on one side of the pad portion 120 in the H direction ( Fig.66The amplification transistor AMP and the selection transistor SEL are arranged on the left side of the page and the other side of the pad portion 120 ( Fig.66 The FD conversion gain switching transistor FDG and the reset transistor RST of the second substrate 260 are connected. The outer shape of the shared unit 541 including the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switching transistor FDG and the reset transistor RST is determined by the following four outer edges.

[0525] The first outer edge is one end ( Fig.66 The first outer edge is set at the amplifying transistor AMP included in the pixel sharing unit 539 and at one side ( Fig.66 The first outer edge is disposed in the center portion of the element separation region 213 in the V direction between the amplifying transistor AMP and the selecting transistor SEL. The second outer edge is disposed at the other end (in the V direction) of the semiconductor layer 260S including the selecting transistor SEL and the amplifying transistor AMP. Fig.66 The second outer edge is set in the pixel sharing unit 539 included in the selection transistor SEL and in the V direction on the other side ( Fig.66 The second outer edge is disposed in the center portion of the element separation region 213 in the V direction between the selection transistor SEL and the amplifier transistor AMP. The third outer edge is disposed at the other end (in the V direction) of the semiconductor layer 260S including the reset transistor RST and the FD conversion gain switching transistor FDG. Fig.66 The third outer edge is set at the lower end of the page of the FD conversion gain switching transistor FDG included in the pixel sharing unit 539 and the other side ( Fig.66 The third outer edge is disposed in the center portion of the element separation region 213 in the V direction between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is disposed at one end (in the V direction) of the semiconductor layer 260S including the reset transistor RST and the FD conversion gain switching transistor FDG. Fig.66 The fourth outer edge is set at the reset transistor RST included in the pixel sharing unit 539 and on one side ( Fig.66 The fourth outer edge is disposed between the FD conversion gain switching transistor FDG (not shown) included in the pixel sharing unit 539 adjacent to the above-mentioned pixel sharing unit 539. More specifically, the fourth outer edge is disposed in a central portion in the V direction of the element separation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0526] In the outer shape of the pixel sharing unit 539 of the second substrate 260 including the above-mentioned first outer edge, second outer edge, third outer edge and fourth outer edge, the third outer edge and the fourth outer edge are arranged to be misaligned with the first outer edge and the second outer edge on one side of the V direction (in other words, arranged to be offset to one side of the V direction). By using this layout, the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG can be arranged as close to the pad portion 120 as possible. Therefore, this outer shape is used to reduce the area of ​​the wiring connecting the above-mentioned components, thereby facilitating the miniaturization of the camera device 1. Note that a VSS contact area 218 is provided between the semiconductor layer 260S including the selection transistor SEL and the amplifier transistor AMP and the semiconductor layer 260S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, a plurality of pixel circuits 210 have the same arrangement.

[0527] The image pickup device 1 having the second substrate 260 as described above also produces the same effects as in the above-described embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 260 is not limited to the arrangement described in the embodiment and the present modification.

[0528] <Variation 3>

[0529] Figure 70 to Figure 75 A modification example of the planar configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.70 The planar structure of the first substrate 100 is schematically shown and corresponds to the planar structure of the first substrate 100 described in the above embodiment. Fig.51 . Fig.71 The planar configuration near the front surface of the semiconductor layer 260S of the second substrate 260 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.52 . Fig.72 The configurations of the first wiring layer W1, the semiconductor layer 260S connected to the first wiring layer W1, and the respective parts of the first substrate 100 are schematically shown, and correspond to those described in the above embodiments. Fig.53 . Fig.73 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.54 . Fig.74An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.55 . Fig.75 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the example described in the above embodiment. Fig.56 .

[0530] In this modification, the semiconductor layer 260S of the second substrate 260 extends in the H direction ( Fig.72 ). Specifically, this modification substantially corresponds to Fig.65 The planar structure of the imaging device 1 shown in FIG. 1 is a structure obtained by rotating the planar structure of the imaging device 1 by 90°.

[0531] For example, as described in the above embodiment, each pixel sharing unit 539 of the first substrate 100 is formed on a pixel area of ​​2 rows×2 columns and has a substantially square planar shape ( Fig.70 ). For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixels 541A and 541B in one pixel row extend in the V direction toward the central portion of the pixel sharing unit 539, and the transfer gates TG3 and TG4 of the pixels 541C and 541D in another pixel row extend in the V direction toward the outside of the pixel sharing unit 539. A pad portion 120 connected to the floating diffusion portion FD is provided in the central portion of the pixel sharing unit 539, and at least in the V direction (in the V direction) of the pixel sharing unit 539. Fig.70 In this case, the V direction position of the through electrodes TGV1 and TGV2 of the transmission gates TG1 and TG2 is closer to the V direction position of the through electrode 120E, and the V direction position of the through electrodes TGV3 and TGV4 of the transmission gates TG3 and TG4 is closer to the V direction position of the through electrode 125E ( Fig.72 ). Therefore, for the same reason as described in the above embodiment, the width of the semiconductor layer 260S extending in the H direction (the dimension in the V direction) can be increased. Therefore, the size of the amplifier transistor AMP can be increased, thereby reducing possible noise.

[0532] In each pixel circuit 210, a selection transistor SEL and an amplifier transistor AMP are arranged in parallel in the H direction, and a reset transistor RST is adjacent to the selection transistor SEL in the V direction via an insulating region 212 ( Fig.71 ). The FD conversion gain switching transistor FDG is adjacent to the reset transistor RST in the H direction. The VSS contact region 218 is provided in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction ( Fig.74), the fourth wiring layer W4 extends in the V direction ( Fig.75 ).

[0533] The image pickup device 1 having the second substrate 260 as described above also produces the same effect as in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 260 is not limited to the arrangement described in the embodiment and this modification. For example, the semiconductor layer 260S described in the above embodiment and modification 1 may extend in the H direction.

[0534] <Variation 4>

[0535] Fig.76 A modified example of the cross-sectional configuration of the image pickup device 1 according to the above-described embodiment is schematically shown. Fig.76 Corresponding to the above embodiment Fig.46 In this modification, the image pickup device 1 includes contact portions 263, 204, 303, and 304 at positions corresponding to the central portion of the pixel array portion 540 in addition to the contact portions 261, 262, 305, and 302. In this respect, the image pickup device 1 in this modification is different from the image pickup device 1 described in the above embodiment.

[0536] The contact portions 263 and 204 are provided in the second substrate 260 and exposed at the joint surface between the second substrate 260 and the third substrate 300. The contact portions 303 and 304 are provided in the third substrate 300 and exposed at the joint surface between the third substrate 300 and the second substrate 260. The contact portion 263 contacts the contact portion 303, and the contact portion 204 contacts the contact portion 304. Specifically, in the image pickup device 1, the second substrate 260 and the third substrate 300 are connected through the contact portions 263, 204, 303 and 304 and the contact portions 261, 262, 305 and 302.

[0537] Now, we will use Fig.77 and Fig.78 The operation of the imaging device 1 will be described. Fig.77 The paths of input signals input from the outside to the image pickup device 1 and power supply potential and reference potential are shown by arrows. Fig.78The signal path of the pixel signal output from the image pickup device 1 to the outside is shown by arrows. For example, the input signal input to the image pickup device 1 via the input portion 510A is sent to the row drive portion 520 (which generates a row drive signal) of the third substrate 300. The row drive signal is sent to the second substrate 260 via the contact portions 303 and 263. In addition, the row drive signal reaches the respective pixel sharing units 539 of the pixel array portion 540 via the row drive signal line 542 in the wiring layer 260T. For the row drive signal that has reached the respective pixel sharing units 539 of the second substrate 260, a drive signal other than the drive signal for the transmission gate TG is input to the pixel circuit 210 to drive the transistor included in the pixel circuit 210. The drive signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV to drive the pixels 541A, 541B, 541C, and 541D. In addition, the power supply potential and the reference potential supplied to the input portion 510A (input terminal 511) of the third substrate 300 from the outside of the image pickup device 1 are transmitted to the second substrate 260 via the contacts 303 and 263, and supplied to the pixel circuit 210 of each pixel sharing unit 539 via the wiring in the wiring layer 260T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through-electrode 125E. On the other hand, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 260 for each pixel sharing unit 539. The pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 204 and 304. The pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300 and then output to the outside via the output section 510B.

[0538] The image pickup device 1 having the contact portions 263, 204, 303, and 304 as described above also produces the same effects as those described in the above embodiment. The position and number of the contact portions, etc. can be changed according to, for example, the circuit design of the third substrate 300 to which the wiring is connected via the contact portions 303 and 304.

[0539] <Variation 5>

[0540] Fig.79 A modification example of the cross-sectional configuration of the image pickup device 1 according to the above-described embodiment is shown. Fig.79 Corresponding to the above embodiment Fig.49In the present modification, a transfer transistor TR having a planar structure is provided in the first substrate 100. In this respect, the image pickup device 1 in the present modification is different from the image pickup device 1 described in the above embodiment.

[0541] In the transfer transistor TR, the transfer gate TG includes only the horizontal portion TGb. In other words, the transfer gate TG does not include the vertical portion TGa, and the transfer gate TG is disposed to face the semiconductor layer 100S.

[0542] The image pickup device 1 including the transfer transistor TR having a planar structure as described above also produces the same effects as those described in the above embodiment. In addition, compared with the method of providing the vertical transfer gate TG in the first substrate 100, the planar transfer gate TG provided in the first substrate 100 can form the photodiode PD to extend closer to the front surface of the semiconductor layer 100S, thereby increasing the saturation charge amount (Qs). In addition, compared with the method of forming the vertical transfer gate TG in the first substrate 100, the method of forming the planar transfer gate TG in the first substrate 100 can include fewer manufacturing steps and is less likely to produce adverse effects on the photodiode PD due to the manufacturing steps.

[0543] <Variation 6>

[0544] Fig.80 This is a modification of the pixel circuit in the image pickup device 1 according to the above-described embodiment. Fig.80 Corresponding to the above embodiment Fig.47 In this modification, the pixel circuit 210 is provided in each pixel (pixel 541A). Specifically, the pixel circuit 210 is not shared by a plurality of pixels. In this respect, the image pickup device 1 in this modification is different from the image pickup device 1 described in the above embodiment.

[0545] The imaging device 1 in this modification is similar to the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided in different substrates (the first substrate 100 and the second substrate 260). Therefore, the imaging device 1 in this modification can also produce the same effects as those of the above embodiment.

[0546] <Variation 7>

[0547] Fig.81 1 shows a modified example of the planar configuration of the pixel separation section 117 described in the above embodiment. A gap may be formed in the pixel separation section 117 surrounding each of the pixels 541A, 541B, 541C, and 541D. Specifically, the entire periphery of the pixels 541A, 541B, 541C, and 541D does not need to be surrounded by the pixel separation section 117. For example, the gap in the pixel separation section 117 may be formed near the pad sections 120 and 125 (see Fig.51 ).

[0548] In the above-mentioned embodiment, it has been described that the pixel separation portion 117 has a FTI structure (in which the pixel separation portion 117 penetrates the semiconductor layer 100S (see FIG. Fig.49 )) example. However, the pixel separation unit 117 may also have a structure other than the FTI structure. For example, the pixel separation unit 117 does not need to be set to completely penetrate the semiconductor layer 100S, and the pixel separation unit 117 may have a structure generally referred to as DTI (Deep Trench Isolation).

[0549] <Application Examples>

[0550] Fig.82 An example of a general configuration of an image pickup system 7 including the image pickup apparatus 1 according to the above-described embodiment and modifications of each embodiment is shown.

[0551] For example, the camera system 7 is, for example, a camera device such as a digital camera or a video camera, or an electronic device such as a portable terminal device (for example, a smartphone or a tablet terminal). The camera system 7 includes, for example, the camera device 1 according to the above-mentioned embodiment and its modified example, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the camera system 7, the camera device 1 according to the above-mentioned embodiment and its modified example, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected together via a bus 249.

[0552] The camera device 1 according to the above-mentioned embodiment and its modified example outputs image data corresponding to the incident light. The DSP circuit 243 is a signal processing circuit for processing the signal (image data) output from the camera device 1 according to the above-mentioned embodiment and its modified example. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 in units of frames. The display section 245 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the camera device 1 according to the above-mentioned embodiment and its modified example. The storage section 246 records the image data of the moving image or the still image captured by the camera device 1 according to the above-mentioned embodiment and its modified example in a recording medium such as a semiconductor memory or a hard disk. The operation section 247 issues operation commands for various functions of the camera system 7 according to the user's operation. The power supply section 248 appropriately supplies various power sources used as operation power sources for the image pickup device 1 , the DSP circuit 243 , the frame memory 244 , the display section 245 , the storage section 246 , and the operation section 247 according to the above-described embodiment and its modifications to these power supply targets.

[0553] Now, the image capturing process in the image capturing system 7 will be described.

[0554] Fig.83 An example of a flowchart of an imaging operation in the imaging system 7 is shown. The user operates the operation section 247 to give an instruction on starting imaging (step S101). Then, the operation section 247 sends an imaging command to the imaging device 1 (step S102). The imaging device 1 (specifically, the system control circuit 36) receives the imaging command and then performs imaging according to a predetermined imaging scheme (step S103).

[0555] The imaging device 1 outputs the image data generated by imaging to the DSP circuit 243. Here, the image data is data for all pixels in the pixel signal generated based on the charge temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (for example, noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to store the image data subjected to the predetermined signal processing, and the frame memory 244 causes the storage unit 246 to store the image data (step S105). In the above method, the imaging system 7 performs imaging.

[0556] In this application example, the imaging device 1 according to the above-described embodiment and the modified examples of each embodiment is applied to the imaging system 7. Therefore, the size of the imaging device 1 can be reduced or the resolution of the imaging device 1 can be increased, so that a small imaging system 7 or a high-resolution imaging system 7 can be provided.

[0557] <Application examples of endoscopic surgery systems>

[0558] Furthermore, the technology according to the present disclosure (the present technology) can be applied to an endoscopic surgery system.

[0559] Fig.84 : is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (the present technology) can be applied.

[0560] exist Fig.84 , a situation is shown in which a surgical staff (doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112; a support arm device 11120 supporting the endoscope 11100; and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0561] The endoscope 11100 includes: a lens barrel 11101 having an area of ​​a predetermined length from the top to be inserted into the body cavity of the patient 11132; and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 configured as a rigid endoscope including the hard lens barrel 11101 is illustrated. However, the endoscope 11100 may also be configured as a flexible endoscope including the flexible lens barrel 11101.

[0562] At the distal end of the lens barrel 11101, an opening is provided, in which an objective lens is mounted. A light source device 11203 is connected to the endoscope 11100, so that light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 through a light guide member extending in the lens barrel 11101, and the light irradiates an observation object in the body cavity of the patient 11132 through the objective lens. Note that the endoscope 11100 may be a forward-viewing endoscope, or may be an oblique-viewing endoscope or a side-viewing endoscope.

[0563] An optical system and an imaging element are provided inside the camera head 11102, so that the reflected light (observation light) from the observation object is focused onto the imaging element by the optical system. The observation light is photoelectrically converted by the imaging element, thereby generating an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 as raw data.

[0564] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0565] Under the control of the CCU 11201 , the display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 .

[0566] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light to the endoscope 11100 when photographing a surgical site.

[0567] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions for changing the imaging conditions (type of irradiation light, magnification or focal length, etc.) of the endoscope 11100.

[0568] The treatment tool control device 11205 controls the drive of the energy device 11112 for cauterizing or cutting tissues, or sealing blood vessels, etc. The pneumoperitoneum device 11206 delivers gas to the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space of the surgeon. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various formats (e.g., text, images, or charts).

[0569] Note that the light source device 11203 that provides irradiation light to the endoscope 11100 when photographing the surgical site may include a white light source, such as an LED, a laser light source, or a combination of an LED and a laser light source. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the observation object is irradiated with lasers from each of the RGB laser light sources in a time-division manner, and the driving of the imaging element of the camera 11102 is controlled synchronously with the irradiation timing. Images corresponding to the colors R, G, and B, respectively, can also be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0570] In addition, the light source device 11203 can be controlled to change the output light intensity at a predetermined time interval. By controlling the driving of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity and acquiring images in a time-division manner, and synthesizing the above images, a high dynamic range image without underexposed blocked upshadows and overexposed highlights can be generated.

[0571] In addition, the light source device 11203 can be configured to provide light of a predetermined wavelength band for special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption of human tissue, a narrower band of light than the irradiation light (i.e., white light) during ordinary observation is irradiated to perform narrow band domain observation (NBI: Narrow Band Imaging), that is, to image predetermined tissues such as blood vessels in a part of the mucosal surface layer with high contrast. Alternatively, in special light observation, an image can be obtained by fluorescence generated by irradiation with excitation light, thereby performing fluorescence observation. In fluorescence observation, fluorescence from human tissue can be observed by irradiating human tissue with excitation light (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG: indocyanine green) into human tissue and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the reagent, to obtain a fluorescence image. As described above, the light source device 11203 can be configured to provide such narrow band domain light and / or excitation light suitable for special light observation.

[0572] Fig.85 It is shown Fig.84 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0573] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0574] The lens unit 11401 is an optical system, which is provided at a connection portion with the lens barrel 11101. Observation light introduced from the distal end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0575] The number of imaging elements constituting the imaging unit 11402 may be one (single-board type) or multiple (multi-board type). For example, in the case where the imaging unit 11402 is composed of a multi-board type imaging element, each imaging element generates image signals corresponding to R, G, and B, respectively, and these image signals can be synthesized to obtain a color image. The imaging unit 11402 may also be constructed to have a pair of imaging elements, which are used to respectively obtain an image signal for the right eye and an image signal for the left eye corresponding to a three-dimensional (3D) display. If a 3D display is performed, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site. Note that in the case where the imaging unit 11402 is composed of a stereoscopic imaging element, a plurality of systems of the lens unit 11401 are provided corresponding to each imaging element.

[0576] In addition, the camera unit 11402 does not have to be arranged on the camera head 11102. For example, the camera unit 11402 can be arranged in the lens barrel 11101 and immediately behind the objective lens.

[0577] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0578] The communication unit 11404 includes a communication device for sending and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 through the transmission cable 11400 as RAW data.

[0579] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to the imaging conditions, such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image.

[0580] Note that imaging conditions such as a frame rate, an exposure value, a magnification, or a focus may be appropriately specified by a user, or may be automatically set based on an acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE: auto exposure) function, an automatic focus (AF: auto focus) function, and an automatic white balance (AWB: auto white balance) function are included in the endoscope 11100.

[0581] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received through the communication unit 11404 .

[0582] The communication unit 11411 includes a communication device for sending and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal sent from the camera 11102 through the transmission cable 11400.

[0583] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The above-mentioned image signal and the above-mentioned control signal can be transmitted through electrical communication, optical communication, or the like.

[0584] The image processing unit 11412 performs various image processing on the image signal in the form of raw data sent from the camera 11102.

[0585] The control unit 11413 performs various controls related to imaging of a surgical site, etc., through the endoscope 11100 and display of an image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0586] In addition, based on the image signal that has been image-processed by the image processing unit 11412, the control unit 11413 controls the display device 11202 to display the captured image of the surgical site, etc. At this time, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy device 11112, etc. by detecting the shape and color of the edges of the objects included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical auxiliary information on the image of the surgical site in an overlaid manner. When the surgical auxiliary information is displayed in an overlaid manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the operation safely.

[0587] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 together is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable for electrical communication and optical communication.

[0588] Here, in the example shown, although communication has been performed in a wired manner using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may also be performed through wireless communication.

[0589] Note that although an endoscopic surgical system has been described as an example, the technology according to the present disclosure can also be applied to any other surgical system, such as a microsurgery system, etc.

[0590] <Application example of mobile object>

[0591] In addition, for example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as: a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship or a robot.

[0592] Fig.86 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0593] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.86In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: Interface) 12053 are shown.

[0594] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating the drive force of the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0595] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as a headlight, a rear light, a brake light, a turn signal light, or a fog light. In this case, it is possible to input radio waves or signals of various switches transmitted from a mobile device that replaces the key to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, the power window device, or the lights of the vehicle.

[0596] The vehicle exterior information detection unit 12030 detects information of the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing or distance detection processing on objects such as pedestrians, vehicles, obstacles, traffic signs, or text on the road surface.

[0597] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or may be non-visible light such as infrared rays.

[0598] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off.

[0599] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information outside or inside the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing the functions of the advanced driver assistance system (ADAS), which includes: collision avoidance or impact reduction of the vehicle, following driving based on the following distance, speed maintenance driving, collision warning of the vehicle or lane departure warning of the vehicle, etc.

[0600] In addition, the microcomputer 12051 can control the driving force generating device, steering mechanism or braking device, etc. based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing collaborative control for automatic driving to enable the vehicle to drive autonomously without relying on the driver's operation.

[0601] Furthermore, based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights and switch from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control for anti-glare.

[0602] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify passengers on the vehicle or the outside of the vehicle of information. Fig.86 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0603] Fig.87 This is a diagram showing an example of the installation position of the camera unit 12031.

[0604] exist Fig.87 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0605] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the following positions: for example, the front nose, rearview mirror, rear bumper and trunk door of the vehicle 12100 and the upper part of the windshield in the vehicle compartment. The camera unit 12101 arranged on the front nose and the camera unit 12105 arranged on the upper part of the windshield in the vehicle compartment mainly obtain the front image of the vehicle 12100. The camera units 12102 and 12103 arranged on the rearview mirror mainly obtain the side image of the vehicle 12100. The camera unit 12104 arranged on the rear bumper or the trunk door mainly obtains the rear image of the vehicle 12100. The camera unit 12105 arranged on the upper part of the windshield in the vehicle compartment is mainly used to detect the front vehicle, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0606] By the way, Fig.87 Examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 disposed on the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 disposed on the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 disposed on the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above is obtained.

[0607] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0608] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the camera ranges 12111 to 12114 and the change in the distance over time (relative speed relative to the vehicle 12100), thereby extracting the three-dimensional object that is closest to the vehicle 12100 on the road and traveling at a predetermined speed (for example, greater than or equal to 0 km / h) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can set the following distance to be maintained in front of the leading vehicle in advance, and can perform automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control) and the like. Therefore, cooperative control such as automatic driving for autonomous driving of the vehicle without relying on the operation of the driver and the like can be performed.

[0609] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, telephone poles, and other three-dimensional objects, extract the classified three-dimensional object data, and then use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver cannot visually recognize. Then, the microcomputer 12051 determines the collision risk used to represent the risk of collision with each obstacle. When the collision risk is greater than or equal to the set value and there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering through the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collision.

[0610] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether there are pedestrians in the images captured by the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following process: a process of extracting feature points in the images captured by the camera units 12101 to 12104 as infrared cameras; and a process of determining whether the object is a pedestrian by pattern matching a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there are pedestrians in the images captured by the camera units 12101 to 12104 and identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 so that a rectangular contour line for emphasis is superimposed on the identified pedestrian and displayed. The sound / image output unit 12052 can also control the display unit 12062 so that an icon or the like for representing a pedestrian is displayed at a desired position.

[0611] Note that embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made to the embodiments without departing from the gist of the present technology.

[0612] The present technology can also take the following configurations. (1)

[0614] A camera element, comprising:

[0615] substrate;

[0616] A first photoelectric conversion region, which is disposed in the substrate;

[0617] a second photoelectric conversion region, which is disposed in the substrate, the second photoelectric conversion region being adjacent to the first photoelectric conversion region;

[0618] a pixel separation section provided in the substrate and provided between the first photoelectric conversion region and the second photoelectric conversion region; and

[0619] a junction region provided in a side wall of the pixel separation portion, the junction region having a first impurity region containing a first impurity and a second impurity region containing a second impurity,

[0620] In which, the length of the side of the first impurity region formed in the side wall of the pixel separation portion is greater than the length between two parallel sides of the pixel separation portion among the four sides of the pixel separation portion surrounding the first photoelectric conversion region, and the side of the first impurity region intersects the two parallel sides of the pixel separation portion perpendicularly. (2)

[0622] An imaging element according to (1) above, wherein, when the length between the two parallel sides of the pixel separation portion is used as a reference, the length of the side of the first impurity region is at least 1.3 times the length between the two parallel sides of the pixel separation portion. (3)

[0624] The image sensor according to (1) or (2) above, wherein the first impurity region includes a protruding portion on the second impurity region side. (4)

[0626] The image pickup element according to any one of (1) to (3) above, wherein the pixel separation portion includes a protrusion. (5)

[0628] The image pickup element according to (3) or (4) above, wherein each of the protrusions i...

Claims

1. An imaging element, comprising: substrate; A first photoelectric conversion region, which is disposed in the substrate; a second photoelectric conversion region, which is disposed in the substrate, the second photoelectric conversion region being adjacent to the first photoelectric conversion region; a pixel separation portion provided in the substrate and provided between the first photoelectric conversion region and the second photoelectric conversion region; and a junction region provided in a side wall of the pixel separation portion, the junction region having a first impurity region containing a first impurity and a second impurity region containing a second impurity, wherein the length of the side of the first impurity region formed in the side wall of the pixel separation portion is greater than the length between two parallel sides of the pixel separation portion among four sides of the pixel separation portion surrounding the first photoelectric conversion region, and the side of the first impurity region intersects the two parallel sides of the pixel separation portion perpendicularly, Wherein, the pixel separation portion includes a protrusion, and The tip of the protrusion faces the gate of the transfer transistor.

2. The imaging element according to claim 1, wherein: When the length between the two parallel sides of the pixel separating portion is used as a reference, the length of the side of the first impurity region is 1.3 times or more the length.

3. The imaging element according to claim 1, wherein: The first impurity region includes a protruding portion on the second impurity region side.

4. The imaging element according to claim 3, wherein: The protruding portion of the first impurity region is formed in a rectangular shape.

5. The imaging element according to claim 3, wherein: The protruding portion of the first impurity region is formed in a triangular shape.

6. The imaging element according to any one of claims 1 to 5, wherein: A junction surface between the first impurity region and the second impurity region is shaped to include a concave portion and a convex portion.

7. The imaging element according to any one of claims 1 to 5, wherein: The wall surface of the pixel separation portion is shaped to include a concave portion and a convex portion.

8. The imaging element according to any one of claims 1 to 5, The bonding region is further provided at at least one of the four corners of the first photoelectric conversion region.

9. The imaging element according to any one of claims 1 to 5, further comprising: The pixel separation portion is in the shape of a cross; and The bonding region is further provided on a side surface of the cross-shaped pixel separation portion.

10. The imaging element according to any one of claims 1 to 5, wherein: The pixel separation portion partially includes a discontinuous portion, and The first impurity region in the discontinuous portion is formed in a bent shape.

11. The imaging element according to claim 10, wherein: A plurality of the discontinuous portions are arranged on one side.

12. The imaging element according to any one of claims 1 to 5, wherein: The first impurity is an N-type impurity and the second impurity is a P-type impurity, or the first impurity is a P-type impurity and the second impurity is an N-type impurity.

13. The imaging element according to any one of claims 1 to 5, wherein: The protruding portion of the pixel separation portion is formed so as not to penetrate through the substrate. 14 . An electronic device having the imaging element according to claim 1 mounted therein.

Images