Image pickup element and image pickup device

Abstract

The imaging element comprises: a first pixel having a first photoelectric conversion unit, a first storage unit for storing charges generated by the first photoelectric conversion unit, and a first output unit for outputting a first signal based on a voltage of the first storage unit; a second pixel having a second photoelectric conversion unit, a second storage unit for storing charges generated by the second photoelectric conversion unit, and a second output unit for outputting a second signal based on a voltage of the second storage unit; an output line connected to the first output unit and the second output unit and outputting a first signal and a second signal to the output line; and a control unit capable of controlling the voltage of the first storage unit to be a first voltage, and capable of controlling the voltage of the second storage unit to be a second voltage different from the first voltage or the first voltage.

Description

Technical Field

[0001] The present invention relates to an imaging element and an imaging device. Background Art

[0002] Conventionally, there is known an imaging element that uses a part of pixels as an element for detecting the focus of an image formed by an imaging lens (for example, Patent Document 1). The values ​​of signals output by pixels for focus detection and pixels for imaging are different.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-103525 Summary of the invention

[0006] According to a first aspect of the present invention, an imaging element comprises: a first pixel having a first photoelectric conversion unit that generates charges by photoelectrically converting light, a first accumulation unit that accumulates the charges generated by the first photoelectric conversion unit, and a first output unit that outputs a first signal based on the voltage of the first accumulation unit; a second pixel having a second photoelectric conversion unit that generates charges by photoelectrically converting light, a second accumulation unit that accumulates the charges generated by the second photoelectric conversion unit, and a second output unit that outputs a second signal based on the voltage of the second accumulation unit; an output line that is connected to the first output unit and the second output unit and outputs the first signal and the second signal to the output line; and a control unit that can control the voltage of the first accumulation unit to be a first voltage, and can control the voltage of the second accumulation unit to be a second voltage different from the first voltage or the first voltage.

[0007] According to a second aspect of the present invention, an image pickup device includes: an image pickup element according to the first aspect; and a generation unit that generates image data based on the first signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a cross-sectional view schematically showing the structure of the imaging device.

[0009] Figure 2 This is a plan view of the imaging element as viewed from the imaging surface side. Figure 2 (a) is the overall diagram of the imaging element. Figure 2 (b) is a magnified view of a portion thereof.

[0010] Figure 3 This is a circuit diagram of a portion of a pixel of an imaging element and a readout circuit.

[0011] Figure 4This is a circuit diagram of the control unit of the imaging element.

[0012] Figure 5 It is a timing chart showing an example of the operation of the imaging element.

[0013] Figure 6 is a cross-sectional view of an imaging element.

[0014] Figure 7 It is a cross-sectional view of an imaging pixel and a focus detection pixel. DETAILED DESCRIPTION

[0015] (Embodiment of the imaging device)

[0016] Figure 1 1 is a cross-sectional view schematically showing the configuration of an imaging device using an imaging element according to Embodiment 1. The imaging device 1 includes an imaging optical system 2, an imaging element 3, a control unit 4, a lens shifting unit 5, and a display unit 6.

[0017] The imaging optical system 2 forms a subject image on an imaging surface of the imaging element 3. The imaging optical system 2 is composed of a lens 2a, a focusing lens 2b, and a lens 2c. The focusing lens 2b is a lens for adjusting the focus of the imaging optical system 2. The focusing lens 2b is configured to be movable in the optical axis Z direction.

[0018] The lens moving unit 5 has an actuator not shown in the figure. The lens moving unit 5 moves the focus lens 2b along the optical axis Z direction through the actuator. The imaging element 3 captures the subject image and outputs a signal. The imaging element 3 has imaging pixels and AF pixels (focus detection pixels). The imaging pixels output signals (image signals) for image generation. The AF pixels output signals (focus detection signals) for focus detection. The control unit 4 controls various parts such as the imaging element 3. The control unit 4 applies image processing and the like to the image signal output by the imaging element 3 to generate image data. The control unit 4 records the image data on a recording medium not shown in the figure, or displays an image based on the image data on the display unit 6. The control unit 4 can also be interpreted as a generation unit that generates an image based on an image signal. The display unit 6 is a display device having a display component such as a liquid crystal panel.

[0019] In addition, the control unit 4 performs focus detection processing required for automatic focus adjustment (AF) of the imaging optical system 2 by a known phase difference detection method. Specifically, the control unit 4 detects the focus position of the focus lens 2b used to form an image based on the imaging optical system 2 on the imaging surface of the imaging element 3. The control unit 4 detects the image shift amount of the first and second images based on a pair of focus detection signals output from the imaging element 3. The control unit 4 calculates the shift amount (defocus amount) between the current position of the focus lens 2b and the focus position based on the detected image shift amount. By driving the focus lens 2b according to the defocus amount, the focus adjustment is automatically performed.

[0020] (Embodiment of Image Pickup Element)

[0021] Figure 2 (a) is a diagram showing the imaging element 3 according to the embodiment of the present invention as viewed from the imaging surface side, that is, from Figure 1 The image pickup device 3 has Figure 2 A plurality of pixels 30 are arranged along the x direction and the y direction. Figure 2 Although some pixels 30 are omitted in the figure, a plurality of pixels 30 may be arranged in the x direction and the y direction, for example, more than 1000 pixels may be arranged.

[0022] A horizontal control unit HC is provided at the left end of the figure in a region (imaging region) where a plurality of pixels 30 are arranged, and a vertical control unit VC is provided at the upper end of the figure. The horizontal control unit HC and the vertical control unit VC are also collectively referred to as a control unit CU.

[0023] (Pixel block composition)

[0024] The image sensor 3 has a plurality of pixel blocks BC. Figure 2 In the figure, one pixel block BC has a plurality of pixels 30 arranged in the x direction and the y direction in the area surrounded by the boundary line BB shown by the dotted line. The area surrounded by the boundary line BB constitutes one pixel block BC. As described above, the plurality of pixels 30 in each pixel block BC have their respective output sections connected to one output line, and each pixel 30 is connected to one readout section. In addition, the plurality of pixels 30 in each pixel block BC may also be connected to a plurality of output lines and to a plurality of readout sections.

[0025] exist Figure 2 In FIG. 1 , for ease of explanation, a portion corresponding to one pixel block BC is hatched. Here, each region surrounded by each boundary line BB indicated by a dotted line is a pixel block BC. The pixel block BC is divided into a plurality of pixels 30, which are arranged in a plurality of pixel blocks BC.

[0026] exist Figure 2In the example shown, 4 pixels 30 are arranged in the x direction and 4 pixels 30 are arranged in the y direction, which is a total of 16 pixels 30, forming one pixel block BC. The number of pixels arranged in the x direction and the y direction in one pixel block BC is not limited to 4, and may be another number such as 6 or 8. The number of pixels arranged in the x direction and the y direction may also be different.

[0027] In addition, the outer shape of the pixel block BC is not limited to Figure 2 The rectangle shown may be any shape including a plurality of pixels 30. In this case, the shape of the boundary line BB is not a simple straight line but a shape in which a plurality of straight lines are connected in a curved manner.

[0028] Figure 2 (b) is an enlarged view showing Figure 2 FIG. 1 shows a diagram of two pixel blocks BC1 and BC2 adjacent to each other in the x direction in the pixel block BC shown in FIG. Figure 2 As shown in (b), one of the three color filters (color filters) having different spectral characteristics of, for example, R (red), G (green), and B (blue) is provided in a plurality of pixels 30. The R color filter mainly transmits light in the red wavelength range, the G color filter mainly transmits light in the green wavelength range, and the B color filter mainly transmits light in the blue wavelength range. The pixels have different spectral characteristics due to the configured color filters. The pixels 30 include pixels that are sensitive to red (R) light (hereinafter referred to as R pixels R), pixels that are sensitive to green (G) light (hereinafter referred to as G pixels G), and pixels that are sensitive to blue (B) light (hereinafter referred to as B pixels B). These pixels 30 are arranged in a so-called Bayer array. The G pixel Gb is a G pixel that is configured along the y direction like the B pixel B, and the G pixel Gr is a G pixel that is configured along the y direction like the R pixel R.

[0029] The pixel block BC1 has four G pixels Gb, four G pixels Gr, four R pixels R, and four B pixels B arranged in a Bayer array. These pixels 30 are imaging pixels Gb, Gr, R, and B (hereinafter also collectively referred to as imaging pixels 30c) used to capture an optical image formed on the imaging surface of the imaging element 3.

[0030] The arrangement of pixels 30 in pixel block BC2 is almost the same as that in pixel block BC1, except that some pixels where B pixels B are arranged in pixel block BC1 are replaced with special pixels Z1 and Z2 (also collectively referred to as special pixels ZZ) which are different from the above-mentioned imaging pixels 30c.

[0031] The special pixel ZZ is, for example, an AF pixel, and its structure will be described later.

[0032] The special pixel ZZ is not limited to the AF pixel, and may be a pixel having a sensitivity different from that of the above-mentioned imaging pixel 30c. In addition, it may be a pixel having a color filter having a spectral characteristic different from that of the above-mentioned imaging pixel 30c.

[0033] The pixel block BC2 includes a plurality of pixels 30, including at least one special pixel ZZ and a plurality of imaging pixels 30c.

[0034] At least one pixel block BC among the plurality of pixel blocks BC is composed of at least one special pixel ZZ and a plurality of imaging pixels 30c, like the pixel block BC2. The plurality of pixel blocks BC of the imaging element 3 may all be composed of the pixel blocks BC2 including the special pixel ZZ. It may also be that at least one pixel block BC2 among the plurality of pixel blocks BC of the imaging element 3 includes the special pixel ZZ, and the other pixel blocks BC are all pixel blocks BC composed of the imaging pixels 30c.

[0035] and a selection unit TV (described later) provided in each pixel 30 Figure 3 ) connected to the vertical selection lines VS1 to VS8 (also collectively referred to as vertical selection lines VS) from Figure 2 The vertical control unit VC shown in (a) of FIG. 1 extends in the y direction. Figure 3 Horizontal selection lines HS1 to HS4 (also collectively referred to as horizontal selection lines HS) connected to the special pixels Z1 and Z2 extend from the horizontal control unit HC in the x direction. Special horizontal selection lines ZS connected to the selection units described later of the special pixels Z1 and Z2 also extend from the horizontal control unit HC in the x direction.

[0036] Reset voltage lines HR1 to HR4 (also collectively referred to as reset voltage lines HR) connected to a reset portion described later of each pixel 30 extend from the horizontal control portion HC in the x direction.

[0037] like Figure 2 As shown in (b), vertical selection lines VS1 to VS8 are shared by multiple pixels 30 arranged along the y direction, and horizontal selection lines HS1 to HS4 are shared by multiple imaging pixels 30c arranged along the x direction. Special horizontal selection line ZS is shared by multiple special pixels ZZ arranged along the x direction. Reset voltage lines HR1 to HR4 are shared by multiple pixels 30 arranged along the x direction.

[0038] Figure 3 It is for Figure 2 FIG. 10( b ) shows a schematic diagram of an electrical circuit of four pixels 30 (two pixels arranged vertically and two pixels arranged horizontally) in an area PB surrounded by a double-dashed line at the lower right of the pixel block BC2. Figure 2As shown in the area PB of (b), the upper left is the G pixel Gb, the upper right is the special pixel Z2, the lower left is the R pixel R, and the lower right is the G pixel Gr.

[0039] The four pixels (Gb, Z2, R, Gr) are basically four-transistor CMOS imaging elements, and as described later, the configuration of so-called selection transistors is different from that of a general four-transistor CMOS imaging element.

[0040] In each pixel (Gb, Z2, R, Gr), the photodiode PD as a photoelectric conversion unit performs photoelectric conversion on the incident light to generate charge and temporarily accumulates the generated charge. The transfer transistor TX transfers the charge accumulated in the photodiode PD to the floating diffusion (FD) region FD formed with the capacitor CC based on the transmission signal sent to its gate through the transmission control line (not shown). The amplifier transistor TA outputs a signal corresponding to the charge generated by the photodiode PD by applying a voltage generated in the FD region FD due to the transferred charge to its gate.

[0041] A power supply voltage VDD is applied to the input side (drain) of the amplifier transistor TA. A reset transistor TR is provided for resetting the FD region FD to a predetermined voltage. The input side (drain) of the reset transistor TR is connected to the reset voltage line HR3 or HR4, and a predetermined voltage described later is supplied from the horizontal control unit HC via the reset voltage line HR.

[0042] The output side (source side) of the amplifier transistor TA of each pixel (Gb, Z2, R, Gr) is connected to the input side of the vertical selection transistor TV. The gate of the vertical selection transistor TV is connected to the vertical selection line VS7 or VS8 to utilize the Figure 2 The vertical selection transistor TV is controlled so as to be conductive or non-conductive by a control signal sent from the vertical control unit VC shown in (a).

[0043] The output side of the vertical selection transistor TV of the image pixel (Gb, R, Gr) is connected to the input side of the horizontal selection transistor TH1. That is, the vertical selection transistor TV and the horizontal selection transistor TH1 are arranged in series. The gate of the horizontal selection transistor TH1 is connected to the horizontal selection line HS3 or HS4. Figure 2 The horizontal selection transistor TH1 is turned on or off by a control signal sent from the horizontal control unit HC shown in (a).

[0044] In the imaging pixel (Gb, R, Gr) of the imaging element 3 of the embodiment, the amplification transistor TA, the vertical selection transistor TV, and the horizontal selection transistor TH1 can be interpreted as an output unit in its entirety or as one of them.

[0045] On the other hand, in the special pixel Z2, the output side of the vertical selection transistor TV is connected to the input side of the special horizontal selection transistor TH2. The gate of the special horizontal selection transistor TH2 is connected to the special horizontal selection line ZS. Figure 2 The control signal sent from the horizontal control unit HC shown in (a) makes the special horizontal selection transistor TH2 conductive or non-conductive.

[0046] The amplification transistor TA, the vertical selection transistor TV, and the special horizontal selection transistor TH2 of the special pixel Z2 of the image sensor 3 of the embodiment can be interpreted as an output unit as a whole or as any one of them.

[0047] The output of the horizontal selection transistor TH1 of the imaging pixel (Gb, R, Gr) in the pixel block BC2 and the output of the special horizontal selection transistor TH2 in the special pixel Z2 in the pixel block BC2 are connected to one output line RW. Moreover, the output line RW is connected to a readout section that reads out the signal of the pixel 30. The readout section has, for example, an AD conversion section ADC that converts an analog signal output from the pixel 30 into a digital signal. In addition, the output line RW is connected to a current source CS that supplies current to each pixel 30.

[0048] The control unit CU controls the voltage of the control signal to the vertical selection line VS and the horizontal selection line HS, so that the signal (output of the amplifier transistor TA) of any one or more pixels (Gb, Z2, R, Gr) in the pixel block BC2 is output to the output line RW. The readout unit reads the signal of the pixel (Gb, Z2, R, Gr) in the pixel block BC2.

[0049] Figure 4 is a circuit diagram included in the horizontal control unit HC. Figure 4 A portion of the circuit included in the horizontal control unit HC, a portion of the plurality of pixels 30, a portion of the horizontal selection line HS connected to the pixels 30 in the above-mentioned pixel blocks BC1 and BC2, a special horizontal selection line ZS, and a portion of the reset voltage line HR are shown.

[0050] Each horizontal selection line HS is connected to selection line switching switches SS1 to SS4 (also collectively referred to as selection line switching switches SS) in the horizontal control unit HC. Each horizontal selection line HS can be switched to be connected to a high voltage line SH that supplies a high voltage such as a power supply voltage VDD or a low voltage line SL that supplies a low voltage such as a ground voltage GND by the selection line switching switch SS.

[0051] For example, when the horizontal selection line HS1 is connected to the high voltage line SH, the horizontal selection transistor TH1 in the pixel 30 connected to the horizontal selection line HS1 is turned on. When the horizontal selection line HS1 is connected to the low voltage line SL, the horizontal selection transistor TH1 is turned off.

[0052] The special horizontal selection line ZS is connected to a special switching switch SZ in the horizontal control unit HC. The special horizontal selection line ZS can be switched to be connected to either the high voltage line SH or the low voltage line SL by the special switching switch SZ. For example, when the special horizontal selection line ZS is connected to the high voltage line SH, the horizontal selection transistor TH2 in the pixel 30 connected to the special horizontal selection line ZS becomes conductive. When the special horizontal selection line ZS is connected to the low voltage line SL, the horizontal selection transistor TH2 becomes non-conductive.

[0053] On the other hand, each reset voltage line HR is connected to reset line switching switches SR1 to SR4 (also collectively referred to as reset line switching switches SR) in the horizontal control unit HC. Each reset voltage line HR can be switched by the reset line switching switch SR to be connected to, for example, a first voltage line RR1 for supplying a first voltage such as a power supply voltage VDD, a second voltage line RR2 for supplying a second voltage closer to the substrate voltage than the first voltage, or a third voltage line RR3 for supplying a third voltage closer to the substrate voltage than the second voltage.

[0054] To the input side of the reset transistor TR in each pixel 30 , one of the first voltage, the second voltage, or the third voltage is applied by the horizontal control unit HC via the reset voltage line HR.

[0055] The selection line switch SS, the special switch SZ, and the reset line switch SR can all be formed by semiconductor switches, for example, MOS transistor circuits.

[0056] Although not shown in the figure, the vertical control unit VC also has Figure 4 The horizontal control unit HC shown in the figure is similarly provided with a switch for switching the voltage applied to each vertical selection line VS.

[0057] The switching of each of these switches, that is, what voltage signal is sent to each of the vertical selection line VS, the horizontal selection line HS, the special horizontal selection line ZS, and the reset voltage line HR can be controlled by the control circuit in the control unit CU.

[0058] Furthermore, the control unit CU can also control the movement of the changeover switch based on instructions from various devices and equipment on which the imaging element is mounted.

[0059] Although not shown in the figure, similarly to the conventional CMOS type imaging element, Figure 3 The gate of the transfer transistor TX and the gate of the reset transistor TR in each pixel 30 shown are connected to a control line (not shown) similar to the horizontal selection line HS or the vertical selection line VS. Furthermore, the control unit CU can control the conduction state of the transfer transistor TX and the reset transistor TR for each of the pixels 30 arranged in one row in the x direction or in one column in the y direction through the control line.

[0060] Alternatively, the transmission transistor TX and the reset transistor TR may be controlled for each pixel 30. For this purpose, for example, each control line is also configured to be composed of control lines in two directions, the horizontal direction and the vertical direction, and the transmission transistor TX and the reset transistor TR are respectively configured by two transistors arranged in series. Furthermore, the gates of the two transistors can be connected to the control line in the horizontal direction and a control line in the vertical direction, respectively.

[0061] In the image sensor 3 of the present embodiment, as described later, signals of an arbitrary number of pixels 30 in one pixel block BC connected to one readout section can be aggregated and read out (binning readout) via the output line RW and the readout section.

[0062] By combining readout, the image sensor 3 can be easily used in a low-resolution mode for outputting image data having a number of pixels less than the total number of pixels of the image sensor. Combined readout means that by combining and reading out two or more pixels 30 in one pixel block BC by the readout unit, noise mixed in the signal of each pixel 30 can be smoothed, thereby obtaining an image with less noise.

[0063] When read out by the readout unit, the combined pixels 30 are preferably pixels of the same color. Therefore, the vertical control unit VC and the horizontal control unit HC control the voltage of the control signal to the vertical selection line VS and the horizontal selection line HS, select two or more pixels 30 of the same color in one pixel block BC, and output these signals (outputs of the amplifier transistor TA) to the output line RW.

[0064] (Reading pixels and clipping pixels)

[0065] When reading out a signal, if an abnormal value is output to the readout unit, such as when the voltage of a signal on the input side of the readout unit is lower than a specified value, the current source CS connected to the output line RW in the pixel block BC or excessive current flowing into the readout unit may be damaged, or the current source CS or the readout unit may be damaged.

[0066] In order to prevent this, the imaging element 3 of this embodiment can suppress excessive current as follows. That is, when reading out any one or more read pixels in a pixel block BC, any other pixels 30 in the pixel block BC are set as limit operation pixels, and the signals of the read pixels and the limit operation pixels are summed and read out, thereby suppressing excessive current.

[0067] By summing and reading out with the limiting action pixel, the lower limit value of the voltage of the summed read signal is limited to a value based on the signal from the limiting action pixel, and can be prevented from falling below this value, thereby eliminating the concern about damage to the readout unit or current source CS.

[0068] The clipping operation pixel functions as a pixel that outputs only a predetermined signal for clipping, and does not need to be a pixel of the same color as the readout pixel.

[0069] The following describes the reading operation of the light intensity signal when the image pickup element 3 of this embodiment is used for shooting. First, as an example, the reading operation of the light intensity signal when the image pickup element 3 is used for shooting is described. Figure 3 The upper left G pixel (camera pixel) Gb in the figure, and the limit operation pixel is configured in Figure 3 The lower left R pixel (imaging pixel) R in FIG. Here, as described later, any other pixel 30 may be selected as a readout pixel and a clipping operation pixel.

[0070] Before an exposure operation for image capture or focus detection, the control unit CU including the horizontal control unit HC controls the reset line switch SR to connect each reset voltage line HR to the first voltage line RR1 that supplies the first voltage. Furthermore, the control unit CU turns on the reset transistor TR and the transfer transistor TX of each pixel 30 to reset the FD region and the photodiode PD to the first voltage.

[0071] Thereafter, the control unit CU renders the transfer transistor TX non-conductive, and performs exposure for the photodiode PD on the imaging element 3 for imaging or focus detection.

[0072] After exposure, a signal based on the charge generated in the photodiode PD by exposure is read out using so-called correlated double sampling. The control unit CU applies a high-level voltage to the horizontal selection line HS3, the horizontal selection line HS4, and the vertical selection line VS7, and turns on the vertical selection transistor TV and the horizontal selection transistor TH1 of the read pixel Gb and the clipping pixel R. As a result, the output of the amplifier transistor TA of each of the read pixel Gb and the clipping pixel R is output to the output line RW and summed.

[0073] Below, also refer to Figure 5 A timing diagram is shown for explanation.

[0074] exist Figure 5 In the timing diagram shown, the horizontal axis indicates time, and TX and TR indicate the voltage of the control signal input to the gate of the transfer transistor TX and the reset transistor TR of each pixel 30. As an example, each transistor in each pixel 30 is set to an nMOS type. Figure 5 In the case where the control signal is at a high level (eg, a power supply voltage), the transistor to which the control signal is input becomes conductive, and when the control signal is at a low level (eg, a ground voltage), the transistor to which the control signal is input becomes non-conductive.

[0075] Figure 5 The HR voltage indicates a voltage supplied to the reset voltage line HR connected to each pixel 30 , and the FD voltage indicates a voltage of the FD region of each pixel 30 .

[0076] At time t0 when reading starts, the control unit CU supplies a low-level control signal to the gates of the transfer transistors TX and the reset transistors TR of the read pixel Gb and the limiter pixel R. Furthermore, the control unit CU supplies the first voltage VC1 to the reset voltage line HR of the read pixel Gb and the limiter pixel R.

[0077] Furthermore, although the FD region FD of the read pixel Gb and the limiter operation pixel R is reset to the first voltage in the above-mentioned reset operation, the voltage of the FD region FD at time t0 is uncertain thereafter due to the influence of noise or the like.

[0078] Next, the control unit CU applies a high-level voltage to the gate of the reset transistor TR of the read pixel Gb during the period from time t1 to time t2, and resets the FD region FD of the read pixel Gb to the first voltage VC1. As a result, the first voltage VC1 is applied to the gate of the amplifier transistor TA in the read pixel Gb, and the amplifier transistor TA outputs an amplified signal based on the amplifier transistor TA, that is, a so-called dark signal that does not reflect the charge accumulated in the photodiode PD. This output is output to the output line RW via the vertical selection transistor TV and the horizontal selection transistor TH1.

[0079] On the other hand, the control unit CU applies a high-level signal to the gate of the reset transistor TR after time t1 for the clipping action pixel R, and supplies the second voltage VC2 to the reset voltage line HR connected to the clipping action pixel R. As a result, the FD region FD of the clipping action pixel R is reset to the second voltage VC2. Therefore, the second voltage VC2 is applied to the gate of the amplifier transistor TA in the clipping action pixel R, and the amplifier transistor TA outputs an amplified signal based on the amplifier transistor TA. The output is output to the output line RW via the vertical selection transistor TV and the horizontal selection transistor TH1.

[0080] In the image sensor 3 of the present embodiment, the signal of the read pixel Gb and the signal of the limiter operation pixel R are summed as so-called source binning. Therefore, the voltage of the signal finally read out from the readout section is almost the same as the higher voltage of the voltage signals when the two signals before summing up are assumed to be read out from the readout section separately.

[0081] Therefore, the second voltage VC2 applied to the reset transistor TR of the clipping action pixel R is set as follows. That is, the second voltage VC2 is set so that the output voltage value of the readout section when only the clipping action pixel R is connected becomes a value not exceeding the assumed value of the output voltage value of the readout section when only the readout pixel Gr outputting the dark signal is connected.

[0082] Specifically, the amplifier transistor TA of each pixel 30 is an nMOS type, so the second voltage VC2 is set to a voltage lower than the first voltage VC1 (close to the ground voltage). Here, if it is a very low voltage, the function of limiting the output signal will be lost, so it is preferably set to a voltage of about 20% to 60% of the first voltage VC1 based on the ground voltage.

[0083] The control unit CU instructs the readout unit to read out the signal, and in this state, the voltage applied to the input unit of the readout unit is AD-converted, and dark signal sampling (dark sampling) is performed.

[0084] Next, the control unit CU applies a high-level voltage to the gate of the transfer transistor TX of the read pixel Gb during the period from time t3 to time t4, and transfers the charge in the photodiode PD generated by the photoelectric conversion to the FD region. On the other hand, at time t3, the voltage supplied to the reset voltage line HR connected to the clipping action pixel R is changed to the third voltage VC3. As a result, the FD region FD of the clipping action pixel R is reset to the third voltage VC3.

[0085] At time t4, the control unit CU instructs the readout unit to read out the signal, and in this state, the voltage applied to the input unit of the readout unit is AD-converted to perform signal sampling.

[0086] The third voltage VC3 is also set as follows: that is, the third voltage VC3 is set so that the output voltage value of the readout section assuming that only the limit operation pixel R is connected does not exceed the assumed value of the output voltage of the readout section assuming that only the readout pixel Gr is connected.

[0087] Specifically, the third voltage VC3 is preferably set to a voltage lower than the second voltage VC2 and approximately 30% to 70% of the second voltage VC2 with respect to the ground voltage.

[0088] In addition, when the amplifying transistor TA in each pixel 30 is of a pMOS type, the high-low relationship among the first voltage, the second voltage, and the third voltage is reversed.

[0089] The readout section calculates the difference between the signal sampling and dark signal sampling results and outputs it as the readout result of the light intensity signal from the readout pixel Gb. Therefore, the readout signal based on the dark signal sampling can be interpreted as a correction signal for correcting the readout signal based on the signal sampling.

[0090] The output read out by the readout section in each pixel block BC is output from the image sensor 3 via an output control circuit (not shown).

[0091] (Selection of readout pixels and limiter operation pixels)

[0092] Next, refer to Figure 2 (b) and Figure 3 , describing the operation of selecting pixels for reading out pixels and pixels for clipping operation by controlling the signal levels of the vertical selection lines VS, the horizontal selection lines HS, and the special horizontal selection lines ZS by the control unit CU.

[0093] First, explain Figure 2 (b) shows a case where, in the pixel block BC2, all the G pixels Gb are selected as read pixels, and two R pixels R connected to the bottommost horizontal selection line HS4 arranged in the pixel block BC2 are selected as limit operation pixels.

[0094] In this case, the control unit CU connects the vertical selection lines VS5 and VS7 to the four G pixels Gb and the two R pixels R and supplies a high-level voltage to turn on the vertical selection transistor TV, and connects the horizontal selection lines HS1, HS3, and HS4 to these pixels and supplies a high-level voltage to turn on the horizontal selection transistor TH1.

[0095] On the other hand, a low-level voltage is supplied to the horizontal selection line HS2 , the special horizontal selection line ZS, and the vertical selection lines VS6 and VS8 that are not connected to these pixels.

[0096] Thus, signals from only four G pixels Gb serving as read pixels and two R pixels R connected to the horizontal selection line HS4 among the pixels 30 in each pixel block BC2 can be connected to the output line RW and read out by the readout unit.

[0097] That is, in the above-mentioned readout process based on correlated double sampling, it is sufficient to read out four G pixels Gb as readout pixels and two R pixels R connected to the horizontal selection line HS4 as slice operation pixels.

[0098] Specifically, the first voltage VC1 is always applied to the reset voltage lines HR1 and HR3 connected to the reset parts of the four G pixels Gb, and the reset transistor TR and the transfer transistor TX are connected to the reset part of the four G pixels Gb. Figure 5 A high-level voltage is applied at the prescribed timing shown (predetermined timing for reading out pixels).

[0099] exist Figure 5 At the prescribed timing (prescribed timing of the clipping action pixel) shown in FIG. 1 , the first voltage VC1, the second voltage VC2, and the third voltage VC3 are applied to the reset voltage line HR4 connected to the reset portion of the two R pixels R connected to the horizontal selection line HS4. In addition, a high-level voltage is applied to the reset transistors TR of the two R pixels R connected to the horizontal selection line HS4 at the prescribed timing.

[0100] Thus, in the pixel block BC2, two R pixels R are set as clipping operation pixels, and four G pixels Gb are set as read pixels, and binning readout can be performed.

[0101] In the above-mentioned readout operation, by applying a low-level voltage to the horizontal selection line HS1, two G pixels Gb connected to the horizontal selection line HS3 in the pixel block BC2 can be set as readout pixels and two R pixels R can be set as limit operation pixels for combined readout.

[0102] In addition, by applying a low-level voltage to the vertical selection line VS5, a G pixel Gb connected to the horizontal selection line HS3 and the vertical selection line VS7 in the pixel block BC2 can be set as a read pixel, and an R pixel R can be set as a limiting action pixel for merged readout.

[0103] It is also possible to select readout pixels and clipping operation pixels from pixels of the same color.

[0104] For example, in pixel block BC2, a high-level voltage is applied only to vertical selection line VS5, a low-level voltage is applied to other vertical selection lines VS, a high-level voltage is applied to horizontal selection lines HS1 and HS3, and a low-level voltage is applied to horizontal selection lines HS2 and HS4.

[0105] Thus, the signals of the two G pixels Gb connected to the vertical selection line VS5 can be connected to the output line RW. This is an example of setting one G pixel Gb as a read pixel and the other G pixel Gb as a limit operation pixel. The horizontal control unit HC controls the signal level supplied to the reset voltage line HR and the horizontal selection line HS as follows.

[0106] according to Figure 5According to the timing diagram, the first voltage VC1 is always supplied to the reset voltage line HR1. On the other hand, the first voltage VC1, the second voltage VC2, and the third voltage VC3 are sequentially supplied to the reset voltage line HR3 according to the timing, and the high-level voltage is appropriately supplied to the gates of the reset transistor TR and the transmission transistor TX according to the timing. In this way, the G pixel Gb connected to the reset voltage line HR1 can be set as a read pixel, and the G pixel Gb connected to the reset voltage line HR3 can be set as a limit operation pixel for reading.

[0107] In the above-described readout example, an example in which the G pixel Gb is used as the readout pixel is described, but the G pixel Gr, the R pixel R, the B pixel B, or the special pixel ZZ may also be used as the readout pixel.

[0108] In this case, as the slice operation pixel, a pixel of the same color as the read pixel can be used in the same manner, or a pixel of a color different from the read pixel can be used.

[0109] When the special pixel ZZ is used as a read pixel or a slice operation pixel, in order to output the signal of the special pixel ZZ to the output line RW, a high-level voltage is applied to the special horizontal selection line ZS connected to the special pixel ZZ instead of the horizontal selection line HS.

[0110] exist Figure 2 In the pixel block BC2 shown in (b), a part of the B pixels B with high sensitivity to blue light are replaced by special pixels Z1 and Z2, but the read operation from the B pixels B in the pixel block BC2 is performed almost the same as the read operation from the above-mentioned G pixels Gr.

[0111] For example, when two B pixels B are set as read pixels and two special pixels Z1 and Z2 are set as limit action pixels to read signals, a high-level voltage is applied to the horizontal selection line HS1, the special horizontal selection line ZS, and the vertical selection line VS6 and the vertical selection line VS8. In addition, a low-level voltage is applied to the other horizontal selection lines HS and the vertical selection lines VS.

[0112] Thus, the signals of the two B pixels B and the two special pixels Z1 and Z2 can be connected only to the output line RW. Also, similarly to the above example, a predetermined voltage is applied to the reset voltage line HR, etc., so that the two B pixels B are read pixels and the two special pixels Z1 and Z2 become limit operation pixels, and the above-mentioned correlated double sampling can be performed.

[0113] In this case, a high-level voltage is applied to the horizontal selection line HS2 instead of the special horizontal selection line ZS, and Figure 5By applying a predetermined voltage to the reset voltage line HR2 at the timing shown, two G pixels Gr connected to the horizontal selection line HS2 can also be used as slice operation pixels.

[0114] In addition, the horizontal selection line HS3 arranged in parallel with the special horizontal selection line ZS is not connected to the special horizontal selection transistor TH2 in the special pixels Z1 and Z2. Therefore, when reading the signal of the B pixel B in the pixel block BC2, no matter what signal the horizontal control unit HC sends to the horizontal selection line HS3, the signal from the special pixels Z1 and Z2 will not be mixed in the signal read from the B pixel B.

[0115] Here, the horizontal selection line HS3 is shared by the pixel block BC2 and other pixel blocks BC such as the pixel block BC1 adjacent in the x direction. Therefore, the signal applied to the horizontal selection line HS3 is preferably a signal suitable for readout by other pixel blocks BC.

[0116] Similarly to the above, the special pixel ZZ can be used as a read pixel, and the other imaging pixels 30 c can be used as clipping operation pixels to read out the signal of the special pixel ZZ.

[0117] As an example, when the special pixel Z2 in the area PB is set as a read pixel and the G pixel Gr in the area PB is read as a limit action pixel, a high-level voltage is applied to the vertical selection line VS8, the horizontal selection line HS4, and the special horizontal selection line ZS. In addition, a low-level voltage is applied to the other vertical selection lines VS and the horizontal selection line HS.

[0118] Thus, the signals of the special pixel Z2 in the area PB and the G pixel Gr in the area PB can be connected only to the output line RW.

[0119] Moreover, similarly to the above example, a predetermined voltage may be applied to the reset voltage line HR etc. so that the special pixel Z2 in the area PB becomes a read pixel and the G pixel Gr in the area PB becomes a limit operation pixel, and the above-mentioned correlated double sampling may be performed.

[0120] The above describes the reading of the signals of the pixels 30 in the pixel block BC2, but the same is true for the other pixel blocks BC. The signals of each pixel 30 of each pixel block BC are output to the output lines RW respectively provided in each pixel block BC, and are read out by the readout unit. In addition, when reading out pixel blocks other than the pixel block BC2, the vertical selection lines VS, the horizontal selection lines HS, and the special horizontal selection lines ZS may also be shared by multiple pixel blocks BC. For example, the horizontal selection lines HS1 to HS4 may also be connected to the pixels 30 of other pixel blocks BC arranged along the x direction relative to the pixel block BC2, as in the case of the pixel block BC1. In addition, the vertical selection lines VS5 to VS8 may also be connected to the pixels 30 of other pixel blocks BC arranged along the y direction relative to the pixel block BC2.

[0121] In addition, the order of reading out the signals of the special pixel ZZ and the imaging pixel (Gb, Gr, R, B) is arbitrary. For example, the control unit CU first selects the special pixel ZZ via the vertical selection line VS and the horizontal selection line HS, and the readout unit reads out its output signal, and then selects the imaging pixel (Gb, Gr, R, B), and the readout unit reads out its output signal.

[0122] The number of pixels of the special pixel ZZ in the pixel block BC (Z1 and Z2) is less than the number of pixels of the imaging pixel 30c (Gb, Gr, R, B totaling 14). Therefore, the time required to read out the signal of the special pixel ZZ is shorter than the time required to read out the signal of the imaging pixel. In other words, the signal of the special pixel ZZ is read out at a higher speed than the signal of the imaging pixel 30c. For example, when the special pixel ZZ is an AF pixel, the signal of the special pixel ZZ is read out before the signal of the imaging pixel (Gb, Gr, R, B), thereby enabling the control unit 4 to perform focus detection at a high speed.

[0123] In addition, two readout units may be provided in one pixel block BC. It is also possible to connect one output line RW to the two readout units so that the two readout units read out the signal of the special pixel ZZ and the signal of the imaging pixel (Gb, Gr, R, B), respectively. Thus, the readout unit can read out the signal of the special pixel ZZ and the signal of the imaging pixel (Gb, Gr, R, B), respectively, under conditions such as the optimal readout gain.

[0124] In the combined readout of the readout pixel and the clipping operation pixel described above, no high-level signal (transmission signal) is applied to the gate of the transfer transistor TX in the clipping operation pixel. Therefore, the photodiode PD in the pixel used as the clipping operation pixel stores the charge (photoelectric signal) generated by exposure.

[0125] Therefore, after the readout based on the combination of the readout pixel and the clipping operation pixel described above is completed, at least one of the pixels used as the clipping operation pixel can be used as a readout pixel and its signal can be read out.

[0126] In the above embodiment, the voltage applied to the reset portion (reset transistor TR) of the clipping action pixel may be two voltages, namely, the first voltage VC1 and the second voltage VC2. In addition, correspondingly, the voltage source connected to the reset voltage line HR via the reset line switching switch SR in the horizontal control unit HC may be the first voltage line RR1 and the second voltage line RR2 supplied with a second voltage closer to the substrate voltage than the first voltage.

[0127] In this case, Figure 5 The HR voltage in the illustrated clipping operation pixel (voltage supplied to the reset voltage line HR connected to the clipping operation pixel) only needs to be the first voltage VC1 from time t0 to time t1 and the second voltage VC2 after time t1.

[0128] In this case, the second voltage VC2 may be set to a voltage of about 20% to 40% of the first voltage VC1 with respect to the ground voltage.

[0129] In the above embodiment, among the pixels 30 that are totaled and read out by the source binning readout, the readout pixel can be interpreted as the first pixel. One of the clipping operation pixels can be interpreted as the second pixel.

[0130] In addition, since the charge photoelectrically converted by the photodiode PD is transferred to the FD region FD of each pixel 30 and stored there, it can be interpreted as a storage unit. Moreover, the FD region FD of the read pixel (first pixel) can also be interpreted as a first storage unit, and the FD region FD of the limit operation pixel (second pixel) can also be interpreted as a second storage unit.

[0131] In addition, in the above embodiment, it is also possible not to use the clipping action pixels, and only the pixels 30 that are summed and read out by source binning are used as a plurality of readout pixels. This can be achieved by not selecting the pixels used as clipping action pixels in the above readout example. Specifically, when performing correlated double sampling, it is sufficient to not select the clipping action pixels using the vertical selection line VS, the horizontal selection line HS, and the special horizontal selection line ZS, or not send signals for controlling various reset voltages or reset transistors TR to the clipping action pixels at a predetermined timing.

[0132] In this case, any one or more of the plurality of pixels 30 that are read out in total can be interpreted as the first pixel, and one or more of the pixels other than the first pixel can be interpreted as the second pixel. Furthermore, the voltage generated in the FD region FD of the first pixel to which the charge generated in the photodiode PD is transferred can be interpreted as the first voltage, and the voltage generated in the FD region FD of the second pixel to which the charge generated in the photodiode PD is transferred can be interpreted as the second voltage.

[0133] Figure 6 3 is a diagram showing a cross section of a pixel 30 portion of the image pickup element 3 according to the present embodiment. Figure 6 In FIG. 1 , only a partial cross section of the entire imaging element 3 is shown. Figure 6 The x-direction and z-direction shown in Figure 1 The directions shown in FIG. 3 are the same. The imaging element 3 is a so-called back-illuminated imaging element. The imaging element 3 performs photoelectric conversion on light incident from above the paper surface. The imaging element 3 includes a first semiconductor substrate 7 and a second semiconductor substrate 8.

[0134] As described above, the image sensor 3 has a plurality of pixels 30. One pixel 30 includes a pixel upper portion 30x provided on the first semiconductor substrate 7 and a pixel lower portion 30y provided on the second semiconductor substrate 8. One pixel upper portion 30x includes one microlens 74, one color filter 73, one light receiving portion 31 of a photodiode PD, and the like.

[0135] The first semiconductor substrate 7 includes a light receiving layer 71 including the light receiving portion 31 of the photodiode PD included in the pixel upper portion 30x, and a wiring layer 72 formed with transistors such as a transfer transistor TX and an amplifying transistor TA. The light receiving layer 71 is arranged on the opposite side (back side) of the wiring layer 72 of the first semiconductor substrate 7. A plurality of light receiving portions 31 are arranged two-dimensionally on the light receiving layer 71.

[0136] Since the pixel upper portion 30 x surrounds the light receiving portion 31 that performs photoelectric conversion on incident light, it can also be interpreted as an imaging portion.

[0137] The second semiconductor substrate 8 is provided with a vertical selection transistor TV, a horizontal selection transistor TH1, a special horizontal selection transistor TH2, a vertical selection line VS, a horizontal selection line HS, a special horizontal selection line ZS, a readout unit, a current source CS, and the like included in the pixel lower portion 30y.

[0138] A plurality of bumps 75 are arranged on the surface of the wiring layer 72. A plurality of bumps 76 corresponding to the plurality of bumps 75 are arranged on the surface of the second semiconductor substrate 8 that faces the wiring layer 72. The plurality of bumps 75 and the plurality of bumps 76 are bonded to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the plurality of bumps 75 and the plurality of bumps 76, that is, the first semiconductor substrate 7 and the second semiconductor substrate 8 are stacked.

[0139] Furthermore, since the readout section that reads out signals from the plurality of pixels 30 is disposed on the second semiconductor substrate 8 , it can also be interpreted as being stacked on the imaging section disposed on the first semiconductor substrate 7 .

[0140] The circuit elements respectively arranged on the first semiconductor substrate 7 and the second semiconductor substrate 8 are merely examples, and some of the components may be arranged on either the first semiconductor substrate 7 or the second semiconductor substrate 8 .

[0141] The photodiode PD including the light receiving layer 71 including the light receiving part 31, the transmission transistor TX, the amplification transistor TA, the vertical selection transistor TV, the horizontal selection transistor TH2, the horizontal selection transistor TH1, the special horizontal selection transistor TH2, the horizontal selection lines HS3, HS4, and the special horizontal selection line ZS can also be formed on the first semiconductor substrate 7, and the readout part and the current source CS can be configured on the second semiconductor substrate 8.

[0142] The vertical control portion VC and the horizontal control portion HC may be arranged on either the first semiconductor substrate 7 or the second semiconductor substrate 8 .

[0143] Here, if a plurality of circuit elements are arranged on the first semiconductor substrate 7 , it is not possible to sufficiently ensure an area or volume for arranging the light receiving unit 31 on the first semiconductor substrate 7 . Therefore, the readout unit and the current source CS are preferably arranged on the second semiconductor substrate 8 .

[0144] The color filter 73 of each pixel 30 is provided with a color filter that matches the spectral sensitivity characteristics of each pixel.

[0145] In addition, a color filter 73 is configured in the special pixel ZZ in the pixel 30. When the special pixel ZZ is an AF pixel, the color filter of G is set to the color filter 73. In addition, the color filter 73 provided in the special pixel ZZ may also be a filter that transmits the full wavelength range of the incident light. In addition, the color filter 73 provided in the special pixel ZZ may also be a color filter 73 having different spectral characteristics from the color filter 73 provided in the imaging pixel 30c.

[0146] When the special pixel ZZ is a pixel for receiving infrared light, the color filter 73 has high transmittance for infrared light and low transmittance for visible light. In addition, when the special pixel ZZ is a pixel for receiving visible light, the color filter 73 has high transmittance for the entire wavelength range of visible light.

[0147] In addition, the sensitivity of the special pixel ZZ may be made different from the sensitivity of the imaging pixel 30c by making the average transmittance of the color filter 73 of the special pixel ZZ different from the average transmittance of the color filter 73 of the imaging pixel 30c. Here, the average transmittance refers to the average value of the transmittance of the full wavelength of the light photoelectrically converted by the light receiving unit 31.

[0148] The sensitivity of the special pixel ZZ may be different from that of the imaging pixel 30 c by making the area of ​​the light receiving portion 31 of the special pixel ZZ different from that of the imaging pixel 30 c or making the conditions for ion implantation into the light receiving portion 31 different.

[0149] Figure 7 is a diagram showing an example of a case where the special pixel ZZ is an AF pixel. Figure 7 In, from Figure 6 The second semiconductor substrate 8 is omitted in the cross-sectional view of the imaging element 3 shown.

[0150] The special pixel Z1 has a light shielding portion 75R shielding the right side of the light receiving portion 31 at the boundary between the color filter 73 and the first semiconductor substrate 7. On the other hand, the special pixel Z2 has a light shielding portion 75L shielding the left side of the light receiving portion 31 at the boundary.

[0151] Of the light incident on the special pixel Z1, the light LL incident obliquely in the -x direction relative to the direction PL perpendicular to the incident surface of the imaging element 3 is blocked by the light shielding portion 75R. On the other hand, of the light incident on the special pixel Z2, the light LR incident obliquely in the +x direction relative to the direction PL perpendicular to the incident surface of the imaging element 3 is blocked by the light shielding portion 75L.

[0152] As a result, the special pixels Z1 and Z2 have lower sensitivities to light incident from different incident directions, and conversely, have relatively higher sensitivities to light incident from different incident directions.

[0153] If the imaging element 3 is applied to Figure 1 In the imaging device, the special pixels Z1 and Z2 become elements with high sensitivity to light passing through from different positions on the pupil plane of the imaging optical system 2, and therefore function as pixels for image plane phase difference focus detection.

[0154] The positions where the light shielding portions 75R and 75L are provided are not limited to the boundary between the color filter 73 and the first semiconductor substrate 7 , and may be provided anywhere between the microlens 74 and the first semiconductor substrate 7 .

[0155] In the above-mentioned embodiment of the imaging element, the arrangement of each pixel 30 is not necessarily in the Bayer array. In addition, the horizontal selection line HS and the special horizontal selection line ZS may extend in the short side direction instead of the long side direction of the imaging element 3, and the vertical selection line VS may extend in the long side direction instead of the short side direction of the imaging element 3.

[0156] In addition, the horizontal selection line HS, the special horizontal selection line ZS, and the vertical selection line VS that control the output of the signal of each pixel 30 may not extend in the horizontal direction (x direction) and the vertical direction (y direction). Moreover, the horizontal selection line HS, the special horizontal selection line ZS, and the vertical selection line VS may not be shared by multiple pixels 30.

[0157] In addition, the output of the signal from the special pixel ZZ often becomes a value smaller than the output of the signal from the imaging pixel 30c due to the provision of the light shielding portions 75R, 75L, etc. Therefore, an amplifier circuit that increases the output of the signal, for example, by about 2 times may be embedded in the special pixel ZZ. Alternatively, the value may be increased by adding an offset to the output signal from the special pixel ZZ.

[0158] Furthermore, in the above-described embodiment, the total number of imaging pixels 30c and B pixels B in each pixel block BC varies depending on whether the pixel block BC includes a special pixel ZZ. Therefore, when performing the above-described combined readout, the size of the added signal of the pixel block BC may also vary depending on whether the pixel block BC includes a special pixel ZZ.

[0159] Therefore, in order to prevent the variation of the added signal, a correction circuit may be provided to increase or decrease the added signal of the pixel block BC including the special pixels ZZ in accordance with the number of special pixels ZZ included in the pixel block BC. The correction circuit may be provided in the pixel block BC or in the imaging element 3 outside the pixel block BC. Alternatively, instead of providing the correction circuit in the imaging element 3, the correction may be performed in the control unit 4.

[0160] For example, in Figure 2In the example shown in (b), the pixel block BC1 does not include the special pixel ZZ, and includes 4 G pixels Gb, G pixels Gr, B pixels B, and R pixels R respectively. On the other hand, the pixel block BC2 includes 2 special pixels ZZ (Z1, Z2), and includes 4 G pixels Gb, G pixels Gr, and R pixels R respectively, but includes only 2 B pixels B. Therefore, when the B pixels B are read out in the pixel block BC2, the added signal is set to (4 / 2) times. As a result, the added signal when the B pixels B are read out in the pixel block BC1 and the pixel block BC2 can be set to be almost the same.

[0161] (Effects of the Embodiments of the Image Pickup Element)

[0162] (1) The imaging element 3 of the above embodiment includes a first pixel and a second pixel. The first pixel includes a photodiode (first photoelectric conversion unit) PD that generates charges by photoelectrically converting light, an FD region (first storage unit) FD that accumulates the charges generated by the photodiode PD, and a selection transistor (first output unit) TH1 that outputs a first signal based on the voltage of the FD region FD, and the second pixel includes a photodiode (second photoelectric conversion unit) PD that generates charges by photoelectrically converting light, an FD region (second storage unit) FD that accumulates the charges generated by the photodiode PD, and a selection transistor (second output unit) TH1 or TH2 that outputs a second signal based on the voltage of the FD region FD. The imaging element 3 of the above embodiment further includes: an output line RW, which is connected to the selection transistor TH1 of the first pixel and the selection transistor TH1 or TH2 of the second pixel and outputs the first signal and the second signal; and a control unit CU, which can control the voltage of the FD region FD of the first pixel to the first voltage, and control the voltage of the FD region FD of the second pixel to the second voltage different from the first voltage or the first voltage.

[0163] Since it is configured in this manner, there is an effect that the output of any one or a plurality of pixels 30 among a plurality of pixels connected to the output line RW can be selected and output to the output line RW.

[0164] (2) Furthermore, the control unit CU can control the second storage unit to the second voltage while the first output unit outputs the first signal. Thus, even when the first signal is an abnormal value outside a predetermined range, it is possible to prevent excessive current from being generated in the current source IS and prevent the imaging element 3 from being damaged.

[0165] Various embodiments and variations have been described above, but the present invention is not limited to these contents. In addition, each embodiment and variation can be applied separately or in combination. Other forms that can be imagined within the scope of the technical thought of the present invention are also included in the scope of the present invention.

[0166] The disclosure contents of the following priority basic applications are incorporated herein by reference.

[0167] Japan Special Application No. 2018-185635 (applied on September 28, 2018)

[0168] Description of Reference Numerals

[0169] 1: imaging device, 2: imaging lens, 3: imaging element, 4: control unit (generating unit), 5: lens moving unit, 7: first semiconductor substrate, 8: second semiconductor substrate, BC, BC1, BC2: pixel block, HC: horizontal control unit, VC: vertical control unit, CU: control unit, pixel 30, Gr, Gb: G pixel, R: R pixel, B: B pixel, Z1, Z2: special pixel, VS, VS1~HS8: ​​vertical selection line, HS, HS1~HS4: horizontal selection line, ZS: special horizontal selection line, HR, HR1~HR4: reset voltage line, PD: photodiode, TX: transfer transistor, TR: reset transistor, TA: amplifier transistor, TV: vertical selection transistor, TH1: horizontal selection transistor, TH2: special horizontal selection transistor, RW: readout line, ADC: readout unit, 31: photosensitive unit, 73: color filter.

Claims

1. An imaging element, characterized in that: The device comprises a plurality of pixel blocks arranged in a matrix along the row direction and the column direction, output lines and a control unit, Each of the plurality of pixel blocks comprises: a first pixel including a first photoelectric conversion unit that generates charges by photoelectrically converting light, a first storage unit that stores the charges generated by the first photoelectric conversion unit, and a first output unit that outputs a first signal for image generation based on a voltage of the first storage unit; and a second pixel including a second photoelectric conversion unit for generating electric charges by photoelectrically converting light, a second storage unit for storing the electric charges generated by the second photoelectric conversion unit, and a second output unit for outputting a second signal for focus detection based on a voltage of the second storage unit, The output line is connected to the first output unit and the second output unit, and the first signal and the second signal are output to the output line. The control unit can control the voltage of the first storage unit to be a first voltage, and can control the voltage of the second storage unit to be a second voltage different from the first voltage or the first voltage.

2. The imaging element according to claim 1, wherein: The control unit controls the second storage unit to have the second voltage while the first output unit is outputting the first signal.

3. The imaging element according to claim 1 or 2, wherein: having a plurality of the first pixels, The control unit controls the voltage of the second storage unit to the second voltage during a period in which each of the plurality of first output units outputs the first signal.

4. The imaging element according to claim 3, wherein: The control unit controls the voltage of the second storage unit to the second voltage while the plurality of first output units are simultaneously outputting the first signal.

5. The imaging element according to claim 1 or 2, wherein: The control unit controls the voltage of the second storage unit to be the first voltage during at least a portion of a period in which the first output unit does not output the first signal.

6. The imaging element according to claim 1 or 2, wherein: The voltage of the first storage section is a voltage based on the charge generated by the first photoelectric conversion section and stored in the first storage section.

7. The imaging element according to claim 1 or 2, wherein: have: a first wiring for setting the voltage of the first storage unit and the voltage of the second storage unit to the first voltage; and a second wiring for setting the voltage of the second storage unit to the second voltage, The control unit controls the voltage of the first storage unit via the first wiring, and controls the voltage of the second storage unit via the second wiring.

8. The imaging element according to claim 1 or 2, wherein: The control unit controls a voltage of at least one of the first storage unit and the second storage unit to be the first voltage or the second voltage.

9. The imaging element according to claim 8, wherein: The control unit controls the voltage of the second storage unit to be the second voltage while the first output unit outputs the first signal, and controls the voltage of the first storage unit to be the second voltage while the second output unit outputs the second signal.

10. The imaging element according to claim 8, wherein: The voltage of the first storage unit is a voltage based on the charge generated by the first photoelectric conversion unit and stored in the first storage unit. The voltage of the second storage section is a voltage based on the charge generated by the second photoelectric conversion section and stored in the second storage section.

11. The imaging element according to claim 8, wherein: have: a first wiring for setting the voltage of the first storage unit and the second storage unit to the first voltage; and a second wiring for setting the voltage of the first storage unit and the second storage unit to the second voltage, The control unit controls the voltages of the first storage unit and the second storage unit via the first wiring and the second wiring.

12. The imaging element according to claim 1 or 2, wherein: The control unit controls the voltage of the second storage unit to be the second voltage or a third voltage different from the first voltage and the second voltage.

13. The imaging element according to claim 12, wherein: The control unit controls the voltage of the second storage unit to the third voltage after controlling the voltage of the second storage unit to the second voltage.

14. The imaging element according to claim 12, wherein: The first output unit outputs a signal for correcting the first signal while the voltage of the second storage unit is the second voltage, and outputs the first signal while the voltage of the second storage unit is the third voltage.

15. The imaging element according to claim 12, wherein: comprising a third wiring for setting the potential of the second storage unit to the third voltage, The control unit controls the voltage of each of the second storage units via the third wiring.

16. The imaging element according to claim 1 or 2, characterized in that: comprising a plurality of first pixels connected to the output line, The first pixel includes a first filter having a first spectral characteristic. The first photoelectric conversion section performs photoelectric conversion on the light transmitted through the first filter.

17. The imaging element according to claim 1 or 2, characterized in that: A readout section is provided, the readout section being stacked on an imaging section having the first pixel and the second pixel and reading out the first signal and the second signal from the output line.

18. An imaging element, characterized in that: The device comprises a plurality of pixel blocks arranged in a matrix along the row direction and the column direction and a control unit. Each of the plurality of pixel blocks comprises: A pixel having a first photoelectric conversion unit for generating electric charges by photoelectrically converting light, a first storage unit for storing the electric charges generated by the first photoelectric conversion unit, and a first output unit for outputting a first signal for focus detection based on a voltage of the first storage unit, The control unit can control the voltage of the first storage unit to be a first voltage or a second voltage different from the first voltage.

19. A camera device, characterized in that: have: The imaging element according to any one of claims 1 to 18; and A generating unit generates image data based on the first signal.

Images