A power semiconductor device and a method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a power semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a groove in a semiconductor substrate of a first doping type, forming a first dielectric layer and a second dielectric layer in the groove; removing the first dielectric layer at a certain depth in a part of the groove top region; removing the second dielectric layer in the groove to form a second groove structure; forming a gate oxide in the second groove, so that an oxide layer at the bottom of the groove sidewall is composed of the first dielectric layer and the gate oxide, and has a relatively thick thickness, so as to form a conductive material without gap filling; selectively removing the conductive material at the groove top to separate the conductive material by a certain distance, so as to form a third groove and a fourth groove in the groove; filling the third groove and the fourth groove with a third dielectric layer, so as to reduce the risk of short circuit and leakage between a shield conductor and a gate conductor, and optimize the capacitance parameter between GS, thereby improving the yield of the power semiconductor device and reducing the reliability risk.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a power semiconductor device and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices are also called power electronic devices, including power diodes, thyristors, VDMOS (vertical double diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral diffused metal oxide semiconductor) field effect transistors and IGBT (insulated gate bipolar transistors). VDMOS field effect transistors include source and drain regions formed on opposite surfaces of a semiconductor substrate. In the on state, the current mainly flows along the longitudinal direction of the semiconductor substrate. In the high-frequency application of power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance.

[0003] On the basis of VDMOS field effect transistor, trench MOS field effect transistor was further developed, wherein a gate conductor was formed in the trench, and a gate dielectric was formed on the sidewall of the trench to separate the gate conductor and the semiconductor layer, thereby forming a channel in the semiconductor layer along the direction of the trench sidewall. The trench process changes the channel from horizontal to vertical, eliminates the effect of the parasitic JFET resistance of the planar structure, and greatly reduces the size of the cell. On this basis, increasing the cell density and increasing the total width of the channel per unit area of ​​the chip can increase the channel width-to-length ratio of the device on a unit silicon wafer, thereby increasing the current, reducing the on-resistance, and optimizing related parameters, achieving the goal of having a smaller die with greater power and high performance. Therefore, the trench process is increasingly used in new power semiconductor devices. In order to reduce the gate-drain capacitance Cgd, the split gate trench (abbreviated as SGT) type power semiconductor device was further developed, wherein the gate conductor extends to the drift region, and the gate conductor and the drain are separated by thick oxide, thereby reducing the gate-drain capacitance Cgd, increasing the switching speed, and reducing the switching loss. At the same time, the shielding conductor extends to the bottom of the gate conductor, separated from the semiconductor layer by an insulating layer, and connected to the source electrode and grounded together, thereby introducing a charge balance effect and reducing the surface electric field (RESURF) effect in the vertical direction of the power semiconductor device. The thicker the shielding dielectric layer thickness and the deeper the trench depth, the higher the withstand voltage, while also further reducing the on-resistance Rdson, thereby reducing the conduction loss.

[0004] The schematic diagram of the structure of the power semiconductor device in the prior art is as follows Figure 1 As shown. As an example, the power semiconductor device is a trench gate MOSFET power semiconductor device.

[0005] like Figure 4 As shown, the trench gate MOSFET power semiconductor device includes a plurality of trenches 11 in an epitaxial layer 10b on a semiconductor substrate 10a. A first dielectric layer 12 and a first conductive material 13 are formed in the trenches, and a gate oxide 14 and a conductive material 15 are formed on the top of the trenches 11. P-type doping 16 and N-type doping 17 are formed on the epitaxy, and a third dielectric layer 18, contact holes and a metal layer 21 are formed on the epitaxy and the top of the trenches, and finally metal electrodes 22, 23, 24 are formed.

[0006] Figure 5 Show Figure 4 A schematic diagram of the local enlarged structure of the power semiconductor device shown.

[0007] like Figure 5 Shown Figure 4 The structure enlarged diagram of the 30 area, wherein the oxide layer between the first conductive material 13 and the conductive material 15 is 14b, and its thickness d2 ≥ the thickness d1 of the trench sidewall gate oxide 14. The conductive material 15 is higher than the epitaxial surface, and the metal electrode 24 is connected to the conductive material 15 through the lead hole, and the distance between the bottom of the lead hole and the oxide layer 14b on the top of the first conductive material is d3. If d3 is smaller, the risk of GS leakage or even GS short circuit is likely to occur. At the same time, in split-gate power semiconductor devices, the gate-source capacitance Cgs is affected by the thickness of the oxide layer between the polycrystalline. The thicker the oxide layer thickness, the smaller the capacitance Cgs, and the faster the switching speed of the device. Therefore, how to maximize the thickness of the oxide layer 14b and optimize the device parameter performance is the content of research by personnel in this industry.

[0008] For split-gate power semiconductor devices with a withstand voltage of more than 100V, the depth of the trench is usually more than 5um, and the thickness of the shield gate is usually more than 5000A. In order to pursue a smaller chip area, the width of the trench is also required to be narrower, so that the aspect ratio of the trench is very large, making the conductive material filling process very complicated, and it is easy to have voids and gaps. Figure 2 As shown, during the filling process of the first polycrystalline 13, cavities 13a and gaps 13b are easily formed, thereby causing the risk of GS leakage or even GS short circuit due to poor filling of the first conductive material. How to optimize the filling process and technology is the subject of research by personnel in this industry.

[0009] Meanwhile, in the prior art, the first conductive material and the conductive material are formed by at least two deposition processes, which is complex and has high cost.

[0010] How to optimize the defect-free filling process and technology of conductive materials with large aspect ratio, how to reduce manufacturing costs, increase the thickness of the oxide layer between two layers of polycrystalline, make the capacitance Cgs smaller, and make the switching speed of the device faster, and at the same time improve the metal electrode wiring method of the conductive material at a low cost to avoid GS abnormalities caused by the metal wiring method between GS. Further improving the thickness of the oxide layer formed at the bottom of the groove side wall, optimizing the withstand voltage between GS, and reducing the risk of leakage short circuit or even gate oxide breakdown between GS are the contents of research by personnel in this industry. Summary of the invention

[0011] In view of the deficiencies in the prior art, the present invention provides a method for manufacturing a power semiconductor device. The technical problem to be solved is how to optimize the product structure to reduce the risk of short circuit and leakage between the shield conductor and the gate conductor, optimize the capacitance parameters between GS, and thereby improve the yield of the power semiconductor device and reduce the reliability risk.

[0012] In order to solve the above technical problems, the present invention provides a technical solution: a method for manufacturing a power semiconductor device, the method steps are as follows:

[0013] S1: Using a semiconductor substrate with a specific doping type as a raw material, forming an epitaxial layer on the substrate, and opening a trench with a certain width and depth on the epitaxial layer;

[0014] S2: sequentially disposing a first dielectric layer and a second dielectric layer on the surface of the epitaxial layer and in the trench;

[0015] S3: removing the surface of the epitaxial layer and the second dielectric layer at the top of the trench by chemical mechanical planarization;

[0016] S4: removing the first dielectric layer on the surface of the epitaxial layer and the top of the trench by wet or dry etching to form a first groove structure;

[0017] S5: removing the second dielectric layer in the groove by wet or dry etching to form a second groove structure;

[0018] S6: performing gate oxide oxidation on the side wall of the second groove close to the epitaxial layer by a thermal oxidation process, so that a conductive material is formed in the second groove;

[0019] S7: selectively removing the conductive material in the groove, and separating the conductive material by a certain distance to form a third groove and a fourth groove;

[0020] S8: filling the third groove and the fourth groove with a third dielectric layer by using a thermal oxidation or chemical vapor deposition (CVD) method;

[0021] S9: Select appropriate dopants, use multiple ion implantation methods to form different types of doping regions, and then perform thermal annealing to activate the impurities to form the device's internal doping region and the required PN junction and other device structures;

[0022] S10: forming a fourth dielectric layer on the surface of the epitaxial layer and the top of the trench by using a chemical vapor deposition (CVD) method, and selectively forming contact holes by using a photolithography and etching process, and performing contact hole implantation;

[0023] S11: Use MOCVD, PVD and other processes to deposit one or more combinations of metal materials such as Ti, TiN, W, AL, ALSI, ALCU, ALSICU, etc. to fill the contact holes, and then use photolithography and etching processes to form metal electrodes.

[0024] Furthermore, in step S1, the material of the semiconductor substrate is a III-V semiconductor GaAs, InP, GaN or a IV semiconductor Si, Ge, the semiconductor substrate is a single crystal silicon substrate doped into N type, the epitaxial layer is a single crystal silicon epitaxial layer doped into N type, and the ratio of the depth to the width of the trench is less than 10Å.

[0025] Furthermore, in step S2, a first dielectric layer is formed by thermal oxidation or chemical vapor deposition (CVD), thermal oxidation includes hydrothermal oxidation (HTO) or selective reactive oxidation (SRO), chemical vapor deposition (CVD) includes low pressure chemical vapor deposition (LPCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD), and the second dielectric layer is composed of one or more of silicon nitride and silicon oxynitride, and the thickness of the second dielectric layer is greater than or equal to 10Å.

[0026] Furthermore, in step S4, when a wet method is used, according to the characteristics of wet etching, the first dielectric layer at the top of the trench will form an arc structure close to the side wall of the epitaxial layer.

[0027] Further, in step S5, wet or dry etching is used to completely remove all the second dielectric layers in the grooves, retaining the morphology of the first dielectric layer formed in S4, and forming a second groove structure with the surface of the epitaxial layer and the arc-shaped sidewalls at the top of the groove exposed. After the second groove is formed, the aspect ratio of the area to be filled with subsequent polycrystalline is smaller than the aspect ratio of the groove.

[0028] Furthermore, in step S6, the thickness of the gate oxide is 50Å~2000Å, an arc-shaped structure appears near the side wall of the epitaxial layer of the second groove, so that the thickness of the bottom of the groove side wall is consistent with the thickness of other areas, the conductive material is composed of in-situ doped polysilicon, the deposition temperature is 500℃~800℃, the square resistance is 3Ω~20Ω, the thickness is 1000Å~20000Å, and the conductive material is filled seamlessly in the groove.

[0029] Further, in step S7, the third groove corresponds to the shielding polycrystalline region of the split-gate power device, and the conductive material in the middle of the groove needs to be retained and the conductive material on both sides needs to be removed. The area where the conductive material is removed needs to be filled with a dielectric layer later. The fourth groove corresponds to the original cell area structure, and the conductive material on both sides of the top of the groove is retained as the gate of the split-gate power device by selective etching, and the conductive material in the middle area of ​​the groove is removed from top to bottom to separate the conductive material into two sections of shielding polycrystalline and gate polycrystalline.

[0030] Further, in step S8, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, and the chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.

[0031] Furthermore, in step S10, chemical vapor deposition (CVD) including low pressure chemical vapor deposition (LPCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) is used to form one or more combinations of dielectric layers such as NSG, BPSG, PSG, SiN, and SiON.

[0032] A power semiconductor device comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the semiconductor substrate, a groove is provided in the epitaxial layer, a first dielectric layer is arranged in the groove, a conductive material is arranged in the first dielectric layer, a gate oxide layer is wrapped outside part of the conductive material, a fourth dielectric layer is arranged on the top of the gate oxide layer, a first conductive window, a second conductive window and a third conductive window are provided on the upper part of the fourth dielectric layer, the bottom end of the first conductive window is connected to the conductive material, an upper source region and a lower source region are arranged between part of the grooves, the bottom end of the second conductive window passes through the upper source region and extends into the lower source region, the bottom end of the third conductive window extends into both sides of the conductive material, and a first metal electrode, a second metal electrode and a third metal electrode are respectively arranged in the first conductive window, the second conductive window and the third conductive window.

[0033] The beneficial effects brought about by this technical solution are: an optimized power semiconductor device is designed, the shield conductor and the gate conductor are simultaneously seamlessly filled, the difficulty of process implementation is reduced, the withstand voltage between GS is optimized, and the risk of leakage, short circuit and even gate oxide breakdown between GS is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0035] Figure 1 A flowchart of a method for manufacturing a power semiconductor device according to the present invention;

[0036] Figure 2 It is a partial structural schematic diagram of a power semiconductor device of the present invention;

[0037] Figure 3 It is a schematic diagram of the main structure of a power semiconductor device of the present invention;

[0038] Figure 4 It is a schematic diagram of the structure of a power semiconductor device in the prior art;

[0039] Figure 5 for Figure 1 Schematic diagram of the local enlarged structure in;

[0040] In the figure: 101-semiconductor substrate, 102-epitaxial layer, 110-groove, 120-first dielectric layer, 150-conductive material, 140-gate oxide layer, 180-fourth dielectric layer, 201-first conductive window, 202-second conductive window, 203-third conductive window, 170-upper source region, 160-lower source region, 211-first metal electrode, 212-second metal electrode, 213-third metal electrode. DETAILED DESCRIPTION

[0041] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention. Figure 1 As shown, the manufacturing method of a power semiconductor device has the following steps:

[0042] S1: Using a semiconductor substrate with a specific doping type as a raw material, forming an epitaxial layer on the substrate, and opening a trench with a certain width and depth on the epitaxial layer;

[0043] S2: sequentially disposing a first dielectric layer and a second dielectric layer on the surface of the epitaxial layer and in the trench;

[0044] S3: removing the surface of the epitaxial layer and the second dielectric layer at the top of the trench by chemical mechanical planarization;

[0045] S4: removing the first dielectric layer on the surface of the epitaxial layer and the top of the trench by wet or dry etching to form a first groove structure;

[0046] S5: removing the second dielectric layer in the groove by wet or dry etching to form a second groove structure;

[0047] S6: performing gate oxide oxidation on the side wall of the second groove close to the epitaxial layer by a thermal oxidation process, so that a conductive material is formed in the second groove;

[0048] S7: selectively removing the conductive material in the groove, and separating the conductive material by a certain distance to form a third groove and a fourth groove;

[0049] S8: filling the third groove and the fourth groove with a third dielectric layer by using a thermal oxidation or chemical vapor deposition (CVD) method;

[0050] S9: Select appropriate dopants, use multiple ion implantation methods to form different types of doping regions, and then perform thermal annealing to activate the impurities to form the device's internal doping region and the required PN junction and other device structures;

[0051] S10: forming a fourth dielectric layer on the surface of the epitaxial layer and the top of the trench by using a chemical vapor deposition (CVD) method, and selectively forming contact holes by using a photolithography and etching process, and performing contact hole implantation;

[0052] S11: Use MOCVD, PVD and other processes to deposit one or more combinations of metal materials such as Ti, TiN, W, AL, ALSI, ALCU, ALSICU, etc. to fill the contact holes, and then use photolithography and etching processes to form metal electrodes.

[0053] An optimized power semiconductor device is designed in this way, which realizes seamless filling of shield conductor and gate conductor at the same time, reduces the difficulty of process implementation, optimizes the withstand voltage between GS, and reduces the risk of leakage, short circuit and even gate oxide breakdown between GS.

[0054] Overall, the trench filling process and technology are optimized, reducing the risk of voids and gaps in polycrystalline filling when the trench aspect ratio is large, thereby reducing the risk of short circuits and leakage between the shield conductor and the gate conductor, and optimizing the capacitance parameters between GS, thereby improving the yield of power semiconductor devices and reducing reliability risks.

[0055] In this embodiment, in step S1, the material of the semiconductor substrate is III-V semiconductor GaAs, InP, GaN or IV semiconductor Si, Ge, the semiconductor substrate is a single crystal silicon substrate doped with N type, the epitaxial layer is a single crystal silicon epitaxial layer doped with N type, the depth to width ratio of the groove is less than 10Å, for trench gate power semiconductor devices with different withstand voltage levels, the depth of the groove is different, usually, for split gate power semiconductor devices, the deeper the depth of the groove, the higher the withstand voltage of the device, the range is 1~15μm, and the width of the groove usually decreases as the chip size decreases. When the aspect ratio of the groove is greater than 10Å, problems such as gaps and voids are likely to occur.

[0056] In this embodiment, in step S2, the first dielectric layer is formed by thermal oxidation or chemical vapor deposition CVD, the thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, the chemical vapor deposition CVD includes pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD, the second dielectric layer is composed of one or more of silicon nitride and silicon oxynitride, and the thickness of the second dielectric layer is greater than or equal to 10Å, thus, the first dielectric layer is used as an isolation layer between the shielding conductor and the semiconductor substrate in the power semiconductor device, and for trench gate power semiconductor devices with different withstand voltage levels, the thickness of the insulating layer is adjusted with the withstand voltage, the depth of the trench, the epitaxial concentration, etc., and generally, the higher the withstand voltage, the thicker the insulating layer. The second dielectric layer can fill the trench completely, or there may be voids and gaps, or it may just cover the inner wall of the trench and the surface of the first dielectric layer.

[0057] In this embodiment, in step S4, when a wet method is used, according to the characteristics of wet etching, the first dielectric layer at the top of the trench will form an arc structure close to the side wall of the epitaxial layer. The arc structure can optimize the morphology of the bottom of the trench side wall and improve the thickness of the gate oxide in the subsequent oxidation process, thereby improving GS withstand voltage, leakage and other parameters and reducing reliability risks.

[0058] In this embodiment, in step S5, wet or dry etching is used to completely remove all the second dielectric layers in the grooves, retain the morphology of the first dielectric layer of the star monster in S4, and form a second groove structure with the surface of the epitaxial layer and the arc-shaped side walls at the top of the groove exposed. After the second groove is formed, the aspect ratio of the area to be filled with subsequent polycrystalline is smaller than the aspect ratio of the groove, which can reduce the damage to the epitaxial surface caused by dry etching and make the subsequent polycrystalline filling process simpler, so that the polycrystalline filling is seamless and void-free.

[0059] In this embodiment, in step S6, the thickness of the gate oxide is 5010Å~2000Å, an arc-shaped structure appears near the side wall of the epitaxial layer of the second groove, so that the thickness of the bottom of the groove wall is consistent with the thickness of other areas, the conductive material is composed of in-situ doped polysilicon, the deposition temperature is 500℃~800℃, the square resistance is 3Ω~20Ω, the thickness is 1000Å~20000Å, and the conductive material is filled in the groove without gaps, otherwise parameter problems such as leakage will occur, affecting reliability.

[0060] In this embodiment, in step S7, the third groove corresponds to the shielding polycrystalline region of the split-gate power device. It is necessary to retain the conductive material in the middle of the groove and remove the conductive material on both sides. The area where the conductive material is removed needs to be filled with a dielectric layer later. The first groove corresponds to the original cell area structure. The conductive materials on both sides of the top of the groove are retained as the gate of the split-gate power device through selective etching, and the conductive material in the middle area of ​​the groove is removed from top to bottom to separate the conductive material into two sections of the shielding polycrystalline and the gate polycrystalline, thereby improving GS parameters such as withstand voltage and leakage and reducing reliability risks.

[0061] In this embodiment, in step S8, thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation SRO, chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD, and the third dielectric layer and the first dielectric layer are made of the same material.

[0062] In this embodiment, in step S10, chemical vapor deposition CVD including low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD is used to form one or more combinations of dielectric layers such as NSG, NPSG, PSG, SiN, SiON, etc., which are used to isolate the device structure in the epitaxial layer from the subsequent metal layer.

[0063] Furthermore, selective formation of contact holes refers to the use of photolithography and etching processes to selectively form a conductive window that penetrates the dielectric layer, gate oxide layer and part of the epitaxial surface. The contact window can be divided into a dielectric layer part and an epitaxial layer part. The epitaxial layer silicon etching depth is 1000Å to 5000Å, which can reduce the on-resistance and enhance the EAS capability. In order to reduce the contact resistance, contact hole injection and RTA, furnace annealing and other processes are usually required after the contact hole is formed.

[0064] like Figure 2 , 3As shown, a power semiconductor device includes a semiconductor substrate 101, an epitaxial layer 102 is arranged on the semiconductor substrate 101, a groove 110 is opened in the epitaxial layer 102, a first dielectric layer 120 is arranged in the groove 110, a conductive material 150 is arranged in the first dielectric layer 120, a gate oxide layer 140 is wrapped around the outside of a part of the conductive material 150, a fourth dielectric layer 180 is arranged on the top of the gate oxide layer 140, and a first conductive window 201, a second conductive window 202 and a third conductive window 203 are opened on the upper part of the fourth dielectric layer 180. The bottom end of the first conductive window 201 is connected to the conductive material 150, an upper source region 170 and a lower source region 160 are arranged between some grooves 110, the bottom end of the second conductive window 202 passes through the upper source region 170 and extends into the lower source region 160, and the bottom end of the third conductive window 203 extends into both sides of the conductive material 150, and the first conductive window 201, the second conductive window 202 and the third conductive window 203 are respectively provided with a first metal electrode 211, a second metal electrode 212 and a third metal electrode 213.

[0065] An optimized power semiconductor device is designed in this way, which realizes seamless filling of the shield conductor and the gate conductor at the same time, reduces the difficulty of process implementation, optimizes the withstand voltage between GS, and reduces the risk of leakage, short circuit and even gate oxide breakdown between GS.

[0066] However, the present invention is not limited thereto, but can be applied to any type of trench power semiconductor devices, including but not limited to SGT devices, IGBT devices, TVS devices, CMOS devices, Bicmos devices, MEMS devices, Schottky devices, memories and other semiconductor devices.

[0067] Finally, it should be noted that the above description is only a preferred example of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a power semiconductor device, Features: The steps are as follows: S1: Using a semiconductor substrate with a specific doping type as a raw material, forming an epitaxial layer on the substrate, and opening a trench with a certain width and depth on the epitaxial layer; S2: sequentially disposing a first dielectric layer and a second dielectric layer on the surface of the epitaxial layer and in the trench; S3: removing the surface of the epitaxial layer and the second dielectric layer at the top of the trench by chemical mechanical planarization; S4: removing the first dielectric layer on the surface of the epitaxial layer and the top of the trench by wet or dry etching to form a first groove structure; S5: removing the second dielectric layer in the groove by wet or dry etching to form a second groove structure; S6: performing gate oxide oxidation on the side wall of the second groove close to the epitaxial layer by a thermal oxidation process, so that a conductive material is formed in the second groove; S7: selectively removing the conductive material in the groove, and separating the conductive material by a certain distance to form a third groove and a fourth groove; S8: filling the third groove and the fourth groove with a third dielectric layer by using a thermal oxidation or chemical vapor deposition (CVD) method; S9: Select appropriate dopants, use multiple ion implantation methods to form different types of doping regions, and then perform thermal annealing to activate the impurities to form the body doping region of the device and the required PN junction device structure; S10: forming a fourth dielectric layer on the surface of the epitaxial layer and the top of the trench by using a chemical vapor deposition (CVD) method, and selectively forming contact holes by using a photolithography and etching process, and performing contact hole implantation; S11: using MOCVD or PVD process to deposit one or more combinations of Ti, TiN, W, Al, AlSi, AlCu, and AlSiCu metal materials to fill the contact holes, and then using photolithography and etching process to form metal electrodes; In step S5, wet or dry etching is used to remove all the second dielectric layers in the grooves, retaining the morphology of the first dielectric layer formed in S4, forming a second groove structure with the surface of the epitaxial layer and the arc-shaped sidewalls at the top of the groove exposed. After the second groove is formed, the aspect ratio of the area to be filled with subsequent polycrystalline is smaller than the aspect ratio of the groove.

2. A method for manufacturing a power semiconductor device according to claim 1, Features: In step S1, the material of the semiconductor substrate is a III-V semiconductor GaAs, InP, GaN or a IV semiconductor Si, Ge, the semiconductor substrate is a single crystal silicon substrate doped into N type, the epitaxial layer is a single crystal silicon epitaxial layer doped into N type, and the ratio of the depth to the width of the trench is less than 10.

3. The method for manufacturing a power semiconductor device according to claim 1, Features: In step S2, a first dielectric layer is formed by thermal oxidation or chemical vapor deposition (CVD), thermal oxidation includes hydrothermal oxidation (HTO) or selective reactive oxidation (SRO), chemical vapor deposition (CVD) includes low pressure chemical vapor deposition (LPCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD), and the second dielectric layer is composed of one or more of silicon nitride and silicon oxynitride, and the thickness of the second dielectric layer is greater than or equal to 10Å.

4. The method for manufacturing a power semiconductor device according to claim 1, Features: In step S4, when a wet method is used, according to the characteristics of wet etching, the first dielectric layer at the top of the trench will form an arc structure close to the side wall of the epitaxial layer.

5. The method for manufacturing a power semiconductor device according to claim 1, Features: In step S6, the thickness of the gate oxide is 50Å~2000Å, an arc-shaped structure appears near the side wall of the epitaxial layer of the second groove, so that the thickness of the bottom of the groove side wall is consistent with the thickness of other areas, the conductive material is composed of in-situ doped polysilicon, the deposition temperature is 500℃~800℃, the square resistance is 3Ω~20Ω, the thickness is 1000Å~20000Å, and the conductive material is filled seamlessly in the groove.

6. The method for manufacturing a power semiconductor device according to claim 1, Features: In step S7, the third groove corresponds to the shielding polycrystalline region of the split-gate power device. It is necessary to retain the conductive material in the middle of the groove and remove the conductive material on both sides. The area where the conductive material is removed needs to be filled with a dielectric layer later. The fourth groove corresponds to the original cell area structure. The conductive material on both sides of the top of the groove is retained as the gate of the split-gate power device by selective etching, and the conductive material in the middle area of ​​the groove is removed from top to bottom to separate the conductive material into two sections of shielding polycrystalline and gate polycrystalline.

7. The method for manufacturing a power semiconductor device according to claim 1, Features: In step S8 , the thermal oxidation includes hydrothermal oxidation of HTO or selective reactive oxidation of SRO, and the chemical vapor deposition CVD includes low pressure chemical vapor deposition LPCVD or sub-atmospheric pressure chemical vapor deposition SACVD.

8. The method for manufacturing a power semiconductor device according to claim 1, Features: In step S10, chemical vapor deposition (CVD) including low pressure chemical vapor deposition (LPCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) is used to form one or more combinations of NSG, BPSG, PSG, SiN, and SiON dielectric layers.

9. A power semiconductor device, comprising: a method for manufacturing a power semiconductor device according to any one of claims 1 to 8; Features: The invention comprises a semiconductor substrate (101), wherein an epitaxial layer (102) is arranged on the semiconductor substrate (101), a groove (110) is opened in the epitaxial layer (102), a first dielectric layer (120) is arranged in the groove (110), a conductive material (150) is arranged in the first dielectric layer (120), a gate oxide layer (140) is wrapped around the outside of part of the conductive material (150), a fourth dielectric layer (180) is arranged on the top of the gate oxide layer (140), a first conductive window (201), a second conductive window (202) and a third conductive window (203) are opened in the upper part of the fourth dielectric layer (180), and the first conductive window (201) is provided with a second conductive window (202) and a third conductive window (203) are provided in the upper part of the fourth dielectric layer (180), and the first conductive window (201) is provided with a second conductive window (202) and a third conductive window (203) are provided in the upper part of the fourth dielectric layer (180). The bottom end of a conductive window (201) is connected to the conductive material (150), an upper source region (170) and a lower source region (160) are arranged between parts of the groove (110), the bottom end of the second conductive window (202) passes through the upper source region (170) and extends into the lower source region (160), the bottom end of the third conductive window (203) extends into both sides of the conductive material (150), and a first metal electrode (211), a second metal electrode (212) and a third metal electrode (213) are respectively arranged in the first conductive window (201), the second conductive window (202) and the third conductive window (203).

Images