Data receiving apparatus, memory apparatus, and operating method thereof

Abstract

Data receiving apparatuses, memory apparatuses, and operating methods thereof are provided. A data receiving apparatus of a memory apparatus includes a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output a differential signal by comparing the input data with the first reference voltage in response to a clock when the first pre-amplifier is selected in response to the previous data; a second pre-amplifier configured to receive inverted previous data, a second reference voltage different from the first reference voltage, and the input data, and to output a common signal in response to the clock when the second pre-amplifier is not selected in response to the previous data; and an amplifier configured to receive the differential signal and the common signal, and to latch the input data by amplifying the differential signal.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0163805, filed on December 10, 2019, with the Korean Patent Office, the entire general reference of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a data receiving apparatus and a memory device having the data receiving apparatus. Background Technology

[0003] Typically, with the development of semiconductor technology, clock frequencies and data rates increase. Furthermore, as the data rate between memory and memory controller increases, distortion occurs in the waveform of data transmitted through the data channel. One cause of this distortion is intersymbol interference (ISI). ISI refers to the phenomenon where previously transmitted data affects the transmission of currently transmitted data due to bandwidth limitations of the data channel. A widely used technique to reduce the impact of ISI is the use of decision feedback equalizers (DFEs), which act as circuits / filters that utilize previous data (e.g., previous symbol decisions) to reduce ISI. Summary of the Invention

[0004] One aspect of the present invention will provide a data receiving apparatus for reducing ISI, a memory device having the receiving apparatus, and a method of operating the same.

[0005] According to one aspect of the present invention, a data receiving device for a memory device may include: a first preamplifier that receives previous data, a first reference voltage, and input data, and outputs a differential signal by comparing the input data with the first reference voltage in response to a clock when the first preamplifier is selected in response to the previous data; a second preamplifier that receives inverted previous data, a second reference voltage different from the first reference voltage, and input data, and outputs a common signal in response to a clock when the second preamplifier is not selected in response to the previous data; and an amplifier that receives the differential signal and the common signal, and latches the input data by amplifying the differential signal.

[0006] According to one aspect of the present invention, a memory device may include: a memory cell array having a plurality of memory cells at the intersection of a plurality of word lines and a plurality of bit lines; a row decoder that selects any one of the plurality of word lines in response to a row address; a bit line sensing amplifier circuit configured to sense and amplify data from a selected memory cell among the plurality of memory cells during a read operation; a column driver that selects a bit line among the plurality of bit lines in response to a column address; and a data input / output device that receives data from the bit line sensing amplifier circuit during a read operation and receives input data from a data pad during a write operation. The data input / output device may include at least one respective data input sensing amplifier connected to each data pad, the at least one respective data input sensing amplifier comprising a first stage and a second stage, the first stage being configured to output a differential signal by amplifying the input data using a reference voltage selected in response to previous data, and the second stage being configured to latch the input data by amplifying the differential signal.

[0007] According to one aspect of the present invention, an operation method of a data receiving device having a first stage and a second stage may include: receiving previous data from another data receiving device; activating a first preamplifier in response to the previous data in the first stage; and amplifying a differential signal output from the first preamplifier in the second stage. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a view illustrating an exemplary data receiving apparatus according to a concept of the present invention;

[0010] Figure 2A and Figure 2B This is a view illustrating a preamplifier according to an exemplary embodiment of the concept of the present invention;

[0011] Figure 3A and 3B This is a view showing a preamplifier with a 3-stack structure;

[0012] Figure 4A This is a view illustrating an amplifier according to an exemplary embodiment of the concept of the present invention;

[0013] Figure 4B This is a view illustrating an amplifier according to another exemplary embodiment of the concept of the present invention;

[0014] Figure 5 This is a view showing the operation timing diagram of a data receiving device according to an exemplary embodiment of the present invention;

[0015] Figure 6A This is a view illustrating the operation timing diagram of the first stage of a data receiving apparatus according to an exemplary embodiment of the present invention. Figure 6B A timing diagram illustrating the operation of the second stage of a data receiving apparatus according to an exemplary embodiment of the present invention is shown.

[0016] Figure 7 This is a view illustrating a memory device according to an exemplary embodiment of the concept of the present invention;

[0017] Figure 8 This is a view illustrating a memory device according to another exemplary embodiment of the concept of the present invention;

[0018] Figure 9 This is a flowchart illustrating an operation method of a data receiving apparatus according to an exemplary embodiment of the present invention;

[0019] Figure 10 This is a view illustrating an exemplary embodiment of a memory system according to the concept of the present invention; and

[0020] Figure 11 This is a view illustrating an example embodiment of a mobile device according to a concept of the present invention. Detailed Implementation

[0021] In the following, exemplary embodiments of the inventive concept will be described clearly and in detail with reference to the accompanying drawings.

[0022] Figure 1 This is a view illustrating an exemplary embodiment of a data receiving apparatus 100 according to a concept of the present invention. (Refer to...) Figure 1 The data receiving device 100 may include a first preamplifier 110, a second preamplifier 120, and an amplifier 130.

[0023] The first preamplifier 110 and the second preamplifier 120 can be selected based on (e.g., in response to) previous data DIN_PRE and DINB_PRE. That is, either the first preamplifier 110 or the second preamplifier 120 can be selected based on the previous data DIN_PRE and DINB_PRE, while the other can be deselected. In the following description, for ease of description, it is assumed that the first preamplifier 110 is selected and the second preamplifier 120 is not selected.

[0024] The first preamplifier 110 can be configured to (i) be selected according to the previous data DIN_PRE, (ii) compare the data DIN (also referred to as input data) with the first reference voltage VREFUP in response to the clock CLK, and (iii) output signals OUTF_UP and OUTFB_UP corresponding to the comparison result (i.e., output signals OUTF_UP and OUTFB_UP in response to comparing the data DIN with the first reference voltage VREFUP).

[0025] The second preamplifier 120 can be configured to (a) be selected based on the inverted previous data DIB_PRE, (b) compare the data DIN with the second reference voltage VREFDN in response to the clock CLK, and (c) output signals OUTF_DN and OUTFB_DN corresponding to the comparison result. Here, the second reference voltage VREFDN can be different from the first reference voltage VREFUP. For example, the second reference voltage VREFDN can be lower than the first reference voltage VREFUP.

[0026] Amplifier 130 can be configured to receive any one of the output signals OUTF_UP and OUTFB_UP of the first preamplifier 110 and the output signals OUTF_DN and OUTFB_DN of the second preamplifier 120, and output amplified data DINA in response to the received output signals.

[0027] like Figure 1 As shown, the data receiving device 100 can be implemented using a two-stage sensing amplifier. The first stage provides amplification circuitry via either the first preamplifier 110 or the second preamplifier 120, and the second stage amplifies the signal amplified in the first stage.

[0028] The first stage can select a reference voltage based on the prior data DIN_PRE and DINB_PRE. For example, a first reference voltage VREFUP can be selected based on the prior data DIN_PRE, and a second reference voltage VREFDN can be selected based on the prior data DINB_PRE. Here, the prior data DIN_PRE and DINB_PRE are complementary data. For example, when the prior data DIN_PRE is '1', the first preamplifier 110 can be activated, allowing the first reference voltage VREFUP to be selected in the first stage. Furthermore, when the prior data DINB_PRE is '1', the second preamplifier 120 can be activated, allowing the second reference voltage VREFDN to be selected in the first stage. However, it should be understood that the selection of the reference voltage in the first stage of this invention is not limited to this.

[0029] In one example embodiment, the first stage can use a switch to remove (e.g., disconnect) the differential signal of an input pair without requiring a stack of transistors. Transmitting the differential signal to the input pair of the second stage allows a current source to initially allow current to flow, helping to charge and drive the internal nodes.

[0030] The second stage can receive the differential signal from the first stage, amplify it, and output the corresponding data.

[0031] Typically, DFE tap weights should be controllable over a constant and wide range in response to process, voltage, and temperature (PVT) variations. In two-stage amplifiers operating at low voltages, circuit performance can be significantly degraded due to transistor stacking. This makes decision logic difficult to implement.

[0032] On the other hand, in the data receiving apparatus 100 of the exemplary embodiment of the present invention, the selection performed by DFE operation can be implemented as a switch connected in parallel to the input pair instead of a transistor connected in series. The non-ideal operating characteristics of this switch can be improved by weakly pre-charging the selected input pair.

[0033] Figure 2A and Figure 2B This is a view showing preamplifiers 110 and 120 according to an exemplary embodiment of the concept of the present invention.

[0034] Reference Figure 2A The first preamplifier 110 may include current sources IC1 and IC2, P-channel metal-oxide-semiconductor (PMOS) transistors PM1 and PM2, N-channel metal-oxide-semiconductor (NMOS) transistors NM1 and NM2, and a first switch SW1.

[0035] The first current source IC1 can be connected between the power supply terminal VDD and the first node ND1. The second current source IC2 can be connected between the power supply terminal VDD and the first node ND1.

[0036] The first PMOS transistor PM1 may have a source connected to the first node ND1, a drain connected to the second node ND2, and a gate for receiving data DIN. The second PMOS transistor PM2 may have a source connected to the first node ND1, a drain connected to the third node ND3, and a gate for receiving a first reference voltage VREFUP. The first NMOS transistor NM1 may be connected between the second node ND2 and the ground terminal GND in response to the clock CLK. The second NMOS transistor NM2 may be connected between the third node ND3 and the ground terminal GND in response to the clock CLK. The first switch SW1 may connect (or disconnect) the second node ND2 and the third node ND3 in response to the previous data DIN_PRE. For example, when the first preamplifier 110 is selected in response to the previous data DIN_PRE, the first switch SW1 may disconnect the second node ND2 and the third node ND3 in response to the previous data DIN_PRE. Here, the differential signals OUTF_UP and OUTFB_UP of the first preamplifier 110 may be output from the second node ND2 and the third node ND3. For example, when the first preamplifier 110 is not selected in response to the previous data DIN_PRE, the first switch SW1 can connect the second node ND2 and the third node ND3 in response to the previous data DIN_PRE. Here, the first preamplifier 110 can output a common signal from the second node ND2 and the third node ND3.

[0037] Meanwhile, the structure of the second preamplifier 120 can be implemented in the same way as the first preamplifier 110.

[0038] Reference Figure 2B The second preamplifier 120 may include current sources IC3 and IC4, PMOS transistors PM3 and PM4, NMOS transistors NM3 and NM4, and a second switch SW2.

[0039] The third current source IC3 can be connected between the power supply terminal VDD and the fourth node ND4. The fourth current source IC4 can be connected between the power supply terminal VDD and the fourth node ND4. The third PMOS transistor PM3 can have a source connected to the fourth node ND4, a drain connected to the fifth node ND5, and a gate for receiving data DIN. The fourth PMOS transistor PM4 can have a source connected to the fourth node ND4, a drain connected to the sixth node ND6, and a gate for receiving the second reference voltage VREFDN. The third NMOS transistor NM3 can be connected between the fifth node ND5 and the ground terminal GND in response to the clock CLK. The fourth NMOS transistor NM4 can be connected between the sixth node ND6 and the ground terminal GND in response to the clock CLK. The second switch SW2 can connect (or disconnect) the fifth node ND5 and the sixth node ND6 in response to the previous data DNB_PRE. Here, the switching operation of the second switch SW2 can be the opposite of the switching operation of the first switch SW1. Here, when the second preamplifier 120 is selected, the differential signals OUTF_DN and OUTFB_DN of the second preamplifier 120 can be output from the fifth node ND5 and the sixth node ND6; when the second preamplifier 120 is not selected, the second preamplifier 120 can output a common signal from the fifth node ND5 and the sixth node ND6.

[0040] at the same time, Figure 2A and 2B The current sources IC1 to IC4 shown can be implemented as (e.g., may include) transistors, and the switches SW1 and SW2 can be implemented as (e.g., may include) transmission gates.

[0041] Figure 3A and 3B This is a view showing preamplifiers 110 and 120 with a 3-stack structure. Therefore, each of the preamplifiers 110 and 120 may have a corresponding 3-stack transistor structure, rather than (i.e., may not have) any 4-stack transistor structure.

[0042] Reference Figure 3A The first preamplifier 110 may include PMOS transistors PM1, PM2, PM5 and PM6, NMOS transistors NM1 and NM2, and a first transmission gate TG1.

[0043] Figure 2A The first current source IC1 shown may include a fifth PMOS transistor PM5. Here, the fifth PMOS transistor PM5 can connect the power supply terminal VDD and the first node ND1 in response to the previous data DIN_PRE, thereby supplying current to the first PMOS transistor PM1 and the second PMOS transistor PM2. Furthermore, Figure 2A The second current source IC2 shown may include a sixth PMOS transistor PM6. Here, the sixth PMOS transistor PM6 can connect the power supply terminal VDD and the first node ND1 in response to the clock CLK, thereby supplying current to the first PMOS transistor PM1 and the second PMOS transistor PM2. Furthermore, Figure 2A The first switch SW1 shown may include a first transmission gate TG1. Here, the first transmission gate TG1 may connect (or disconnect) the second node ND2 and the third node ND3 in response to the previous data DIN_PRE.

[0044] Reference Figure 3B The second preamplifier 120 may include PMOS transistors PM3, PM4, PM7 and PM8, NMOS transistors NM3 and NM4, and a second transmission gate TG2.

[0045] Figure 2B The third current source IC3 shown may include a seventh PMOS transistor PM7. Here, the seventh PMOS transistor PM7 can connect the power supply terminal VDD and the fourth node ND4 in response to the inverted previous data DNB_PRE, thereby supplying current to the third PMOS transistor PM3 and the fourth PMOS transistor PM4. Furthermore, Figure 2B The fourth current source IC4 shown may include an eighth PMOS transistor PM8. Here, the eighth PMOS transistor PM8 can connect the power supply terminal VDD and the fourth node ND4 in response to the clock CLK to supply current to the third PMOS transistor PM3 and the fourth PMOS transistor PM4. Furthermore, Figure 2B The second switch SW2 shown may include a second transmission gate TG2. Here, the second transmission gate TG2 may connect (or disconnect) the fifth node ND5 and the sixth node ND6 in response to the inverted previous data DNB_PRE.

[0046] at the same time, Figure 3A and Figure 3B The preamplifiers 110 and 120 shown can receive previous data DIN_PRE and DIB_PRE as inputs, and one of the input pairs can be selected. After opening the corresponding transmission gate, the selected preamplifier can output the differential signal to amplifier 130. On the other hand, after shorting the corresponding transmission gate, the unselected preamplifier can filter out the differential signal.

[0047] Simultaneously, all outputs of the first stage can be sent to the input of the second stage. This structure is the first preamplifier stage of a sense amplifier that amplifies data input at small swing level rail-to-rail. Data low has a signal level obtained by adding a common signal to a differential negative signal, and data high has a signal level obtained by adding a common signal to a differential positive signal.

[0048] The first stage can sense the data DIN and the reference voltages VREFUP and VREFDN on the falling edge of the clock CLK, amplify the detected voltage difference, and transmit the amplified voltage difference to the latch of the second stage.

[0049] To compensate for ISI, the previously selected data DIN_PRE and DINB_PRE can activate one of the two input pairs. The activated input pair will deactivate the corresponding transmission gate. As a result, the input signals (i.e., the data DIN and the reference voltage VREFUP or VREFDN) can be properly amplified, thereby driving the second stage.

[0050] Inactive input pairs can turn on the corresponding transmission gates. Therefore, the differential components of the inputs are not transmitted to the outputs. However, because each output is pulled up to the power supply terminal VDD, it can help drive the circuitry itself. To first transmit the signals of the active input pairs to the next stage, the previous data DIN_PRE and DIB_PRE can precharge the internal nodes by partially driving the PMOS current source. Therefore, differential signals that cannot be completely removed from the transmission gates can be separated in time.

[0051] Simultaneously, the preamplifier stage of this invention can select a reference voltage favorable for sensing based on prior data DIN_PRE and DNB_PRE. Furthermore, because the preamplifier stage of this invention does not use a method of selecting the reference voltage by stacking transistors, it is advantageous for driving low voltages. Additionally, input pairs not selected by the DFE do not transmit differential signals, but the bandwidth of the circuit can be increased by transmitting a common signal used to drive the next stage (e.g., the signal required to drive the next stage).

[0052] Figure 4A This is a view illustrating an amplifier 130 according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 4A Amplifier 130 may include PMOS transistors PM9 to PM14 and NMOS transistors NM5 to NM10.

[0053] The ninth PMOS transistor PM9 may include a source connected to the power supply terminal VDD, a drain connected to the seventh node ND7, and a gate for receiving the inverted feedback output signal OUTB_F. The tenth PMOS transistor PM10 may include a source connected to the power supply terminal VDD, a drain connected to the seventh node ND7, and a gate connected to the eighth node ND8. The eleventh PMOS transistor PM11 may include a source connected to the power supply terminal VDD, a drain connected to the ninth node ND9, and a gate for receiving the inverted feedback output signal OUTB_F. The twelfth PMOS transistor PM12 may include a source connected to the power supply terminal VDD, a drain connected to the eighth node ND8, and a gate connected to the seventh node ND7. The thirteenth PMOS transistor PM13 may include a source connected to the power supply terminal VDD, a drain connected to the eighth node ND8, and a gate for receiving the feedback output signal OUT_F. The fourteenth PMOS transistor PM14 may include a source connected to the power supply terminal VDD, a drain connected to the tenth node ND10, and a gate for receiving the feedback output signal OUT_F.

[0054] The fifth NMOS transistor NM5 may include the drain of the tenth PMOS transistor PM10 (i.e., the drain connected to the seventh node ND7), the source connected to the ninth node ND9, and the gate connected to the eighth node ND8. The sixth NMOS transistor NM6 may include the drain connected to the ninth node ND9, the source connected to the ground terminal GND, and the gate receiving the inverted first differential signal OUTFB_UP. The seventh NMOS transistor NM7 may include the drain connected to the ninth node ND9, the source connected to the ground terminal GND, and the gate receiving the inverted second differential signal OUTFB_DN. The eighth NMOS transistor NM8 may include the drain of the twelfth PMOS transistor PM12 (i.e., the drain connected to the eighth node ND8), the source connected to the tenth node ND10, and the gate connected to the seventh node ND7. The ninth NMOS transistor NM9 may include the drain connected to the tenth node ND10, the source connected to the ground terminal GND, and the gate receiving the first differential signal OUTF_UP. The tenth NMOS transistor NM10 may include a drain connected to the tenth node ND10, a source connected to the ground terminal GND, and a gate for receiving the second differential signal OUTF_DN.

[0055] Meanwhile, the final output signals DIN_O and DINB_O of amplifier 130 can be output from the seventh node ND7 and the eighth node ND8.

[0056] The second-stage amplifier 130 can receive the outputs of the first stage, OUTF_UP, OUTF_DN, OUTFB_UP, and OUTFB_DN, as inputs to drive the latch.

[0057] One of the first differential signal OUTF_UP, the inverted first differential signal OUTFB_UP, the second differential signal OUTF_DN, and the inverted second differential signal OUTFB_DN can differentially drive the latch using the signal selected by the DFE path. Furthermore, because the first stage is turned on, the other of the first differential signal OUTF_UP, the inverted first differential signal OUTFB_UP, the second differential signal OUTF_DN, and the inverted second differential signal OUTFB_DN can common-mode drive the circuit.

[0058] The drain of one NMOS transistor can be pulled down first based on the differential signal caused by the difference in input voltage, allowing the inverter to be driven first. Since the drains of both NMOS transistors can be pulled down, the output of the cross-coupled latch can be determined. The input signal can be amplified into a signal that is ultimately moved rail-to-rail.

[0059] At the same time, Figure 4A In the amplifier 130 shown, each of the ninth PMOS transistor PM9, the eleventh PMOS transistor PM11, the thirteenth PMOS transistor PM13, and the fourteenth PMOS transistor PM14 can supply a power supply voltage to the corresponding nodes ND7, ND8, ND9, and ND10 in response to the corresponding feedback output signal OUT_F. However, the structure of the amplifier of the present invention is not limited to this. The amplifier of the present invention may not include a transistor for performing a node reset operation.

[0060] Figure 4B This is a view illustrating another exemplary embodiment of an amplifier 130a according to the concept of the present invention. (Refer to...) Figure 4B ,and Figure 4A Compared to the amplifier 130 shown in the figure, amplifier 130a may have a structure in which transistors PM9, PM11, PM13 and PM14, which perform node reset operations, are removed.

[0061] Conventional DFE structures compensate for ISI by selectively applying current to the input transistors of the sense amplifier based on loop decisions. However, this method causes the current consumption of the sense amplifier to vary depending on the input difference and PVT changes. Therefore, the tap weights of the DFE are not relatively constant.

[0062] In contrast, the DFE structure of the exemplary embodiment of the present invention can compensate for ISI more effectively and consistently by using an input reference voltage.

[0063] Figure 5 This is a view illustrating the operation timing diagram of a data receiving apparatus 100 according to an exemplary embodiment of the present invention. (Refer to...) Figure 5 In the case of data conversion mode, ISI (Inter-Signal Interference) occurs due to channel characteristics, resulting in low swing. When the input data has an output that is the opposite of the previous data, the reference voltage can be chosen advantageously.

[0064] Figure 6A This is a view illustrating the operation timing diagram of the first stage of a data receiving apparatus 100 according to an exemplary embodiment of the present invention. (Refer to...) Figure 6A By performing the first-level operation on the falling edge of the clock CLK, the low / high of the data DIN can be initially determined.

[0065] Figure 6B This is a view illustrating the second-level operation timing diagram of a data receiving apparatus 100 according to an exemplary embodiment of the present invention. (Refer to...) Figure 6B This allows performing second-level operations on the output of the first level, ultimately determining whether the data DIN is low or high. For example... Figure 6B As shown, the low or high values ​​of the data DIN can be clearly distinguished.

[0066] Meanwhile, the data receiving device 100 of the exemplary embodiment of the present invention can be applied to the data input sensing amplifier DINSA of the memory device. Figure 7 ).

[0067] Figure 7 This is a view illustrating a memory device 200 according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 7 The memory device 200 includes a memory cell array (or, memory cell array) 210, a row decoder 220, a bit line sense amplification (BLSA) circuit 230, a column decoder (e.g., a column driver) 240, a data input / output circuit 250, and input / output pads (or “solder pads”) 260 (DQ1 to DQk, where k is an integer of 2 or greater).

[0068] The memory cell array 210 may include at least one memory bank array. The at least one memory bank array may include a plurality of memory cells (or memory units) disposed at the intersections of multiple word lines and multiple bit lines. In one example embodiment, each of the plurality of memory cells may be a volatile or non-volatile memory cell.

[0069] The row decoder 220 can be configured to select any one of multiple word lines in response to a row address. That is, in data write / read mode, the row decoder 220 can decode the row address output from the address buffer and select the word line corresponding to the row address. The address buffer can receive and store addresses from an external memory controller, including bank address, row address, and column address. The address register can provide the received bank address to the bank control logic, the received row address to the row address multiplexer, and the received column address to the column address latch.

[0070] Bit line sensing amplifier circuit 230 can be configured to sense / amplify data in selected memory cells. For example, bit line sensing amplifier circuit 230 can sense data by sensing / amplifying bit lines selected by column decoder 240. In one example embodiment, bit line sensing amplifier circuit 230 may include multiple sensing amplifiers.

[0071] The column decoder 240 can be configured to select the bit lines connected to the memory cell in response to the column address. That is, in data write / read mode, the column decoder 240 can decode the column address output from the address buffer and select the bit line corresponding to the column address.

[0072] The data input / output circuit 250 can receive (amplify and latch) data from an external device via input / output pads DQ1 to DQk during write operations, and can transmit the received data to the bit line sensing amplifier circuit 230. Furthermore, the data input / output circuit 250 can receive data sensed by the bit line sensing amplifier circuit 230 from the memory cell corresponding to the address during read operations, and can output the received data to an external device via input / output pads DQ1 to DQk.

[0073] Specifically, the data input / output circuit 250 may include a data input / output buffer and a plurality of data input sense amplifiers (DINSAs). In a non-limiting example, the plurality of data input sense amplifiers (DINSAs) may include a first data input sense amplifier configured to receive input data and a second data input sense amplifier configured to store previous data.

[0074] Data input sense amplifier DINSA can be used Figures 1 to 6B The data receiving device described herein and one or more of its operations are implemented.

[0075] The data input / output buffer can provide data DQ to the error correction circuitry based on a clock signal from the memory controller during a write operation, and can provide data DQ from the error correction circuitry to the memory controller during a read operation. The error correction circuitry can generate a parity bit based on the data bits of data DQ provided from the data input / output buffer during a write operation, and provide a codeword including the data DQ and the parity bit to the data input / output circuitry 250. The data input / output circuitry 250 can write the codeword to the memory bank array. Furthermore, during a read operation, the error correction circuitry can receive a codeword read from the memory bank array from the data input / output circuitry 250. The error correction circuitry can perform ECC decoding on the data DQ using the parity bit included in the read codeword and correct at least one erroneous bit included in the data DQ to provide the corrected data to the data input / output buffer.

[0076] The control logic can be configured to control the overall operation of the memory device 200. The control logic may include refresh control circuitry, a command decoder, and a mode register circuitry. The refresh control circuitry can receive a refresh signal decoded from the command decoder and output an internal row address to the row decoder 220 to refresh a word line of the memory cell array 210. The command decoder can receive commands (CMD) from an external device (memory controller). Figure 10 It can internally generate command signals (e.g., activation signal, read signal, write signal, refresh signal, etc.) decoded from the received command CMD. In response to a Mode Register Set (MRS) command / Extended Mode Register Set (EMRS) command for specifying the operating mode of the memory device 200, the mode register circuit can set the internal mode register. Furthermore, the mode register circuit can output an activation signal in response to input / output signals to control the operation of the input / output circuitry according to the write / read operation.

[0077] at the same time, Figure 7 The data input / output circuit 250 shown includes a data input sense amplifier (DINSA) on each input / output pad. However, the inventive concept is not limited thereto. The memory device of the inventive concept may include multiple data input sense amplifiers corresponding to one input / output pad.

[0078] Figure 8 This is a view illustrating a memory device 200a according to another exemplary embodiment of the concept of the present invention. (Refer to...) Figure 8 The memory device 200a includes a data input / output circuit 250a, and... Figure 7 Compared to the data input / output circuit 250 shown in the figure, the data input / output circuit 250a includes multiple data input sense amplifiers DINSA on a data pad.

[0079] Figure 9 This is a flowchart illustrating an operation method of a data receiving apparatus according to an exemplary embodiment of the present invention. (Refer to...) Figures 1 to 9 The data receiving device 100 can be operated as follows.

[0080] The first stage of the data receiving device 100 (see Figure 1 The data receiving device 100 can receive data DIN and previous data DIN_PRE and DINB_PRE synchronously with clock CLK (S110). Here, previous data DIN_PRE and DINB_PRE can be received from another data receiving device. The first-stage preamplifier can be activated / selected based on the received previous data DIN_PRE and DINB_PRE (S120). Subsequently, the second stage of the data receiving device 100 (see...) Figure 1 The latching operation of data DIN can be performed by receiving and amplifying the differential signal from the activated preamplifier (S130).

[0081] The data receiving device 100 of an exemplary embodiment of the present invention may include a two-stage (double-tail) sense amplifier capable of selecting a reference voltage and operating with low voltage.

[0082] The data receiving device 100 of an exemplary embodiment of the present invention can use switches to select input pairs and reference voltages to sense data without the need for a stack of transistors.

[0083] According to an example embodiment of the present invention, the data receiving device 100 can quickly and reliably enter latch drive by pre-charging the differential signal into the node receiving the input pair in the second stage via a current source.

[0084] Figure 10 This is a view illustrating a memory system 1000 according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 10 The memory system 1000 may include at least one memory device 1100 and a host device 1200 for controlling the memory device 1100.

[0085] The host device 1200 can transmit clock CLK, command CMD, and address ADD to store data in or retrieve data stored in memory device 1100. The host device 1200 can exchange data with memory device 1100 via multiple data lines DQL. For example, the host device 1200 can be a memory controller or a central processing unit (CPU).

[0086] In one example embodiment, host device 1200 may communicate with memory device 1100 via a Graphics Double Data Rate (GDDR) interface. However, since the inventive concept is not limited thereto, host device 1200 may communicate with memory device 1100 via at least one of various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Non-Volatile Memory High Speed ​​(NVMe), etc.

[0087] Under the control of the host device 1200, the memory device 1100 can store data received via multiple data lines (DQL), or can send stored data to the host device 1200 via multiple data lines (DQL). In one embodiment, the memory device 1100 may include dynamic random access memory (DRAM). However, since the inventive concept is not limited thereto, the memory device 1100 may include at least one of various memory devices such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0088] The memory device 1100 may include a data line driver 1110 configured to control each of a plurality of data lines (DQL). The DQL driver 1110 may generate a reference voltage or set of reference voltages for determining the data provided through each of the plurality of data lines (DQL).

[0089] Specifically, the DQL driver 1110 can be... Figures 1 to 9 The data receiving device 100 described herein and one or more of its operations are implemented.

[0090] Information regarding the reference voltage for each of the multiple data lines in the DQL can be stored in a separate memory circuit (e.g., stored in a mode register as code). The DQL driver 1110 can generate internal code based on the aforementioned code, and generate a reference voltage or a group of reference voltages based on the generated internal code. The code for the reference voltage of each of the multiple data lines in the DQL can be determined during the training process of the memory device 1100.

[0091] Figure 11 This is a view illustrating a mobile device 3000 according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 11 The mobile device 3000 may include an application processor 3100, at least one DRAM 3200, at least one storage device 3300, at least one sensor 3400, a display device 3500, an audio device 3600, a network processor 3700, and at least one input / output device 3800. For example, the mobile device 3000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, or wearable computer.

[0092] Application processor 3100 can be configured to control the overall operation of mobile device 3000. Application processor 3100 can execute applications that provide internet browsers, games, videos, etc. In one example embodiment, application processor 3100 may include a single core or multiple cores. For example, application processor 3100 may include multiple cores (such as dual-core, quad-core, hexa-core, etc.). In one example embodiment, application processor 3100 may also include internal or external cache memory.

[0093] Application processor (AP) 3100 may include controller (CNTL) 3110, neural processor (NPU) 3120, and interface (IF) 3130. In one embodiment, NPU 3120 may be optionally provided or omitted.

[0094] In one embodiment, the application processor 3100 may be implemented as a system-on-a-chip (SoC). The kernel of the operating system driving on the SoC may include a device driver and an input / output (I / O) scheduler for controlling the storage device 3300. The device driver may control the access performance of the storage device 3300 by referring to the number of synchronization queues managed by the I / O scheduler, or it may control CPU modes, dynamic voltage and frequency scaling (DVFS) levels, etc., within the SoC.

[0095] DRAM 3200 can be connected to controller 3110. DRAM 3200 can store data required for the operation of application processor 3100. For example, DRAM 3200 can temporarily store operating system (OS) and application data, or can be used as a runtime space for various software code.

[0096] DRAM 3200 can be configured to, for example Figures 1 to 10The two-stage sensing amplifier described herein is used to receive data. One of the DRAMs 3200 can have a latency and bandwidth (BW) that is relatively faster than that of the I / O device or flash memory. The DRAM 3200 can be initialized as a temporary storage location for OS and application data when the mobile power is on, OS and application data can be loaded and used, or it can be used as a runtime space for various software code. The mobile device can perform multitasking operations by loading several applications simultaneously, and the switching and running speed between applications can be used as a performance indicator of the mobile device. Another of the DRAMs 3200 can be connected to the NPU 3120. This DRAM 3200 can store data related to one or more artificial intelligence processes.

[0097] Storage device 3300 can be connected to interface 3130. In one example embodiment, interface 3130 can operate via one of the following communication protocols: DDR, DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), Non-Volatile Memory High Speed ​​(NVMe), Peripheral Component Interconnect High Speed ​​(PCIe), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Universal Storage Bus (USB) Attached SCSI, Internet Small Computer System Interface (iSCSI), Fibre Channel, and Ethernet Fibre Channel (FCoE). In one example embodiment, any of storage devices 3300 can be included in mobile device 3000 in an embedded form. In another example embodiment, any of storage devices 3300 can be included in mobile device 3000 in a removable manner.

[0098] Storage device 3300 can be configured to store user data. For example, storage device 3300 can store data collected from sensor 3400, or it can store network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) 4K content. Storage device 3300 may include at least one non-volatile memory device. For example, storage device 3300 may include a solid-state drive (SSD), an embedded multimedia card (eMMC), etc.

[0099] In one example embodiment, the storage device 3300 may be implemented as a separate chip within the application processor 3100, or it may be implemented together with the application processor 3100 as a package.

[0100] In one example embodiment, the storage device 3300 can be mounted using various types of packages. For example, the storage device 3300 can be mounted using packages such as: package on package (PoP), ball grid array (BAG), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in-package (SIP), multi-chip package (MCP), wafer-level construction package (WTP), wafer-level processing stacked package (WSP), etc.

[0101] Sensor 3400 can be configured to sense the external environment of mobile device 3000. In one example embodiment, sensor 3400 may include an image sensor that senses an image. In this case, sensor 3400 can transmit the generated image information to application processor 3100. In another example embodiment, sensor 3400 may include a biosensor that senses biometric information. For example, sensor 3400 can sense fingerprints, iris patterns, vascular patterns, heart rate, blood glucose, etc., and generate sensing data corresponding to the sensed information. It should be understood that sensor 3400 is not limited to image sensors and biosensors. The sensor 3400 of this invention can include any sensor (such as an illuminance sensor, an acoustic sensor, an accelerometer, etc.).

[0102] The display device 3500 can be configured to output data. For example, the display device 3500 can output image data sensed by the sensor 3400, or data calculated by the application processor 3100.

[0103] The audio device 3600 can be configured to output voice data to the outside (i.e., the outside of the mobile device 3000) or detect external voice.

[0104] The network processor 3700 can be configured to communicate with external devices via wired or wireless communication methods.

[0105] The input / output device 3800 can be configured to input data to or output data from the mobile device 3000. The input / output device 3800 may include devices that provide digital input and output functions (such as USB or storage devices, digital cameras, SD cards, touch screens, DVDs, modems, network adapters, etc.).

[0106] The decision feedback equalizer (DFE) circuit of an exemplary embodiment of the present invention can have a small swing level input signal, and the DFE circuit can be applied to products that need / benefit from equalization due to ISI caused by channel characteristics.

[0107] The DFE circuit of an exemplary embodiment of the present invention can use two reference voltages for a two-stage (two-stage) sense amplifier.

[0108] The DFE circuit of an exemplary embodiment of the present invention can use a differential signal bypass method by switching during the selection process of the DFE.

[0109] The DFE circuit of an exemplary embodiment of the present invention can drive the selected input pair in advance by driving the current source according to the DFE decision.

[0110] As described above, according to exemplary embodiments of the present invention, a data receiving device, a memory device having the data receiving element, and a method of operating thereof may include a two-stage sensing amplifier that outputs different differential signals based on previous data, thereby improving data receiving operation.

[0111] The various advantages and effects of the present invention are not limited to those described above. Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A data receiving device for a memory device, the data receiving device comprising: The first preamplifier is configured to receive previous data, a first reference voltage, and input data, and when the first preamplifier is selected in response to the previous data, to output a differential signal by comparing the input data with the first reference voltage in response to a clock. The second preamplifier is configured to receive inverted previous data, a second reference voltage different from the first reference voltage, and input data, and to output a common signal in response to a clock when the second preamplifier is not selected in response to the previous data. as well as The amplifier is configured to receive differential and common signals and to latch input data by amplifying the differential signals.

2. The data receiving device according to claim 1, in, The first preamplifier is also configured to output a common signal in response to a clock when the first preamplifier is not selected in response to previously inverted data, and The second preamplifier is further configured to output a differential signal by comparing the input data with a second reference voltage in response to a clock when the second preamplifier is selected in response to the inverted previous data.

3. The data receiving device according to claim 1 or 2, wherein, The first preamplifier includes: The first current source is connected between the power supply terminal and the first node; The second current source is connected between the power supply terminal and the first node; The first PMOS transistor has a source connected to a first node, a drain connected to a second node, and a gate configured to receive input data. The second PMOS transistor has a source connected to a first node, a drain connected to a third node, and a gate configured to receive a first reference voltage. The first NMOS transistor has a drain connected to the second node, a source connected to the ground terminal, and a gate configured to receive a clock. The second NMOS transistor has a drain connected to a third node, a source connected to ground, and a gate configured to receive a clock signal; and The first switch is configured to disconnect the second and third nodes from each other in response to previous data, and The differential signals are output from the second node and the third node, respectively.

4. The data receiving device according to claim 3, wherein, The second preamplifier includes: The third current source is connected between the power supply terminal and the fourth node; The fourth current source is connected between the power supply terminal and the fourth node; The third PMOS transistor has a source connected to the fourth node, a drain connected to the fifth node, and a gate configured to receive input data. The fourth PMOS transistor has a source connected to the fourth node, a drain connected to the sixth node, and a gate configured to receive a second reference voltage. The third NMOS transistor has a drain connected to the fifth node, a source connected to the ground terminal, and a gate configured to receive a clock. The fourth NMOS transistor has a drain connected to the sixth node, a source connected to ground, and a gate configured to receive a clock signal; and The second switch is configured to connect the fifth and sixth nodes to each other in response to inverted previous data, and The common signal is output from the fifth and sixth nodes.

5. The data receiving device according to claim 4, wherein, Each of the first to fourth current sources includes its own transistor.

6. The data receiving device according to claim 4, in, The first current source includes a fifth PMOS transistor, which has a source connected to a power supply terminal, a drain connected to a first node, and a gate configured to receive previous data. The second current source includes a sixth PMOS transistor, which has a source connected to a power supply terminal, a drain connected to the first node, and a gate configured to receive a clock signal. The third current source includes a seventh PMOS transistor, which has a source connected to a power supply terminal, a drain connected to a fourth node, and a gate configured to receive inverted previous data. The fourth current source includes an eighth PMOS transistor, which has a source connected to a power supply terminal, a drain connected to a fourth node, and a gate configured to receive a clock.

7. The data receiving device according to claim 4, wherein, Each of the first and second switches includes its own transmission gate.

8. The data receiving device according to claim 4, in, The first switch includes a first transmission gate, which is configured to disconnect the second node and the third node from each other in response to previous data. The second switch includes a second transmission gate configured to connect the fifth and sixth nodes to each other in response to inverted previous data.

9. The data receiving device according to claim 4, wherein, The amplifier includes: The ninth PMOS transistor has a source connected to a power supply terminal, a drain connected to a seventh node, and a gate configured to receive an inverted feedback output signal. The tenth PMOS transistor has a source connected to the power supply terminal, a drain connected to the seventh node, and a gate connected to the eighth node. The eleventh PMOS transistor has a source connected to a power supply terminal, a drain connected to the ninth node, and a gate configured to receive an inverted feedback output signal. The twelfth PMOS transistor has a source connected to the power supply terminal, a drain connected to the eighth node, and a gate connected to the seventh node. The thirteenth PMOS transistor has a source connected to a power supply terminal, a drain connected to the eighth node, and a gate configured to receive a feedback output signal. The fourteenth PMOS transistor has a source connected to a power supply terminal, a drain connected to the tenth node, and a gate configured to receive a feedback output signal. The fifth NMOS transistor has a drain connected to the seventh node, a source connected to the ninth node, and a gate connected to the eighth node. The sixth NMOS transistor has a drain connected to the ninth node, a source connected to ground, and a gate configured to receive an inverted output signal from the differential signal of the first preamplifier. The seventh NMOS transistor has a drain connected to the ninth node, a source connected to ground, and a gate configured to receive the inverted output signal of the second preamplifier. The eighth NMOS transistor has a drain connected to the eighth node, a source connected to the tenth node, and a gate connected to the seventh node. The ninth NMOS transistor has a drain connected to the tenth node, a source connected to ground, and a gate configured to receive an output signal from a differential signal of a first preamplifier; and The tenth NMOS transistor has a drain connected to the tenth node, a source connected to ground, and a gate configured to receive the output signal of the second preamplifier. The input data is locked between the seventh and eighth nodes.

10. The data receiving apparatus according to claim 1 or 2, wherein, The amplifier includes a cross-coupled latch.

11. A memory device, the memory device comprising: A memory cell array having multiple memory cells at the intersection of multiple word lines and multiple bit lines; The line decoder is configured to select any one of the plurality of word lines in response to a line address; The bit-line sensing amplification circuit is configured to sense and amplify data from a selected memory cell among the plurality of memory cells during a read operation; A column driver is configured to select one of the multiple bit lines in response to a column address; as well as The data input / output device is configured to receive data from the bit line sensing amplifier circuit during a read operation and to receive input data from the data pad during a write operation. The data input / output device includes at least one data input sensing amplifier connected to each data pad, and Each of the at least one data input sensing amplifiers includes a first stage and a second stage, the first stage being configured to amplify the input data by using a reference voltage selected in response to previous data to output a differential signal, and the second stage being configured to latch the input data by amplifying the differential signal.

12. The memory device according to claim 11, wherein, Level 1 includes: The first preamplifier is configured to output a differential signal to the second stage in response to previous data; and The second preamplifier is configured to output a common signal to the second stage in response to previous data.

13. The memory device according to claim 12, wherein, Each of the first and second preamplifiers includes its own stacked 3 transistors.

14. The memory device according to any one of claims 11 to 13, wherein, The second stage includes a cross-coupled sensing amplifier configured to receive differential signals.

15. The memory device according to any one of claims 11 to 13, wherein, The at least one data input sensing amplifier includes: A first data input sensing amplifier is configured to receive input data; and The second data input sensing amplifier is configured to store previous data.

16. A method of operating a data receiving device, the data receiving device having a first stage and a second stage, the method comprising: Receive previous data from another data receiving device; In the first stage, a first preamplifier is activated in response to previous data, and a differential signal is output in the first preamplifier by amplifying the input data using a reference voltage selected in response to the previous data. as well as In the second stage, the input data is latched by amplifying the differential signal output from the first preamplifier.

17. The operating method according to claim 16, wherein, The first preamplifier includes a 3-stacked transistor structure and does not include any 4-stacked transistor structure.

18. The operating method according to claim 16 or 17, further comprising: In response to previous data, a reference voltage is selected from several different reference voltages; as well as In response to previous data, the two nodes of the first preamplifier are connected or disconnected via a switch.

19. The operating method according to claim 18, further comprising: The selected reference voltage is compared with the input data in the first preamplifier.

20. The operating method according to claim 18, further comprising: In response to the previous data, the common signal is output from a second preamplifier, which is different from the first preamplifier, to the second stage.

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