Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. The method comprises: obtaining a substrate including a memory cell array region; forming a word line groove; forming a word line conductive film in the word line groove; forming a photoresist on the surface of the substrate, the photoresist covers the word line conductive film of the word line part and exposes the word line conductive film outside the word line contact part; making the thickness of the word line conductive structure of the word line contact part greater than the thickness of the word line conductive structure not covered by the photoresist. By forming the photoresist on the surface of the substrate, the thickness of the word line conductive structure of the word line contact part is greater than the thickness of the word line conductive structure not covered by the photoresist, thereby reducing the window position depth of the word line contact hole in the word line contact structure, reducing the process time in the process of forming the contact hole, reducing the excessive erosion of the side wall of the contact hole with a shallow window depth in the contact hole process, and avoiding the device short circuit abnormality caused by the contact hole abnormality.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] When making a contact window structure of a dynamic random access memory, since different contact window structures correspond to different contact hole depths, using the same process to prepare contact holes with different contact window structures will result in insufficient process window opening depth. For example, when the active area contact hole has stopped on the surface of the active area, the deeper word line contact hole stays above the word line conductive structure and has not yet completed the window opening. Continuing to etch the word line contact hole will cause the active area contact hole to be etched into the active area. At the same time, the sidewalls of the contact hole will also have the problem of hole expansion, which can easily cause the characteristic size of the device to become larger or cause device short circuit abnormalities caused by sidewall etching. Summary of the invention

[0003] Based on this, it is necessary to provide a new method for manufacturing a semiconductor device and a new semiconductor device to address the above problems.

[0004] A method for manufacturing a semiconductor device, comprising:

[0005] Obtaining a substrate, the substrate comprising a memory cell array region;

[0006] forming word line trenches arranged at intervals in the memory cell array region;

[0007] Filling the word line conductive material in the word line trench to form a word line conductive film;

[0008] forming a photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line contact portion and exposes the word line conductive film outside the word line contact portion;

[0009] Using the photoresist as a barrier layer, etching the word line conductive film not covered by the photoresist to a target height to obtain a word line conductive structure, so that the thickness of the word line conductive structure at the word line contact portion is greater than the thickness of the word line conductive structure not covered by the photoresist;

[0010] The photoresist is removed.

[0011] In one embodiment, the word line contact portion is located at an end of the word line conductive structure.

[0012] In one of the embodiments, a ratio of a thickness of the word line conductive structure of the word line contact portion to a thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.0.

[0013] In one embodiment, after removing the photoresist, the method further comprises:

[0014] forming a first insulating dielectric layer on the surface of the substrate;

[0015] The first insulating dielectric layer is patterned to form a word line contact hole on the word line contact portion.

[0016] In one embodiment, the substrate also includes a peripheral circuit area, the peripheral circuit area includes a transistor active area, a second insulating dielectric layer is formed on the surface of the active area, the second insulating dielectric layer is patterned, and an active area contact hole is formed on the source area / drain area of ​​the active area.

[0017] In one embodiment, a height difference between the active area contact hole and the word line contact hole is greater than or equal to 0 and less than 20% of the height of the active area contact hole.

[0018] In one embodiment, the word line contact hole and the active area contact hole are formed by the same process.

[0019] In one embodiment, the first insulating dielectric layer and the second insulating dielectric layer are formed by the same process.

[0020] In one embodiment, the semiconductor device is a dynamic random access memory.

[0021] The above-mentioned manufacturing method includes: obtaining a substrate, the substrate including a memory cell array area; forming spaced word line grooves in the memory cell array area; filling the word line grooves with word line conductive material to form a word line conductive film; forming a photoresist on the surface of the substrate, the photoresist covering the word line conductive film at the word line contact part and exposing the word line conductive film outside the word line contact part; using the photoresist as a barrier layer, etching the word line conductive film not covered by the photoresist to a target depth to obtain a word line conductive structure, so that the thickness of the word line conductive structure at the word line contact part is greater than the thickness of the word line conductive structure not covered by the photoresist. The present application forms a photoresist on the surface of a substrate, wherein the photoresist covers a word line conductive film of a word line contact portion and exposes the word line conductive film outside the word line contact portion, and then etches the word line conductive film not covered by the photoresist to a target height using the photoresist as a barrier layer, so that the thickness of the word line conductive structure of the word line contact portion in the formed word line conductive structure is greater than the thickness of the word line conductive structure not covered by the photoresist. Compared with the word line conductive structure in which the thickness of the word line conductive structure of the word line contact portion is equal to the thickness of the word line conductive structure not covered by the photoresist, the window opening position depth of the word line contact hole in the word line contact portion is reduced, the process time in the process of forming the contact hole is reduced, the excessive erosion of the side wall of the contact hole with a shallow window opening depth in the contact hole process is reduced, and the device short circuit abnormality caused by the contact hole abnormality is avoided.

[0022] A semiconductor device, comprising:

[0023] A substrate having a memory cell array region formed thereon, wherein the memory cell array region has word line trenches arranged at intervals;

[0024] A word line conductive structure, wherein the word line conductive structure includes a word line conductive structure of a word line contact portion and a word line conductive structure outside the word line contact portion;

[0025] The thickness of the word line conductive structure at the word line contact portion is greater than the thickness of the word line conductive structure outside the word line contact portion.

[0026] In one embodiment, the word line contact portion is located at an end of the word line conductive structure.

[0027] In one embodiment, a ratio of a thickness of the word line conductive structure of the word line contact portion to a thickness of the word line conductive structure outside the word line contact portion is greater than or equal to 1.5 and less than or equal to 4.0.

[0028] In one embodiment, the device further comprises:

[0029] A peripheral circuit area, the peripheral circuit area includes a transistor active area, and the active area has a source area / drain area;

[0030] An insulating dielectric layer, the insulating dielectric layer being located on the surface of the word line conductive structure and the active area;

[0031] a word line contact structure, the word line contact structure being located on the word line contact portion and in contact with the word line contact portion;

[0032] An active area contact structure is provided, wherein the active area contact structure is located on the transistor active area and contacts the source area / drain area of ​​the transistor active area.

[0033] In one embodiment, a height difference between the active area contact structure and the word line contact structure is greater than or equal to 0 and less than 20% of the height of the active area contact structure.

[0034] In one embodiment, the active area contact structure and the word line contact structure are formed simultaneously.

[0035] In one embodiment, the semiconductor device is a dynamic random access memory.

[0036] The semiconductor device includes a substrate, a memory cell array area is formed on the substrate, and the memory cell array area is formed with word line grooves arranged at intervals; a word line conductive structure, the word line conductive structure includes a word line conductive structure of a word line contact part and a word line conductive structure outside the word line contact part; wherein the thickness of the word line conductive structure of the word line contact part is greater than the thickness of the word line conductive structure outside the word line contact part. The device substrate surface of the present application is formed with a word line conductive structure of a word line contact part, the thickness of which is greater than the thickness of the word line conductive structure outside the word line contact part. Compared with a device in which the thickness of the word line conductive structure of the word line contact part in the word line conductive structure is equal to the thickness of the word line conductive structure outside the word line contact part, the depth of the window position of the word line contact hole is reduced, the process time in the process of forming the contact hole is reduced, the excessive erosion of the side wall of the contact hole with a shallow window depth in the contact hole process is reduced, and the device short circuit abnormality caused by the contact hole abnormality is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a flow chart of a method for manufacturing a semiconductor device in one embodiment;

[0038] Figure 2a is a flow chart of forming a word line contact hole in one embodiment;

[0039] Figure 2b is a flow chart of forming an active area contact hole in one embodiment;

[0040] Figure 3a is a cross-sectional view of a semiconductor device in one embodiment;

[0041] Figure 3b is a cross-sectional view of a semiconductor device after a word line conductive film is formed in one embodiment;

[0042] Figure 3c is a cross-sectional view of a semiconductor device after an insulating dielectric layer is formed in one embodiment;

[0043] Figure 4a is a cross-sectional view of a word line contact portion in a direction vertical to the word line conductive film after the word line conductive film is formed in one embodiment;

[0044] Figure 4b After forming a photoresist in one embodiment Figure 4a The corresponding cross-sectional view;

[0045] Figure 4c After forming the insulating dielectric layer in one embodiment Figure 4b The corresponding cross-sectional view;

[0046] Figure 5a is a cross-sectional view of a region outside a word line contact portion in a direction vertical to the word line conductive film after a word line conductive film is formed in one embodiment;

[0047] Figure 5b After forming the word line conductive structure in one embodiment Figure 5a The corresponding cross-sectional view;

[0048] Figure 5c After forming the insulating dielectric layer in one embodiment Figure 5b The corresponding cross-sectional view. DETAILED DESCRIPTION

[0049] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0052] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0055] When a typical dynamic random access memory is making contact window structures connecting word lines, bit lines, source / drain regions of transistor active areas, and transistor gate regions, since the contact holes corresponding to different contact window structures need to be opened to different target depths, when the contact holes are prepared using the same process, one contact hole has reached the corresponding target depth, while the other contact holes have not yet completed opening. At this time, the window opening continues, and the sidewalls of the contact holes will continue to be expanded while the contact hole depth increases, which can easily cause the device feature size to become larger or the side etching device to short-circuit abnormalities. For example, the transistor active area contact hole (Active Area Contact, AA Contact) has stopped on the surface of the active area, and the deeper word line contact hole (Word line Contact, WL Contact) stays above the word line conductive structure and has not yet completed opening. When etching continues, the transistor active area contact hole will be etched into the active area, resulting in a spiking effect.

[0056] like Figure 1 , Figure 3a , Figure 3b , Figure 3c , Figure 4a-4c , Figure 5a-5c As shown, in one embodiment, a method for manufacturing a semiconductor device is provided, comprising:

[0057] S102, obtaining a substrate.

[0058] The substrate 102 includes a memory cell array region, and the substrate may be at least one of silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (SSiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0059] S104, forming a word line trench.

[0060] The memory cell array region is provided with word line trenches 104 arranged at intervals. The memory cell array region is provided with a plurality of mutually independent word line trenches, the word line trenches extending along a first direction and arranged at intervals along a second direction, the first direction and the second direction intersecting each other.

[0061] In one embodiment, the word line trench is formed by dry etching. In another embodiment, the word line trench is formed by wet etching.

[0062] In one embodiment, the word line trench is formed by two process steps.

[0063] S106, forming a word line conductive film.

[0064] The word line trench 104 is filled with a word line conductive material to form a word line conductive film 108. In one embodiment, before forming the word line conductive film 108, an insulating layer 110 is formed on the inner wall of the word line trench 104. The insulating layer 110 can be a silicon dioxide film layer.

[0065] In one embodiment, before filling the word line conductive material in the word line trench 104 , a first metal layer is formed on the inner wall of the word line trench. For example, the first metal layer may be a titanium / titanium nitride metal layer having adhesion and barrier functions.

[0066] In one embodiment, the word line conductive material is formed by a plasma chemical vapor deposition process. In one embodiment, the word line conductive material is formed by a physical vapor deposition process. In one embodiment, the word line conductive material is a metal conductive material, such as a metal tungsten material, a metal tungsten composite material, a metal aluminum material, etc.

[0067] In one embodiment, after removing excess word line conductive material on the surface of the substrate, a word line conductive film 108 is formed in the word line trench 104 .

[0068] In one embodiment, the excess word line conductive material on the substrate surface is removed by chemical mechanical polishing. In another embodiment, the excess word line conductive material on the substrate surface is removed by etching, such as wet etching, dry etching, etc.

[0069] S108, forming a photoresist.

[0070] A photoresist 112 is formed on the surface of the substrate 102, i.e., a photoresist with a photolithography pattern is formed on the surface of the substrate, the photoresist 112 covers the word line groove 115 of the word line contact part 114, i.e., the word line conductive film of the word line contact part, and exposes the word line groove 116 outside the word line contact part 114, i.e., the word line conductive film outside the word line contact part.

[0071] Specifically, photoresist is coated on the surface of the substrate, and then the photoresist is exposed and developed to expose the word line conductive film outside the word line contact part (that is, the array area of ​​the device is developed), and the unexposed photoresist covers the word line conductive film at the word line contact part, thereby protecting the word line conductive film at the word line contact part.

[0072] S110 , forming a word line conductive structure.

[0073] The word line conductive structure 117 is obtained by etching the word line conductive film not covered by the photoresist to a target height with the photoresist 112 as a barrier layer, that is, the word line conductive film 108 is thinned with the photoresist 112 as a barrier layer to obtain the word line conductive structure 117, so that the thickness of the word line conductive structure at the word line contact portion 114 is greater than the thickness of the word line conductive structure not covered by the photoresist 112. Etching the word line conductive film not covered by the photoresist to a target height means etching the word line conductive film not covered by the photoresist until the remaining word line conductive film is less than 5 nanometers below the substrate surface, as long as the remaining word line conductive film can achieve the purpose of avoiding short circuit between the word line and the bit line and other contact windows and other structures.

[0074] S112, removing the photoresist.

[0075] The photoresist on the substrate surface is removed.

[0076] In one embodiment, the word line conductive structure 117 is located on the shallow trench isolation oxide layer 121 .

[0077] In one embodiment, the word line contact 114 is located at an end of the word line conductive structure 117 .

[0078] In one embodiment, the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.0. In an actual process, the value of the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure not covered by the photoresist is set as needed, such as 1.7, 1.9, 2.0, 2.2, 2.5, 2.7, 2.9, 3.0, 3.3, 3.5, 3.7, 3.9, etc.

[0079] like Figure 2a As shown, in one embodiment, after step S112, the following steps are further included:

[0080] S202, forming a first insulating dielectric layer.

[0081] A first insulating dielectric layer is formed on the surface of the word line conductive structure 117 .

[0082] In one embodiment, after removing the photoresist on the word line conductive structure, a first insulating dielectric layer film is formed on the surface of the substrate. For example, the first insulating dielectric layer film can be formed on the surface of the substrate by physical vapor deposition or chemical vapor deposition; then, the first insulating dielectric layer is formed by removing excess first insulating dielectric layer film on the surface of the substrate by etching or chemical mechanical polishing.

[0083] In one embodiment, the first insulating dielectric layer is a silicon oxide insulating layer.

[0084] S204, forming a word line contact hole.

[0085] like Figure 3a As shown, the first insulating dielectric layer is patterned to form a word line contact hole 119 on the word line contact portion 114 .

[0086] like Figure 2b As shown, in one embodiment, the substrate further includes a peripheral circuit area, the peripheral circuit area includes a transistor active area, and the method for manufacturing the semiconductor device further includes:

[0087] S201, forming a second insulating dielectric layer.

[0088] A second insulating dielectric layer is formed on the surface of the transistor active area.

[0089] In one embodiment, the second insulating dielectric layer and the first insulating dielectric layer are formed by the same process.

[0090] S203, forming active area contact holes.

[0091] The second insulating dielectric layer is patterned to form an active region contact hole 120 on the source region / drain region 106 of the active region.

[0092] In one embodiment, the height difference between the active area contact hole 120 and the word line contact hole 119 is greater than or equal to 0 and less than 20% of the height of the active area contact hole. In the actual process flow, the height difference between the active area contact hole and the word line contact hole 119 can be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19% of the height of the active area contact hole, etc.

[0093] In one embodiment, the word line contact hole 119 and the active area contact hole 120 are formed by the same process.

[0094] In one embodiment, the semiconductor device is a dynamic random access memory.

[0095] The above-mentioned manufacturing method includes: obtaining a substrate, the substrate including a memory cell array area; forming spaced word line grooves in the memory cell array area; filling the word line grooves with word line conductive material to form a word line conductive film; forming a photoresist on the surface of the substrate, the photoresist covering the word line conductive film at the word line contact part and exposing the word line conductive film outside the word line contact part; using the photoresist as a barrier layer, etching the word line conductive film not covered by the photoresist to a target depth to obtain a word line conductive structure, so that the thickness of the word line conductive structure at the word line contact part is greater than the thickness of the word line conductive structure not covered by the photoresist. The present application forms a photoresist on the surface of a substrate, wherein the photoresist covers a word line conductive film of a word line contact portion and exposes the word line conductive film outside the word line contact portion, and then etches the word line conductive film not covered by the photoresist to a target height using the photoresist as a barrier layer, so that the thickness of the word line conductive structure of the word line contact portion in the formed word line conductive structure is greater than the thickness of the word line conductive structure not covered by the photoresist. Compared with the word line conductive structure in which the thickness of the word line conductive structure of the word line contact portion is equal to the thickness of the word line conductive structure not covered by the photoresist, the window opening position depth of the word line contact hole in the word line contact portion is reduced, the process time in the process of forming the contact hole is reduced, the excessive erosion of the side wall of the contact hole with a shallow window opening depth in the contact hole process is reduced, and the device short circuit abnormality caused by the contact hole abnormality is avoided.

[0096] like Figure 3a , Figure 3b , Figure 3c As shown, in one embodiment, a semiconductor device is provided, comprising:

[0097] A substrate 102 is formed on the substrate 102, and a memory cell array region is formed in the memory cell array region with spaced word line trenches 104. A plurality of mutually independent word line trenches are formed in the memory cell array region, and the word line trenches extend along a first direction and are spaced along a second direction, and the first direction and the second direction intersect. The substrate can be at least one of silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (SSiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).

[0098] The word line conductive structure 117 includes the word line conductive structure of the word line contact portion 114 and the word line conductive structure outside the word line contact portion 114 .

[0099] In one embodiment, the word line contact portion 114 is located at an end of the word line conductive structure 117 .

[0100] In one embodiment, the word line conductive structure 117 is a metal conductive structure, such as a metal tungsten conductive structure, a metal tungsten composite conductive structure, a metal aluminum conductive structure, etc.

[0101] The thickness of the word line conductive structure of the word line contact portion 114 is greater than the thickness of the word line conductive structure outside the word line contact portion 114 .

[0102] In one embodiment, the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is greater than or equal to 1.5 and less than or equal to 4.0. In the actual semiconductor device design process, the value of the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is set as needed, for example, 1.7, 1.9, 2.0, 2.2, 2.5, 2.7, 2.9, 3.0, 3.3, 3.5, 3.7, 3.9, etc.

[0103] In one embodiment, the device further comprises:

[0104] The word line contact hole 119 is formed on the word line contact portion 114 and the bottom of the word line contact hole 119 contacts the upper surface of the word line contact portion 114 .

[0105] The active area contact hole 120 is formed on the transistor active area and the bottom of the active area contact hole 120 contacts the upper surface of the source / drain area 106 of the transistor active area.

[0106] In one embodiment, the device further comprises:

[0107] A peripheral circuit region, the peripheral circuit region includes a transistor active region, the active region has a source region / drain region 106;

[0108] An insulating dielectric layer 118 is located on the surface of the word line conductive structure and the active area.

[0109] In one embodiment, the insulating dielectric layer 118 includes a first insulating dielectric layer located on the surface of the word line conductive structure 117 and a second insulating dielectric layer located on the surface of the transistor active region.

[0110] A word line contact structure is located on the word line contact portion 114 and contacts the word line contact portion 114 .

[0111] The word line contact structure is located in a word line contact hole 119 formed on the word line contact portion 114 . The word line contact structure is a conductive structure for leading out the word line conductive structure 117 .

[0112] In one embodiment, the word line contact structure is a metal conductive structure, such as a metal tungsten conductive structure, a metal tungsten composite conductive structure, a metal aluminum conductive structure, etc.

[0113] Active area contact structure, the active area contact hole is located on the transistor active area and contacts the source area / drain area 106 of the transistor active area.

[0114] The active region contact structure is located in the active region contact hole 120 formed on the source region / drain region 106 . The active region contact structure is a conductive structure for leading out the source region / drain region 106 of the transistor.

[0115] In one embodiment, the active region contact structure is a metal conductive structure, such as a metal tungsten conductive structure, a metal tungsten composite conductive structure, a metal aluminum conductive structure, and the like.

[0116] In one embodiment, the height difference between the active area contact structure and the word line contact structure is greater than or equal to 0 and less than 20% of the height of the active area contact structure. In an actual semiconductor device, the height difference between the active area contact structure and the word line contact structure can be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19% of the height of the active area contact structure, etc.

[0117] In one embodiment, the height difference between the active area contact hole 120 and the word line contact hole 119 is greater than or equal to 0 and less than twenty percent of the height of the active area contact hole. In actual semiconductor devices, the height difference between the active area contact hole and the word line contact hole 119 can be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19% of the height of the active area contact hole, etc.

[0118] In one embodiment, the device further includes a first metal layer, which is located in the word line groove, and the upper surface of the first metal layer contacts the lower surface of the word line conductive structure. For example, the first metal layer can be a titanium / titanium nitride metal layer that plays an adhesion and barrier role.

[0119] In one embodiment, the semiconductor device is a dynamic random access memory.

[0120] The semiconductor device includes a substrate, a memory cell array area is formed on the substrate, and the memory cell array area is formed with word line grooves arranged at intervals; a word line conductive structure, the word line conductive structure includes a word line conductive structure of a word line contact part and a word line conductive structure outside the word line contact part; wherein the thickness of the word line conductive structure of the word line contact part is greater than the thickness of the word line conductive structure outside the word line contact part. The device substrate surface of the present application is formed with a word line conductive structure of a word line contact part, the thickness of which is greater than the thickness of the word line conductive structure outside the word line contact part. Compared with a device in which the thickness of the word line conductive structure of the word line contact part in the word line conductive structure is equal to the thickness of the word line conductive structure outside the word line contact part, the depth of the window position of the word line contact hole is reduced, the process time in the process of forming the contact hole is reduced, the excessive erosion of the side wall of the contact hole with a shallow window depth in the contact hole process is reduced, and the device short circuit abnormality caused by the contact hole abnormality is avoided.

[0121] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Obtaining a substrate, the substrate comprising a memory cell array region; forming word line trenches arranged at intervals in the memory cell array region; Filling the word line trench with a word line conductive material to form a word line conductive film, wherein the surface of the word line conductive film is flush with the surface of the substrate; forming a photoresist on the surface of the substrate, wherein the photoresist covers the word line conductive film of the word line contact portion and exposes the word line conductive film outside the word line contact portion; Using the photoresist as a barrier layer, etching the word line conductive film not covered by the photoresist to a target height to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact portion is greater than the thickness of the word line conductive structure not covered by the photoresist, that is, the surface of the word line contact portion is flush with the surface of the substrate, and the surface of the word line conductive structure is lower than the surface of the substrate; removing the photoresist; The substrate further includes a peripheral circuit region, and the peripheral circuit region includes a transistor active region. The method further includes: An insulating dielectric layer is formed on the surface of the substrate, wherein the insulating dielectric layer includes a first insulating dielectric layer located in the memory cell array area and a second insulating dielectric layer located in the peripheral circuit area, wherein the first insulating dielectric layer covers the surface of the word line contact portion and the word line conductive structure, and the second insulating dielectric layer covers the surface of the transistor active area, wherein the surfaces of the first insulating dielectric layer and the second insulating dielectric layer are flush, and wherein the first insulating dielectric layer and the second insulating dielectric layer are formed by the same process; The first insulating dielectric layer and the second insulating dielectric layer are patterned, a word line contact hole is formed on the word line contact portion, and an active area contact hole is formed on the transistor active area.

2. The method according to claim 1, characterized in that The word line contact portion is located at an end of the word line conductive structure.

3. The method according to claim 1, characterized in that The word line contact hole and the active area contact hole are formed by the same process.

4. The method according to claim 1, characterized in that A ratio of a thickness of the word line conductive structure of the word line contact portion to a thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.

0.

5. A semiconductor device comprising: A substrate having a memory cell array region formed thereon, wherein the memory cell array region has word line trenches arranged at intervals; A word line conductive structure, wherein the word line conductive structure includes a word line conductive structure of a word line contact portion and a word line conductive structure outside the word line contact portion; Wherein, the thickness of the word line conductive structure at the word line contact portion is greater than the thickness of the word line conductive structure outside the word line contact portion; The substrate further comprises a peripheral circuit region, wherein the peripheral circuit region comprises a transistor active region; an insulating dielectric layer, the insulating dielectric layer comprising a first insulating dielectric layer located in the memory cell array region and a second insulating dielectric layer located in the peripheral circuit region, the first insulating dielectric layer covers the surface of the word line contact portion and the word line conductive structure, the second insulating dielectric layer covers the surface of the transistor active region, the surfaces of the first insulating dielectric layer and the second insulating dielectric layer are flush, and the first insulating dielectric layer and the second insulating dielectric layer are formed by the same process; A word line contact hole, wherein the word line contact hole is formed in the first insulating dielectric layer; An active area contact hole is formed in the second insulating dielectric layer.

6. The device according to claim 5, characterized in that The word line contact portion is located at an end of the word line conductive structure.

7. The device according to claim 5, characterized in that A ratio of a thickness of the word line conductive structure of the word line contact portion to a thickness of the word line conductive structure outside the word line contact portion is greater than or equal to 1.5 and less than or equal to 4.

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8. The device according to claim 5, characterized in that a word line contact structure, wherein the word line contact structure is formed in the word line contact hole and contacts the word line contact portion; An active area contact structure is formed in the active area contact hole and contacts the transistor active area.

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