Solid-state imaging device and imaging apparatus

Abstract

The object of the present invention is to improve noise performance. A solid-state imaging device according to an embodiment of the present invention comprises: a plurality of photoelectric conversion elements (333) arranged in a two-dimensional lattice in row and column directions and generating charges respectively according to the amount of received light; and a detection unit (400) detecting a photocurrent based on the charges generated in the plurality of photoelectric conversion elements. At least a portion of the photoelectric conversion elements and the detection unit are arranged in different chips (201a, 201b).

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and an imaging apparatus. Background Art

[0002] Conventional imaging devices and the like include synchronous solid-state imaging devices that capture image data (frames) in synchronization with a synchronization signal (e.g., a vertical synchronization signal). Such typical synchronous solid-state imaging devices are allowed to acquire image data only once in each cycle of the synchronization signal (e.g., 1 / 60 second). In this case, it is difficult to meet the demand for higher-speed processing in fields related to transportation, robots, and the like. Therefore, an asynchronous solid-state imaging device has been proposed, which includes a detection circuit provided for each pixel to detect in real time that the amount of received light exceeds a threshold value as an address event. An asynchronous solid-state imaging device that detects address events for each pixel is also referred to as a DVS (dynamic vision sensor).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [PTL 1]

[0006] JP-T-2016-533140 Summary of the invention

[0007] [Technical issues]

[0008] However, a typical DVS is configured such that a photoelectric conversion element for generating a charge corresponding to the amount of received light and a circuit for detecting the presence or absence of an address event trigger based on a change in the current value of a photocurrent generated by the charge generated in the photoelectric conversion element (hereinafter referred to as a pixel circuit) are integrated on the same substrate. In this case, a dark current from the photoelectric conversion element flows into a transistor constituting the pixel circuit, and causes a problem in which the noise characteristics of the DVS are degraded.

[0009] Therefore, the present disclosure proposes a solid-state imaging device and an imaging apparatus capable of improving noise characteristics.

[0010] [Solution to the problem]

[0011] In order to solve the above problems, a solid-state imaging device according to one aspect of the present disclosure includes: a plurality of photoelectric conversion elements arranged in a two-dimensional grid shape in a matrix direction, and each photoelectric conversion element generates a charge corresponding to the amount of received light; and a detection unit that detects a photocurrent generated by the charge generated in each of the plurality of photoelectric conversion elements. At least a portion of the photoelectric conversion element and the detection unit are provided on different chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram depicting a schematic configuration example of a solid-state imaging device and an imaging apparatus according to the first embodiment.

[0013] Figure 2 : is a diagram depicting an example of a stacked structure of the solid-state imaging device according to the first embodiment.

[0014] Figure 3 is a block diagram depicting a functional configuration example of the solid-state imaging device according to the first embodiment.

[0015] Figure 4 is a circuit diagram depicting a schematic configuration example of a unit pixel according to the first embodiment.

[0016] Figure 5 is a block diagram depicting a schematic configuration example of an address event detection unit according to the first embodiment.

[0017] Figure 6 is a circuit diagram depicting another schematic configuration example of the current-voltage conversion circuit according to the first embodiment.

[0018] Figure 7 is a circuit diagram depicting a schematic configuration example of a subtractor and a quantizer according to the first embodiment.

[0019] Figure 8 is a cross-sectional view illustrating an example of a cross-sectional structure of the solid-state imaging device according to the first embodiment.

[0020] Fig. 9 is a plan view illustrating an example of a layer diagram of the first chip according to the first embodiment.

[0021] Fig.10 is a plan view illustrating an example of a layer diagram of the second chip according to the first embodiment.

[0022] Fig.11 is a plan view illustrating another example of a layer diagram of the second chip according to the first embodiment.

[0023] Fig.12 It is a graph showing the relationship between transistor current and noise.

[0024] Fig.13 is a cross-sectional diagram depicting a schematic configuration example of a transistor according to the second embodiment.

[0025] Fig.14 It is represented by an example Fig.13 A graph showing the current-voltage characteristics of a transistor.

[0026] Fig.15 is a schematic diagram depicting another configuration example of the transistor according to the second embodiment.

[0027] Fig.16 is a schematic diagram depicting still another configuration example of the transistor according to the second embodiment.

[0028] Fig.17 is a cross-sectional view (1) depicting an example of a manufacturing process of a solid-state imaging device according to the third embodiment.

[0029] Fig.18 is a cross-sectional view (2) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0030] Fig.19 is a cross-sectional view (3) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0031] Fig. 20 is a cross-sectional view (4) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0032] Fig.21 is a cross-sectional view (5) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0033] Fig. 22 is a cross-sectional view (6) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0034] Fig.23 is a cross-sectional view (7) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0035] Fig.24 is a cross-sectional view (8) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0036] Fig.25 is a cross-sectional view (9) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0037] Fig.26 is a cross-sectional view (10) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0038] Fig. 27 is a cross-sectional view (11) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0039] Fig.28 is a cross-sectional view (12) depicting an example of a manufacturing process of the solid-state imaging device according to the third embodiment.

[0040] Fig.29 is a circuit diagram depicting a schematic configuration example of a unit pixel according to the fourth embodiment.

[0041] Fig.30 is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to a fourth embodiment.

[0042] Fig.31 is a plan view illustrating an example of a layer diagram of a first chip according to the fourth embodiment.

[0043] Fig.32 is a circuit diagram depicting a schematic configuration example of a unit pixel according to the fifth embodiment.

[0044] Fig.33 is a circuit diagram depicting another schematic configuration example of a unit pixel according to the fifth embodiment.

[0045] Fig.34 : is a diagram depicting an example of a stacked structure of a solid-state imaging device according to a sixth embodiment.

[0046] Fig.35 is a circuit diagram depicting a schematic configuration example of a unit pixel according to the sixth embodiment.

[0047] Fig.36 is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to a seventh embodiment.

[0048] Fig.37 is a block diagram depicting a functional configuration example of a solid-state imaging device according to an eighth embodiment.

[0049] Fig.38 is a block diagram depicting a schematic configuration example of a column ADC according to the eighth embodiment.

[0050] Fig.39 is a circuit diagram depicting a schematic configuration example of a unit pixel according to the eighth embodiment.

[0051] Fig.40 is a timing chart showing an operation example of the solid-state imaging device according to the eighth embodiment.

[0052] Fig.41 is a flowchart showing an operation example of the solid-state imaging device according to the eighth embodiment.

[0053] Fig.42 is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to an eighth embodiment.

[0054] Fig.43 is a plan view illustrating an example of a layer diagram of a first chip according to the eighth embodiment.

[0055] Fig.44 is a plan view illustrating an example of a layer diagram of a second chip according to the eighth embodiment.

[0056] Fig.45 : is a diagram depicting an example of a stacked structure of a solid-state imaging device according to a ninth embodiment.

[0057] Fig.46 is a circuit diagram depicting a schematic configuration example of a unit pixel according to the ninth embodiment.

[0058] Fig.47 is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to a ninth embodiment.

[0059] Fig.48 is a block diagram depicting a schematic configuration example of a pixel array unit according to a tenth embodiment.

[0060] Fig.49 is a schematic diagram depicting a configuration example of a pixel block adopting a Bayer array as a color filter array.

[0061] Fig.50 is a schematic diagram depicting a configuration example of a pixel block adopting an X-Trans (registered trademark) type array as a color filter array.

[0062] Fig.51 is a schematic diagram depicting a configuration example of a pixel block that adopts a Quad Bayer array as a color filter array.

[0063] Fig.52 is a schematic diagram depicting a configuration example of a pixel block that adopts a white RGB array as a color filter array.

[0064] Fig.53 is a circuit diagram depicting a schematic configuration example of a pixel block according to the tenth embodiment.

[0065] Fig.54 is a timing chart showing an operation example of the solid-state imaging device according to the tenth embodiment.

[0066] Fig.55 is a flowchart showing an operation example of the solid-state imaging device according to the tenth embodiment.

[0067] Fig.56 is a plan view depicting an example of a layer diagram of a first chip according to a first example of the tenth embodiment.

[0068] Fig.57 is a plan view depicting an example of a layer diagram of a second chip according to the first example of the tenth embodiment.

[0069] Fig.58 is a plan view depicting an example of a layer diagram of a first chip according to the second example of the tenth embodiment.

[0070] Fig.59 is a plan view depicting an example of a layer diagram of a second chip according to a second example of the tenth embodiment.

[0071] Fig.60 is a plan view depicting an example of a layer diagram of a first chip according to the third example of the tenth embodiment.

[0072] Fig.61 is a plan view depicting an example of a layer diagram of a second chip according to the third example of the tenth embodiment.

[0073] Fig.62 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0074] Fig.63 is a diagram to help explain an example of the installation positions of the vehicle exterior information detecting portion and the imaging portion. DETAILED DESCRIPTION

[0075] Hereinafter, one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the following embodiments, the same parts have the same reference numerals to omit repeated descriptions.

[0076] Furthermore, the present disclosure will be described in the following order of items.

[0077] 1. Introduction

[0078] 2. First embodiment

[0079] 2.1 Configuration example of imaging device

[0080] 2.2 Configuration Examples of Solid-State Imaging Devices

[0081] 2.2.1 Examples of stacked structures of solid-state imaging devices

[0082] 2.2.2 Functional configuration examples of solid-state imaging devices

[0083] 2.3 Configuration example of unit pixel

[0084] 2.4 Configuration Example of Address Event Detection Unit

[0085] 2.4.1 Configuration example of current-voltage conversion unit

[0086] 2.4.2 Configuration Example of Subtractor and Quantizer

[0087] 2.5 Settings of each layer

[0088] 2.6 Example of cross-sectional structure of solid-state imaging device

[0089] 2.7 Layer Board Diagram Example

[0090] 2.7.1 First Chip

[0091] 2.7.2 Second Chip

[0092] 2.7.2.1 Source Follower Type

[0093] 2.7.2.2 Gain Boost Type

[0094] 2.8 Operation and Effect

[0095] 3. Second embodiment

[0096] 3.1 Improvement of transistor noise characteristics

[0097] 3.1.1 Using FDSOI (Fully Depleted Silicon on Insulator)

[0098] 3.1.2 Use of Tunnel FET and Fin FET

[0099] 3.2 Operation and Effect

[0100] 4. Third embodiment

[0101] 4.1 Manufacturing process of solid-state imaging devices

[0102] 4.2 Operation and Effect

[0103] 5. Fourth embodiment

[0104] 5.1 Example of unit pixel configuration

[0105] 5.2 Example of a cross-sectional structure of a solid-state imaging device

[0106] 5.3 Layer Diagram Example

[0107] 5.4 Operation and Effect

[0108] 6. Fifth embodiment

[0109] 7. Sixth embodiment

[0110] 7.1 Examples of stacked structures of solid-state imaging devices

[0111] 7.2 Example of unit pixel configuration

[0112] 8. Seventh embodiment

[0113] 8.1 Example of Cross-Section Structure of Solid-State Imaging Device

[0114] 9. Eighth Embodiment

[0115] 9.1 Functional Configuration Example of Solid-State Imaging Device

[0116] 9.1.1 Configuration Example of Column ADC

[0117] 9.2 Example of unit pixel configuration

[0118] 9.3 Operation Examples of Solid-State Imaging Devices

[0119] 9.3.1 Time Diagram

[0120] 9.3.2 Flowchart

[0121] 9.4 Example of Cross-Section Structure of Solid-State Imaging Device

[0122] 9.5 Layer Diagram Example

[0123] 9.5.1 First Chip

[0124] 9.5.2 Second Chip

[0125] 9.6 Operation and Effect

[0126] 10. Ninth Embodiment

[0127] 10.1 Example of Cross-Sectional Structure of Solid-State Imaging Device

[0128] 10.2 Operation and Effect

[0129] 11. Tenth Embodiment

[0130] 11.1 Configuration Example of Pixel Array Unit

[0131] 11.2 Example of a pixel block

[0132] 11.2.1 Bayer Array

[0133] 11.2.2 X-Trans (registered trademark) array

[0134] 11.2.3 Quad Bayer Array

[0135] 11.2.4 White RGB Array

[0136] 11.3 Example of pixel block configuration

[0137] 11.4 Operation Examples of Solid-State Imaging Devices

[0138] 11.4.1 Time Diagram

[0139] 11.4.2 Flowchart

[0140] 11.5 Layer Diagram Example

[0141] 11.5.1 First Example

[0142] 11.5.1.1 First Chip

[0143] 11.5.1.2 Second Chip

[0144] 11.5.2 Second Example

[0145] 11.5.3 Third Example

[0146] 11.6 Operation and Effect

[0147] 12. Application examples for mobile objects

[0148] 1. Introduction

[0149] A typical DVS adopts a so-called event-driven driving system that detects the presence or absence of an address event trigger for each unit pixel and, when the address event trigger is detected, reads a pixel signal from the unit pixel corresponding to the address event trigger.

[0150] Note that a unit pixel in this specification is a minimum unit of a pixel including one photoelectric conversion element (also referred to as a light receiving element), and corresponds to, for example, a point in image data read from an image sensor. In addition, an address event is an event caused for each address assigned to each of a plurality of unit pixels arranged in a two-dimensional grid shape, for example, an excess of a current value of a current (hereinafter referred to as a photocurrent) generated by electric charge generated in a photoelectric conversion element or an amount of change in a current value exceeding a specific threshold value.

[0151] As described above, a typical DVS adopts a configuration in which a photoelectric conversion element and a pixel circuit are provided on the same substrate. In the above configuration in which the photoelectric conversion element and the circuit element are provided on the same substrate, dark current flows from the photoelectric conversion element into each transistor constituting the pixel circuit. Therefore, the noise characteristics of the DVS may be degraded.

[0152] In addition, in a configuration where the photoelectric conversion element and the circuit element are arranged on the same substrate, the proportion of the photoelectric conversion element in the light receiving surface is reduced. As a result, there is a problem that the noise characteristics deteriorate as the quantum efficiency of the incident light (hereinafter referred to as the light receiving efficiency) decreases.

[0153] In addition, in a configuration where the photoelectric conversion element and the circuit element are provided on the same substrate, it is generally difficult to ensure a sufficient area for each transistor constituting the pixel circuit. In this case, the noise characteristics of each transistor deteriorate, and thus the problem of deterioration of the DVS noise characteristics arises.

[0154] Therefore, the embodiments described in detail below are several examples of a solid-state imaging device and an imaging apparatus capable of reducing degradation in noise characteristics.

[0155] 2. First embodiment

[0156] First, a solid-state imaging device and an imaging apparatus according to a first embodiment will be described in detail with reference to the drawings.

[0157] 2.1 Configuration example of imaging device

[0158] Figure 1 1 is a block diagram illustrating a schematic configuration example of a solid-state imaging device and an imaging apparatus according to a first embodiment. Figure 1 As shown, for example, the imaging apparatus 100 includes an imaging lens 110, a solid-state imaging device 200, a recording unit 120, and a control unit 130. It is assumed that the imaging apparatus 100 constitutes a camera mounted on an industrial robot, a vehicle-mounted camera, or the like.

[0159] The imaging lens 110 is an example of an optical system that converges incident light and forms an image of the light on a light receiving surface of the solid-state imaging device 200. The light receiving surface may be a surface on which a photoelectric conversion element of the solid-state imaging device 200 is disposed. The solid-state imaging device 200 performs photoelectric conversion on the incident light to generate image data. In addition, the solid-state imaging device 200 performs predetermined signal processing, such as noise removal and white balance adjustment, on the generated image data. The result obtained by the signal processing and the detection signal indicating the presence or absence of the address event trigger are output to the recording unit 120 via the signal line 209. Note that a method for generating a detection signal indicating the presence or absence of the address event trigger will be described below.

[0160] For example, the recording unit 120 includes a flash memory, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), or the like, and records data input from the solid-state imaging device 200 .

[0161] The control unit 130 includes, for example, a CPU (Central Processing Unit) and the like, and outputs various instructions via a signal line 139 to control the respective units of the imaging apparatus 100 , for example, the solid-state imaging device 200 .

[0162] 2.2 Configuration Examples of Solid-State Imaging Devices

[0163] Next, a configuration example of the solid-state imaging device 200 will be described in detail with reference to the drawings.

[0164] 2.2.1 Examples of stacked structures of solid-state imaging devices

[0165] Figure 2 1 is a diagram illustrating an example of a stacked structure of a solid-state imaging device according to the first embodiment. Figure 2 As shown, the solid-state imaging device 200 has a structure in which a light receiving chip 201 and a detection chip 202 are stacked in the up-down direction. For example, the light receiving chip 201 has a double-layer structure, which includes a first chip 201a and a second chip 201b fixed to each other. The photoelectric conversion element is arranged on the first chip 201a, and the pixel circuit is arranged on the second chip 201b.

[0166] The bonding between the first chip 201a and the second chip 201b and the bonding between the light receiving chip 201 (specifically, the second chip 201b) and the detection chip 202 can be achieved by, for example, so-called direct bonding, which flattens each bonding surface and fixes the two surfaces by inter-electronic forces. However, it is not required to adopt such a bonding method. For example, a bonding method such as the so-called Cu-Cu bonding can be adopted, which includes copper (Cu) and electrode pads formed on each bonding surface and bump bonding.

[0167] In addition, for example, the light receiving chip 201 and the detection chip 202 are electrically connected to each other via a connection portion such as a TSV (Through Silicon Via) penetrating a semiconductor substrate. Examples of connections suitable for use with TSVs include: a so-called double TSV method in which two TSVs are connected on the chip outer surface, namely, a TSV provided on the light receiving chip 201 and a TSV provided from the light receiving chip 201 to the detection chip 202; and a so-called shared TSV method in which the light receiving chip 201 and the detection chip 202 are connected via a TSV penetrating from the light receiving chip 201 to the detection chip 202.

[0168] However, in the case where Cu-Cu bonding or bump bonding is used for bonding between the light receiving chip 201 and the detection chip 202 , the two chips are electrically connected via the Cu-Cu bonding portion or the bump bonding portion.

[0169] 2.2.2 Functional configuration examples of solid-state imaging devices

[0170] Figure 3 1 is a block diagram illustrating an example of a functional configuration of a solid-state imaging device according to a first embodiment. Figure 3 As shown, the solid-state imaging device 200 includes a driving circuit 211 , a signal processing unit 212 , an arbitrator 213 , and a pixel array unit 300 .

[0171] A plurality of unit pixels are arranged in a two-dimensional grid shape on the pixel array unit 300. As described in detail below, for example, the unit pixel includes a photoelectric conversion element (e.g., a photodiode) and a pixel circuit (corresponding to the address event detection unit 400 described below in this embodiment), which detects the presence or absence of an address event trigger based on whether the current value of the photocurrent generated by the charge generated in the photoelectric conversion element or the amount of change in the current value exceeds a predetermined threshold. The pixel circuit here can be shared by a plurality of photoelectric conversion elements. In this case, each unit pixel includes a photoelectric conversion element and a pixel circuit to be shared.

[0172] The plurality of unit pixels of the pixel array unit 300 may be grouped into a plurality of pixel blocks, each pixel block including a predetermined number of unit pixels. Hereinafter, a group of unit pixels or pixel blocks arranged in a horizontal direction will be referred to as a "row", and a group of unit pixels or pixel blocks arranged in a direction perpendicular to the row will be referred to as a "column".

[0173] When an address event trigger is detected in the pixel circuit, each unit pixel outputs a request to read a signal from the unit pixel to the arbitrator 213 .

[0174] The arbitrator 213 arbitrates requests from one or more unit pixels and sends a predetermined response to the unit pixel that has issued the request based on the result of the arbitration. The unit pixel that has received the response outputs a detection signal indicating an address event trigger to the driving circuit 211 and the signal processing unit 212.

[0175] The driving circuit 211 sequentially drives the unit pixels that have all output the detection signal, so that the unit pixel triggered corresponding to the detected address event outputs a signal corresponding to the received light amount to, for example, the signal processing unit 212 .

[0176] The signal processing unit 212 performs predetermined signal processing on the signal input from the unit pixel, and supplies the result of the signal processing and a detection signal indicating an address event to the recording unit 120 via the signal line 209 .

[0177] 2.3 Configuration example of unit pixel

[0178] Next, a configuration example of the unit pixel 310 will be described. Figure 4 1 is a circuit diagram illustrating a schematic configuration example of a unit pixel according to the first embodiment. Figure 4 As shown, for example, the unit pixel 310 includes a light receiving unit 330 and an address event detection unit 400. Note that, for example, Figure 4 The logic circuit 210 may include Figure 3 The driving circuit 211, the signal processing unit 212 and the logic circuit of the arbiter 213 are shown in FIG.

[0179] For example, the light receiving unit 330 includes a photoelectric conversion element 333 , such as a photodiode. The output of the light receiving unit 330 is connected to the address event detection unit 400 .

[0180] For example, the address event detection unit 400 includes a current voltage conversion unit 410 and a subtractor 430. Note that the address event detection unit 400 also includes a buffer, a quantizer, and a transmission unit. Figure 5 and other figures describe the details of the address event detection unit 400.

[0181] In this configuration, the photoelectric conversion element 333 of the light receiving unit 330 performs photoelectric conversion on incident light to generate electric charge. The electric charge generated by the photoelectric conversion element 333 is input to the address event detection unit 400 as a photocurrent of a current value corresponding to the amount of electric charge.

[0182] 2.4 Configuration Example of Address Event Detection Unit

[0183] Figure 5 1 is a block diagram illustrating a schematic configuration example of an address event detection unit according to the first embodiment. Figure 5 As shown, except Figure 4 In addition to the current-to-voltage conversion unit 410 , the subtractor 430 , and the quantizer 440 , the address event detection unit 400 further includes a buffer 420 and a transmission unit 450 .

[0184] The current-voltage conversion unit 410 converts the photocurrent received from the light receiving unit 330 into a voltage signal indicating the logarithm of the photocurrent, and outputs the voltage signal thus generated to the buffer 420 .

[0185] The buffer 420 corrects the voltage signal received from the current-voltage conversion unit 410 and outputs the corrected voltage signal to the subtractor 430 .

[0186] The subtractor 430 reduces the voltage level of the voltage signal received from the buffer 420 according to the row driving signal received from the driving circuit 211 , and outputs the reduced voltage signal to the quantizer 440 .

[0187] The quantizer 440 quantizes the voltage signal received from the subtractor 430 into a digital signal, and outputs the digital signal thus generated as a detection signal to the transmission unit 450 .

[0188] The transmission unit 450 transmits the detection signal received from the quantizer 440 to the signal processing unit 212 and other units. For example, when an address event trigger is detected, the transmission unit 450 outputs a request to the arbitrator 213 for transmitting the detection signal indicating the address event from the transmission unit 450 to the driving circuit 211 and the signal processing unit 212. Thereafter, when a response to the request is received from the arbitrator 213, the transmission unit 450 outputs the detection signal to the driving circuit 211 and the signal processing unit 212.

[0189] 2.4.1 Configuration example of current-voltage conversion unit

[0190] For example, Figure 5 The current-voltage conversion unit 410 of the configuration shown may be a so-called source follower type current-voltage conversion unit, which includes an LG transistor 411, an amplifying transistor 412, and a constant current circuit 415, as shown in FIG. Figure 4However, this configuration is not required. For example, the current-to-voltage conversion unit 410 may be a so-called gain-boost type current-to-voltage converter, which includes two LG transistors 411 and 413, two amplifying transistors 412 and 414, and a constant current circuit 415, as shown in FIG. Figure 6 as shown in the example.

[0191] like Figure 4 As shown, for example, the source of the LG transistor 411 and the gate of the amplifying transistor 412 are connected to the cathode of the photoelectric conversion element 333 of the light receiving unit 330. For example, the drain of the LG transistor 411 is connected to the power supply terminal VDD.

[0192] Furthermore, for example, the source of the amplifier transistor 412 is grounded, and the drain of the amplifier transistor 412 is connected to the power supply terminal VDD via the constant current circuit 415. For example, the constant current circuit 415 may include a load MOS (Metal Oxide Semiconductor) transistor, for example, a P-type MOS transistor.

[0193] Meanwhile, in the case of a gain-boost type, for example, Figure 6 As shown, the source of the LG transistor 411 and the gate of the amplifying transistor 412 are connected to the cathode of the photoelectric conversion element 333 of the light receiving unit 330. In addition, for example, the drain of the LG transistor 411 is connected to the source of the LG transistor 413 and the gate of the amplifying transistor 412. For example, the drain of the LG transistor 413 is connected to the power supply terminal VDD.

[0194] In addition, for example, the source of the amplifier transistor 414 is connected to the gate of the LG transistor 411 and the drain of the amplifier transistor 412. For example, the drain of the amplifier transistor 414 is connected to the power supply terminal VDD via the constant current circuit 415.

[0195] Figure 4 or Figure 6 The connection relationship depicted in constitutes a ring source follower circuit. In this configuration, the photocurrent received from the light receiving unit 330 is converted into a voltage signal indicating a logarithmic value of the amount of charge corresponding to the photocurrent. Note that, for example, each of the LG transistors 411 and 413 and the amplifying transistors 412 and 414 may include an NMOS transistor.

[0196] 2.4.2 Configuration Example of Subtractor and Quantizer

[0197] Figure 7 1 is a circuit diagram illustrating a schematic configuration example of a subtractor and a quantizer according to the first embodiment. Figure 7 As shown, the subtractor 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. In addition, the quantizer 440 includes a comparator 441.

[0198] One end of the capacitor 431 is connected to the output terminal of the buffer 420, and the other end is connected to the input terminal of the inverter 432. The capacitor 433 is connected in parallel to the inverter 432. The switch 434 opens and closes a path connecting both ends of the capacitor 433 according to a row driving signal.

[0199] The inverter 432 inverts the voltage signal input via the capacitor 431. The inverter 432 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 441.

[0200] When the switch 434 is turned on, the voltage signal Vinit is input to the buffer 420 side of the capacitor 431. In addition, the opposite side becomes a virtual ground terminal. For convenience, it is assumed that the potential of the virtual ground terminal is zero. At this time, assuming that the capacity of the capacitor 431 is C1, the potential Qinit accumulated in the capacitor 431 is expressed by the following equation (1). On the other hand, the two ends of the capacitor 433 are short-circuited. Therefore, the accumulated charge of the capacitor 433 becomes zero.

[0201] Qin it=C1×Vinit (1)

[0202] Then, considering the case where the voltage on the buffer 420 side of the capacitor 431 is changed to Vafter by turning off the switch 434, the charge Qafter accumulated in the capacitor 431 is expressed by the following equation (2).

[0203] Qafter=C1×Vafter (2)

[0204] On the other hand, assuming that the output voltage is Vout, the charge Q2 accumulated in the capacitor 433 is expressed by the following equation (3).

[0205] Q2=-C2×Vout (3)

[0206] At this time, the total amount of charge of the capacitors 431 and 433 does not change. Therefore, the following equation (4) holds true.

[0207] Qinit=Qafter+Q2 (4)

[0208] The following equation (5) is obtained by replacing equation (4) with equations (1) to (3).

[0209] Vout=-(C1 / C2)×(Vafter-Vinit) (5)

[0210] Equation (5) represents the subtraction operation of the voltage signal. The gain of the subtraction result is C1 / C2. It is generally desirable to maximize the gain. Therefore, a design in which a large value is specified for C1 and a small value is specified for C2 is preferred. On the other hand, when C2 is too small, the noise characteristics may deteriorate as the kTC noise increases. Therefore, the capacity reduction of C2 is limited to the noise allowable range. In addition, an address event detection unit 400 including a subtractor 430 is installed for each unit pixel. Therefore, the area of ​​capacitors C1 and C2 is limited. The values ​​of capacitors C1 and C2 are determined based on these conditions.

[0211] The comparator 441 compares the voltage signal received from the subtractor 430 with a predetermined threshold voltage Vth applied to the inverting input terminal (-). The comparator 441 outputs a signal indicating the comparison result to the transmission unit 450 as a detection signal.

[0212] In addition, assuming that the conversion gain of the current-to-voltage conversion unit 410 is CG log And when the gain of the buffer 420 is "1", the entire gain A of the above-mentioned address event detection unit 400 is expressed by the following equation (6).

[0213]

Mathematical formula 1

[0214]

[0215] In equation (6), i photo _n is the photocurrent of the nth unit pixel and is expressed in, for example, amperes (A). In this case, N represents the number of unit pixels 310 in the pixel block and is set to "1" in the present embodiment.

[0216] 2.5 Settings of each layer

[0217] like Figure 4 As shown, the light receiving unit 330 in the above configuration is, for example, arranged Figure 2 The first chip 201a of the light receiving chip 201 shown in FIG. 1 is provided with the LG transistor 411 and the amplifying transistor 412 of the current voltage conversion unit 410 of the pixel circuit (address event detection unit 400), for example. Figure 2 2. In addition, another configuration (another circuit configuration will be hereinafter provided with reference number "510") is provided, for example, on the detection chip 202. Note that for the sake of clarity, in the following description, the configuration provided on the second chip 201b will be referred to as the upper pixel circuit 500. In the case where the current-voltage conversion unit 410 is a source follower type (see Figure 4), the upper pixel circuit 500 includes an LG transistor 411 and an amplifying transistor 412. On the other hand, in the case where the current-voltage conversion unit 410 is a gain-boosting type, the upper pixel circuit 500 includes two LG transistors 411 and 413 and two amplifying transistors 412 and 414.

[0218] like Figure 4 As shown, for example, the light receiving unit 330 provided on the first chip 201a in the light receiving chip 201 and the upper pixel circuit 500 provided on the second chip 201b are electrically connected to each other via a connection portion 501 penetrating from the first chip 201a to the second chip 201b.

[0219] Furthermore, for example, the upper layer pixel circuit 500 provided on the second chip 201 b and another circuit configuration 510 provided on the detection chip 202 are electrically joined to each other via a connection portion 502 penetrating from the second chip 201 b to the detection chip 202 .

[0220] Note that each of the connection portions 501 and 502 may include, for example, a TSV, a Cu-Cu bonding portion, a bump bonding portion, or the like.

[0221] 2.6 Example of cross-sectional structure of solid-state imaging device

[0222] Figure 8 : is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to the first embodiment. Note that Figure 8 A cross-sectional structure example of the solid-state imaging device 200 taken along a plane perpendicular to the light incident surface (light receiving surface) is depicted.

[0223] like Figure 8 As shown, the solid-state imaging device 200 has a structure in which a detection chip 202 is further fixed to a light receiving chip 201 having a stacked structure produced by fixing a first chip 201 a and a second chip 201 b .

[0224] For example, each of the bonding surface 610 between the first chip 201a and the second chip 201b and the bonding surface 620 between the light receiving chip 201 and the detection chip 202 may be a directly bonded surface. However, as described above, Cu-Cu bonding, bump bonding, etc. may be used instead of direct bonding.

[0225] For example, the first chip 201 a includes a semiconductor substrate 601 and an interlayer dielectric 608 .

[0226] The semiconductor substrate 601 includes a photoelectric conversion element 333 (light receiving unit 330) including an n-type semiconductor region 606 and a p-type semiconductor region 605 surrounding the n-type semiconductor region 606. The photoelectric conversion element 333 receives incident light entering from the back side of the semiconductor substrate 601 via the on-chip lens 602. A flattening film 603 for flattening the surface on which the on-chip lens 602 is mounted, a color filter not shown, or the like may be provided between the photoelectric conversion element 333 and the on-chip lens 602.

[0227] The n-type semiconductor region 606 is a charge accumulation region in which charges (electrons) generated by photoelectric conversion are accumulated. The impurity concentration on the side opposite to the light incident surface (upper surface side) in the p-type semiconductor region 605 surrounding the n-type semiconductor region 606 may be higher than the impurity concentration on the light incident surface side (lower surface side). Specifically, the photoelectric conversion element 333 may have a HAD (hole accumulation diode) structure, and the p-type semiconductor region 605 may be formed to reduce the generation of dark current in each interface on the lower surface side and the upper surface side of the n-type semiconductor region 606.

[0228] Pixel separation units 604 that electrically and optically separate the plurality of photoelectric conversion elements 333 are provided in a two-dimensional grid shape on the semiconductor substrate 601 as viewed from the back side. Each photoelectric conversion element 333 is provided in a rectangular region partitioned by the pixel separation unit 604.

[0229] In each photoelectric conversion element 333 , the anode is grounded, and the cathode includes a contact layer 607 from which charges generated in the photoelectric conversion element 333 are extracted.

[0230] The interlayer dielectric 608 is an insulator for electrical isolation between the first chip 201a and the second chip 201b, and is provided on the front surface side of the semiconductor substrate 601, that is, on the side bonded with the second chip 201b. For example, the bonding surface 610 of the interlayer dielectric 608 is flattened to directly bond to the second chip 201b.

[0231] For example, the second chip 201 b includes a semiconductor substrate 611 , an interlayer dielectric 612 , and a wiring layer 613 .

[0232] The semiconductor substrate 611 includes the LG transistor 411 and the amplifying transistor 412 constituting the upper pixel circuit 500. For example, the source of the LG transistor 411 and the gate of the amplifying transistor 412 are electrically connected to the contact layer 607 of the photoelectric conversion element 333 via TSV 501a, TSV 501b, TSV 501c, and wiring 501d. The TSV 501a penetrates from the upper surface of the interlayer dielectric 612 via the semiconductor substrate 611 and the interlayer dielectric 608 to the contact layer 607 formed on the semiconductor substrate 601, the TSV 501b penetrates from the upper surface of the interlayer dielectric 612 to the source of the LG transistor 411, the TSV 501c also penetrates from the upper surface of the interlayer dielectric 612 to the gate of the amplifying transistor 412, and the wiring 501d electrically connects the TSVs 501a, 501b, and 501c on the upper surface side of the interlayer dielectric 612. TSV 501a, TSV 501b, TSV 501c, and wiring 501d constitute Figure 4 The connecting portion 501 in.

[0233] For example, the wiring layer 613 includes an insulating layer and a multilayer wiring formed in the insulating layer. For example, the wiring is connected to the gate of the LG transistor 411 and the drain of the amplifying transistor 412.

[0234] Furthermore, the wiring layer 613 includes a pad (Cu pad) 619 made of copper (Cu) and exposed on a bonding surface 620 bonded to the detection chip 202. The Cu pad 619 is connected to the gate of the LG transistor 411 and the drain of the amplifying transistor 412 via wiring of the wiring layer 613.

[0235] For example, the detection chip 202 includes a semiconductor substrate 621 , an interlayer dielectric 622 , and a wiring layer 623 .

[0236] For example, as another circuit configuration 510 , the semiconductor substrate 621 includes a circuit element 511 including the constant current circuit 415 of the current-voltage conversion unit 410 , a circuit other than the address event detection unit 400 , the logic circuit 210 , and the like.

[0237] For example, similar to the wiring layer 613 of the second chip 201 b , the wiring layer 623 includes an insulating layer and multilayer wiring formed in the insulating layer. For example, the wiring is electrically connected to the circuit element 511 provided on the semiconductor substrate 621 .

[0238] Furthermore, the wiring layer 623 includes a Cu pad 629 exposed on the bonding surface 620 bonded to the second chip 201 b. The Cu pad 629 is connected to the circuit element 511 via the wiring of the wiring layer 623 .

[0239] The Cu pad 619 exposed on the surface of the wiring layer 613 of the second chip 201b and the Cu pad 629 exposed on the surface of the wiring layer 623 of the detection chip 202 constitute a Cu-Cu bonding portion that electrically and mechanically bonds the second chip 201b and the detection chip 202. Specifically, Figure 8 In the example shown, Figure 4 The connection portion 502 in FIG. 5 includes a Cu-Cu bonding portion.

[0240] 2.7 Layer Board Diagram Example

[0241] Next, examples of respective layer diagrams of the first chip 201 a and the second chip 201 b will be described.

[0242] 2.7.1 First Chip

[0243] Fig. 9 1 is a plan view illustrating an example of a layer diagram of a first chip according to the present embodiment. Fig. 9 As shown, the photoelectric conversion elements 333 of the light receiving unit 330 are arranged on the first chip 201a in a two-dimensional grid shape. For example, each photoelectric conversion element 333 is arranged in a rectangular area. In addition, each photoelectric conversion element 333 includes a contact layer 607 connected to the TSV 501a constituting the connection portion 501.

[0244] 2.7.2 Second Chip

[0245] 2.7.2.1 Source Follower Type

[0246] Fig.10 The current-to-voltage conversion unit 410 is a source follower type (see Figure 4 ) is a plan view of an example of a layer diagram of the second chip. Fig.10 As shown, upper pixel circuits 500 each including an LG transistor 411 and an amplifying transistor 412 are arranged in a two-dimensional grid shape on the second chip 201b. For example, each upper pixel circuit 500 is formed in an area substantially equivalent to the area of ​​each photoelectric conversion element 333 arranged on the first chip 201a.

[0247] For example, the LG transistor 411 in each upper pixel circuit 500 includes a gate 4111, a diffusion region 416 formed on the source side relative to the gate 4111, and a diffusion region 417 formed on the drain side relative to the gate 4111. In addition, for example, the amplification transistor 412 includes a gate 4121, a diffusion region 418 formed on the source side relative to the gate 4121, and a diffusion region 419 formed on the drain side relative to the gate 4121.

[0248] The TSV 501a constituting the connection portion 501 and the gate 4121 of the amplification transistor 412 are connected to the diffusion region 416 on the source side of the LG transistor 411. On the other hand, the power supply voltage VDD is connected to the diffusion region 417 on the drain side.

[0249] The ground voltage VSS is connected to the diffusion region 418 on the source side of the amplifying transistor 412. On the other hand, the gate 4111 of the LG transistor 411 is connected to the diffusion region 419 on the drain side.

[0250] 2.7.2.2 Gain Boost Type

[0251] Fig.11 The current-to-voltage conversion unit 410 is a gain-boost type (see Figure 6 ) is a plan view of an example of a layer diagram of the second chip. Fig.11 As shown, upper pixel circuits 500 each including LG transistors 411 and 413 and amplifying transistors 412 and 414 are arranged in a two-dimensional grid shape on the second chip 201b. For example, each upper pixel circuit 500 is formed in an area substantially equivalent to the area of ​​each photoelectric conversion element 333 arranged on the first chip 201a.

[0252] In each upper pixel circuit 500, the gate 4131 of the LG transistor 413 is set on the drain side of the LG transistor 411, and the gate 4141 of the amplifier transistor 414 is set on the drain side of the amplifier transistor 412, which is similar to the configuration of Fig.10 The arrangement of each upper pixel circuit 500 is shown.

[0253] The diffusion region 417 on the source side with respect to the gate 4131 of the LG transistor 413 is shared by the LG transistor 411. On the other hand, the power supply voltage VDD is connected to the diffusion region 4171 on the drain side instead of the diffusion region 417.

[0254] The amplifier transistor 412 shares the diffusion region 419 on the source side with respect to the gate 4141 of the amplifier transistor 414. On the other hand, the diffusion region 4191 on the drain side is connected to the gate 4131 of the LG transistor 413.

[0255] 2.8 Operation and Effect

[0256] According to the present embodiment, as described above, the photoelectric conversion element 333 of the light receiving unit 330 and the upper pixel circuit 500 are respectively provided on the semiconductor substrates 601 and 611, and the semiconductor substrates 601 and 611 are electrically separated from each other via the interlayer dielectric 608. This arrangement can reduce the dark current from the photoelectric conversion element 333 into each transistor constituting the upper pixel circuit 500. Therefore, the reduction of the degradation of the DVS noise characteristic can be achieved.

[0257] In addition, the arrangement in which the photoelectric conversion element 333 and the upper pixel circuit 500 are both arranged on different substrates can increase the proportion of the photoelectric conversion element 333 in the light receiving surface. In this case, the light receiving efficiency of the incident light can be improved. Therefore, the degradation of the DVS noise characteristics can be further reduced.

[0258] Furthermore, the arrangement in which the photoelectric conversion element 333 and the upper pixel circuit 500 are both provided on different substrates can ensure a sufficient area for each transistor constituting the upper pixel circuit 500. Therefore, by reducing the degradation of the noise characteristic of each transistor, the degradation of the DVS noise characteristic can be further reduced.

[0259] 3. Second embodiment

[0260] Next, a solid-state imaging device and an imaging apparatus according to a second embodiment will be described in detail with reference to the drawings.

[0261] 3.1 Improvement of transistor noise characteristics

[0262] As described above, the DVS noise characteristic deteriorates not only due to the dark current flowing from the photoelectric conversion element 333 into the upper pixel circuit 500, but also due to the deterioration of the noise characteristic of each transistor constituting the upper pixel circuit 500. Here, Fig.12 : represents the relationship between the noise and current of each transistor constituting the upper pixel circuit 500. Fig.12 In FIG. 1 , the horizontal axis represents the drain current of each transistor, and the vertical axis represents the noise component of each transistor.

[0263] like Fig.12 As shown, the noise of each transistor constituting the upper pixel circuit 500 increases in proportion to the amount of current. This indicates that the thermal noise S Vg The thermal noise S in the saturation region of the transistor dominates the noise characteristics of the transistor. Vg It can be expressed by the following equation (7). In equation (7), k is the Boltzmann coefficient, T is the absolute temperature, and gm is the transconductance.

[0264] [Mathematical formula 2]

[0265]

[0266] It is obvious from equation (7) that increasing the transconductance gm of the transistor reduces the thermal noise S in the saturation region of the transistor. Vg is effective. The transconductance gm of the transistor can be expressed by the following equation (8). In equation (8), W is the gate area of ​​the transistor.

[0267] [Mathematical formula 3]

[0268]

[0269] As is apparent from equation (8), in order to increase the transconductance gm of the transistor, there is a method of increasing the gate area W of the transistor. For example, in the first embodiment, by increasing the gate area of ​​the LG transistor 411 and the amplifying transistor 412 constituting the pixel circuit, it is possible to achieve the reduction of the thermal noise S of the LG transistor 411 and the amplifying transistor 412 by reducing the thermal noise S of the LG transistor 411 and the amplifying transistor 412. Vg To improve the noise characteristics.

[0270] In addition, there is the following method as another method of increasing the transconductance gm of the transistor.

[0271] 3.1.1 Using FDSOI (Fully Depleted Silicon on Insulator)

[0272] There is a method of using an FDSOI substrate as the semiconductor substrate 611 of the second chip 201 b constituting the upper pixel circuit 500 as a method of increasing the transistor transconductance gm.

[0273] Fig.13 is a cross-sectional view illustrating a schematic configuration example of a transistor formed on an FDSOI substrate. Fig.13 As shown, for example, the FDSOI substrate 701 includes a support substrate 704 (eg, a silicon substrate), an embedded oxide film 703 (eg, a silicon oxide film) located on the support substrate 704 , and a thin silicon film 702 located on the embedded oxide film 703 .

[0274] Each transistor 700 in the upper pixel circuit 500 (corresponding to the LG transistor 411 and the amplifying transistor 412 in the first embodiment, or the LG transistors 411 and 413 and the amplifying transistors 412 and 414) includes a source 707 and a drain 708 arranged on the silicon film 702 and a gate insulating film 706 and a gate 705 arranged in the area sandwiched between the source 707 and the drain 708 in the silicon film 702.

[0275] In such a configuration, the gate controllability of the transistor 700 can be enhanced by applying a reverse bias to the support substrate 704. Note that, for example, the reverse bias may be applied directly to the support substrate 704 from the back or side, or may be applied to a contact layer formed on the support substrate 704 and exposed to the bottom of the trench penetrating from the silicon thin film 702 to the embedded oxide film 703.

[0276] Fig.14 It is an example Fig.13 A graph showing the current-voltage characteristics of a transistor. Fig.14The solid line in φ represents the case where a voltage equivalent to the voltage applied to the gate 705 is applied as a reverse bias, and the dotted line represents the case where the supporting substrate 704 is grounded (no reverse bias).

[0277] like Fig.14 As shown, by applying a reverse bias to the transistor 700, the drain current doubles or more. This indicates that the transconductance gm of the transistor 700 is doubled or more improved by applying a reverse bias. Therefore, by using the FDSOI substrate 701 as the semiconductor substrate 611 of the second chip 201b, and applying a reverse bias to the LG transistor 411 and the amplifier transistor 412 formed on the FDSOI substrate 701, the thermal noise S Vg Can be reduced to 1 / 2 or lower.

[0278] 3.1.2 Use of Tunnel FET and Fin FET

[0279] In addition, the thermal noise S in the subthreshold region of the transistor Vg It can be expressed by the following equation (9). In equation (9), q is the elementary charge, S is the subthreshold coefficient, V d is the drain voltage.

[0280]

Mathematical formula 4

[0281]

[0282] It is obvious from equation (9) that reducing the subthreshold coefficient S of the transistor can reduce the thermal noise S in the subthreshold region of the transistor. Vg is effective.

[0283] Examples of transistors having a small subthreshold coefficient S include transistors having sharp on-off characteristics (subthreshold characteristics) caused by tunneling current, such as, by way of example, Fig.15 The tunnel FET 710 described in Fig.16 Fin FET 720 described in .

[0284] By using a transistor having a small subthreshold coefficient S for each transistor constituting the upper pixel circuit 500 as described above, it is possible to achieve a reduction in the thermal noise S of the transistor. Vg To improve the noise characteristics. For example, by using a transistor with a subthreshold coefficient S reduced to 1 / 2, the thermal noise S Vg Theoretically it can be reduced to 1 / 4.

[0285] 3.2 Operation and Effect

[0286] According to the present embodiment, as described above, transistors having a preferred transconductance gm or a subthreshold coefficient S can be used for transistors constituting the upper pixel circuit 500 to reduce thermal noise of the transistors. As a result, reduction in degradation of DVS noise characteristics can be achieved.

[0287] Note that other configurations, operations, and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0288] 4. Third embodiment

[0289] In the third embodiment, an example of a manufacturing process of the solid-state imaging device 200 according to the present disclosure will be described. Note that this embodiment presented by way of example is a case where the FDSOI substrate 701 presented by way of example in the second embodiment is used for the semiconductor substrate 611 of the second chip 201b. However, this embodiment is similarly applicable to solid-state imaging devices 200 having other configurations.

[0290] 4.1 Manufacturing process of solid-state imaging devices

[0291] Figures 17 to 28 1 and 2 are cross-sectional views each illustrating an example of a manufacturing process of a solid-state imaging device according to the third embodiment. In this manufacturing process, a pixel separation unit 604 having a grid shape is first provided on a p-type semiconductor substrate 601, wherein an acceptor is diffused into a separation region, and in each separation region, a corresponding photoelectric conversion element 333 is formed.

[0292] Subsequently, donor ions are implanted into each region separated by the pixel separation unit 604 from the front surface side of the semiconductor substrate 601 to form the photoelectric conversion element 333 including the p-type semiconductor region 605 and the n-type semiconductor region 606 .

[0293] Thereafter, donor ions are implanted into the front surface side of the semiconductor substrate 601 in such a manner as to reach the n-type semiconductor region 606 to form a contact layer 607 electrically connected to the n-type semiconductor region 606 .

[0294] Then, silicon oxide (SiO2) is deposited on the semiconductor substrate 601 by using, for example, a plasma CVD (Chemical Vapor Deposition) method to form an interlayer dielectric 608. Subsequently, the surface of the interlayer dielectric 608 is planarized using, for example, CMP (Chemical Mechanical Polishing).

[0295] Thereafter, a planarization film 603 and an on-chip lens 602 are provided on the back side of the semiconductor substrate 601. In this way, as Fig.17 As shown, a first chip 201 a before individualization is formed.

[0296] Then, if Fig.18As shown, the surface of the silicon oxide film 731 of the SOI substrate 701A (support substrate (e.g., silicon substrate) 704, embedded oxide film (e.g., silicon oxide film) 703 and silicon layer 702A) on which the silicon oxide film 731 is formed is fixed to the surface of the interlayer dielectric 608 of the first chip 201a to directly bond the SOI substrate 701A and the first chip 201a. Note that the surface of the silicon oxide film 731 is flattened by, for example, CMP.

[0297] Then, if Fig.19 As shown, the thickness of the silicon layer 702A of the SOI substrate 701A is reduced to form a silicon thin film 702 .

[0298] Afterwards, if Fig. 20 As shown, an element separation insulating film (also referred to as a channel stop layer) 732 is formed so as to reach the middle of the support substrate 704 from the silicon thin film 702. Note that each element separation insulating film 732 is formed not only in the region separating the LG transistor 411 and the amplifying transistor 412 of the upper pixel circuit 500, but also in the region where the reverse bias is applied in each of the LG transistor 411 and the amplifying transistor 412. Note that in the following description, the layer lower than the interlayer dielectric 608 of the first chip 201a is not shown in the figure.

[0299] Then, if Fig.21 As shown, a silicon oxide film 706A is formed on the surface of the silicon thin film 702 on which the element isolation insulating film 732 has been formed.

[0300] Then, if Fig. 22 As shown, a region to which a reverse bias is applied in a region separated by an element separation insulating film 732 is etched by, for example, RIE (Reactive Ion Etching) to form a groove 733 through which the support substrate 704 is exposed.

[0301] Afterwards, if Fig.23 As shown, the gate 705 (corresponding to the gate 4111 or 4121) of each transistor (411 and 412) is formed on the silicon oxide film 706A in the region separated by the element separation insulating film 732 and in which the LG transistor 411 and the amplification transistor 412 are formed.

[0302] Then, if Fig.24 As shown, for example, the surface of the FDSOI substrate 701 on which the gate 705 is formed is etched back to remove the exposed silicon oxide film 706A and to form a gate insulating film 706 under the gate 705. Thereafter, as shown in FIG. Fig.25As shown, using the gate 705 and the element separation insulating film 732 as masks, predetermined dopant ions are implanted into the surface of the FDSOI substrate 701, for example, to form a source 707 and a drain 708, with an area included in the silicon thin film 702 and located below the gate 705 sandwiched between the source 707 and the drain 708, and a contact layer 734 is formed, and a reverse bias is applied in the area included in the supporting substrate 704 and exposed by the groove 733.

[0303] Then, if Fig.26 As shown, for example, silicon nitride (SiN) is deposited on the FDSOI substrate 701 using a plasma CVD method to form the interlayer dielectric 612 .

[0304] Then, if Fig. 27 As shown, a through hole through which the gate 705 and the contact layer 734 are exposed is formed in the interlayer dielectric 612, and a through hole is formed that penetrates the interlayer dielectric 612, the FDSOI substrate 701, the silicon oxide film 731, and the interlayer dielectric 608 and is formed as a hole through which the contact layer 607 is exposed. TSV 501a connected to the contact layer 607, TSV 501c connected to the gate 705, and TSV 736 connected to the contact layer 734 are formed in the corresponding through holes thus formed. Note that TSV 501b connected to the source of the LG transistor 411 is similarly formed, but is not shown in the figure.

[0305] Afterwards, if Fig.28 As shown, wiring 501d connecting TSV 501a, TSV 501b and TSV 501c is formed on the interlayer dielectric 612, and wiring 737 connecting TSV 736 to a predetermined wiring is formed. In this way, the upper pixel circuit 500 including the LG transistor 411 and the amplification transistor 412 is formed on the FDSOI substrate 701.

[0306] Then, the wiring layer 613 is formed on the FDSOI substrate 701, and the Cu pads 619 of the wiring layer 613 and the Cu pads 629 of the wiring layer 623 of the detection chip 202 are bonded to each other (Cu-Cu bonding) to manufacture the solid-state imaging device 200 according to the present embodiment (see Figure 8 ). Note that the detection chip 202 is produced separately.

[0307] 4.2 Operation and Effect

[0308] As described above, according to the present embodiment, a solid-state imaging device 200 can be manufactured, which includes a photoelectric conversion element 333 of a light receiving unit 330 and an upper pixel circuit 500, which are respectively arranged on a semiconductor substrate 601 and a FDSOI substrate 701 (or a semiconductor substrate 611 that can replace the FDSOI substrate 701), which are different substrates and are electrically separated from each other via an interlayer dielectric 608.

[0309] Note that other configurations, operations, and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0310] 5. Fourth embodiment

[0311] According to the fourth embodiment, in the solid-state imaging device 200 of the above embodiment, an overflow gate (OFG) is provided between the photoelectric conversion element 333 and the address event detection unit 400. The solid-state imaging device and the imaging apparatus according to the fourth embodiment will be described in detail with reference to the drawings.

[0312] In this embodiment, the configuration and operation of the imaging device and the solid-state imaging device may be similar to the configuration and operation of the above-described embodiment. However, in this embodiment, the light receiving unit 330 of the unit pixel 310 is Fig.29 The light receiving unit 730 is shown instead.

[0313] 5.1 Example of unit pixel configuration

[0314] Fig.29 is a circuit diagram illustrating a schematic configuration example of a unit pixel according to the present embodiment. Fig.29 As shown, in the unit pixel 310 according to this embodiment, the light receiving unit 330 (see Figure 4 and other figures) Fig.29 The light receiving unit 730 is shown instead.

[0315] The light receiving unit 730 includes an OFG (Overflow Gate) transistor 332 and a photoelectric conversion element 333. For example, the OFG transistor 332 may include an N-type MOS transistor (hereinafter referred to as an NMOS transistor).

[0316] The source of the OFG transistor 332 is connected to the cathode of the photoelectric conversion element 333, and the drain of the OFG transistor 332 is connected to the address event detection unit 400 via the connection portion 501. In addition, a control signal OFG for controlling the transfer of the charge generated in the photoelectric conversion element 333 to the address event detection unit 400 is applied from the drive circuit 211 to the gate of the OFG transistor 332.

[0317] 5.2 Example of a cross-sectional structure of a solid-state imaging device

[0318] Fig.30 : is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to the present embodiment. Note that Fig.30 Describes something like Figure 8 An example of a cross-sectional structure of the solid-state imaging device 200 taken along a plane perpendicular to the light incident surface (light receiving surface).

[0319] like Fig.30 As shown, for example, the solid-state imaging device 200 includes an OFG transistor 332 disposed on a semiconductor substrate 601 of a first chip 201a in a stacked structure and a cross-sectional structure similar to that of the example Figure 8 The stacked structure and cross-sectional structure of the solid-state imaging device 200 are shown.

[0320] Therefore, according to the present embodiment, in addition to the n-type semiconductor region 606 for the photoelectric conversion element 333, the n-type semiconductor region 3322 that becomes the drain of the OFG transistor 332 is provided on the semiconductor substrate 601. For example, the n-type semiconductor region 606 and the n-type semiconductor region 3322 are electrically separated from each other via the p-type semiconductor region 715. The TSV 501a of the connection portion 501 is electrically connected to the n-type semiconductor region 3322 via the contact layer 607.

[0321] In addition, the gate 3321 of the OFG transistor 332 is also provided on the semiconductor substrate 601. The gate 3321 reaches the middle of the n-type semiconductor region 606 from the n-type semiconductor region 3322 via the p-type semiconductor region 715. Therefore, by applying a high-level control signal OFG to the gate 3321, the charge accumulated in the n-type semiconductor region 606 of the photoelectric conversion element 333 begins to flow into the second chip 201b via the OFG transistor 332 and the TSV 501a.

[0322] 5.3 Layer Diagram Example

[0323] In addition, the example of the layer diagram of the second chip 201b according to this embodiment can be similar to that of the reference Fig.10 or Fig.11 The example of the layer diagram explained in the first embodiment. On the other hand, the example of the layer diagram of the first chip 201a is Fig.31 The example plywood diagram shown is used instead.

[0324] like Fig.31 As shown, according to the example of the layer diagram of the first chip 201a of this embodiment, the gate 3321 of the OFG transistor 332 is similar to Fig. 9 The layout of the illustrated layer diagram example is provided between the photoelectric conversion element 333 and the contact layer 607 .

[0325] 5.4 Operation and Effect

[0326] According to the present embodiment, as described above, the OFG transistor 332 for controlling the readout of the charge from the photoelectric conversion element 333 is provided between the photoelectric conversion element 333 and the address event detection unit 400. In addition, the OFG transistor 332 is provided on the same first chip 201a as the photoelectric conversion element 333. According to the present embodiment, this configuration realizes the readout of the charge from the photoelectric conversion element 333 at a necessary time.

[0327] Note that other configurations, operations, and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0328] 6. Fifth embodiment

[0329] Next, an imaging apparatus and a solid-state imaging device according to a fifth embodiment will be described in detail with reference to the drawings.

[0330] According to the above-described embodiment, the upper pixel circuit 500 provided on the second chip 201b is a part of the transistors (LG transistor 411 (or LG transistors 411 and 413) and amplifying transistor 412 (or amplifying transistors 412 and 414)) of the current-voltage conversion unit 410 in the address event detection unit 400. However, the upper pixel circuit 500 provided on the second chip 201b is not limited to a circuit including these circuit elements. For example, Fig.32 As shown, by way of example, the entire address event detection unit 400 may be disposed on the second chip 201b. Fig.33 As shown, by way of example, in addition to the entire address event detection unit 400 , the driving circuit 211 of the logic circuit 210 may be disposed on the second chip 201 b .

[0331] As described above, the configuration provided on the second chip 201b can be modified in various ways. Even in this case, the photoelectric conversion element 333 of the light receiving unit 330 and the circuit element provided on the second chip 201b are respectively provided on the semiconductor substrates 601 and 611, which are different substrates electrically separated from each other via the interlayer dielectric 608. Therefore, the degradation of the DVS noise characteristic can be reduced by reducing the entry of the dark current from the photoelectric conversion element 333.

[0332] Notice, Fig.32 and 33 The examples are based on the reference Fig.29 The case of the solid-state imaging device 200 described in the fourth embodiment. However, the present embodiment is not limited to this example, and may be based on the case of the solid-state imaging device 200 according to other embodiments, for example, Figure 4 A solid-state imaging device 200 is depicted by way of example in FIG.

[0333] In addition, other configurations, operations and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0334] 7. Sixth embodiment

[0335] Next, an imaging apparatus and a solid-state imaging device according to a sixth embodiment will be described in detail with reference to the drawings.

[0336] 7.1 Examples of stacked structures of solid-state imaging devices

[0337] According to the above-described embodiment, the light receiving chip 201 has a two-layer configuration including the first chip 201a and the second chip 201b, and the detection chip 202 is fixed to the configuration to constitute the solid-state imaging device 200 having a three-layer stacked structure (see Figure 2 ). However, the number of stacked layers is not limited to three. Fig.34 As shown, by way of example, a four-layer stacking structure may be adopted, in which a logic chip 203 is stacked in addition to the light receiving chip 201 and the detection chip 202 of the double-layer structure.

[0338] 7.2 Example of unit pixel configuration

[0339] Fig.35 2 is a circuit diagram illustrating a schematic configuration example of a unit pixel in the case where the solid-state imaging device has a four-layer stacked structure. Fig.35 In the case of the four-layer stacked structure shown, for example, the logic circuit 210 such as the drive circuit 211, the signal processing unit 212 and the arbiter 213 is allowed to be set on the logic chip 203 at the bottom layer (the fourth layer). However, this configuration is not required, but can be modified in various ways. For example, a portion of the logic circuit 210 (for example, the drive circuit 211) can be set on the second chip 201b or the detection chip 202, and the remaining circuits can be set on the logic chip 203. Alternatively, a portion of the address event detection unit 400 can be set on the logic chip 203.

[0340] As described above, by adopting a four-layer stacked structure, a larger area can be allocated to the transistors constituting the pixel circuit. Therefore, by further reducing the thermal noise of the transistors, the DVS noise characteristics can be further improved.

[0341] Notice, Fig.35 The example describes the Fig.29The case of the solid-state imaging device 200 described in the fourth embodiment. However, the present embodiment is not limited to this example, but can be applied to the case based on the solid-state imaging device 200 according to other embodiments, for example, by way of example Figure 4 A solid-state imaging device 200 is depicted in FIG.

[0342] In addition, other configurations, operations and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0343] 8. Seventh embodiment

[0344] Next, an imaging apparatus and a solid-state imaging device according to a seventh embodiment will be described in detail with reference to the drawings.

[0345] 8.1 Example of Cross-Section Structure of Solid-State Imaging Device

[0346] Fig.36 1 is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to the present embodiment. Fig.36 As shown, for example, the solid-state imaging device 200 has a structure in which a hydrogen supply film 751 is added to the wiring layer 613 of the second chip 201b and a hydrogen diffusion prevention film 752 is added between the first chip 201a and the second chip 201b, and its cross-sectional structure is similar to that of the reference Fig.30 Cross-sectional structure of the solid-state imaging device 200 described in the fourth embodiment. Note that each of the wiring layers 613 and 623 and the interlayer dielectrics 612 and 622 includes a silicon nitride film.

[0347] For example, the hydrogen supply film 751 may include a silicon nitride film (hereinafter referred to as a plasma SiN film) having a large hydrogen content and formed by a plasma CVD method or the like. As described above, a plasma SiN film (hydrogen supply film 751) having a large hydrogen content is provided near the interface between the layers, each of which includes a silicon nitride film (wiring layers 613 and 623 and interlayer dielectrics 612 and 622). In this case, mesh defects generated at the interface by hydrogen atoms diffused from the plasma SiN film can be repaired. In this way, the noise characteristics of the circuit elements constituting the pixel circuit are improved. As a result, improvement in DVS noise characteristics can be achieved.

[0348] Meanwhile, for example, the hydrogen diffusion prevention film 752 may include a silicon nitride film (hereinafter referred to as LP-SiN film) having a small hydrogen content and formed by low-pressure plasma CVD or the like. As described above, by providing the LP-SiN film (hydrogen diffusion prevention film 752) having a low hydrogen content between the pixel circuit and the photoelectric conversion element 333, diffusion of hydrogen atoms from the pixel circuit to the photoelectric conversion element 333 can be reduced. In this way, a reduction in quantum efficiency caused by binning between pixels can be reduced.

[0349] Notice, Fig.36 The example describes the Fig.30 The case of the solid-state imaging device 200 described in the fourth embodiment. However, the present embodiment is not limited to this example, but may be based on the case of the solid-state imaging device 200 according to other embodiments, for example, Figure 8 A solid-state imaging device 200 is depicted in FIG.

[0350] In addition, other configurations, operations and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0351] 9. Eighth Embodiment

[0352] Next, a solid-state imaging device and an imaging apparatus according to an eighth embodiment will be described in detail with reference to the drawings.

[0353] In the above embodiment, an example of a configuration for detecting an address event trigger has been mainly described. However, according to the present embodiment, in addition to the configuration for detecting an address event trigger, an example of a configuration for reading a pixel signal from a unit pixel corresponding to a detected address event trigger will be described.

[0354] Note that the schematic configuration and stacking structure of the imaging device according to the present embodiment may be similar to that described in reference to, for example, Figure 1 and Figure 2 The schematic configuration example and stack structure example of the imaging device 100 are described in the first embodiment. Therefore, detailed description of these is omitted.

[0355] 9.1 Functional Configuration Example of Solid-State Imaging Device

[0356] Fig.37 1 is a block diagram illustrating an example of a functional configuration of a solid-state imaging device according to an eighth embodiment. Fig.37 As shown, except for Figure 3 The solid-state imaging device 200 further includes a column ADC 220 in addition to a configuration similar to that of the illustrated solid-state imaging device 200 .

[0357] The driving circuit 211 sequentially drives the unit pixels 810 that have output detection signals according to a predetermined response from the arbitrator 213, so that the unit pixels 810 triggered by the detected address event output analog pixel signals corresponding to the received light amount to the signal processing unit 212, for example.

[0358] The column ADC 220 converts the analog pixel signal received from each column of the unit pixel 810 into a digital signal. Thereafter, the column ADC 220 provides the digital pixel signal generated by the conversion to the signal processing unit 212.

[0359] The signal processing unit 212 performs predetermined signal processing, such as CDS (Correlated Double Sampling) processing (noise removal) and white balance adjustment, on the pixel signal received from the column ADC 220. Then, the signal processing unit 212 supplies the result of the signal processing and the detection signal of the address event to the recording unit 120 via the signal line 209.

[0360] 9.1.1 Configuration Example of Column ADC

[0361] Fig.38 1 is a block diagram illustrating a schematic configuration example of a column ADC according to the present embodiment. Fig.38 As shown, the column ADC 220 includes a plurality of ADCs 230 provided for each column of the unit pixel 810 .

[0362] Each ADC 230 converts the analog pixel signal acquired in the vertical signal line VSL into a digital signal. For example, the ADC 230 converts the analog pixel signal into a digital signal having a larger number of bits than the detection signal. Thereafter, the ADC 230 provides the generated digital signal to the signal processing unit 212.

[0363] 9.2 Example of unit pixel configuration

[0364] Next, a configuration example of a unit pixel according to the present embodiment will be described. Fig.39 is a circuit diagram illustrating a schematic configuration example of a unit pixel according to the present embodiment. Fig.39 As shown, for example, the unit pixel 810 includes a light receiving unit 830 instead of the light receiving unit 730, and also includes a pixel signal generating unit 320, which is configured similarly to that of the example. Fig.29 The configuration of the unit pixel 310 is shown.

[0365] In addition to Fig.29 In addition to a configuration similar to that of the light receiving unit 730 in FIG. 8 , the light receiving unit 830 further includes a transfer transistor 331. Similar to the OFG transistor 332, the source of the transfer transistor 331 is connected to the cathode of the photoelectric conversion element 333, and the drain of the transfer transistor 331 is connected to the pixel signal generating unit 320 via the connection portion 801. Note that, for example, similar to the connection portion 501, the connection portion 801 may be a TSV, a Cu-Cu bonding portion, a bump bonding portion, or the like penetrating from the first chip 201a to the second chip 201b.

[0366] For example, the pixel signal generating unit 320 includes a reset transistor 321 , an amplifying transistor 322 , a selecting transistor 323 , and a floating diffusion layer (floating diffusion: FD) 324 .

[0367] For example, each of the transfer transistor 331 and the OFG transistor 332 of the light receiving unit 830 may include an NMOS transistor. Similarly, for example, each of the reset transistor 321, the amplification transistor 322, and the selection transistor 323 of the pixel signal generating unit 320 may include an NMOS transistor.

[0368] The transfer transistor 331 transfers the charge generated in the photoelectric conversion element 333 to the floating diffusion layer 324 according to the control signal TRG from the drive circuit 211. The OFG transistor 332 supplies an electric signal (photocurrent) based on the charge generated in the photoelectric conversion element 333 to the address event detection unit 400 according to the control signal OFG from the drive circuit 211.

[0369] The floating diffusion layer 324 accumulates the charge transferred from the photoelectric conversion element 333 via the transfer transistor 331. The reset transistor 321 releases (initializes) the charge accumulated in the floating diffusion layer 324 according to the reset signal from the drive circuit 211. The amplifier transistor 322 acquires a pixel signal in the vertical signal line VSL, the pixel signal indicating a voltage value corresponding to the charge amount of the charge accumulated in the floating diffusion layer 324. The selection transistor 323 switches the connection between the amplifier transistor 322 and the vertical signal line VSL according to the selection signal SEL from the drive circuit 211. Note that the analog pixel signal acquired in the vertical signal line VSL is read by the column ADC 220 and converted into a digital pixel signal.

[0370] In response to the instruction of the start of address event detection of the control unit 130, the driving circuit 211 of the logic circuit 210 outputs a control signal OFG for turning on the OFG transistors 332 of all the light receiving units 830 included in the pixel array unit 300. As a result, the photocurrent generated in the corresponding photoelectric conversion element 333 of the light receiving unit 830 is provided to the address event detection unit 400 of each unit pixel 810 via the OFG transistor 332.

[0371] When an address event trigger is detected based on the photocurrent from the light receiving unit 830, the address event detection unit 400 of each unit pixel 810 outputs a request to the arbiter 213. In response to the request, the arbiter 213 arbitrates the requests from the respective unit pixels 810, and based on the result of the arbitration, sends a predetermined response to each unit pixel 810 that has issued the request. Each unit pixel 810 that has received the request provides a detection signal indicating the presence or absence of an address event trigger to the drive circuit 211 and the signal processing unit 212 of the logic circuit 210.

[0372] The driving circuit 211 causes the OFG transistor 332 of the unit pixel 810 as a supplier of the detection signal to enter an off state. As a result, the supply of the photocurrent from the light receiving unit 830 to the address event detection unit 400 in the unit pixel 810 is stopped.

[0373] Subsequently, the drive circuit 211 brings the transfer transistor 331 in the light receiving unit 830 of the unit pixel 810 into a conductive state according to the control signal TRG. As a result, the charge generated in the photoelectric conversion element 333 of the light receiving unit 830 is transferred to the floating diffusion layer 324 via the transfer transistor 331. Thereafter, a pixel signal indicating a voltage value corresponding to the charge amount of the charge accumulated in the floating diffusion layer 324 is acquired in the vertical signal line VSL connected to the selection transistor 323 of the pixel signal generating unit 320.

[0374] As described above, the solid-state imaging device 200 outputs the pixel signal from the unit pixel 810 corresponding to the detected address event trigger to the column ADC 220 .

[0375] According to such a configuration, similar to the above-described embodiment, the upper pixel circuit 500 provided on the second chip 201b may include the LG transistor 411 and the amplifying transistor 412 (or the LG transistors 411 and 413 and the amplifying transistors 412 and 414) in the current-voltage conversion unit 410 of the address event detection unit 400. In addition, in the present embodiment, for example, the upper pixel circuit 500 may further include a reset transistor 321, an amplifying transistor 322, and a selection transistor 323 constituting the pixel signal generation unit 320. Note that the floating diffusion layer 324 includes a wiring extending from the cathode of the photoelectric conversion element 333 to the source of the reset transistor 321 and the gate of the amplifying transistor 322 via the connecting portion 801. In addition, in the following description, the transistors (the LG transistor 411 and the amplifying transistor 412 or the LG transistors 411 and 413 and the amplifying transistors 412 and 414) of the current-voltage conversion unit 410 included in the upper pixel circuit 500 will be referred to as the upper detection circuit 410A.

[0376] 9.3 Operation Examples of Solid-State Imaging Devices

[0377] Next, the operation of the solid-state imaging device 800 according to the present embodiment will be described with reference to the drawings.

[0378] 9.3.1 Time Diagram

[0379] First, an example of the operation of the solid-state imaging device 800 will be described with reference to a timing chart. Fig.40 is a timing chart showing an operation example of the solid-state imaging device according to the present embodiment.

[0380] like Fig.40As shown, when the control unit 130 instructs the start of detection of an address event at time T0, the drive circuit 211 raises the control signal OFG applied to the gates of the OFG transistors 332 of all the light receiving units 830 in the pixel array unit 300 to a high level. As a result, the OFG transistors 332 of all the light receiving units 830 enter a conductive state, and photocurrents based on the charges generated in the photoelectric conversion elements 333 of the respective light receiving units 830 are supplied from the respective light receiving units 830 to the respective address event detection units 400.

[0381] Furthermore, during the high level period of the control signal OFG, all control signals TRG applied to the gates of the transmission transistors 331 in the respective light receiving cells 830 are kept at a low level. Therefore, during this period, the transmission transistors 331 of all the light receiving cells 830 are in an off state.

[0382] Next, a case is assumed in which the address event detection unit 400 of one of the unit pixels 810 detects an address event trigger during a high level period of the control signal OFG. In this case, the address event detection unit 400 that has detected the address event trigger sends a request to the arbitrator 213. In response to the request, the arbitrator 213 arbitrates the request and then returns a response to the request to the address event detection unit 400 that has issued the request.

[0383] For example, the address event detection unit 400 having received the response raises the detection signal input to the driving circuit 211 and the signal processing unit 212 to a high level during the period of time T1 to T2. In this explanation, it is assumed that the detection signal is a one-bit signal indicating a conduction event detection result.

[0384] The driving circuit 211 having received the high level detection signal from the address event detection unit 400 at time T1 lowers all control signals OFG to low level at next time T2. As a result, the supply of photocurrent from all light receiving units 830 of the pixel array unit 300 to the address event detection unit 400 is stopped.

[0385] In addition, the drive circuit 211 raises the selection signal SEL applied to the gate of the selection transistor 323 of the pixel signal generating unit 320 in the unit pixel 810 (hereinafter referred to as the readout target unit pixel) triggered by the detected address event to a high level at time T2, and also raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel signal generating unit 320 to a high level for a fixed pulse period. As a result, the charge accumulated in the floating diffusion layer 324 of the pixel signal generating unit 320 is released, and the floating diffusion layer 324 is reset (initialized). In this way, the voltage acquired in the vertical signal line VSL in the initialized state of the floating diffusion layer 324 is read by the ADC 230 included in the column ADC 220 and connected to the vertical signal VSL as a pixel signal of a reset level (hereinafter referred to as a reset level), and is converted into a digital signal.

[0386] At time T3 after the reset level is read out, the drive circuit 211 then applies a control signal TRG of a fixed pulse period to the gate of the transfer transistor 331 of the light receiving unit 830 in the readout target unit pixel 810. As a result, the charge generated in the photoelectric conversion element 333 of the light receiving unit 830 is transferred to the floating diffusion layer 324 of the pixel signal generating unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 is acquired in the vertical signal line VSL. In this way, the voltage acquired in the vertical signal line VSL is read by the ADC 230 included in the column ADC 220 and connected to the vertical signal VSL as a pixel signal of a signal level (hereinafter referred to as a signal level) of the light receiving unit 830, and is converted into a digital value.

[0387] The signal processing unit 212 performs CDS processing for obtaining the difference between the reset level and the signal level read in the aforementioned manner as a net pixel signal corresponding to the light reception amount of the photoelectric conversion element 333 .

[0388] Thereafter, the driving circuit 211 lowers the selection signal SEL applied to the gate of the selection transistor 323 of the pixel signal generating unit 320 of the readout target unit pixel 810 to a low level at time T4, and also raises the control signal OFG applied to the gate of the OFG transistor 332 of all the light receiving units 830 to a high level. As a result, the detection of the address event trigger of all the light receiving units 830 is restarted.

[0389] 9.3.2 Flowchart

[0390] Next, an example of the operation of the solid-state imaging device 800 will be described with reference to a flowchart. Fig.411 is a flowchart showing an operation example of the solid-state imaging device according to the present embodiment. For example, when a predetermined application for detecting an address event is executed, the operation starts.

[0391] like Fig.10 As shown, each unit pixel 810 in the pixel array unit 300 first detects the presence or absence of an address event trigger in the current operation (step S101). Then, the driving circuit 211 determines whether an address event trigger has been detected in any unit pixel 810 (step S102).

[0392] In the case where the address event trigger is not detected (No in step S102), the current operation proceeds to step S104. On the other hand, in the case where the address event trigger is detected (Yes in step S102), the driving circuit 211 reads the pixel signal from the unit pixel 810 corresponding to the detected address event trigger (step S103), and the process proceeds to step S104.

[0393] In step S104, it is determined whether to end the current operation. In the case where the current operation is not ended (No in step S104), the current operation returns to step S101, and this step and subsequent steps are repeated. On the other hand, in the case where the current operation is about to end (Yes in step S104), the current operation ends.

[0394] 9.4 Example of Cross-Section Structure of Solid-State Imaging Device

[0395] Fig.42 : is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to the present embodiment. Note that Fig.42 Depicting, for example, Fig.30 A cross-sectional configuration example of the solid-state imaging device 800 taken along a plane perpendicular to the light incident surface (light receiving surface).

[0396] like Fig.42 As shown, for example, the solid-state imaging device 800 includes a transfer transistor 331 disposed on a semiconductor substrate 601 of a first chip 201a in a stacked structure and a cross-sectional structure similar to that of the example Fig.29 The stacked structure and cross-sectional structure of the solid-state imaging device 200 are shown.

[0397] Therefore, according to the present embodiment, the semiconductor substrate 601 includes the gate 3311 of the transfer transistor 331, the n-type semiconductor region 3312 as the drain of the transfer transistor 331, and the contact layer 807 for extracting the charge generated in the photoelectric conversion element 333 via the transfer transistor 331. For example, similar to the electrical separation between the n-type semiconductor region 606 and the n-type semiconductor region 3322, electrical separation is performed between the n-type semiconductor region 606 and the n-type semiconductor region 3312 by the p-type semiconductor region 715.

[0398] For example, the contact layer 807 is electrically connected to the source of the reset transistor 321 via a TSV 801a that passes through the semiconductor substrate 611 and the interlayer dielectric 608 from the upper surface of the interlayer dielectric 612 to the contact layer 807 formed on the semiconductor substrate 601, a TSV 801b that penetrates from the upper surface of the interlayer dielectric 612 to the source of the reset transistor 321, and a wiring 801d that electrically connects the TSVs 801a and 501b on the upper surface side of the interlayer dielectric 612. In addition, the contact layer 807 is connected to the gate (not shown) of the amplifier transistor 322 via a TSV 801c that penetrates from the upper surface of the interlayer dielectric 612 to the gate of the amplifier transistor 412, which is not shown, and a wiring 801d. The TSV 801a, the TSV 801b, the TSV 801c, and the wiring 801d constitute Fig.39 The connecting part 801 in.

[0399] The gate 3311 of the transfer transistor 331 reaches the middle of the n-type semiconductor region 606 from the n-type semiconductor region 3312 via the p-type semiconductor region 715. Therefore, according to the high-level control signal TRG applied to the gate 3311, the charge accumulated in the n-type semiconductor region 606 of the photoelectric conversion element 333 begins to flow into the second chip 201b via the transfer transistor 331 and the TSV 801a.

[0400] 9.5 Layer Diagram Example

[0401] Next, an example of a layer diagram of the first chip 201 a and the second chip 201 b according to the present embodiment will be described.

[0402] 9.5.1 First Chip

[0403] Fig.43 1 is a plan view illustrating an example of a layer diagram of a first chip according to the present embodiment. Fig.43 As shown, according to an example of a layer diagram of the first chip 201a of this embodiment, it is similar to Fig.31In the layout of the example of the layer diagram shown, the gate 3311 of the transfer transistor 331 and the contact layer 807 are provided at a corner opposite to the corner where the gate 3321 of the OFG transistor 332 and the contact layer 607 are provided with respect to the photoelectric conversion element 333 .

[0404] 9.5.2 Second Chip

[0405] Fig.44 1 is a plan view illustrating an example of a layer diagram of a second chip according to the present embodiment. Fig.44 An example of a source follower type current-to-voltage conversion unit 410 is depicted (see Figure 4 ), but other types may also be used. For example, the current-to-voltage conversion unit 410 is similarly applicable to a gain-boost type (see Figure 6 ).

[0406] like Fig.44 As shown, the second chip 201b includes an upper pixel circuit 500 arranged in a two-dimensional grid shape. The upper pixel circuit 500 includes an upper detection circuit 410A including an LG transistor 411 and an amplifying transistor 412, and a pixel signal generating unit 320 including a reset transistor 321, an amplifying transistor 322, a selecting transistor 323 and a floating diffusion layer 324. For example, each upper pixel circuit 500 is formed in an area substantially equivalent to the area of ​​each photoelectric conversion element 333 provided on the first chip 201a. Note that the upper detection circuit 410A may be similar to the upper pixel circuit 500 in the above-described embodiment.

[0407] For example, the reset transistor 321 in each pixel signal generating unit 320 includes a gate 3211, a diffusion region 325 formed on the source side relative to the gate 3211, and a diffusion region 326 formed on the drain side relative to the gate 3211. For example, the diffusion region 325 on the source side is connected to the TSV 801a constituting the connection portion 801. The diffusion region 326 on the drain side is connected to the power supply voltage VDD.

[0408] For example, the amplifying transistor 322 includes a gate 3221 and a diffusion region 327 formed on the drain side relative to the gate 3221. A diffusion region 326 on the source side relative to the gate 3221 is shared by the reset transistor 321. The gate 3221 is connected to a diffusion region 325 on the source side of the reset transistor 321 and is connected to the TSV 801a. A wiring 3241 connecting the gate 3221 with the diffusion region 325 of the reset transistor 321 and the TSV 801a serves as a floating diffusion layer 324.

[0409] For example, the selection transistor 323 includes a gate 3231 and a diffusion region 328 formed on the drain side relative to the gate 3231. A diffusion region 327 on the source side relative to the gate 3231 is shared by the amplification transistor 322. A vertical signal line VSL is connected to the diffusion region 328 on the drain side.

[0410] 9.6 Operation and Effect

[0411] As described above, even in the case where the pixel signal generating unit 320 for reading the pixel signal from the unit pixel 810 is provided in addition to the address event detecting unit 400 for detecting the address event trigger, by providing the pixel signal generating unit 320 on the second chip 201b or on a chip in a layer lower than the second chip 201b, it is possible to reduce the dark current flowing from the photoelectric conversion element 333 into each transistor constituting the pixel signal generating unit 320. Therefore, it is possible to achieve reduction in degradation of the DVS noise characteristic.

[0412] Note that in this embodiment, the case based on the solid-state imaging device 200 according to the fourth embodiment is presented by way of example. However, this embodiment is not limited to this example, but may be based on the case of the solid-state imaging device 200 according to other embodiments, for example, the solid-state imaging device 200 according to the first embodiment.

[0413] In addition, other configurations, operations and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0414] 10. Ninth Embodiment

[0415] Next, a solid-state imaging device and an imaging apparatus according to a ninth embodiment will be described in detail with reference to the drawings.

[0416] Although the pixel signal generating unit 320 is provided on the second chip 201b in the eighth embodiment, the layer where the pixel signal generating unit 320 is provided is not limited to the second chip 201b. For example, the third chip 201c may be added to the light receiving chip 201, such as Fig.45 As shown, the pixel signal generating unit 320 may be disposed on the third chip 201c, as shown in FIG. Fig.46 shown.

[0417] 10.1 Example of Cross-Sectional Structure of Solid-State Imaging Device

[0418] Fig.47 : is a cross-sectional view illustrating an example of a cross-sectional structure of a solid-state imaging device according to the present embodiment. Note that Fig.47 Depicting, for example, Fig.42An example of a cross-sectional structure of the solid-state imaging device 800 taken along a plane perpendicular to the light incident surface (light receiving surface).

[0419] like Fig.47 As shown, for example, the solid-state imaging device 800 according to the present embodiment includes a third chip including a semiconductor substrate 821, an interlayer dielectric 822, a wiring layer 613, and an interlayer insulating film 811, and is similar to the reference Fig.42 The cross-sectional structure of the solid-state imaging device 800 described in the eighth embodiment is provided between the second chip 201 b and the detection chip 202 .

[0420] According to this layer structure, the pixel signal generating unit 320 (for example, the reset transistor 321) is provided on the semiconductor substrate 821. In addition, the TSV 801a in the connection portion 801 connecting the source of the reset transistor 321 and the gate of the amplification transistor 322 and the drain of the transfer transistor 331 passes from the upper surface of the interlayer dielectric 822 through the semiconductor substrate 821, the interlayer insulating film 811, the semiconductor substrate 611 and the interlayer dielectric 608 to reach the contact layer 807 formed on the semiconductor substrate 601 to be connected to the contact layer 807.

[0421] Note that the interlayer insulating film 811 between the second chip 201 b and the third chip 201 c does not need to be provided on the third chip 201 c side, but may be provided on the second chip 201 b side.

[0422] 10.2 Operation and Effect

[0423] As described above, by increasing the chip (e.g., the third chip 201c) in which the upper pixel circuit 500 is provided, it is allowed to increase the area allocated to each transistor constituting the upper pixel circuit 500. In this way, a sufficient area can be ensured for each transistor constituting the upper pixel circuit 500. Therefore, by reducing the degradation of the noise characteristic of each transistor, the degradation of the DVS noise characteristic can be further reduced.

[0424] Note that in this embodiment, the case based on the solid-state imaging device 800 according to the eighth embodiment is presented by way of example. However, this embodiment is not limited to this example, but may be based on the case of the solid-state imaging device 200 according to other embodiments, for example, the solid-state imaging device 200 according to the first embodiment.

[0425] In addition, other configurations, operations and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0426] 11. Tenth Embodiment

[0427] Next, a solid-state imaging device and an imaging apparatus according to a tenth embodiment will be described in detail with reference to the drawings.

[0428] As described above, the plurality of unit pixels of the pixel array unit 300 may be grouped into a plurality of pixel blocks, each pixel block including a predetermined number of unit pixels. Therefore, in the present embodiment, the case where the plurality of unit pixels of the pixel array unit 300 are grouped into a plurality of pixel blocks will be described in detail with reference to the accompanying drawings. Note that the case based on the solid-state imaging device 800 according to the eighth embodiment will be presented below. However, the present embodiment is not limited to this example, but may be based on the case of the solid-state imaging device 200 according to other embodiments, for example, the solid-state imaging device 200 according to the first embodiment.

[0429] 11.1 Configuration Example of Pixel Array Unit

[0430] Fig.48 1010 is a block diagram illustrating a schematic configuration example of a pixel array unit according to the present embodiment. As described above, a plurality of unit pixels in the present embodiment are grouped into a plurality of pixel blocks 1010. Fig.48 As shown, the plurality of photoelectric conversion elements 333 of the pixel array unit 300 in this embodiment are grouped into a plurality of pixel blocks 1010. Each pixel block 1010 includes a plurality of photoelectric conversion elements 333 arranged in I rows×J columns (I and J: positive integers). Therefore, each pixel block 1010 includes a plurality of unit pixels arranged in a plurality of I rows×J columns (I and J: positive integers).

[0431] In addition to the plurality of photoelectric conversion elements 333 arranged in I rows×J columns, each pixel block 1010 includes a pixel signal generating unit 320 and an address event detecting unit 400. The pixel signal generating unit 320 and the address event detecting unit 400 are shared by the plurality of photoelectric conversion elements 333 in each pixel block 1010. In other words, each unit pixel in the same pixel block 1010 includes one photoelectric conversion element 333, the pixel signal generating unit 320 and the address event detecting unit 400 as a shared unit. The coordinates of each unit pixel are defined according to the coordinates of the photoelectric conversion elements 333 arranged in a two-dimensional grid shape on the light receiving surface of the solid-state imaging device 800.

[0432] One vertical signal line VSL is wired in one column of the pixel block 1010. Therefore, assuming that the number of columns of the pixel block 1010 is m (m: a positive integer), m vertical signal lines VSL are provided in the pixel array unit 300.

[0433] The pixel signal generating unit 320 generates, as a pixel signal, a signal indicating a voltage value corresponding to the charge amount of the photocurrent supplied from each photoelectric conversion element 333. The pixel signal generating unit 320 supplies the generated pixel signal to the column ADC 220 via the vertical signal line VSL.

[0434] The address event detection unit 400 detects the presence or absence of an address event trigger based on whether the current value of the photocurrent or the change in the current value provided by each photoelectric conversion element 333 in the same pixel block 1010 has exceeded a predetermined threshold. For example, the address event may include a turn-on event indicating that the change has exceeded an upper threshold and a turn-off event indicating that the change is less than a lower threshold. In addition, for example, the detection signal of the address event may include one bit indicating the detection result of the turn-on event and one bit indicating the detection result of the turn-off event. Note that the address event detection unit 400 may be configured to detect a turn-on event or a turn-off event.

[0435] When an address event is triggered, the address event detection unit 400 provides a request to send a detection signal to the arbitrator 213. Thereafter, when a response to the request is received from the arbitrator 213, the address event detection unit 400 provides a detection signal to the driving circuit 211 and the signal processing unit 212.

[0436] The driving circuit 211 that has received the supply of the detection signal performs readout of each unit pixel belonging to the pixel block 1010 (the pixel block 1010 includes the address event detection unit 400 that has supplied the detection signal). In response to the readout, a pixel signal having an analog value is sequentially input to the column ADC 220 from each unit pixel in the pixel block 1010 corresponding to the readout target.

[0437] 11.2 Example of a pixel block

[0438] For example, in Fig.48 In the configuration shown, the pixel block 1010 includes a combination of photoelectric conversion elements 333 for receiving wavelength components required for reconstructing colors. For example, in the case of reconfiguring colors based on the three primary colors of RGB, one pixel block 1010 includes a combination of a photoelectric conversion element 333 for receiving red (R) light, a photoelectric conversion element 333 for receiving green (G) light, and a photoelectric conversion element 333 for receiving blue (B) light.

[0439] Therefore, according to the present embodiment, for example, based on an array of wavelength selection elements (e.g., color filters) provided for each photoelectric conversion element 333 (hereinafter referred to as a color filter array), a plurality of photoelectric conversion elements 333 arranged in a two-dimensional grid shape in the pixel array unit 300 are grouped into a plurality of pixel blocks 1010.

[0440] There are various types of color filter arrays, for example, a 2×2 pixel Bayer array, a 3×3 pixel color filter array for an X-Trans (registered trademark) CMOS sensor (hereinafter referred to as an X-Trans (registered trademark) type array), a 4×4 pixel quad Bayer array (also called a Quadra array), and a 4×4 pixel color filter that combines a Bayer array and a white RGB color filter (hereinafter referred to as a white RGB array).

[0441] Therefore, several examples of pixel blocks 1010 employing a typical color filter array will be described below.

[0442] 11.2.1 Bayer Array

[0443] Fig.49 FIG. 1 is a schematic diagram illustrating an example of a configuration of a pixel block using a Bayer array as a color filter array. Fig.49 In the case of the Bayer array shown, one pixel block 1010A has a basic pattern (hereinafter also referred to as a unit pattern) of photoelectric conversion elements 333 including 2×2 units (i.e., 4 in total), which are repeating units in the Bayer array. Therefore, for example, each pixel block 1010A in this example includes a photoelectric conversion element 333R having a red (R) color filter, a photoelectric conversion element 333Gr having a green (Gr) color filter, a photoelectric conversion element 333Gb having a green (Gb) color filter, and a photoelectric conversion element 333B having a blue (B) color filter.

[0444] 11.2.2 X-Trans (registered trademark) array

[0445] Fig.50 is a schematic diagram depicting a configuration example of a pixel block that adopts an X-Trans (registered trademark) type array as a color filter array. Fig.50As shown, one pixel block 1010B in this example has a basic pattern (hereinafter similarly referred to as a unit pattern) including 3×3 pixels (i.e., 9 in total) of photoelectric conversion elements 333, which are repeating units in an X-Trans (registered trademark) type array. Therefore, for example, each pixel block 1010B in this example includes: five photoelectric conversion elements 333G, each of which has a green (G) color filter arranged along two diagonal lines in a rectangular area forming the unit pattern; two photoelectric conversion elements 333R, each of which has a red (R) color filter arranged point-symmetrically with respect to the central axis corresponding to the photoelectric conversion element 333G located at the center of the rectangular area; and two photoelectric conversion elements 333B, each of which has a blue (B) color filter arranged similarly point-symmetrically with respect to the central axis corresponding to the photoelectric conversion element 333G located at the center of the rectangular area.

[0446] 11.2.3 Quad Bayer Array

[0447] Fig.51 FIG. 1 is a schematic diagram illustrating an example of a configuration of a pixel block using a quad-Bayer array as a color filter array. Fig.51 In the case of the Bayer array shown, one pixel block 1010C has a basic pattern (hereinafter similarly referred to as a unit pattern) including 4×4 units (i.e., 16 in total) of photoelectric conversion elements 333, which are repeating units in the four Bayer array. Therefore, for example, each pixel block 1010C in this example includes: 2×2 (i.e., four in total) pixel photoelectric conversion elements 33R, each pixel photoelectric conversion element 33R having a red (R) color filter; 2×2 (i.e., four in total) photoelectric conversion elements 33Gr, each photoelectric conversion element 33Gr having a green (Gr) color filter; 2×2 (i.e., four in total) photoelectric conversion elements 333Gb, each photoelectric conversion element 333Gb having a green (Gb) color filter; and 2×2 (i.e., four in total) photoelectric conversion elements 333B, each photoelectric conversion element 333B having a blue (B) color filter.

[0448] 11.2.4 White RGB Array

[0449] Fig.52 FIG. 1 is a schematic diagram illustrating an example of a configuration of a pixel block using a white RGB array as a color filter array. Fig.52In the case of the white RGB array shown, one pixel block 1010D has a basic pattern (hereinafter similarly referred to as a unit pattern) including 4×4 units (i.e., 16 in total) of photoelectric conversion elements 333, which are repeating units in the white RGB Bayer array. Therefore, for example, each pixel block 1010D in this example includes a photoelectric conversion element 333W, each photoelectric conversion element 333W having a white RGB color filter for receiving each wavelength component of light of the three primary colors of RGB, and arranged between each photoelectric conversion element 333R, photoelectric conversion element 333G, and photoelectric conversion element 333G, each photoelectric conversion element 333R having a red (R) color filter, each photoelectric conversion element 333G having a green (G) color filter, and each photoelectric conversion element 333B having a blue (B) color filter.

[0450] In the case of adopting a white RGB array, note that, for example, by using the signal processing unit 212 to perform signal processing on the pixel signal based on the charges transferred from the respective photoelectric conversion elements 333R, 333G, 333B and 333W, image data indicating one frame read from the pixel array unit 300 can be converted into image data in the Bayer array.

[0451] As described above, in the case where a color filter is provided for the photoelectric conversion element 333, a group of photoelectric conversion elements 333 constituting a repeated unit pattern in the color filter array can be used as a combination of photoelectric conversion elements 333 for receiving a wavelength component of light required for reconstructing color.

[0452] However, it is not required to adopt such a configuration. One pixel block 1010 may include multiple unit patterns. In addition, it is not required to adopt a unit pattern. Multiple photoelectric conversion elements 333 in the pixel array unit 300 may be grouped into multiple pixel blocks 1010 so that each pixel block 1010 includes the photoelectric conversion element 333 required for reconstructing the color.

[0453] In addition, for example, in the case of a quad Bayer array, one pixel block 1010 may include a group of photoelectric conversion elements of the same color in a unit pattern, or one pixel block 1010 may include a total of four photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B to include photoelectric conversion elements 333 of corresponding colors, each photoelectric conversion element 333 having one color.

[0454] 11.3 Example of pixel block configuration

[0455] Next, a configuration example of the pixel block 1010 will be described. Fig.53 1 is a circuit diagram illustrating a schematic configuration example of a pixel block according to the tenth embodiment. Fig.53As shown, for example, the pixel block 1010 includes a pixel signal generating unit 320, a light receiving unit 1030, and an address event detecting unit 400. Note that, for example, Fig.53 The logic circuit 210 may include Fig.37 The driving circuit 211, the signal processing unit 212 and the logic circuit of the arbiter 213 are shown in FIG.

[0456] For example, the light receiving unit 1030 includes a photoelectric conversion element 333R having a red (R) color filter, a photoelectric conversion element 333Gr having a green (Gr) color filter, a photoelectric conversion element 333Gb having a green (Gb) color filter, and a photoelectric conversion element 333B having a blue (B) color filter. In addition, the light receiving unit 1030 includes four transfer transistors 331R, 331Gr, 331Gb, and 331B provided in a one-to-one correspondence for the four photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B, and includes a transfer transistor 331 and an OFG transistor 332.

[0457] The control signal TRGR, TRGGr, TRGGb or TRGB is respectively supplied to the gates of the transfer transistors 331R, 331Gr, 331Gb and 331B from the drive circuit 211. In addition, the control signal TRG is supplied from the drive circuit 211 to the gate of the transfer transistor 331. The control signal OFG is supplied from the drive circuit 211 to the gate of the OFG transistor 332. The outputs via the respective transfer transistors 331R, 331Gr, 331Gb and 331B are integrated at a node 334. The node 334 is connected to the pixel signal generating unit 320 via the transfer transistor 331, and is also connected to the address event detecting unit 400 via the OFG transistor 332. Note that the transfer transistor 331 may be omitted.

[0458] For example, each of the transfer transistors 331R, 331Gr, 331Gb, and 331B, the transfer transistor 331, and the OFG transistor 332 of the light receiving unit 1030 includes an NMOS transistor.

[0459] Each of the photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B of the light receiving unit 1030 photoelectrically converts light that is included in incident light and has a specific wavelength component to generate electric charges.

[0460] The transfer transistors 331R, 331Gr, 331Gb, and 331B transfer charges respectively generated in the photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B to the node 334 according to control signals TRGR, TRGGr, TRGGb, and TRGB applied to the respective gates.

[0461] The transfer transistor 331 transfers the charge at the node 334 to the floating diffusion layer 324 of the pixel signal generating unit 320 according to the control signal TRG. On the other hand, the OFG transistor 332 supplies the charge at the node 334 as a photocurrent to the address event detecting unit 400 according to the control signal OFG.

[0462] In response to the instruction of address event detection start issued from the control unit 130, the driving circuit 211 of the logic circuit 210 outputs control signals OFG, TRGR, TRGGr, TRGGb, and TRGB for making the OFG transistors 332 and all the transfer transistors 331R, 331Gr, 331Gb, and 331B of all the light receiving units 1030 included in the pixel array unit 300 enter the on state, and also outputs a control signal TRG for making the transfer transistors 331 of all the light receiving units 1030 enter the off state. As a result, the photocurrent generated in each photoelectric conversion element 333R, 333Gr, 333Gb, and 333B of the light receiving unit 1030 is provided to the address event detection unit 400 of each pixel block 1010 via the node 334 and the OFG transistor 332.

[0463] When an address event trigger is detected based on the photocurrent from the light receiving unit 1030, the address event detection unit 400 of each pixel block 1010 outputs a request to the arbiter 213. In response to the request, the arbiter 213 arbitrates the requests from the respective pixel blocks 1010, and based on the result of the arbitration, sends a predetermined response to each pixel block 1010 that has issued the request. Each pixel block 1010 that has received the request provides a detection signal indicating the presence or absence of an address event trigger to the drive circuit 211 and the signal processing unit 212 of the logic circuit 210.

[0464] The driving circuit 211 causes the OFG transistor 332 of the pixel block 1010 as the supplier of the address event detection signal to enter the off state. As a result, the supply of the photocurrent from the light receiving unit 1030 to the address event detection unit 400 in the pixel block 1010 is stopped.

[0465] Subsequently, the drive circuit 211 outputs a control signal TRG for turning on the transfer transistor 331 in the light receiving unit 1030 of the pixel block 1010. Subsequently, the drive circuit 211 sequentially outputs control signals TRGR, TRGGr, TRGGb, and TRGB for turning on the transfer transistors 331R, 331Gr, 331Gb, and 331B of the light receiving unit 1030 at different times. As a result, the charges generated in the photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B of the light receiving unit 1030 are sequentially transferred to the floating diffusion layer 324 via the transfer transistors 331R, 331Gr, 331Gb, and 331B and the transfer transistor 331. Thereafter, in the vertical signal line VSL connected to the selection transistor 323 of the pixel signal generating unit 320, pixel signals indicating voltage values ​​corresponding to the charge amount accumulated in the floating diffusion layer 324 are sequentially acquired.

[0466] As described above, the solid-state imaging device 200 sequentially outputs pixel signals to the column ADC 220 from the unit pixels belonging to the pixel block 1010 corresponding to the detected address event trigger.

[0467] According to such a configuration, the upper pixel circuit 500 set on the second chip 201b may include the LG transistor 411 and the amplifying transistor 412 (or the LG transistors 411 and 413 and the amplifying transistors 412 and 414) in the current-voltage conversion unit 410 of the address event detection unit 400 and the reset transistor 321, the amplifying transistor 322 and the selecting transistor 323 constituting the pixel signal generating unit 320, similar to the above-mentioned eighth embodiment.

[0468] 11.4 Operation Examples of Solid-State Imaging Devices

[0469] Next, the operation of the solid-state imaging device 800 according to the present embodiment will be described in detail with reference to the drawings.

[0470] 11.4.1 Time Diagram

[0471] First, an example of the operation of the solid-state imaging device 200 will be described with reference to a timing chart. Fig.54 is a timing chart showing an operation example of the solid-state imaging device according to the present embodiment.

[0472] like Fig.54As shown, when the control unit 130 instructs the start of detection of the address event at time T0, the drive circuit 211 raises the control signal OFG applied to the gate of the OFG transistor 332 of all the light receiving units 1030 in the pixel array unit 300 to a high level, and also raises the control signals TRGR, TRGGr, TRGGb and TRGB applied to the gates of the transfer transistors 331R, 331Gr, 331Gb and 331B of all the light receiving units to a high level. As a result, the OFG transistors 332 and the transfer transistors 331R, 331Gr, 331Gb and 331B of all the light receiving units 1030 enter a conducting state, and the photocurrent generated by the charge generated in the respective photoelectric conversion elements 333R, 333Gr, 333Gb and 333B is supplied from the respective light receiving units 330 to the respective address event detection units 400. Note that during this period, the transfer transistors 331 of all the light receiving units 1030 in the pixel array unit 300 enter a disconnected state.

[0473] Next, assume a case where the address event detection unit 400 of one pixel block 1010 detects an address event trigger during a high level period of the control signal OFG. In this case, the address event detection unit 400 that has detected the address event trigger sends a request to the arbitrator 213. A response to the request is returned from the arbitrator 213 to the address event detection unit 400 that has issued the request.

[0474] For example, the address event detection unit 400 having received the response raises the detection signal input to the driving circuit 211 and the signal processing unit 212 to a high level during the period of time T1 to T2. In this explanation, it is assumed that the detection signal is a one-bit signal indicating a conduction event detection result.

[0475] The drive circuit 211 that has received the high-level detection signal from the address event detection unit 400 at time T1 reduces all control signals OFG and all control signals TRGR, TRGGr, TRGGb, and TRGB to a low level at the next time T2. As a result, the supply of photocurrent from all light receiving units 1030 of the pixel array unit 300 to the address event detection unit 400 is stopped.

[0476] In addition, at time T2, the drive circuit 211 raises the selection signal SEL applied to the gate of the selection transistor 323 of the pixel signal generating unit 320 in the pixel block 1010 corresponding to the readout target to a high level, and also raises the reset signal RST applied to the gate of the reset transistor 321 of the same pixel signal generating unit 320 to a high level within a fixed pulse period. As a result, the charge accumulated in the floating diffusion layer 324 of the pixel signal generating unit 320 is discharged (initialized), and the unit pixel is reset in units of pixel blocks. In this way, the voltage acquired in the vertical signal line VSL in the initialized state of the floating diffusion layer 324 is included in the column ADC 220 and read by the ADC 230 connected to the vertical signal VSL as the reset level of each pixel block 1010, and is converted into a digital value.

[0477] At time T3 after the reset level is read out, the control signal TRG applied to the gate of the transfer transistor 331 in the pixel block 1010 corresponding to the readout target is then raised to a high level. In addition, the drive circuit 211 applies the control signal TRGR of a fixed pulse period to the gate of the transfer transistor 331R in the pixel block 1010 corresponding to the readout target, for example. As a result, the charge generated in the photoelectric conversion element 333 is transferred to the floating diffusion layer 324 of the pixel signal generating unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 is acquired in the vertical signal line VSL. In this way, the voltage acquired in the vertical signal line VSL is read by the ADC 230 included in the column ADC 220 and connected to the vertical signal VSL as a red signal level, and is converted into a digital value.

[0478] The signal processing unit 212 performs CDS processing for obtaining the difference between the reset level and the signal level read in the aforementioned manner as a net pixel signal corresponding to the received light amount of the photoelectric conversion element 333R.

[0479] Subsequently, the drive circuit 211 applies a control signal TRGGr of a fixed pulse period to, for example, the gate of the transfer transistor 331Gr in the pixel block 1010 similarly corresponding to the readout target at time T4 after the signal level is read out based on the photoelectric conversion element 333R. As a result, the charge generated in the photoelectric conversion element 333Gr is transferred to the floating diffusion layer 324 of the pixel signal generating unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 is acquired in the vertical signal line VSL. Thereafter, the ADC 230 of the column ADC 220 reads the voltage acquired in the vertical signal line VSL as a green (Gr) signal level and converts it into a digital value.

[0480] Thereafter, the ADC 230 of the column ADC 220 reads the signal levels based on the respective photoelectric conversion elements 333Gb and 333B of the pixel block 1010 corresponding to the readout target in a similar manner and converts them into digital values ​​(times T5 and T6 ).

[0481] Subsequently, when the readout based on the signal levels of all the photoelectric conversion elements 333 in the pixel block 1010 corresponding to the readout target is completed, the drive circuit 211 lowers the control signal TRG applied to the gates of the transfer transistors 331 of all the light receiving units 330 in the pixel array unit 300 to a low level, and similarly, also raises the control signals TRGR, TRGGr, TRGGb, and TRGB applied to the gates of the transfer transistors 331R, 331Gr, 331Gb, and 331B to a high level in all the light receiving units 330. As a result, the detection of the address event trigger is restarted in all the light receiving units 330 of the pixel array unit 300.

[0482] 11.4.2 Flowchart

[0483] Next, an example of the operation of the solid-state imaging device 800 will be described with reference to a flowchart. Fig.55 1 is a flowchart showing an operation example of the solid-state imaging device according to the present embodiment. For example, when a predetermined application for detecting an address event is executed, the operation starts.

[0484] like Fig.55 As shown, each pixel block 1010 of the pixel array unit 300 first detects the presence or absence of an address event trigger in the current operation (step S1001). Then, the driving circuit 211 determines whether an address event trigger has been detected in any pixel block 1010 (step S1002).

[0485] In the case where the address event trigger is not detected (No in step S1002), the current operation proceeds to step S1004. On the other hand, in the case where the address event trigger is detected (Yes in step S1002), the driving circuit 211 sequentially reads pixel signals from the unit pixels of the pixel block 1010 corresponding to the detected address event trigger, and sequentially reads pixel signals from each unit pixel of the pixel block 1010 corresponding to the readout target (step S1003), and the process proceeds to step S1004.

[0486] In step S1004, it is determined whether to end the current operation. In the case where the current operation is not ended (No in step S1004), the current operation returns to step S1001, and repeats this step and subsequent steps. On the other hand, in the case where the current operation is about to end (Yes in step S1004), the current operation ends.

[0487] 11.5 Layer Diagram Example

[0488] Next, several examples of various layer diagrams of the first chip 201a and the second chip 201b according to the present embodiment will be described. Although an example of a source follower type current-voltage conversion unit 410 will be presented in the following description (see Figure 4 ), but other types may also be used. For example, the current-to-voltage conversion unit 410 is similarly applicable to a gain-boost type (see Figure 6 ).

[0489] 11.5.1 First Example

[0490] 11.5.1.1 First Chip

[0491] Fig.56 is a plan view illustrating an example of a layer diagram of a first chip according to a first example. Fig.56 As shown, the first chip 201a includes a two-dimensional grid-shaped light receiving unit 1030. In each light receiving unit 1030, a plurality of photoelectric conversion elements 333 constituting the pixel block 1010 are formed into I rows×J columns. In this example, four photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B constituting a unit pattern of the Bayer array are formed into two rows×two columns.

[0492] The four photoelectric conversion elements 333R, 333Gr, 333Gb, and 333B constituting the unit pattern include transfer transistors 331R, 331Gr, 331Gb, and 331B at corners facing each other, respectively. The drains of the transfer transistors 331R, 331Gr, 331Gb, and 331B are connected to a node 334 (see FIG. 1 ) as a common node. Fig.53 ). The OFG transistor 332 is provided on a wiring connecting the node 334 and the TSV 501a of the connection portion 501. The transfer transistor 331 is provided on a wiring connecting the node 334 and the TSV 801a of the connection portion 801.

[0493] 11.5.1.2 Second Chip

[0494] Fig.57 is a plan view illustrating an example of a layer diagram of a second chip according to the first example. Fig.57 As shown, the second chip 201b includes an upper pixel circuit 500 in a two-dimensional grid shape, similar to the reference Fig.44The second chip 201b described in the eighth embodiment. Each upper pixel circuit 500 includes an upper detection circuit 410A and a pixel signal generating unit 320, the upper detection circuit 410A includes an LG transistor 411 and an amplifying transistor 412, and the pixel signal generating unit 320 includes a reset transistor 321, an amplifying transistor 322, a selecting transistor 323 and a floating diffusion layer 324. For example, each upper pixel circuit 500 is formed in an area substantially equivalent to the area of ​​each photoelectric conversion element 333 formed on the first chip 201a. Note that the upper detection circuit 410A can be similar to the upper pixel circuit 500 in the above-mentioned embodiment.

[0495] 11.5.2 Second Example

[0496] Fig.58 is a plan view depicting an example of a layer diagram of a first chip according to a second example. Fig.59 is a plan view depicting an example of a layer diagram of a second chip according to the second example.

[0497] According to the present embodiment, the group of photoelectric conversion elements 333 for which the address event detection unit 400 monitors the presence or absence of an address event trigger and the group of photoelectric conversion elements 333 for which the pixel signal generation unit 320 reads pixel signals do not necessarily need to coincide with each other. Fig.58 As shown, each address event detection unit 400 can be configured to monitor the photoelectric conversion elements 333R, 333Gr, 333Gb and 333B in the (2j+1) column and (2j+2) column (j: 0 or a larger integer) of the photoelectric conversion elements 333 in the (2i+1) row and (2i+2) row (i: 0 or a larger integer), and read pixel signals from the photoelectric conversion elements 333R, 333Gr, 333Gb and 333B in the (2j) column and (2j+1) column of the photoelectric conversion elements 333 in the (2i+1) row and (2i+2) row.

[0498] In this case, if Fig.59 As shown, the second chip 201 b has a layout in which the address event detection unit 400 is disposed in an even-numbered column, and the pixel signal generation unit 320 is disposed in an odd-numbered column.

[0499] Note that all pixel signal generating units 320 that each process at least one of the plurality of photoelectric conversion elements 333 monitored by the address event detecting unit 400 may be configured to read pixel signals from the plurality of photoelectric conversion elements 333 processed by each pixel signal generating unit 320 when an address event trigger is detected by one address event detecting unit 400. The address event detecting unit 400 and the pixel signal generating unit 320 may be associated with each other in advance, and when one address event detecting unit 400 detects an address event trigger, the pixel signal generating unit 320 associated with the corresponding address event detecting unit 400 may be configured to read the pixel signal.

[0500] 11.5.3 Third Example

[0501] Fig.60 is a plan view depicting an example of a layer diagram of a first chip according to the third example. Fig.61 is a plan view depicting an example of a layer diagram of a second chip according to the third example.

[0502] In the second example, the address event detection unit 400 and the pixel signal generation unit 320 are alternately arranged in the row direction. On the other hand, in the third example, the address event detection unit 400 and the pixel signal generation unit 320 are alternately arranged not only in the row direction but also in the column direction.

[0503] In the third example, if Fig.60 As shown, each address event detection unit 400 can be configured to monitor a total of four (or two) photoelectric conversion elements 333R, 333Gr, 333Gb and 333B in the (2i+1) row (2j+1) column, (2i+1) row (2j+2) column, (2i+2) row (2j+1) column and (2i+2) row (2j+2) column, and each pixel signal generating unit 320 can be configured to read pixel signals from a total of four (or one or two) photoelectric conversion elements 333R, 333Gr, 333Gb and 333B in the 2i row 2j column, 2i row (2j+1) column, (2i+1) row 2j column and (2i+1) row (2j+1) column.

[0504] In this case, if Fig.61 As shown, the second chip 201 b has a layout such that the address event detection unit 400 is disposed in an odd row of an even column, and the pixel signal generation unit 320 is disposed in an even row of an odd column.

[0505] Note that, similar to the second example, when an address event trigger is detected by one address event detection unit 400, all pixel signal generation units 320 that each process at least one of the plurality of photoelectric conversion elements 333 monitored by the address event detection unit 400 may be configured to read pixel signals from the plurality of photoelectric conversion elements 333 processed by each pixel signal generation unit 320. The address event detection unit 400 and the pixel signal generation unit 320 may be associated with each other in advance, and when an address event trigger is detected by one address event detection unit 400, the pixel signal generation unit 320 associated with the corresponding address event detection unit 400 may be configured to read pixel signals.

[0506] 11.6 Operation and Effect

[0507] According to the configuration of the present embodiment, as described above, a group of multiple (N) unit pixels (pixel block 1010) for receiving the wavelength component of light required for color reconfiguration is designated as a unit (pixel block unit) for detecting the presence or absence of an address event trigger. In the case where an address event trigger is detected in units of pixel blocks, pixel signals are read in units of pixel blocks. In this case, when an address event is triggered on a unit pixel of a certain wavelength component, pixel signals of all wavelength components required for color reconfiguration are synchronously read. Therefore, correct color reconfiguration can be achieved. As a result, a solid-state imaging device and an event-driven imaging apparatus capable of acquiring a color image with correctly reconfigured colors can be obtained.

[0508] Note that in this embodiment, the case based on the solid-state imaging device 800 according to the eighth embodiment is presented by way of example. However, this embodiment is not limited to this example, but may be based on the case of the solid-state imaging device 200 according to other embodiments, for example, the solid-state imaging device 200 according to the first embodiment.

[0509] In addition, other configurations, operations, and effects may be similar to those of the above-described embodiments, and thus will not be described in detail here.

[0510] 12. Application examples for mobile objects

[0511] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body (e.g., a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot).

[0512] Fig.62 : is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0513] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.62 In the example shown, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output portion 12052, and an in-vehicle network interface 12053 are shown as a functional configuration of the integrated control unit 12050.

[0514] The driving system control unit 12010 controls the operation of devices related to the vehicle driving system according to various programs. For example, the driving system control unit 12010 serves as a control device for a driving force generating device (e.g., an internal combustion engine, a driving motor, etc.) for generating a driving force for the vehicle, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force for the vehicle, etc.

[0515] The body system control unit 12020 controls the operation of various devices provided to the body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lights (e.g., a headlight, a reverse light, a brake light, a turn signal light, a fog light, etc.). In this case, a radio wave or a signal of various switches transmitted from a mobile device as a substitute for a key may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0516] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging part 12031. The vehicle exterior information detection unit 12030 causes the imaging part 12031 to image the image of the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a process of detecting an object such as a person, a vehicle, an obstacle, a sign, a character on the road surface, etc., or a process of detecting the distance thereof.

[0517] The imaging part 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging part 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging part 12031 may be visible light, or may be invisible light such as infrared rays.

[0518] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection portion 12041 that detects the driver's state. The driver state detection portion 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection portion 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0519] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control of functions intended to implement an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation of the vehicle, following driving based on following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0520] In addition, the microcomputer 12051 can perform collaborative control intended for autonomous driving based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040 by controlling the driving force generating device, steering mechanism, braking device, etc., which enables the vehicle to drive autonomously without relying on the driver's operation, etc.

[0521] In addition, the microcomputer 12051 may output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam, for example, based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030.

[0522] The sound / image output portion 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the occupants of the vehicle or the outside of the vehicle of information. Fig.62 In the example of FIG. 12064 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0523] Fig.63 is a diagram depicting an example of the installation position of the imaging portion 12031.

[0524] exist Fig.63 , the imaging portion 12031 includes imaging portions 12101 , 12102 , 12103 , 12104 and 12105 .

[0525] Imaging parts 12101, 12102, 12103, 12104 and 12105 are arranged, for example, at the positions of the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at the position of the upper part of the windshield inside the vehicle. The imaging part 12101 arranged at the front nose and the imaging part 12105 arranged at the upper part of the windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The imaging parts 12102 and 12103 arranged to the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging part 12104 arranged at the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging part 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0526] By the way, Fig.63 An example of the shooting range of the imaging parts 12101 to 12104 is depicted. Imaging range 12111 represents the imaging range of the imaging part 12101 set at the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging parts 12102 and 12103 set at the side mirrors. Imaging range 12114 represents the imaging range of the imaging part 12104 set at the rear bumper or the rear door. For example, by superimposing the image data imaged by the imaging parts 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above is obtained.

[0527] At least one of the imaging parts 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging parts 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0528] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging parts 12101 to 12104, thereby extracting the nearest three-dimensional object that is particularly present on the driving path of the vehicle 12100 and is traveling in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / hour) as the leading vehicle. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, cooperative control for automatic driving can be performed so that the vehicle travels autonomously without relying on the operation of the driver or the like.

[0529] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging parts 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 is difficult to visually identify. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display part 12062, and performs forced deceleration or evasive steering via the driving system control unit 12010. The microcomputer 12051 can therefore help driving to avoid collisions.

[0530] At least one of the imaging parts 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether there is a pedestrian in the imaging images of the imaging parts 12101 to 12104. For example, such identification of pedestrians is performed by extracting feature points in the imaging images of the imaging parts 12101 to 12104 as infrared cameras and determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaging images of the imaging parts 12101 to 12104 and thus identifies the pedestrian, the sound / image output part 12052 controls the display part 12062 so that a square outline for emphasis is displayed so as to be superimposed on the identified pedestrian. The sound / image output part 12052 may also control the display part 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0531] An example of a vehicle control system to which the present disclosure is applicable has been described above. The technology according to the present disclosure is applicable to the imaging part 12031, the driver state detection part 12041, etc. in the above configuration.

[0532] The technical scope of the present disclosure is not limited to the above-described embodiments of the present disclosure, but can be modified in various ways without departing from the scope of the subject matter of the present disclosure. In addition, the constituent elements of the different embodiments and modifications can be appropriately modified.

[0533] In addition, the advantageous effects of the various embodiments described in this specification are presented only by way of example, and the advantageous effects are not limited to these effects, but may include other advantageous effects.

[0534] Note that the present technology can also adopt the following configurations.

[0535] (1) A solid-state imaging device comprising:

[0536] a plurality of photoelectric conversion elements arranged in a two-dimensional grid shape in a matrix direction, and each of the photoelectric conversion elements generates a charge corresponding to an amount of received light; and

[0537] a detection unit that detects a photocurrent generated by the charge generated in each of the plurality of photoelectric conversion elements, wherein

[0538] The photoelectric conversion element and at least a part of the detection unit are arranged on different chips.

[0539] (2) The solid-state imaging device according to (1) above, wherein

[0540] The detection unit includes a current-voltage conversion circuit, and the current-voltage conversion circuit includes a source follower circuit having a ring shape,

[0541] The photoelectric conversion element is provided on a first chip, and

[0542] The source follower circuit is disposed on a second chip bonded to the first chip.

[0543] (3) The solid-state imaging device according to the above (2), wherein the detection unit is provided on the second chip.

[0544] (4) The solid-state imaging device according to (2) or (3) above, further comprising:

[0545] A first transistor is provided between the photoelectric conversion element and the detection unit, wherein:

[0546] The first transistor is disposed on the first chip.

[0547] (5) The solid-state imaging device according to any one of (2) to (4) above, further comprising:

[0548] a logic circuit coupled to the detection unit, wherein

[0549] The logic circuit is provided on a third chip different from the first chip and the second chip.

[0550] (6) The solid-state imaging device according to any one of (2) to (5) above, further comprising:

[0551] A drive circuit controls the reading of charges from the photoelectric conversion element, wherein

[0552] The driving circuit is arranged on the second chip.

[0553] (7) The solid-state imaging device according to any one of (2) to (6) above, further comprising:

[0554] a generating unit that generates a pixel signal having a voltage value corresponding to the charge amount of the charge generated in the photoelectric conversion element, wherein

[0555] The generating unit is arranged on the second chip.

[0556] (8) The solid-state imaging device according to any one of (2) to (6) above, further comprising:

[0557] a generating unit that generates a pixel signal having a voltage value corresponding to the charge amount of the charge generated in the photoelectric conversion element, wherein

[0558] The generating unit is provided on a fourth chip bonded between the first chip and the second chip.

[0559] (9) The solid-state imaging device according to (7) or (8) above, further comprising:

[0560] A second transistor is provided between the photoelectric conversion element and the generating unit, wherein:

[0561] The second transistor is disposed on the first chip.

[0562] (10) The solid-state imaging device according to any one of (7) to (9) above, wherein

[0563] The plurality of photoelectric conversion elements are divided into a plurality of groups, each group being composed of one or more photoelectric conversion elements, and

[0564] The detection unit and the generation unit are provided for each of the plurality of groups.

[0565] (11) The solid-state imaging device according to (10) above, wherein each of the plurality of groups is composed of a combination of photoelectric conversion elements each receiving a wavelength component of light required to reconfigure the color of incident light.

[0566] (12) The solid-state imaging device according to (10) or (11) above, wherein

[0567] The detection unit is coupled to a first group of the plurality of groups,

[0568] The generating unit is coupled to a second group of the plurality of groups, and

[0569] At least one of the photoelectric conversion elements belonging to the first group also belongs to the second group.

[0570] (13) The solid-state imaging device according to any one of (2) to (12) above, wherein

[0571] The source follower circuit comprises

[0572] a third transistor having a source electrode connected to the photoelectric conversion element, and

[0573] A fourth transistor, a gate of the fourth transistor is connected to the photoelectric conversion element, and a drain of the fourth transistor is connected to the gate of the third transistor.

[0574] (14) The solid-state imaging device according to (13) above, wherein

[0575] The source follower circuit also includes

[0576] a fifth transistor having a source electrode coupled to a drain electrode of the third transistor, and

[0577] A sixth transistor, wherein a source of the sixth transistor is coupled to the gate of the third transistor and the drain of the fourth transistor, and a gate of the sixth transistor is coupled to the drain of the third transistor and the source of the fifth transistor.

[0578] (15) The solid-state imaging device according to (13) or (14) above, wherein the third transistor and the fourth transistor are MOS (Metal Oxide Semiconductor) transistors.

[0579] (16) The solid-state imaging device according to (13) or (14) above, wherein the third transistor and the fourth transistor include a terminal to which a reverse bias is applied.

[0580] (17) The solid-state imaging device according to (16) above, wherein the second chip is an SOI (Silicon On Insulator) substrate.

[0581] (18) The solid-state imaging device according to (13) or (14) above, wherein the third transistor and the fourth transistor are tunnel FETs (field effect transistors) or fin FETs.

[0582] (19) The solid-state imaging device according to any one of (2) to (18) above, further comprising:

[0583] a hydrogen supply film provided on the second chip, and the hydrogen supply film supplies hydrogen atoms to the second chip; and

[0584] An anti-diffusion film is interposed between the first chip and the second chip, and the anti-diffusion film prevents hydrogen atoms from diffusing from the second chip to the photoelectric conversion element.

[0585] (20) An imaging device comprising:

[0586] Solid-state imaging devices;

[0587] An optical system that forms an image of incident light on a light receiving surface of the solid-state imaging device; and

[0588] A control unit controls the solid-state imaging device, wherein:

[0589] The solid-state imaging device comprises:

[0590] a plurality of photoelectric conversion elements arranged in a two-dimensional grid shape in a matrix direction, and each of the photoelectric conversion elements generates a charge corresponding to an amount of received light; and

[0591] a detection unit that detects a photocurrent generated by the charge generated in each of the plurality of photoelectric conversion elements, wherein

[0592] The photoelectric conversion element and at least a part of the detection unit are arranged on different chips.

[0593] [reference numerals list]

[0594] 100 Imaging Device

[0595] 110 Imaging lens

[0596] 120 Recording Units

[0597] 130 Control unit

[0598] 139, 209 signal line

[0599] 200 Solid-state imaging devices

[0600] 201 Optical Receiver Chip

[0601] 201a First Chip

[0602] 201b Second chip

[0603] 201c Third Chip

[0604] 202 Detection Chip

[0605] 203 Logic Chip

[0606] 210 Logic Circuits

[0607] 211 drive circuit

[0608] 212 Signal Processing Unit

[0609] 213 Arbitrator

[0610] 220 columns ADC

[0611] 230 ADC

[0612] 300 pixel array unit

[0613] 310 pixels per unit

[0614] 320 pixel signal generation unit

[0615] 321 Reset transistor

[0616] 322 Amplifier Transistor

[0617] 323 Select transistor

[0618] 324 Floating Diffusion Layer

[0619] 325, 326, 327, 328, 416, 417, 418, 419, 4171, 4191 diffusion area

[0620] 3211, 3221, 3231, 3311, 3321, 4111, 4121, 4131, 4141 Gate

[0621] 330, 730, 830, 1030 optical receiving unit

[0622] 331, 331B, 331Gb, 331Gr, 331R Pass Transistors

[0623] 332 OFG transistor

[0624] 333, 333B, 333G, 333Gb, 333Gr, 333R, 333W photoelectric conversion element

[0625] 334 nodes

[0626] 400 Address Event Detection Unit

[0627] 410 Current-voltage conversion unit

[0628] 410A Upper detection circuit

[0629] 411, 413 LG transistor

[0630] 412, 414 Amplifier transistor

[0631] 415 Constant Current Circuit

[0632] 420 Buffer

[0633] 430 Subtractor

[0634] 431, 433 capacitor

[0635] 432 Inverter

[0636] 434 Switch

[0637] 440 Quantizer

[0638] 441 Comparator

[0639] 450 Transmission Unit

[0640] 500 upper pixel circuit

[0641] 501, 502, 801 connection part

[0642] 501a, 501b, 501c, 736, 801a, 801b, 801c TSV

[0643] 501d, 737, 801d, 3241 wiring

[0644] 510 Circuit Configuration

[0645] 511 Circuit Elements

[0646] 601, 611, 621 Semiconductor substrate

[0647] 602 On-chip lens

[0648] 603 planarization film

[0649] 604 pixel separation unit

[0650] 605 p-type semiconductor region

[0651] 606, 3312, 3322n-type semiconductor region

[0652] 607, 734, 807 contact layer

[0653] 608, 612, 622 Interlayer dielectric

[0654] 610, 620 joint surface

[0655] 613, 623 wiring layer

[0656] 619, 629 Cu pad

[0657] 700 transistors

[0658] 701 FDSOI substrate

[0659] 701A SOI substrate

[0660] 702 Silicon film

[0661] 702A Silicon layer

[0662] 703 embedded oxide film

[0663] 704 Support substrate

[0664] 705 Gate

[0665] 706 Gate insulation film

[0666] 706A, 731 Silicon oxide film

[0667] 707 Source

[0668] 708 Drain

[0669] 710 Tunnel FET

[0670] 720 FinFET

[0671] 732 Component separation insulating film

[0672] 733 Groove

[0673] 751 Hydrogen Supply Membrane

[0674] 752 Hydrogen diffusion barrier

[0675] 1010, 1010A, 1010B, 1010C, 1010D pixel blocks

[0676] VSL Vertical Signal Line.

Claims

1. An asynchronous solid-state imaging device, comprising: A plurality of photoelectric conversion elements are arranged in a two-dimensional grid shape in a matrix direction, and each photoelectric conversion element generates a charge corresponding to an amount of received light; as well as A detection unit, the detection unit comprising a current-voltage conversion unit, a subtractor, a buffer, a quantizer, and a transmission unit, the detection unit being configured to detect the presence or absence of an address event trigger of a corresponding photoelectric conversion element based on whether a current value of a photocurrent generated by charges generated in each of a plurality of photoelectric conversion elements or a change in the current value exceeds a predetermined threshold, wherein: The photoelectric conversion element and at least a part of the detection unit are arranged on different chips.

2. The asynchronous solid-state imaging device according to claim 1, wherein: The current-voltage conversion unit includes a source follower circuit having a ring shape, The photoelectric conversion element is provided on a first chip, and The source follower circuit is disposed on a second chip bonded to the first chip.

3. The asynchronous solid-state imaging device according to claim 2, wherein: The detection unit is disposed on the second chip.

4. The asynchronous solid-state imaging device according to claim 2, further comprising: A first transistor is provided between the photoelectric conversion element and the detection unit, wherein: The first transistor is disposed on the first chip.

5. The asynchronous solid-state imaging device according to claim 2, further comprising: A logic circuit is connected to the detection unit, wherein The logic circuit is provided on a third chip different from the first chip and the second chip.

6. The asynchronous solid-state imaging device according to claim 2, further comprising: A drive circuit controls the reading of charges from the photoelectric conversion element, wherein The driving circuit is arranged on the second chip.

7. The asynchronous solid-state imaging device according to claim 2, further comprising: a generating unit that generates a pixel signal having a voltage value corresponding to the charge amount of the charge generated in the photoelectric conversion element, the generating unit including a reset transistor, an amplifying transistor, a selecting transistor and a floating diffusion layer, wherein, The generating unit is arranged on the second chip.

8. The asynchronous solid-state imaging device according to claim 2, further comprising: a generating unit that generates a pixel signal having a voltage value corresponding to the charge amount of the charge generated in the photoelectric conversion element, the generating unit including a reset transistor, an amplifying transistor, a selecting transistor and a floating diffusion layer, wherein, The generating unit is provided on a fourth chip bonded between the first chip and the second chip.

9. The asynchronous solid-state imaging device according to claim 7, further comprising: A second transistor is provided between the photoelectric conversion element and the generating unit, wherein: The second transistor is disposed on the first chip.

10. The asynchronous solid-state imaging device according to claim 7, wherein: The plurality of photoelectric conversion elements are divided into a plurality of groups, each group being composed of one or more photoelectric conversion elements, and The detection unit and the generation unit are provided for each of the plurality of groups.

11. The asynchronous solid-state imaging device according to claim 10, wherein: Each of the plurality of groups is constituted by a combination of photoelectric conversion elements, each of which receives a wavelength component of light required to reconfigure the color of incident light.

12. The asynchronous solid-state imaging device according to claim 10, wherein: The detection unit is connected to a first group of the plurality of groups, The generating unit is connected to a second group of the plurality of groups, and At least one of the photoelectric conversion elements belonging to the first group also belongs to the second group.

13. The asynchronous solid-state imaging device according to claim 2, wherein: The source follower circuit comprises a third transistor having a source connected to the photoelectric conversion element, and A fourth transistor, a gate of the fourth transistor is connected to the photoelectric conversion element, and a drain of the fourth transistor is connected to the gate of the third transistor.

14. The asynchronous solid-state imaging device according to claim 13, wherein: The source follower circuit also includes a fifth transistor, a source of the fifth transistor being connected to a drain of the third transistor, and A sixth transistor, wherein a source of the sixth transistor is connected to the gate of the third transistor and the drain of the fourth transistor, and a gate of the sixth transistor is connected to the drain of the third transistor and the source of the fifth transistor.

15. The asynchronous solid-state imaging device according to claim 13, wherein: The third transistor and the fourth transistor include MOS (Metal Oxide Semiconductor) transistors.

16. The asynchronous solid-state imaging device according to claim 13, wherein: The third transistor and the fourth transistor each include a terminal to which a reverse bias is applied.

17. The asynchronous solid-state imaging device according to claim 16, wherein: The second chip includes a SOI (Silicon On Insulator) substrate.

18. The asynchronous solid-state imaging device according to claim 13, wherein: The third transistor and the fourth transistor are tunnel FETs (field effect transistors) or fin FETs.

19. The asynchronous solid-state imaging device according to claim 2, further comprising: a hydrogen supply film provided on the second chip, and the hydrogen supply film supplies hydrogen atoms to the second chip; as well as An anti-diffusion film is interposed between the first chip and the second chip, and the anti-diffusion film prevents hydrogen atoms from diffusing from the second chip to the photoelectric conversion element.

20. An imaging device comprising: The asynchronous solid-state imaging device according to any one of claims 1 to 19; An optical system that forms an image of incident light on a light receiving surface of the asynchronous type solid-state imaging device; and A control unit controls the asynchronous solid-state imaging device.

Images