Solid state drive and method of operating a solid state drive

Abstract

Solid-state drives (SSDs) and methods for operating SSDs are disclosed. The SSD may include an interface for receiving read and write requests from applications on a host machine. A storage device including at least one chip can store data. An SSD controller can handle read and write requests from applications. A configuration module can configure the SSD. The storage device for a reliability table may include a reliability table containing entries specifying the SSD's configuration and reliability for those configurations.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 948,792, filed December 16, 2019, and U.S. Non-Provisional Patent Application No. 16 / 853,731, filed April 20, 2020, which are incorporated herein by reference for all purposes. Technical Field

[0002] The inventive concept generally relates to storage systems, and more specifically, to storage systems that provide variable levels of reliability. Background Technology

[0003] Ideally, storage devices (such as solid-state drives (SSDs)) should be perfect: every bit written can be read without errors. But the real world is imperfect: despite the best efforts of SSD manufacturers, errors still occur occasionally.

[0004] To help consumers, manufacturers can provide estimates of device reliability. For example, a manufacturer might report 99.99% reliability (or its equivalent, an average error rate of 1 bit per 1000 bits written and / or read). (In reality, this reliability is relatively low: it would imply at least one error in almost every page written to the SSD. However, this level of reliability serves as an example.)

[0005] However, this reliability relates to the number of bits written to or read from the SSD. This reliability cannot accurately reflect the reliability of the data from an application's perspective. There are other functions performed by the SSD that may affect its true reliability.

[0006] There is a need to more accurately determine and control the reliability of storage systems. Summary of the Invention

[0007] Some embodiments of the inventive concept provide a solid-state drive (SSD) comprising: an interface for receiving read and write requests from a first application on a host; a storage device for data, the storage device including at least one chip; an SSD controller for processing the read and write requests from the first application on the host using the storage device; a configuration module for configuring the SSD; and a storage device for a reliability table, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the SSD and a first reliability of the first configuration of the SSD, and the second entry identifying a second configuration of the SSD and a second reliability of the second configuration of the SSD.

[0008] Some embodiments of the inventive concept provide a method for operating a solid-state drive (SSD), the method comprising: determining a desired reliability for the SSD, the SSD including a storage device for data, the storage device including at least one chip; accessing a first entry from a reliability table of the SSD, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the SSD and a first reliability of the first configuration of the SSD, the second entry identifying a second configuration of the SSD and a second reliability of the second configuration of the SSD; and configuring the SSD according to the first entry.

[0009] Some embodiments of the inventive concept provide a method for operating a solid-state drive (SSD), the method comprising: sending a reliability request from an application on a host to the SSD, the reliability request requesting valid reliability of the SSD; receiving the valid reliability of the SSD from the SSD at the application on the host; sending a reliability table request from the application on the host to the SSD, the reliability table request requesting a reliability table stored on the SSD; receiving the reliability table from the SSD at the application on the host, each entry in the reliability table identifying the configuration of the SSD and the reliability of the SSD configuration; selecting entries in the reliability table based at least on the expected reliability for the application on the host; and sending a configuration request from the application on the host to the SSD, the configuration request identifying entries in the reliability table. Attached Figure Description

[0010] Figure 1 A system including a client and a server, according to an embodiment of the inventive concept, is shown, the server including a solid-state drive (SSD).

[0011] Figure 2 It shows Figure 1 Details of the server.

[0012] Figure 3 It shows Figure 1 Details of the SSD.

[0013] Figure 4 It shows Figure 1 The reliability table for SSDs.

[0014] Figure 5 It shows Figure 1 Optional illustrations of SSDs.

[0015] Figure 6 It shows in Figure 5 Applications and Figure 1 Messages exchanged between SSDs.

[0016] Figure 7 An embodiment of the invention is shown for use with respect to the inventive concept. Figure 1The flowchart illustrates an example process by which an SSD configures itself to provide the desired reliability.

[0017] Figure 8 It shows the use of Figure 1 The flowchart shows an example of how an SSD configures itself.

[0018] Figures 9A to 9B It shows the use of Figure 1 A flowchart illustrating an example process for determining the expected reliability of an SSD.

[0019] Figure 10 It shows the use of Figure 1 SSD determination Figure 1 A flowchart illustrating an example process for ensuring the effective reliability of SSDs.

[0020] Figures 11A to 11B An embodiment of the invention is shown for use with respect to the inventive concept. Figure 5 Application instructions Figure 1 The SSD provides a flowchart of an example process for achieving the desired reliability. Detailed Implementation

[0021] Detailed reference will now be made to embodiments of the inventive concept, examples of which are illustrated in the accompanying drawings. In the following detailed description, several specific details are set forth to enable a thorough understanding of the inventive concept. However, it should be understood that those skilled in the art can practice the inventive concept without these specific details. In other instances, well-known methods, processes, components, circuits, and networks are not described in detail to avoid unnecessarily obscuring aspects of the embodiments.

[0022] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the inventive concept, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module.

[0023] The terminology used herein in the description of the inventive concept is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used in the description of the inventive concept and the appended claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will also be understood that the term “and / or,” as used herein, refers to and covers any and all possible combinations of one or more of the associated listed items. It will also be understood that the terms “comprising” and / or “including”, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Components and features in the accompanying drawings are not necessarily drawn to scale.

[0024] As an example of how the reliability figures listed by manufacturers may not accurately reflect the true reliability of a storage device, consider data compression. If a solid-state drive (SSD) compresses data before it is written, a single bit error in the compressed data can actually affect multiple bits in the original data. For example, if data is compressed at an effective ratio of 2:1 (i.e., the size of the data written is half the size of the original data), a single bit error can be expected to affect two bits in the original data, effectively doubling the average error rate. Or, in the worst case, an error could prevent the SSD from successfully decompressing the compressed data back to the original data, resulting in the loss of the entire original data.

[0025] Alternatively, consider data deduplication. In deduplication, SSDs attempt to improve storage efficiency by identifying identical blocks of data that span multiple files (or even entire files that are stored equivalently multiple times). Instead of storing multiple copies of data, an SSD can store only one copy and reference that copy from various files that include that data block. However, if an error exists in data that should have been copied, that error becomes an error in every file that uses that data, further amplifying the error rate. For example, if the same data is used in three different files, a single error in the copied data is effectively three errors in three different files.

[0026] Furthermore, different applications may have different reliability requirements. For example, one application might want no more than one error in 1MB of data written by the application, while another application might want no more than one error in 1GB of data written by the application. Although applications can specify such reliability rates to help choose from different available storage devices, there is currently no way to support multiple different reliability levels for a single storage device.

[0027] According to the implementation, the SSD may include multiple levels, and reliability may be managed at these multiple levels. These levels may include the memory chip itself (where data is actually stored), and the memory chip may be a flash memory chip (such as a NAND flash memory chip), a non-volatile memory chip, or other types of memory chip that uses an error correction code (ECC) module (which can detect and / or correct errors read from the memory chip) and a RAID / erasure coding implementation (where data may be stored across multiple memory chips via multiple channels to provide some redundancy).

[0028] There are various ways to provide error detection and correction, such as using Redundant Array of Independent Disks (RAID) or Erasure Coding (EC). For example, RAID 1, RAID 5, RAID 6, or any alternative erasure coding implementation that supports error correction can be used. Each implementation provides a different level of reliability.

[0029] The ECC module can also be used, and any desired ECC algorithm can be implemented. Example algorithms that can provide error detection and / or correction include basic parity check, cyclic redundancy check (CRC), Hamming codes, etc., all of which are well-known schemes for performing error detection and / or correction. Each implementation provides a different level of reliability.

[0030] Finally, NAND flash memory chips also offer several options regarding reliability. For example, consider a single-level cell (SLC). An SLC can store one bit of data. By applying the appropriate voltage to the cell, the SSD can determine that bit (i.e., by applying one voltage to the cell, the cell can be determined to store the value "0", while by applying different voltages to the cell, the cell can be determined to store the value "1"). A multi-level cell (MLC) stores two bits of data, thus requiring up to four different voltage levels to determine the value stored in the cell; a three-level cell (TLC) stores up to three bits of data, thus requiring up to eight different voltage levels to determine the value stored in the cell; and a four-level cell (QLC) stores up to four bits, requiring up to 16 different voltage levels to determine the value stored in the cell.

[0031] As the number of bits stored in a cell increases, the width of the voltage range that separates the different possible stored values ​​decreases. Therefore, QLC (and the same applies to MLC and TLC) is more likely to return such errors than SLC will, due to errors arising from the processing of the applied voltage. Furthermore, as the number of bits stored in a cell increases, they tend to support fewer writes. Thus, SLC can support up to 100,000 data writes, while QLC can support a maximum of only 100 data writes (after which errors are more likely to occur during data writing). (Additionally, because the number of voltages that must be applied to a cell to determine its value increases with the number of bits stored in the cell, reading data from a cell from a QLC may take longer than reading data from a cell from an SLC.)

[0032] Because there is a relationship between the number of bits stored in a cell and the probability of errors due to incorrect handling of the input voltage, it is reasonable to conclude that QLC is more likely to experience such errors than other cell types (or, alternatively, QLC is the least reliable cell type), and SLC is the least likely to experience such errors (or, SLC is the most reliable). Of course, unless the NAND flash memory chip provides both types of cells, it is impossible to store data in a desired cell type to achieve a specific level of reliability. However, it is possible to use a cell to store fewer bits than it is capable of storing, thereby improving the cell's reliability.

[0033] Consider the QLC type. If a QLC stores 4 bits of data, its reliability is as advertised. However, if a QLC stores, for example, only one bit (leaving the other three bits with default or "don't care" values), then the QLC is effectively simulating an SLC. Errors that might arise from processing errors in voltages that differentiate between the values ​​of the "don't care" bits become irrelevant: there are actually only two input voltages that need to be applied to determine the value in the cell. (The embodiments of the inventive concept do not suggest that a QLC could be implemented to potentially store and read only one bit, but rather that the information returned in relation to the "don't care" bit can be ignored along with any errors that might be associated with that information. The embodiments of the inventive concept also do not suggest storing only one bit at a time in a QLC, which could lead to the QLC supporting an increased number of write operations.) Therefore, if a QLC stores only one bit, the error rate can be reduced, thereby enhancing reliability. This will also be true for any cell type used to store fewer bits than designed: therefore, QLC can emulate TLC, MLC, or SLC, TLC can emulate MLC or SLC, MLC can emulate SLC, and all QLC, TLC, and MLC offer improvements in their reliability. (Note that the reverse is not possible: even with reduced cell type reliability, no cell type can store more than the specified number of bits of information.)

[0034] A QLC can be taken and tested empirically to determine how reliable it is when storing fewer than 4 bits: the same applies to TLC and MLC. Apart from the amount of data written to the QLC, this test will be no different from how a QLC (or other cell types) is tested to determine their normal reliability. Therefore, for each cell type, the reliability can be determined when storing any number of bits (even when storing fewer than the maximum number of bits supported by the cell).

[0035] For RAID / erasure coding and ECC modules, there are mathematical models that can estimate their reliability, or their reliability can be empirically determined through actual use (very similar to how the reliability of various cell types can be determined).

[0036] Indeed, error correction schemes at various levels of SSDs are not entirely independent of each other. That is, if the RAID implementation and the ECC module have an error rate of 10... -10 And using QLC storage, only one bit has 10 -10 If the error rate is 10, then combining all three will not produce an error rate of 10. -30The error rate (the product of individual error rates). However, solutions at various levels are at least partially complementary: a combination of error correction schemes used at more than one level of the SSD can provide a reliability rate that exceeds the reliability that can be provided by any single level in isolation.

[0037] When manufacturing SSD devices, the reliability of each error correction combination can be tested at various levels, and the overall reliability of any individual combination can be determined. Therefore, for example, if the NAND flash memory includes QLC, there will be four possible variations (using QLC to store four bits, three bits, two bits, or one bit), and if ECC provides three different error correction schemes, and RAID / erasure coding implementations provide 10 different error correction variations, there will be a total of 120 different combinations (4 × 3 × 10 = 120). The manufacturer can test each such combination and determine the individual reliability of each combination. This information can then be stored in the storage device within the SSD: for example, within the configuration module. The configuration module can also be responsible for selecting appropriate error correction combinations at various levels to achieve the desired reliability.

[0038] In some embodiments of the inventive concept, applications can specify the reliability to be applied to their data. For example, some applications may require highly reliable data, while others may be less concerned about data loss (e.g., for temporary data or data that is easily reconstructable even if lost). Given the specified reliability for a given application, the configuration module can configure the SSD to achieve that target reliability for the data used by the application using appropriate error correction combinations based on the reliability of various error correction combinations. Note that if multiple applications are writing data to the same SSD, the configuration module can configure the entire SSD to operate at the highest reliability required by any application, or the configuration module can configure different areas of the SSD to operate at different reliability levels. For example, without changing the RAID or ECC implementation, the SSD can store only one bit in the QLC for data requiring higher reliability and four bits in the QLC for data tolerating lower reliability. Note that embodiments of the inventive concept can support managing reliability in any desired data unit (page, block, plane, die, chip, or across the entire SSD).

[0039] In other embodiments of the inventive concept, the application may simply provide data without additional requirements for data reliability. In such embodiments of the inventive concept, more specifically, in embodiments where the SSD may use compression, deduplication, or any other transaction that could affect reliability, the SSD can track what the effective reliability (how much) is for any given unit of data. Thus, if the application's raw data is being compressed, the SSD can track the effective compression ratio of the data, which can be used to determine the multiplier for the error rate. Alternatively, if the SSD uses deduplication, the SSD can track how many files are sharing a given unit of data, which can also be used to determine the multiplier for the error rate. Then, to ensure that advertised reliability is achieved, the configuration module can combine this information with the reliability rates of various error correction combinations to select an appropriate combination for providing advertised reliability (considering how errors multiply based on SSD operations).

[0040] It's important to note that reliability is not the only variable to consider when choosing an error correction combination to achieve the desired reliability (although it can be a primary one). If reliability were the sole consideration, an SSD could simply be configured to use the error correction combination that provides the highest reliability and perform accordingly: higher reliability cannot be achieved. However, various error correction combinations have other effects. These other effects include space overhead and performance. For example, if a QLC is used to store only one bit of information, the QLC operates with high reliability but is only 1 / 4 efficient in terms of storage (because a QLC can store up to four bits). Performance is also a consideration: different error correction combinations may require different processing times for data, which can affect the SSD's latency.

[0041] Therefore, taking other factors into account, the configuration module can choose which error correction combination to use to configure the SSD to provide the target reliability. For example, if space overhead is considered a significant factor, an error correction combination that allows the QLC to store four bits of data (relying more on the ECC module or RAID / erase coding) can be superior to one that stores only one bit in the QLC. Alternatively, if performance is a greater concern compared to space overhead, an error correction combination that relies less on the ECC module or RAID / erase coding to correct data can be advantageous even if it means the QLC stores only one bit of data.

[0042] Figure 1 A system including a client and a server, according to an embodiment of the inventive concept, is shown, the server including a solid-state drive (SSD). Figure 1In the diagram, clients 105-1 and 105-2 are shown communicating with server 110 via network 115. Clients 105-1 and 105-2, and server 110, can form a client-server relationship: clients 105-1 and 105-2 can issue commands, and server 110 can execute these commands. Alternatively, server 110 can be a computer directly used by end users, thus avoiding the involvement of clients 105-1 and 105-2.

[0043] Network 115 can be any kind of network or a variety of networks. For example, network 115 can include a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), or a global network (such as the Internet), among other possibilities. Data can be sent directly through network 115, or it can be protected: for example, using encryption or a virtual private network (VPN). Network 115 can include wired or wireless connections. Furthermore, network 115 can include any desired combination of these options. For example, clients 105-1 and 105-2 can connect to a LAN wirelessly, the LAN then connects to the Internet via a wired connection, and the Internet then connects to another LAN connected to server 110. The connection between clients 105-1 and 105-2 and server 110 can vary: the connection does not have to be the same in all cases.

[0044] Server 110 may include processor 120, memory 125, and solid-state drive (SSD) 130. Processor 120 may include a software stack containing an operating system, applications, storage software (such as a file system), and controller software to manage devices attached to server 110 (such as memory 125 and SSD 130). Processor 120 can be any type of processor: for example, an Intel Xeon, Celeron, Itanium, or Atom processor, an AMD Opteron processor, an ARM processor, etc. Although... Figure 1 A single processor 120 is shown, but server 110 may include any number of processors, each of which may be a single-core or multi-core processor, and may be mixed in any desired combination.

[0045] Memory 125 can be conventional memory used in server 110. Memory 125 can be any type of memory (such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), persistent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM) (such as magnetoresistive random access memory (MRAM), etc.)). Memory 125 can be volatile or non-volatile memory. Memory 125 can also be any desired combination of different memory types. Memory 125 can be controlled by a memory controller ( Figure 1 (Not shown in the image) The memory controller can be a separate component with a driver within server 110, which is part of the software stack. Memory 125 can be used to store data that may be referred to as "short-term data": that is, data that is not expected to be stored for a long time. Examples of short-term data may include temporary files, data used locally by the application (which may have been copied from other storage locations), etc.

[0046] Processor 120 and memory 125 can also support an operating system, under which various applications can run. These applications can issue requests to read data from or write data to memory 125 or SSD 130. Unlike memory 125, which can be used to store data that may be referred to as "short-term data," SSD 130 can be a storage device used to store data that is considered "long-term data" (i.e., data expected to be stored for a long time). SSD 130 can be accessed using controller software in a software stack running on processor 120. Although Figure 1 Only one SSD 130 is shown, but embodiments of the inventive concept can include any type of storage device connected via any desired connection. Therefore, SSD 130 can be replaced by a Serial AT Accessory (SATA) hard drive, an Ethernet SSD, or any other type of storage device. Furthermore, embodiments of the inventive concept can include any number (zero or more) of storage devices, each of which can be of any desired type: thus, multiple different types of storage devices can be mixed in the server.

[0047] Figure 2 It shows Figure 1 Details of server 110. Figure 2Typically, server 110 may include one or more processors 120, which may include a memory controller 205 and a clock 210, which may be used to coordinate the operation of components of the machine (e.g., server 110). Processor 120 may also be coupled to memory 125, which, for example, may include random access memory (RAM), read-only memory (ROM), or other state-keeping media. Processor 120 may also be coupled to storage device 130 and to network connector 215, which may be, for example, an Ethernet connector or a wireless connector. Processor 120 may also be connected to bus 220, to which user interface 225 and input / output interface ports, as well as other components, may be attached. The input / output interface ports may be managed using input / output (I / O) engine 230.

[0048] Figure 3 It shows Figure 1 Details of the SSD 130. Figure 3 In this configuration, SSD 130 may include Host Interface Logic (HIL) 305, SSD controller 310, and various memory chips 315-1 to 315-8 (also referred to as "memory storage devices"), which can be organized into various channels 320-1 to 320-4. Host Interface Logic 305 manages the SSD 130 in relation to other components (such as...). Figure 1 Communication between the processor 120 (or other SSD) and the SSD 130. This communication may include read requests for reading data from the SSD 130 and write requests for writing data to the SSD 130. The host interface logic 305 may manage the interface through a single port, or it may manage the interface through multiple ports. Optionally, the SSD 130 may include multiple ports, each of which may have a separate host interface logic 305 for managing the interface through that port. Embodiments of the inventive concept may also combine possibilities (e.g., an SSD with three ports may have one host interface logic for managing one port and a second host interface logic for managing the other two ports).

[0049] SSD controller 310 can use a memory controller ( Figure 3 (Not shown) to manage read and write operations, garbage collection operations, and other operations on memory chips 315-1 to 315-8. Memory chips 315-1 to 315-8 can be any kind of memory chip (such as NAND flash memory chips or other non-volatile memory chips), but embodiments of the inventive concept can be extended to other storage systems (such as non-volatile RAM (NVRAM)).

[0050] The SSD controller 310 may include a translation layer 325, an error correction code module 330, a RAID / erase coding module 335, a configuration module 340, and a reliability table storage device 345. The translation layer 325 can manage the storage device from... Figure 1 The SSD 130 maps logical block addresses (LBAs) used by applications running on processor 120 to physical block addresses (PBAs) where data is actually stored on the SSD 130. By using translation layer 325 (which, in some embodiments of the inventive concept, may also be referred to as flash translation layer 325), the SSD 130 can move data across memory chips 315-1 to 315-8 without requiring the application to keep up with the current location of the data (e.g., this might happen when an application requests to overwrite data with a new value (SSDs typically do not support in-place overwriting and therefore store the new data in a new location), or when a block containing some valid data undergoes garbage collection). Translation layer 325 can be implemented as a table stored in some (preferably) non-volatile storage device located somewhere within the SSD 130.

[0051] Error correction code (ECC) module 330 can apply error correction codes to data to be written to memory chips 315-1 to 315-8. In some embodiments of the inventive concept, ECC module 330 can be applied to data, regardless of which memory chips 315-1 to 315-8 will store the data; in other embodiments, each channel 320-1 to 320-4 (or each memory chip 315-1 to 315-8) can have its own ECC module 330. ECC module 330 can implement any desired error correction algorithm and therefore can (depending on the implemented algorithm) support the detection and / or correction of any number of errors. Example algorithms that can be used by ECC module 330 include parity check codes, cyclic redundancy check (CRC) codes, or Hamming codes. ECC module 330 can be implemented using a general-purpose processor that executes appropriate instructions, or it can be implemented using a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), graphics processing unit (GPU), or any other desired implementation.

[0052] The RAID / erasure coding module 335 can implement any desired RAID or erasure coding scheme to store data on memory chips 315-1 to 315-8. (Because a Redundant Array of Independent Disks (RAID) describes a specific set of implementations of erasure coding, the RAID / erasure coding module 335 can be more generally described as an erasure coding module without functional reduction.) Typically, the RAID / erasure coding module 335 can take the data to be written to the SSD 130, divide the data into various units, and store those units on different memory chips 315-1 to 315-8. To introduce redundancy, the same data can be stored on multiple memory chips 315-1 to 315-8, or error correction information (such as parity check codes, CRC codes, or Hamming codes) can be used. In this way, errors can be detected or corrected. (Note that the same basic approach can be used at different scales in both the RAID / erasure coding module 335 and the ECC module 330: therefore, the solutions can complement each other.) The erasure coding module 335 can be implemented using a general-purpose processor that executes appropriate instructions, or it can be implemented using an FPGA, ASIC, GPU, or any other desired implementation.

[0053] Configuration module 340 can be used to program which technologies will be used to improve reliability. While one might wonder how different reliability technologies can be used, the answer is simple. ECC module 330 and RAID / erasure coding module 335 can support different error correction technologies. Each error correction technology has (potentially) different reliability rates. Configuration module 340 can be used to instruct ECC module 330 and / or RAID / erasure coding module 335 which error correction can be used at a given time.

[0054] However, this answer leads to a follow-up question: if different error correction techniques offer varying degrees of reliability, why not always use the most reliable method? The answer is: different techniques might have other implications for the operation of the SSD 130, potentially offsetting the benefits of greater reliability. For example, consider the possibility that the same data could be stored in each of memory chips 315-1 through 315-8. This method introduces eight-fold replication of the data, meaning the failure of a single memory chip would not result in data loss. The drawback of this method is that because the same data is stored eight times, the total available storage of the SSD 130 will not exceed the total available storage of a single memory chip. In other words, the total available storage provided by the SSD 130 will be only one-eighth of the actual storage provided by the SSD 130, or alternatively, 87.5% of the available storage is reserved for redundant copies of the data. If the data is so sensitive that eight-fold replication is necessary, this cost might be acceptable; but for most users, such redundancy is excessive, and the reduction in available storage is unacceptable.

[0055] Therefore, the configuration module 340 can be used to instruct (or program, or configure: any term may be preferred) the ECC module 330 and the RAID / erasure coding module 335 to use a specific technology among those provided by the ECC module 330 and the RAID / erasure coding module 335.

[0056] In addition to the ECC module 330 and the RAID / erasure encoding module 335, there are other components that can be configured by the configuration module 340: specifically, memory chips 315-1 to 315-8. Different memory chips can provide different ways of storing data, which can affect the reliability of the memory chips. To understand this fact, it is important to understand the different types of memory storage devices.

[0057] Memory manages data at different levels of granularity depending on what is happening. For example, the basic unit of access for reading and writing data is a page (which can have any desired size: for example, 4KB of data). If a page is free, it can be written to. However, when new data replaces old data, a page may not be overwritten: in this case, the original page can be marked invalid, and new data can be written to a new page. Pages are organized into groups called blocks: for example, a block can have 64 pages or 128 pages. A block (or a superblock as a group of blocks) is typically the unit used for erasing data (which returns the page to a free state awaiting rewriting). Therefore, if any valid data exists in a block that has been selected for erasure, the valid data should be copied out of the block before the block is erased (so that the valid data is not lost when the block is erased).

[0058] However, even at a finer level, variations exist in data storage. Individual units (called cells) store data at a finer granularity than pages. (Individual cells cannot be directly accessed: entire pages can be read or written as units.) Each cell is designed to respond to different voltages applied: these different responses can be used to read values ​​from the cell (or write data to the cell).

[0059] In its simplest form, a cell has a single trigger voltage at which its response changes (the trigger voltage can be considered a dividing point). That is, the response when a voltage below this trigger voltage is applied differs from the response when a voltage above it is applied. Therefore, for example, if the input voltage can vary arbitrarily from 0V to 5V, then 2.5V could be the point at which the cell can begin to respond. (How the cell responds can depend on the value stored in the cell. For example, if the cell represents the binary value 0, the cell can output one voltage, while if the cell represents the binary value 1, the cell can output another voltage.) A cell that stores only a single bit is sometimes called a single-level cell (SLC).

[0060] A Multilayer Cell (MLC) refers to a cell that stores more than one bit. Although "more than" can be understood as meaning "two or more," in practice, an MLC typically stores two bits, while a Three-Level Cell (TLC) can store three bits, a Four-Level Cell (QLC) can store four bits, and so on. Because MLCs (and all other cell types that store more than one bit) store multiple bits, they have multiple trigger voltages. For example, if the input voltage can vary arbitrarily from 0V to 5V, an MLC can have trigger voltages of 1V, 2V, 3V, and 4V. Based on the trigger voltage, the flash memory chip can determine the actual value stored in the cell. Thus, for example, if the trigger voltage is 1V, the cell can store the value 00; if the trigger voltage is 2V, the cell can store the value 01; if the trigger voltage is 3V, the cell can store the value 10; and if the trigger voltage is 4V, the cell can store the value 11.

[0061] Different cell types have different advantages and disadvantages. Clearly, the ability to store more than one bit of information per cell means fewer cells are needed to store the same amount of data. Therefore, if data is stored in an SLC, more SLCs are needed to store the same amount of data than MLC, TLC, or QLC. Although individual cells storing more bits tend to be more expensive than those storing fewer bits, the increased cost can be offset by requiring fewer such cells. Therefore, to store the same amount of data, QLC is generally cheaper than TLC, TLC is cheaper than MLC, and MLC is cheaper than SLC.

[0062] However, there are other factors that can offset the cost. First, because SSDs must be tested against multiple different voltages to determine the values ​​stored in the cells, the increased number of such tests can slow down cell performance. Consider QLC, for example. Because QLC stores four bits of data, it can take any of 16 possible values. Therefore, reading a QLC might require testing it against 16 possible trigger voltages, which takes longer than testing it against two trigger voltages. Consequently, QLC might be slower to read than TLC, TLC might be slower than MLC, and MLC might be slower than SLC. Furthermore, the more bits a cell can store, the fewer program / erase cycles it will have over its lifetime. For example, SLC might guarantee 100,000 program / erase operations before a cell fails, while for MLC, that number might drop to 10,000, for TLC to 1,000, and for QLC to 100. Therefore, different types of cells can be used well for different storage profiles: QLC is well used for storing data that hardly ever changes, while SLC is used for data that changes with relative frequency.

[0063] The final drawback of cell types again relates to the number of trigger voltages required for cells storing higher-density data. The greater the number of trigger voltages, the closer those voltages can be to each other. However, the closer the trigger voltages are to each other, the more susceptible the cell is to potential errors. Consider, for example, a QLC. Because a QLC can store four bits of data, there are 16 possible values ​​in a QLC. Differentiating between these 16 possible values ​​can require 16 trigger voltages, meaning the gap between trigger voltages can be slightly greater than 0.25V. For a cell, a large drop or surge in voltage is not necessary for it to interpret the response as a different voltage than actually expected, meaning a QLC might incorrectly respond to read attempts. (Although the error margin is larger due to the fewer trigger voltages to consider, the same analysis applies to both MLC and TLC cell types.)

[0064] Therefore, returning to the issue of reliability, a QLC can store higher density data, but at the cost of reduced error margin. However, just because a QLC (or any type of cell that stores two or more bits of data) can store multiple bits does not mean that a QLC (or any type of cell that stores two or more bits of data) must store multiple bits. Such a QLC can be used to store fewer than four bits of data, and any values ​​assigned to the other bits in the QLC are ignored during read operations. By storing fewer bits in the QLC, the actual number of trigger voltages is reduced, which can widen the error margin. (Note that the QLC can still be hardwired to test against all 16 trigger voltages; only the probability of error is reduced, not the time required to access the cell.)

[0065] For example, suppose the QLC is used to store only one bit of data. This value (or the bit itself) (which is either 0 or 1) can be stored in any of the four bits of the QLC, and the other bits are effectively ignored by the SSD (i.e., those bits can be assigned any arbitrary value when the cell is written to, any value read from those bits can be ignored, and only the bit of interest can be returned). Because the QLC now effectively has only one trigger voltage, the likelihood of the cell being incorrectly written to or read (e.g., due to voltage fluctuations) is reduced.

[0066] Therefore, the reliability of an SSD can also be affected by changing the operating behavior of each memory chip 315-1 to 315-8. However, several issues need to be considered. First, whether the reliability of an SSD can be affected by changing the operating behavior of memory chips 315-1 to 315-8 depends on the type of cells used in memory chips 315-1 to 315-8. The higher the data density of the cells, the more options exist for affecting the reliability of the SSD. For example, SLC only stores one bit of data; therefore, the reliability of an SSD using only SLC cannot be improved by changing the operating behavior of SLC.

[0067] Furthermore, the improvements described above operate only in one direction. A cell capable of storing higher-density data can be used to store lower-density data by omitting some bits from the cell. However, it is impossible to reduce the reliability of an SSD by attempting to store more bits than the cell can store. For example, since an SLC can only store one bit of data, it is impossible to store two bits in an SLC (regardless of the tolerable reduction in reliability). (Of course, a cell storing fewer bits than it can store can increase its data density, as long as that increase does not exceed the cell's capacity. Therefore, for example, a QLC capable of storing four bits but currently only storing two bits can increase its data density to three or four bits, but not to five bits.)

[0068] Secondly, similar to using memory chips 315-1 through 315-8 to store the same data, storing fewer bits per cell than it can store can result in less usable storage for the SSD. For example, consider an SSD using QLC cells with a total usable storage capacity of 1TB. If the QLC is used to store only one bit per cell, the SSD will only have 256GB (25% of the total usable storage capacity) of effective capacity: the remaining 768GB of storage is "lost" in the unused bits of the QLC.

[0069] On the other hand, different memory chips can be configured to achieve different overall reliability. Therefore, for example, suppose memory chips 315-1 through 315-8 all use QLC cells. Memory chip 315-1 can be configured to store only one bit in each cell, thus providing improved reliability at the cost of reduced available storage. On the other hand, memory chip 315-2 can be configured to store four bits in each cell, thus providing maximum available storage at the cost of lower reliability.

[0070] The configuration module 340 can be implemented using a general-purpose processor that executes appropriate instructions, or using an FPGA, ASIC, GPU, or any other desired implementation. Figure 3 In this diagram, the ECC module 330, RAID / erase coding module 335, and configuration module 340 are shown as separate components. Because these components can be manufactured and installed separately within the SSD 130, they can be implemented as individual components. Furthermore, these components can actually reside in physically different locations. For example, as discussed above and referenced below... Figure 5Further discussion suggests that the ECC module 330 can be applied to a single channel (but to multiple memory chips), while the RAID / erase coding module 335 can be applied to multiple channels. In such a configuration, it is unlikely that any of the ECC module 330, RAID / erase coding module 335, and configuration module 340 will be implemented using common hardware. However, in some embodiments of the inventive concept, it may be feasible to implement any or all of these components using common hardware.

[0071] The above discussion focuses on what configuration module 340 can do to configure memory chips 315-1 to 315-8, ECC module 330, and RAID / erasure encoding module 335, but it has not yet explained what would trigger configuration module 340 to perform such an operation. Below, Figures 5 to 6 The discussion covered what could trigger the configuration module 340 to perform its operations.

[0072] Finally, to support configuration module 340, SSD 130 may include reliability table storage device 345. Reliability table storage device 345 can store a reliability table. This reliability table can provide information about the reliability provided by various combinations of schemes used by memory chips 315-1 to 315-8, ECC module 330, and RAID / erasure coding module 335.

[0073] Figure 4 It shows Figure 1 The reliability table for the SSD 130. Figure 4 The reliability table 405 is shown in the diagram. The reliability table 405 includes various columns (such as storage scheme 410, ECC scheme 415, and erase coding scheme 420). Commonly, storage scheme 410, ECC scheme 415, and erase coding scheme 420 form configuration 425: that is, for a given entry in the reliability table 405, storage scheme 410, ECC scheme 415, and erase coding scheme 420 are specified. Figure 3 Memory chips 315-1 to 315-8 Figure 3 ECC module 330 and Figure 3 The RAID / erasure coding module 335 can be configured in various ways. Other columns may include reliability 470 (which can specify the overall reliability for a given configuration), space overhead 430 (which can specify any space limitations caused by using a specific configuration), and performance 435 (which can specify any performance limitations caused by using a specific configuration). If reliability is listed alone as a configuration option... Figure 1 For SSD130 driver considerations, space overhead 430 and performance 435 can be omitted from reliability table 405.

[0074] Reliability Table 405 may include Figure 1 Entries for various possible configurations of the SSD 130. For example, Figure 4 Reliability is represented by six entries: 440, 445, 450, 455, 460, and 465. Each entry represents... Figure 1 The SSD 130 has different possible configurations. Therefore, for example, entry 440 identifies the reliability of such a configuration. Figure 3 The memory chips 315-1 to 315-8 use memory scheme 1, for Figure 3 The ECC module 330 uses ECC scheme 1, and for Figure 3 The RAID / erase coding module 335 uses erase coding scheme 1. For this configuration, the overall reliability is 10^-50% for write or read operations. 12 One error per bit. This configuration also imposes no space or performance overhead (entry 440 can represent, for example...). Figure 1 With the default configuration of the SSD 130, the reliability of entry 440 can be [percentage missing]. Figure 1 (The advertised reliability of the SSD 130). Conversely, entry 445 indicates a configuration that... Figure 3 The memory chips 315-1 to 315-8 use memory scheme 2, for Figure 3 The ECC module 330 uses ECC scheme 1, and for Figure 3 The RAID / erasure encoding module 335 uses erasure encoding scheme 1. This configuration has 10 write or read operations. 14 The reliability rate is 1 error per bit, but an error is imposed. Figure 1 The available storage capacity of the SSD 130 is reduced by 50% (but without incurring performance overhead). For example, entry 445 could represent a configuration where data is written to two different memory chips for redundancy, which improves the overall reliability of the SSD 130, but at the cost of reduced available storage.

[0075] Entries 450 and 455 are similar to entries 440 and 445, but... Figure 3 The ECC module 330 uses ECC scheme 2. As can be seen, these configurations each have 10 16 The reliability of a single error in 10 bits and 10 18 Reliability of 1 error per bit: 10% improvement over the configurations shown in entries 440 and 445. 4 However, because ECC Scheme 2 may require more computing resources than ECC Scheme 1, the configurations represented by entries 450 and 455 may impose a 25% performance hit (i.e., compared to using the configurations represented by entries 440 and 445, using the configurations represented by entries 450 and 455...). Figure 1 The SSD 130 may take up to 25% more time to process read and / or write requests.

[0076] Entries 460 and 465 are similar to entries 440 and 445, but... Figure 3 The RAID / erasure encoding module 335 uses erasure encoding scheme 2. As can be seen, these configurations each have 10 14 The reliability of a single error in 10 bits and 10 17 A reliability rate of 1 error per bit represents a reliability increase of 10 to 100 times. However, because erasure coding scheme 2 may require more computational resources than erasure coding scheme 1, the configurations represented by entries 460 and 465 may impose a 10% performance penalty (i.e., compared to using the configurations represented by entries 440 and 445, using the configurations represented by entries 460 and 465 results in a lower performance rate). Figure 1 The SSD 130 may take up to 10% longer to process read and / or write requests.

[0077] Note that the improvements provided solely by erasure coding scheme 2 are different for the two configurations represented by entries 460 and 465. Entries 460 and 465 state the fact that, despite providing any reliability relative to only one component, the improvements will be used for... Figure 1 Combining different schemes for different components of the SSD 130 can provide improvements, but the benefits of combining schemes for different components are not entirely orthogonal. In other words, a reliability option using multiple components may be superior to a reliability option using a single component, but when using two components to enhance reliability, the reliability rates of the two components cannot be simply multiplied together to determine the reliability rate. Therefore, for example, even... Figure 3 Memory chips 315-1 to 315-8 Figure 3 ECC module 330 and Figure 3 The RAID / erasure encoding module 335 contains 10... 10 A specific scheme with an error rate of 1 in 1 bit, even when using all three schemes together, does not necessarily result in a read or write error rate of 10. 30 The error rate of one bit out of every bit.

[0078] Therefore, if the reliability of a combination of options cannot be calculated as the product of the reliability rates of the individual options, how can the reliability rate of a particular configuration be determined for each entry in Reliability Table 405? Figure 1For the manufacturer of the SSD 130, the answer is to test each possible configuration individually. That is, various SSDs can be configured to use every possible combination of configurations. These SSDs can then be tested to understand their respective error rates (as well as space and performance overhead). This information can then be stored in a reliability table 405 for all SSDs manufactured according to the same specification.

[0079] Furthermore, despite Figure 4 For use only Figure 3 Memory chips 315-1 to 315-8 Figure 3 ECC module 330 and Figure 3 The reliability (as well as space and performance overhead) of each in the RAID / erasure coding module 335 is shown in the combination of different schemes, but the reliability table 405 can also be used to show the reliability (as well as space and performance overhead, if desired) of individual schemes. For example, the reliability table 405 may include information for... Figure 3 The entries for memory scheme 1 and memory scheme 2 of memory chips 315-1 to 315-8, without having for Figure 3 ECC module 330 or Figure 3 The associated scheme of the RAID / erasure encoding module 335: In this case, those entries can represent the reliability of using storage scheme 1 and storage scheme 2 respectively (without adding from...) Figure 3 ECC module 330 or Figure 3 (Any reliability enhancements to the RAID / erasure coding module 335). Similarly, reliability table 405 may include entries only for ECC scheme 1 and ECC scheme 2 and / or for erasure coding scheme 1 and erasure coding scheme 2.

[0080] Reliability table 405 can be searched along multiple axes. For example, reliability table 405 can be used to determine the reliability of a particular configuration (as well as other results such as space overhead and / or performance)). Reliability table 405 can also be used to identify configurations that support a particular level of reliability. That is, given a specific expected reliability rate, reliability table 405 can be searched to find the specific configuration that provides that reliability rate (or a superior reliability rate).

[0081] If multiple configurations can provide the desired reliability (or superior reliability), then Figure 3 The configuration module 340 can use any desired method to select between options. For example, Figure 3 The configuration module 340 can be configured to provide a maximum or minimum reliability rate that meets or exceeds the desired reliability rate. Alternatively, Figure 3The configuration module 340 can select a configuration that provides a sufficient reliability with minimal other results by using the configuration's space overhead results and / or performance results (if the configuration's space overhead results and / or performance results are included in the reliability table 405). Figure 3 The configuration module 340 can also use any other desired technology to select from multiple configurations that provide sufficient reliability.

[0082] To aid in identifying specific combinations in reliability table 405, reliability table 405 may also include an identifier 475. Identifier 475 can be a unique identifier assigned to each entry in reliability table 405. Thus, for example, entry 440 could be assigned identifier "1", entry 445 could be assigned identifier "2", and so on. Note that identifier 475 is not required to be numeric or sequential. For example, identifier 475 could be a random string, a hash of the information shown in the entry, or any other desired identifier. The only helpful element is that identifier 475 can be unique, such that a unique entry in reliability table 405 can be located using a given identifier.

[0083] Return to Figure 3 ,although Figure 3 The SSD 130 is shown as comprising eight memory chips 315-1 to 315-8 organized into four channels 320-1 to 320-4, but embodiments of the inventive concept can support any number of memory chips organized into any number of channels. Similarly, although Figure 3 The structure of an SSD is shown, but other storage devices (such as hard disk drives) can be implemented using different structures, but with similar potential benefits.

[0084] Figure 5 It shows Figure 1 Optional view of the SSD 130. Figure 5 In the diagram, SSD 130 is shown to include a RAID / erasure encoding module 335 and ECC modules 330-1, 330-2, and 330-3, which can operate along channels 320-1, 320-2, and 320-3, respectively. Channels 320-1, 320-2, and 320-3 include memory chips 315-1, 315-3, and 315-5. Therefore, data can be organized using RAID or erasure encoding to be stored across multiple memory chips, each of which can operate on different (or the same) channels.

[0085] Data can be received from applications 505-1 and 505-2 (although any number (or one or more) of applications may exist). Each application may have its own expected reliability 510-1 and 510-2. The expected reliability for each application represents the reliability rate that the application expects. Note that reliability 510-1 and 510-2 do not have to be consistent: each application may expect different reliability rates.

[0086] Each application 505-1 and 505-2 can have its own associated namespaces 515-1 and 515-2, respectively. Namespaces 515-1 and 515-2 provide a way to organize data from each application, making the data easily identifiable and / or grouped together. The use of namespaces 515-1 and 515-2 is optional.

[0087] Figure 5 This involves the concepts of deduplication and data compression. Deduplication refers to the idea that multiple copies of specific data can exist on an SSD 130. Instead of storing multiple copies, a single copy can be stored, with other copies referencing the stored copy. This reduces the amount of space used when storing multiple files.

[0088] For example, consider image files (such as pictures (photos)). It's not uncommon for the same photo to be stored multiple times with different filenames (because it's easy to forget that a photo was previously stored with different names). However, for the host or SSD 130, identifying that a particular file is a copy of a previously stored file is simple enough (assuming the SSD 130 includes some processing capabilities for identifying copy files). There's no need to store the same photo multiple times: a single copy (along with references from other folders where copies are stored) will suffice.

[0089] As an example of how data duplication can be identified, a password hash can be generated for each file. If two files have the same password hash, there is a strong possibility that the two files contain the same data. Therefore, determining whether a new file is a copy of a file already stored on the SSD 130 only requires: generating a password hash for the new file, comparing that password hash with the password hashes of other files (possibly using hash tables), and if a match is found, performing a (verbose) comparison of the data in the matching files.

[0090] Note that deduplication can operate on any desired unit of data. While files are a common unit for deduplication, other units can be blocks or pages (the unit of data within an SSD 130). Other units of data can also be used.

[0091] On the other hand, compression refers to a technique that allows data to be stored in a way that takes up less space than the original data. For example, consider the number 10. 100 (Often referred to as 10 to the power of 100 (googol)). Storing this number as a raw value would take approximately 2... 300 One bit or 2 38 One byte (assuming the computer is designed to store such a large integer). Alternatively, the number could also be represented as 100 zeros followed by one 1. Using an encoding scheme (such as RunLength Encoding), the value could be represented using four bytes: 1, 1, 100, 0 (i.e., one copy of the value "1" and 100 copies of the value "0"). Because four bytes are significantly less than 2... 38 The space savings from encoding this value are at least significant, given that it is only a few bytes. (Although "compression" as a term usually refers to algorithms that encode data using structures such as Huffman codes, in this context, "compression" refers to any technique that can be used to reduce the amount of space occupied by data, and therefore can include techniques that typically involve the use of terms such as "encoding".)

[0092] While deduplication and data compression have their benefits because they reduce the "footprint" of data that might appear on a storage device, they also have potential drawbacks, especially when discussing errors. For example, suppose a particular file stored on an SSD 130 actually contains data for five different files (one original file and four copies). Because the four copies point to the same data as the original file, if a single bit error exists anywhere in the stored files, that error will be read every time any of the different files is accessed. Therefore, a single bit error in the data stored on the SSD 130 is actually better understood as five bit errors: one identical bit error in the original file and one in each copy. In other words, deduplication has amplified the error rate of the SSD 130 by that many times over the number of referenced copies of the file.

[0093] Similarly, compression can affect the true error rate. Consider again how run-length encoding could be used to store 10... 100 Example. If the value "0" is replaced by "1" (a single bit error), the error will be amplified across the entire length of the code. Alternative representation: 10 100The encoding will now represent the number "1" repeated 101 times: a very different value. Therefore, a single bit error in compressed data may actually more effectively mean a large number of bit errors. As a general rule, a single bit error can be roughly amplified proportionally to the compression ratio of the technique used. Therefore, if the compression technique results in compressing the data by a factor of two (i.e., taking up half the space), a single bit error actually means two bit errors in the data; if the compression technique results in compressing the data by a factor of three (i.e., taking up one-third of the space), a single bit error actually means three bit errors in the data, and so on. (In the worst case, a single bit error in compressed data may actually make it impossible to recover the original data.)

[0094] Therefore, although Figure 4 The entries in Reliability Table 405 are a useful starting point for assessing the reliability of the SSD 130, but they do not fully represent its true reliability. Therefore, the SSD 130 (possibly via Configuration Module 340) can track the transactions being performed on behalf of Applications 505-1 and 505-2 (deduplication and data compression are two examples of transactions) and use those transactions to determine the multiplier. Then, (as per the SSD 130-based configuration from...) Figure 4 The reliability of the SSD 130 (as determined in Reliability Table 405) can be multiplied by this multiplier to determine the effective reliability of the SSD 130.

[0095] The multiplier used for reliability can be determined using any desired method. For example, an SSD 130 could track a specific transaction, determine the multiplier applicable to that transaction, and then retain the larger of that multiplier and previous multipliers. However, this approach assumes that the multipliers are independent of each other. Such an assumption is reasonable if deduplication is the only technique used that could introduce multipliers, or if compression is the only technique used that could introduce multipliers. However, if a compressed file subsequently undergoes deduplication, individual bit errors may double as a result of both space-saving schemes.

[0096] Therefore, the SSD 130 can not only track the highest multiplier to date, but also track the highest multiplier applicable to each space-saving scheme individually. In this way, the SSD 130 can consider not only whether a new multiplier is the highest for a single scheme, but also whether the multiplier can be used across schemes. For example, suppose the SSD 130 currently tracks the following: 2.0 for the highest compression multiplier, 5.0 for the highest deduplication multiplier, and 5.0 for the highest overall multiplier (based on the assumption that a file that has undergone compression has not been stored more than twice on the SSD 130). Then, if the SSD 130 tracks a file that has previously been compressed and deduplicated being written to for the third time, that would mean that three copies of that file are now stored on the SSD 130 (and have been deduplicated). Therefore, although the transaction does not increase the highest compression multiplier (because no new compression has occurred) or the highest deduplication multiplier (because the current maximum number of copies for any file is 5), the highest overall multiplier may increase to 6.0 (because there are three copies of the compressed file constrained by multiplier 2.0). Therefore, regardless of how much the reliability might otherwise be (e.g., in...) Figure 4 (The reliability rates listed in Reliability Table 405 can be multiplied by 6.0 to determine the effective reliability of the SSD 130. Optionally, the SSD 130 can track the highest multipliers used for compression and deduplication separately and apply both to the reliability to determine the minimum effective reliability of the SSD 130. (Because there may not be data stored on the SSD 130 that has undergone both compression and deduplication, this calculation may overemphasize the impact of transactions, but a conservative calculation can still be used.)

[0097] This impact of transactions on the effective reliability of the SSD 130 can also be used as a factor in selecting the configuration for the SSD 130. For example, knowing that a multiplier exists due to the data stored on the SSD 130, the configuration module 340 can use this multiplier when comparing the reliability of various configurations with the expected reliability 510-1 and 510-2 of applications 505-1 and 505-2. That is, simply using... Figure 4 Comparing the reliability listed in Reliability Table 405 with the expected reliability of 510-1 and 510-2 may be insufficient: given the data currently stored on the SSD 130, Figure 4 The reliability figures listed in Table 405 may need to be adjusted for multipliers to reflect the effective reliability of the SSD 130.

[0098] Figure 6 It shows in Figure 5 Application 505-1 and Figure 1The messages exchanged between the SSDs 130. In one embodiment of the inventive concept, application 505-1 may send a reliability message 605 to the SSD 130: the reliability message 605 may include Figure 5 Expected reliability 510-1. (Although in Figure 6 Not shown in the image, but Figure 5 Application 505-2, as well as any other application using the SSD 130, can also send their own desired reliability. Then, as shown by self-configuration 610, the SSD 130 can (using...) Figure 3 The configuration module 340) configures itself to satisfy all provided expected reliability (i.e., to satisfy all provided expected reliability by satisfying the most stringent reliability provided).

[0099] However, in another embodiment of the inventive concept, application 505-1 can send a reliability request 615. Reliability request 615 can request (as determined above) the effective reliability of SSD 130, and the effective reliability of SSD 130 can be returned as message 620. Application 505-1 can also send a reliability table request 625, which can request from SSD 130... Figure 4 Reliability Table 405: SSD 130 can be returned via message 630. Figure 4 The reliability table 405 is used to respond. Then, 505-1 can be applied to select the option that provides sufficient reliability ( Figure 5 The configuration (which provides the expected reliability of 510-1 or some superior reliability) can be sent to the SSD 130, and a configuration request 635 can be sent to identify... Figure 4 The SSD 130 can then configure itself according to the entries expected in the reliability table 405, as shown by the self-configuration 640.

[0100] However, note that self-configuration 640 is shown as a dashed line. There are two reasons for this. First, it is assumed that application 505-1 will compare the effective reliability rate received in message 620: if the effective reliability rate is higher than... Figure 5 If the expected reliability 510-1 is met, then application 505-1 will not send configuration request 635 (in this case, self-configuration 640 will not be needed). However, in some embodiments of the inventive concept, application 505-1 may not request effective reliability from SSD 130, but simply obtain it from... Figure 4The reliability table 405 selects the desired configuration, and a configuration request 635 is sent accordingly. In such an embodiment of the inventive concept, the SSD 130 (possibly via configuration module 340) can compare the effective reliability with the reliability of the configuration identified in configuration request 635. If the effective reliability of the SSD 130 is greater than the reliability of the configuration identified in configuration request 635, the SSD 130 can skip self-configuration 640 (because the current configuration is already good enough).

[0101] Secondly, as mentioned above, application 505-1 may not be able to operate in isolation: other applications (such as, Figure 5 Applications 505-2 may be sending their own configuration requests 635. In such a case, the SSD 130 may choose to self-configure in a way that satisfies all applications, and thus can be configured based on the configuration with the highest reliability (based on the assumption that the application requesting that configuration cannot be satisfied by a configuration with lower reliability). Therefore, although the SSD 130 can perform self-configuration 640, self-configuration 640 may involve a configuration different from the configuration specified in configuration request 635.

[0102] exist Figure 6 In the configuration module 340, configuration module 340 can be configured Figure 1 The SSD 130 responds to application 505-1. However, the configuration module 340 can also operate "spontaneously" to configure... Figure 1 The SSD 130. For example, given a desired reliability (among other possibilities, it could be as received from application 505-1 as reliability message 605). Figure 5 The expected reliability 510-1, or it may be Figure 1 In the case of SSD 130 (based on manufacturer-reported reliability), configuration module 340 can track... Figure 1 The effective reliability of the SSD130. If Figure 1 If the effective reliability of the SSD 130 should drop below the expected reliability, then the configuration module 340 can choose to provide a new configuration that offers the expected reliability (taking into account any multiplier factors) to ensure... Figure 1 The reliability of the SSD 130 remains at an acceptable level.

[0103] It's worth mentioning: How can the configuration module 340 be configured? Figure 1 The SSD 130. As discussed above, Figure 4 The entries in Reliability Table 405 specify that will be Figure 3 Memory chips 315-1 to 315-8 Figure 3 ECC module 330 and Figure 3The RAID / erasure encoding module 335 uses a specific scheme. For configuration... Figure 1 The configuration module 340 can instruct the SSD 130 on which scheme to use for these components. In other words, the configuration module 340 can instruct... Figure 3 The memory chips 315-1 to 315-8 store a specific number of bits in each cell and / or indicate Figure 3 The ECC module 330 uses a specific ECC scheme and / or indicates that... Figure 3 The RAID / erasure encoding module 335 uses a specific erasure encoding scheme. Note that the scheme for altering existing data can involve... Figure 1 The SSD 130 reads data and changes the scheme applied to that data to maintain sufficient reliability. Therefore, for example, if data is currently stored using four bits per QLC cell, and now needs to be stored using only two bits per QLC cell, then... Figure 3 Data in memory chips 315-1 to 315-8 can be read, temporarily buffered somewhere (some local storage device of server 110 or main memory), and then written back to memory chips 315-1 to 315-8 using a new storage scheme. Similarly, applying a new ECC scheme or erase encoding scheme can involve reading data from SSD 130 and writing data to SSD 130 to apply the change.

[0104] Figure 7 An embodiment of the invention is shown for use with respect to the inventive concept. Figure 1 The SSD 130 is configured to provide a flowchart of an example process for delivering the desired reliability. Figure 7 In block 705, Figure 3 The configuration module 340 can determine the... Figure 1 The expected reliability of the SSD 130. As discussed above, Figure 3 The configuration module 340 can select its own desired reliability, or it can... Figure 6 Reliability message 605 from Figure 5 Application 505-1 receiver Figure 5 Expected reliability 510-1. In block 710, Figure 3 The configuration module 340 can be determined Figure 1 The SSD 130's effective reliability. In block 715, Figure 3 The configuration module 340 can Figure 1The effective reliability of the SSD 130 is compared with the expected reliability (taking into account any multipliers due to transactions). If the effective reliability is sufficient to meet the expected reliability (i.e., the effective reliability is not less than the expected reliability), the process is completed, and Figure 3 The configuration module 340 no longer needs to do anything.

[0105] On the other hand, if the effective reliability is less than the expected reliability, then in block 720, Figure 3 The configuration module 340 can access Figure 4 The reliability table 405 is used to consider the entries therein. In block 725, Figure 3 The configuration module 340 can be used Figure 4 Select entries from Reliability Table 405 that have a reliability at least as high as the expected reliability (considering any multiplier). In Block 730, Figure 3 The configuration module 340 can be configured according to the Figure 4 Configure the settings in the selected item of Reliability Table 405. Figure 1 The SSD 130 was then processed.

[0106] Figure 8 It shows the use of Figure 1 A flowchart illustrating the example process of an SSD 130 configuring itself. In Figure 8 In block 805, Figure 3 The configuration module 340 can Figure 3 One or more of the memory chips 315-1 to 315-8 are configured to use a specific memory scheme. In block 810, Figure 3 The configuration module 340 can Figure 3 The ECC module 330 is configured to use a specific error correction code scheme. In block 815, Figure 3 The configuration module 340 can Figure 3 The RAID / erasure encoding module 335 is configured to use a specific erasure encoding scheme. As shown by dashed lines 820, 825 and 830, blocks 805, 810 and 815 are all independently optional and can be omitted.

[0107] Figures 9A to 9B It shows the use of Figure 1 A flowchart illustrating an example process for determining the expected reliability of an SSD 130. Figure 9A In block 905, Figure 1 The SSD 130 can receive Figure 6 Reliability message 605 can specify the expected reliability for SSD 130.

[0108] Optionally, in block 910 ( Figure 9B), Figure 1 The SSD 130 can be obtained from Figure 5 Application 505-1 receiver Figure 6 Reliability request 615. In block 915, Figure 1 The SSD 130 can be confirmed. Figure 1 The effective reliability of the SSD130. In block 920, the SSD130 can be used as an effective reliability... Figure 6 Message 620 sent Figure 5 Application 505-1. Note that, as shown by dashed line 925, blocks 910, 915, and 920 are optional.

[0109] In block 930, Figure 5 Application 505-1 can send Figure 6 The reliability table request is in block 625. In block 935, Figure 1 The SSD130 can be obtained from Figure 3 The reliability table of storage device 345 was obtained. Figure 4 Reliability table 405. In block 940, Figure 1 The SSD 130 can Figure 4 Reliability table 405 is sent as message 630 Figure 5 Application 505-1. Finally, in block 945, Figure 5 Application 505-1 can send configuration request 635 to Figure 1 SSD 130, request Figure 3 The configuration module 340 is configured according to the reliability table 405. Figure 6 Configure the entries identified in configuration request 635. Figure 1 The SSD 130.

[0110] Figure 10 It shows the use of Figure 1 SSD 130 confirmed Figure 1 A flowchart illustrating an example process for ensuring the effective reliability of the SSD 130. Figure 10 In block 1005, Figure 1 The SSD 130 can (at least, according to) Figure 1 (Current configuration of SSD 130) Figure 1 The SSD 130's advertised reliability. At block 1010, the SSD 130 can be traced by... Figure 5 Application 505-1 (or representative) Figure 5 The application 505-1) requests the current transaction. In block 1015, Figure 1 The SSD 130 can determine the multiplier (or more than one) in response to the current transaction (and previous transactions). Finally, in block 1020, Figure 1The SSD 130 can multiply the advertised reliability by one or more multipliers to determine... Figure 1 The SSD 130's effective reliability.

[0111] Figures 11A to 11B An embodiment of the invention is shown for use with respect to the inventive concept. Figure 5 Application 505-1 instruction Figure 1 The SSD 130 provides a flowchart of an example process for achieving expected reliability. Figure 11A In block 1105, Figure 5 The application of 505-1 can simply... Figure 5 Expected reliability 510-1 (as Figure 6 Reliability message 605) was sent to Figure 1 The SSD is 130. At this time, Figure 5 Application 505-1 can be completed, providing support for Figure 5 The expected reliability of 510-1 is left to the people. Figure 1 The SSD 130.

[0112] Optionally, in block 1110, Figure 5 Application 505-1 can Figure 6 Reliability request 615 was sent Figure 1 The SSD is 130. In block 1115, Figure 5 Application 505-1 can be used as Figure 6 Message 620 received Figure 1 The current effective reliability of the SSD 130. In block 1120, Figure 5 Application 505-1 can (such as) Figure 6 (Message 620 received) Figure 1 The effective reliability of the SSD 130 and Figure 5 Compare the expected reliability of 510-1. If... Figure 1 The effective reliability of the SSD 130 is at least comparable to Figure 5 If the expected reliability is as high as 510-1, then the process can end (because no further action is required).

[0113] On the other hand, if Figure 1 The effective reliability of the SSD 130 is less than Figure 5 The expected reliability 510-1 (or, if as indicated by the dashed arrow 1125, Figure 5 Application 505-1 Select Request to configure with specific settings Figure 1 The SSD 130, and with Figure 1 (Irrelevant to the effective reliability of SSD 130), then in block 1130 ( Figure 11B ) place, Figure 5Application 505-1 can Figure 6 Reliability table request 625 sent Figure 1 The SSD is 130. In block 1135, Figure 1 The SSD 130 can Figure 4 Reliability table 405 is sent as message 630 Figure 5 Application 505-1. In block 1140, Figure 5 Application 505-1 can be used Figure 4 Select the entry that provides the desired reliability from reliability table 405. Finally, in block 1145, Figure 5 Application 505-1 can send Figure 6 Configuration request 635, request based on Figure 4 Select the item from Reliability Table 405 to configure Figure 1 The SSD 130.

[0114] exist Figures 7 to 11B Some embodiments of the inventive concept are shown in the figure. However, those skilled in the art will recognize that other embodiments of the inventive concept are also possible by changing the order of blocks, by omitting blocks, or by including links not shown in the figure. Whether explicitly described or not, all such variations of the flowchart are considered embodiments of the inventive concept.

[0115] Embodiments of the inventive concept offer technical advantages over existing technologies. In conventional systems, the reliability of storage devices is set by the manufacturer and is largely beyond the user's control. Embodiments of the inventive concept not only empower consumers with a degree of control over the reliability of storage devices but also allow for the automation of such management. Applications can specify desired reliability (or can specify a particular configuration of the storage device to achieve the desired reliability). The storage device can then maintain that level of reliability by changing the configuration as needed based on its usage.

[0116] The following discussion is intended to provide a brief, general description of one or more suitable machines in which specific aspects of the inventive concept can be implemented. One or more machines can be controlled at least in part by input from conventional input devices (such as keyboards, mice, etc.) and by instructions received from another machine, interaction with a virtual reality (VR) environment, biometric feedback, or other input signals. As used herein, the term "machine" is intended to broadly encompass a single machine, a virtual machine, or a system of machines, virtual machines, or devices that are communicatively combined and operate together. Exemplary machines include computing devices (such as personal computers, workstations, servers, portable computers, handheld devices, telephones, tablets, etc.) and transportation devices such as private or public transportation (e.g., cars, trains, taxis, etc.).

[0117] One or more machines may include embedded controllers (such as programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), embedded computers, smart cards, etc.). One or more machines may utilize one or more connections to one or more remote machines, such as via network interfaces, modems, or other communication couplings. Machines may be interconnected via physical and / or logical networks (such as intranets, the Internet, local area networks, wide area networks, etc.). Those skilled in the art will understand that network communications may utilize technologies including radio frequency (RF), satellite, microwave, and IEEE 802.11. Various wired and / or wireless short- or long-range carrier waves and protocols, including optical, infrared, cable, and laser technologies.

[0118] Embodiments of this invention can be described by referring to or in conjunction with associated data, including functions, procedures, data structures, applications, etc., which, when accessed by a machine, enable the machine to perform tasks or define abstract data types or low-level hardware contexts. For example, the associated data can be stored in volatile and / or non-volatile memory (e.g., RAM, ROM, etc.), or in other storage devices and their associated storage media (including hard disk drives, floppy disks, optical storage devices, magnetic tape, flash memory, memory sticks, digital video disks, bio-storage devices, etc.). The associated data can be transmitted over a transmission environment (including physical and / or logical networks) in the form of packets, serial data, parallel data, propagated signals, etc., and can be used in compressed or encrypted formats. The associated data can be used in a distributed environment and stored locally and / or remotely for machine access.

[0119] Embodiments of the inventive concept may include a tangible, non-transitory machine-readable medium comprising instructions executable by one or more processors, the instructions including instructions for performing elements of the inventive concept as described herein.

[0120] The various operations described above can be performed by any suitable means capable of performing those operations (such as various hardware and / or software components, circuits, and / or modules). The software may include an ordered list of executable instructions for implementing logical functions and may be implemented in any processor-readable medium for use by, or in conjunction with, an instruction execution system, device, or apparatus (such as a single-core or multi-core processor or a system containing a processor).

[0121] The methods or algorithms described in conjunction with the embodiments disclosed herein, as well as the blocks or steps of functionality, can be implemented directly in hardware, in a software module executed by a processor, or a combination of both. If implemented in software, the functionality can be stored as one or more instructions or code on or transferred on a tangible, non-transitory computer-readable medium. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0122] Having described and illustrated the principles of the inventive concept with reference to the illustrated embodiments, it will be appreciated that the illustrated embodiments can be modified in arrangement and detail without departing from such principles, and can be combined in any desired manner. Furthermore, although the foregoing discussion has focused on particular embodiments, other configurations are contemplated. Specifically, even when expressions such as "according to an embodiment of the inventive concept" are used herein, these phrases are intended to encompass the general possibilities of embodiments and are not intended to limit the inventive concept to a particular embodiment configuration. As used herein, these terms can refer to the same or different embodiments that can be combined into other embodiments.

[0123] The foregoing illustrative embodiments are not to be construed as limiting the inventive concept. Although some embodiments have been described, it will be readily understood by those skilled in the art that many modifications are possible with respect to those embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

[0124] The embodiments of the inventive concept can be extended to the following statements without limitation:

[0125] Statement 1: Embodiments of the inventive concept include a solid-state drive (SSD), the SSD comprising:

[0126] An interface used to receive read and write requests from the first application on the host;

[0127] A storage device for data, the storage device comprising at least one chip;

[0128] An SSD controller is used to process read and write requests from a first application on the host using the storage device;

[0129] Configuration module, used to configure SSD; and

[0130] A storage device for a reliability table, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the SSD and a first reliability of the first configuration of the SSD, and the second entry identifying a second configuration of the SSD and a second reliability of the second configuration of the SSD.

[0131] Statement 2. Embodiments of the inventive concept include the SSD described in Statement 1, wherein the interface can receive configuration requests from a first application on the host.

[0132] Statement 3: An embodiment of the inventive concept includes the SSD described in Statement 2, wherein the configuration request includes an identifier of one of the first and second entries in the reliability table.

[0133] Statement 4. An embodiment of the inventive concept includes the SSD described in Statement 3, wherein the configuration module can reconfigure the SSD based on an identifier from one of the first and second entries in the reliability table.

[0134] Statement 5. Embodiments of the inventive concept include the SSD described in Statement 1, wherein the interface can receive a reliability message from a first application on the host, the reliability message including a first desired reliability for the first application on the host.

[0135] Statement 6. Embodiments of the inventive concept include the SSD described in Statement 5, wherein the configuration module can configure the SSD based at least on a first desired reliability according to one of a first entry and a second entry in a reliability table.

[0136] Statement 7. Embodiments of the inventive concept include the SSD as described in Statement 6, wherein the configuration module can configure the SSD based at least on a first desired reliability for a first application on the host and a second desired reliability for a second application on the host, according to one of a first entry and a second entry in a reliability table.

[0137] Statement 8. Embodiments of the inventive concept include the SSD according to Statement 1, wherein the at least one chip provides at least a first storage scheme having a first chip reliability and a second storage scheme having a second chip reliability.

[0138] Statement 9. Embodiments of the inventive concept include the SSD described in Statement 8, wherein a first configuration of the SSD identifies a first storage scheme, and a second configuration of the SSD identifies a second storage scheme.

[0139] Statement 10: Embodiments of the inventive concept include the SSD as described in Statement 1, the SSD further including an error correction code (ECC) module, the ECC module providing at least a first ECC scheme with a first ECC reliability and a second ECC scheme with a second ECC reliability.

[0140] Statement 11: An embodiment of the inventive concept includes the SSD described in Statement 10, wherein a first configuration of the SSD identifies a first ECC scheme, and a second configuration of the SSD identifies a second ECC scheme.

[0141] Statement 12: Embodiments of the inventive concept include the SSD described in Statement 1, wherein the SSD further includes at least one of an erasure coding module and a redundant array of independent disks (RAID) module, the erasure coding module providing at least a first erasure coding scheme having a first erasure coding reliability and a second erasure coding scheme having a second erasure coding reliability, and the RAID module providing at least a first RAID scheme having a first RAID reliability and a second RAID scheme having a second RAID reliability.

[0142] Statement 13. An embodiment of the inventive concept includes the SSD described in Statement 12, wherein a first configuration of the SSD identifies at least one of a first erasure coding scheme and a first RAID scheme, and a second configuration of the SSD identifies at least one of a second erasure coding scheme and a second RAID scheme.

[0143] Statement 14. An embodiment of the inventive concept includes the SSD according to Statement 1, wherein a first entry in the reliability table identifies at least one of a first space overhead and a first performance of a first configuration of the SSD, and a second entry in the reliability table identifies at least one of a second space overhead and a second performance of a second configuration of the SSD.

[0144] Statement 15. Embodiments of the inventive concept include the SSD described in Statement 1, wherein the at least one chip includes at least one NAND flash memory chip.

[0145] Statement 16. An embodiment of the inventive concept includes a method comprising:

[0146] Determine the expected reliability for a solid-state drive (SSD), which includes a storage device for data and includes at least one chip;

[0147] The first entry in the SSD reliability table is accessed from the SSD, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the SSD and a first reliability of the first configuration of the SSD, the second entry identifying a second configuration of the SSD and a second reliability of the second configuration of the SSD; and

[0148] Configure the SSD according to the first entry.

[0149] Statement 17. Embodiments of the inventive concept include the method according to Statement 16, wherein:

[0150] The first entry includes a first storage scheme for the chip;

[0151] The second entry includes a second memory scheme for the chip; and

[0152] The steps for configuring an SSD according to the first entry include configuring the chip according to a first storage scheme or a second storage scheme.

[0153] Statement 18. Embodiments of the inventive concept include the method according to Statement 16, wherein:

[0154] SSDs include an error correction code (ECC) module;

[0155] The first entry includes the first ECC scheme for the ECC module;

[0156] The second entry includes a second ECC scheme for the ECC module; and

[0157] The steps for configuring the SSD according to the first entry include configuring the ECC module according to either the first ECC scheme or the second ECC scheme.

[0158] Statement 19. Embodiments of the inventive concept include the method according to Statement 16, wherein:

[0159] The SSD includes at least one of an erase coding module and a redundant array of independent disks (RAID) module;

[0160] The first entry includes at least one of a first erasure coding scheme for an erasure coding module and a first RAID scheme for a RAID module;

[0161] The second entry includes at least one of a second erasure coding scheme for the erasure coding module and a second RAID scheme for the RAID module; and

[0162] The steps for configuring an SSD according to the first entry include configuring an erase coding module according to a first erase coding scheme or a second erase coding scheme, and configuring a RAID module according to a first RAID scheme or a second RAID scheme, at least one of the following:

[0163] Statement 20: Embodiments of the inventive concept include the method according to Statement 16, wherein the step of determining the desired reliability for a solid-state drive (SSD) includes receiving the desired reliability from an application on the host at the SSD.

[0164] Statement 21: Embodiments of the inventive concept include the method according to Statement 20, wherein the step of accessing the first entry in the reliability table from the SSD includes:

[0165] Access the first and second entries in the reliability table; and

[0166] The first entry is identified as having a reliability at least as high as the expected reliability.

[0167] Statement 22. Embodiments of the inventive concept include the method according to Statement 16, the method further comprising:

[0168] At the SSD, receive a reliability request for valid SSD reliability from the application on the host.

[0169] Determine the effective reliability of the SSD; and

[0170] Applications that deliver effective reliability from SSDs to the host.

[0171] Statement 23. Embodiments of the inventive concept include the method according to Statement 22, wherein the step of determining the effective reliability of the SSD includes:

[0172] Determine the reliability of SSD notifications;

[0173] Track operations on the SSD;

[0174] The multiplier is determined based on operations performed on the SSD; and

[0175] The reliability of the notification is multiplied by a multiplier to determine the effective reliability.

[0176] Statement 24. Embodiments of the inventive concept include the method according to Statement 16, wherein the step of accessing a first entry in the reliability table from the SSD includes receiving an identifier of the first entry in the reliability table from an application on the host at the SSD.

[0177] Statement 25. Embodiments of the inventive concept include the method according to Statement 24, wherein the step of accessing the first entry in the reliability table from the SSD further includes sending the first entry in the reliability table from the SSD to an application on the host.

[0178] Statement 26. Embodiments of the inventive concept include the method according to Statement 16, wherein:

[0179] The first entry in the reliability table identifies at least one of the first space overhead and first performance of the first configuration of the SSD;

[0180] The second entry in the reliability table identifies at least one of the second space overhead and second performance of the second configuration of the SSD; and

[0181] The steps to access the first entry in the reliability table from the SSD include accessing the first entry in the reliability table from the SSD based on at least one of expected space overhead and expected performance, as well as expected reliability.

[0182] Statement 27. Embodiments of the inventive concept include the method according to Statement 16, wherein the at least one chip comprises at least one NAND flash memory chip.

[0183] Statement 28. An embodiment of the inventive concept includes a method comprising:

[0184] A reliability request is sent from the application on the host to the SSD, requesting the SSD to ensure its effective reliability.

[0185] Effective and reliable reception of SSDs from SSDs at the application site on the host machine;

[0186] The reliability table request is sent from the application on the host to the SSD, and the reliability table request requests the reliability table stored on the SSD.

[0187] At the application on the host, a reliability table is received from the SSD. Each entry in the reliability table identifies the SSD configuration and the reliability of the SSD configuration.

[0188] Entries in the reliability table should be selected based at least on the expected reliability for applications used on the host machine; and

[0189] The configuration request is sent from the application on the host to the SSD, and the configuration request identifies entries in the reliability table.

[0190] Statement 29. Embodiments of the inventive concept include the method according to Statement 28, the method further comprising:

[0191] Compare the effective reliability of the SSD with the expected reliability for applications used on a host machine; and

[0192] At least based on the fact that the effective reliability of the SSD exceeds the expected reliability for applications used on the host, no configuration requests are sent to the SSD.

[0193] Statement 30. Embodiments of the inventive concept include the method according to Statement 28, wherein the step of selecting an entry in a reliability table based at least on the expected reliability for an application on a host includes: selecting an entry in the reliability table whose SSD configuration has a reliability at least as high as the expected reliability.

[0194] Statement 31: Embodiments of the inventive concept include the method according to Statement 28, wherein:

[0195] Each entry in the reliability table also identifies at least one of the SSD's primary space overhead and primary performance characteristics.

[0196] The second entry in the reliability table identifies at least one of the second space overhead and the second performance; and

[0197] The step of selecting entries in the reliability table based at least on the expected reliability for the application on the host includes selecting entries in the reliability table based at least on at least one of expected space overhead and expected performance and the expected reliability for the application on the host.

[0198] Statement 32: Embodiments of the inventive concept include an article comprising a non-transitory storage medium having instructions stored thereon, which, when executed by a machine, cause:

[0199] Determine the expected reliability for a solid-state drive (SSD), which includes a storage device for data and includes at least one chip;

[0200] The first entry in the SSD reliability table is accessed from the SSD, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the SSD and a first reliability of the first configuration of the SSD, the second entry identifying a second configuration of the SSD and a second reliability of the second configuration of the SSD; and

[0201] Configure the SSD according to the first entry.

[0202] Statement 33. Embodiments of the inventive concept include the articles described in Statement 32, wherein:

[0203] The first entry includes a first storage scheme for the chip;

[0204] The second entry includes a second memory scheme for the chip; and

[0205] The steps for configuring an SSD according to the first entry include configuring the chip according to a first storage scheme or a second storage scheme.

[0206] Statement 34. Embodiments of the inventive concept include the articles described in Statement 32, wherein:

[0207] SSDs include an error correction code (ECC) module;

[0208] The first entry includes the first ECC scheme for the ECC module;

[0209] The second entry includes a second ECC scheme for the ECC module; and

[0210] The steps for configuring the SSD according to the first entry include configuring the ECC module according to either the first ECC scheme or the second ECC scheme.

[0211] Statement 35. Embodiments of the inventive concept include the articles described in Statement 32, wherein:

[0212] The SSD includes at least one of an erase coding module and a redundant array of independent disks (RAID) module;

[0213] The first entry includes at least one of a first erasure coding scheme for an erasure coding module and a first RAID scheme for a RAID module;

[0214] The second entry includes at least one of a second erasure coding scheme for the erasure coding module and a second RAID scheme for the RAID module; and

[0215] The steps for configuring an SSD according to the first entry include configuring an erase coding module according to a first erase coding scheme or a second erase coding scheme, and configuring a RAID module according to a first RAID scheme or a second RAID scheme, at least one of the following:

[0216] Statement 36. Embodiments of the inventive concept include the article described in Statement 32, wherein the step of determining the desired reliability for a solid-state drive (SSD) includes receiving the desired reliability from an application on the host at the SSD.

[0217] Statement 37. Embodiments of the inventive concept include the article described in Statement 36, wherein the step of accessing the first entry in the reliability table from the SSD includes:

[0218] Access the first and second entries in the reliability table; and

[0219] The first entry is identified as having a reliability at least as high as the expected reliability.

[0220] Statement 38. Embodiments of the inventive concept include the article according to Statement 32, wherein a non-transitory storage medium has additional instructions stored thereon, which, when executed by a machine, cause:

[0221] At the SSD, receive a reliability request for valid SSD reliability from the application on the host.

[0222] Determine the effective reliability of the SSD; and

[0223] Applications that deliver effective reliability from SSDs to the host.

[0224] Statement 39. Embodiments of the inventive concept include the article described in Statement 38, wherein the step of determining the effective reliability of the SSD includes:

[0225] Determine the reliability of SSD notifications;

[0226] Track operations on the SSD;

[0227] Determining the multiplier based on operations on the SSD; and

[0228] The reliability of the notification is multiplied by a multiplier to determine the effective reliability.

[0229] Statement 40. Embodiments of the inventive concept include the article according to Statement 32, wherein the step of accessing a first entry in a reliability table from an SSD includes receiving an identifier of the first entry in the reliability table from an application on a host at the SSD.

[0230] Statement 41: Embodiments of the inventive concept include the article according to Statement 40, wherein the step of accessing a first entry in a reliability table from an SSD includes sending the first entry in the reliability table from the SSD to an application on a host.

[0231] Statement 42: Embodiments of the inventive concept include the articles described in Statement 32, wherein:

[0232] The first entry in the reliability table identifies at least one of the first space overhead and first performance of the first configuration of the SSD;

[0233] The second entry in the reliability table identifies at least one of the second space overhead and second performance of the second configuration of the SSD; and

[0234] The steps to access the first entry in the reliability table from the SSD include accessing the first entry in the reliability table from the SSD based on at least one of expected space overhead and expected performance, as well as expected reliability.

[0235] Statement 43: One embodiment of the present invention includes the article described in Statement 32, wherein the at least one chip comprises at least one NAND flash memory chip.

[0236] Statement 44. Embodiments of the inventive concept include an article comprising a non-transitory storage medium having instructions stored thereon, which, when executed by a machine, cause:

[0237] A reliability request is sent from the application on the host to the SSD, requesting the SSD to ensure its effective reliability.

[0238] Effective and reliable reception of SSDs from SSDs at the application site on the host machine;

[0239] The reliability table request is sent from the application on the host to the SSD, and the reliability table request requests the reliability table stored on the SSD.

[0240] At the application on the host, a reliability table is received from the SSD. Each entry in the reliability table identifies the SSD configuration and the reliability of the SSD configuration.

[0241] Entries in the reliability table should be selected based at least on the expected reliability for applications used on the host machine; and

[0242] The configuration request is sent from the application on the host to the SSD, and the configuration request identifies entries in the reliability table.

[0243] Statement 45. Embodiments of the inventive concept include the article according to Statement 44, wherein a non-transitory storage medium has additional instructions stored thereon, which, when executed by a machine, cause:

[0244] Compare the effective reliability of the SSD with the expected reliability for applications used on a host machine; and

[0245] At least based on the fact that the effective reliability of the SSD exceeds the expected reliability for applications used on the host, no configuration requests are sent to the SSD.

[0246] Statement 46. Embodiments of the inventive concept include the article according to Statement 44, wherein the step of selecting an entry in a reliability table based at least on the expected reliability for an application on a host includes selecting an entry in the reliability table whose SSD configuration has a reliability at least as high as the expected reliability.

[0247] Statement 47. Embodiments of the inventive concept include the articles described in Statement 44, wherein:

[0248] Each entry in the reliability table also identifies at least one of the SSD's primary space overhead and primary performance characteristics.

[0249] The second entry in the reliability table identifies at least one of the second space overhead and the second performance; and

[0250] The step of selecting entries in the reliability table based at least on the expected reliability for the application on the host includes selecting entries in the reliability table based at least on at least one of expected space overhead and expected performance and the expected reliability for the application on the host.

[0251] Therefore, given the wide variety of substitutions for the embodiments described herein, this detailed description and the appended materials are intended to be illustrative only and should not be considered as limiting the scope of the inventive concept. Thus, all such modifications that may fall within the scope and spirit of the claims and their equivalents are protected as claimed by the inventive concept.

Claims

1. A solid-state drive, comprising: An interface used to receive read and write requests from the first application on the host; A storage device for data, the storage device comprising at least one chip; A solid-state drive controller for using the storage device to process read and write requests from a first application on the host. A configuration module is used to configure the solid-state drive; as well as A storage device for a reliability table, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the solid-state drive and a first reliability of the first configuration of the solid-state drive, and the second entry identifying a second configuration of the solid-state drive and a second reliability of the second configuration of the solid-state drive.

2. The solid-state driver according to claim 1, wherein, The interface receives configuration requests from the first application on the host.

3. The solid-state driver according to claim 2, wherein, The configuration request includes the identifier of one of the first and second entries in the reliability table.

4. The solid-state driver according to claim 1, wherein, The interface receives a reliability message from a first application on the host, the reliability message including a first expected reliability for the first application on the host.

5. The solid-state driver according to claim 4, wherein, The configuration module configures the solid-state drive based at least on a first expected reliability and according to one of the first and second entries in the reliability table.

6. The solid-state driver according to claim 1, wherein, The at least one chip provides at least a first storage scheme with first chip reliability and a second storage scheme with second chip reliability.

7. The solid-state driver according to claim 6, wherein, The first configuration of the solid-state drive identifies a first storage scheme, and the second configuration of the solid-state drive identifies a second storage scheme.

8. The solid-state driver according to any one of claims 1 to 7 further includes an error correction code module, wherein the error correction code module provides at least a first error correction code scheme having a first error correction code reliability and a second error correction code scheme having a second error correction code reliability.

9. The solid-state driver according to claim 8, wherein, The first configuration of the solid-state drive identifies a first error correction code scheme, and the second configuration of the solid-state drive identifies a second error correction code scheme.

10. The solid-state drive according to any one of claims 1 to 7, further comprising at least one of an erase coding module and a RAID module, wherein the erase coding module provides at least a first erase coding scheme with a first erase coding reliability and / or a second erase coding scheme with a second erase coding reliability, and the RAID module provides at least a first RAID scheme with a first RAID reliability and / or a second RAID scheme with a second RAID reliability.

11. The solid-state driver according to claim 10, wherein, The first configuration of the solid-state drive identifies at least one of a first erase coding scheme and a first RAID scheme, and the second configuration of the solid-state drive identifies at least one of a second erase coding scheme and a second RAID scheme.

12. A method of operating a solid-state drive, comprising: Determine the expected reliability for a solid-state drive, which includes a storage device for data, the storage device including at least one chip; Accessing a first entry in a reliability table from a solid-state drive, the reliability table including at least a first entry and a second entry, the first entry identifying a first configuration of the solid-state drive and a first reliability of the first configuration of the solid-state drive, the second entry identifying a second configuration of the solid-state drive and a second reliability of the second configuration of the solid-state drive; and Configure the solid-state drive according to the first entry.

13. The method according to claim 12, wherein: The first entry includes a first storage scheme for the chip; The second entry includes a second storage scheme for the chip; as well as The steps for configuring a solid-state drive according to the first entry include: configuring the chip according to a first storage scheme or a second storage scheme.

14. The method according to claim 12, wherein: Solid-state drives include error correction code modules; The first entry includes a first error correction code scheme for the error correction code module; The second entry includes a second error correction code scheme for the error correction code module; as well as The steps for configuring the solid-state drive according to the first entry include: configuring the error correction code module according to the first error correction code scheme or the second error correction code scheme.

15. The method according to claim 12, wherein: The solid-state drive includes at least one of an erase coding module and a RAID module; The first entry includes at least one of a first erasure coding scheme for an erasure coding module and a first RAID scheme for a RAID module; The second entry includes at least one of a second erasure coding scheme for the erasure coding module and a second RAID scheme for the RAID module; as well as The steps of configuring a solid-state drive according to the first item include: configuring an erase coding module according to a first erase coding scheme or a second erase coding scheme, and configuring at least one of a RAID module according to a first RAID scheme or a second RAID scheme.

16. The method according to claim 12, wherein, The steps to determine the expected reliability for a solid-state drive include receiving the expected reliability from the application on the host at the solid-state drive.

17. The method according to claim 16, wherein, The steps to access the first entry in the reliability table from a solid-state drive include: Access the first and second entries in the reliability table; and The first entry is identified as having a reliability at least as high as the expected reliability.

18. The method according to claim 12, wherein, The steps to access the first entry in the reliability table from the solid-state drive include: receiving the identifier of the first entry in the reliability table from the application on the host at the solid-state drive.

19. A method of operating a solid-state drive, comprising: A reliability request is sent from the application on the host to the solid-state drive, requesting the effective reliability of the solid-state drive. The application on the host machine receives effective reliability data from the solid-state drive. The reliability table request is sent from the application on the host to the solid-state drive, and the reliability table request requests the reliability table stored on the solid-state drive. At the application level on the host, a reliability table is received from the solid-state drive. Each entry in the reliability table identifies the configuration of the solid-state drive and the reliability of the solid-state drive configuration. Entries in the reliability table should be selected based at least on the expected reliability for applications used on the host machine; as well as A configuration request is sent from the application on the host to the solid-state drive, and the configuration request identifies entries in the reliability table.

20. The method according to claim 19, wherein, The step of selecting entries in the reliability table based at least on the expected reliability for applications on the host machine includes: selecting entries in the reliability table whose solid-state drive configuration has a reliability at least as high as the expected reliability.

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