Executing circuits using disposable states

Abstract

An execution circuit is provided. A storage circuit retains a storage state of the execution circuit. An operation receiving circuit receives an operation signal corresponding to an operation to be performed from an issue circuit, the operation to be performed accessing the storage state of the execution circuit from the storage circuit. A function circuit seeks to perform the operation in response to the operation signal by accessing the storage state of the execution circuit from the storage circuit. A deletion request receiving circuit receives a deletion signal and deletes the storage state of the execution circuit from the storage circuit in response to the deletion signal. A state loss indicating circuit responds to the operation signal by indicating an error when the storage state of the execution circuit is not present and is required for the operation. Furthermore, a data processing apparatus is provided comprising an issue circuit for issuing an operation to an execution circuit. The execution circuit stores a storage state accessed during execution of the operation, and an error detection circuit detects an error indication from the execution circuit that the storage state is required for performing the operation and that the storage state is deleted.

Description

Technical Field

[0001] This technology relates to data processing, and in particular to the use of execution circuits that can be found in pipelines. Background Technology

[0002] In data processing devices, it may be desirable to allow users to extend the instruction set to support additional execution units. Such execution units can be used to provide efficient hardware implementations of specialized processing that would otherwise be time-consuming using a general-purpose execution unit. For example, the instruction set can be extended to provide cryptographic instructions that encrypt data using a key. Using a traditional general-purpose ALU might require many processor cycles. However, processing time can be improved by providing a dedicated cryptographic unit specifically designed to perform cryptographic operations much faster than a general-purpose ALU, which is typically designed to perform many other operations. Cryptographic instructions can then be provided to specifically use the cryptographic unit instead of the ALU. However, one limitation of doing so is that storing the execution unit's state is problematic. In particular, such state may have to be saved and restored as part of a context switch, which not only increases the time spent performing context switches but also adds to its complexity, as the data to be stored and restored must be determined. There are also difficulties in providing memory access for such execution units, as this requires various security and permission checks. These difficulties can be mitigated by preventing the execution unit from storing its state, but this limits the complexity of the execution unit and may prevent the execution of many functions. Summary of the Invention

[0003] From the first exemplary configuration, an execution circuit is provided, comprising: a storage circuit for maintaining a stored state of the execution circuit; an operation receiving circuit for receiving an operation signal corresponding to an operation to be performed from a issuing circuit, the operation accessing the stored state of the execution circuit from the storage circuit; a function circuit for seeking to perform an operation in response to the operation signal by accessing the stored state of the execution circuit from the storage circuit; a deletion request receiving circuit for receiving a deletion signal and deleting the stored state of the execution circuit from the storage circuit in response to the deletion signal; and a state loss indication circuit for responding to the operation signal by indicating an error when the stored state of the execution circuit is absent and required for the operation.

[0004] From a second exemplary configuration, a data processing method is provided, the data processing method comprising: maintaining a storage state of an execution circuit; receiving from a publishing circuit an operation signal corresponding to an operation to be performed, the operation accessing the storage state of the execution circuit; seeking to perform the operation in response to the operation signal by accessing the storage state of the execution circuit; receiving a deletion signal and deleting the storage state of the execution circuit in response to the deletion signal; and responding to the operation signal by indicating an error when the storage state of the execution circuit does not exist and is required for the operation.

[0005] From a third exemplary configuration, a computer program is provided for controlling a host data processing device to provide an instruction execution environment. The computer program includes: a data structure for maintaining a stored state; operation receiving programming logic for receiving an operation signal corresponding to an operation to be performed from issuing programming logic, the operation accessing the stored state; function programming logic for seeking to perform an operation in response to the operation signal by accessing the stored state from the data structure; deletion request receiving programming logic for receiving a deletion signal and deleting the stored state from the data structure in response to the deletion signal; and state loss indication programming logic for responding to the operation signal by indicating an error when the stored state is absent and required for the operation.

[0006] From a fourth exemplary configuration, a data processing apparatus is provided, comprising: a publishing circuit for publishing an operation to an execution circuit, wherein the execution circuit is adapted to store a storage state accessed during the execution of the operation; and an error detection circuit for detecting an error indication from the execution circuit, the error indication being that the storage state is required to perform the operation and that the storage state does not exist.

[0007] From the fifth example configuration, a data processing method is provided, which includes: issuing an operation to an execution circuit, wherein the execution circuit stores a storage state accessed during the execution of the operation; and detecting an error indication from the execution circuit, the error indication indicating that the storage state is required for the execution of the operation and that the storage state does not exist.

[0008] From the sixth exemplary configuration, a computer program is provided for controlling a host data processing device to provide an instruction execution environment. The computer program includes: publishing programming logic for publishing an operation to the execution programming logic, wherein the execution programming logic is adapted to store a storage state accessed during the execution of the operation; and error detection programming logic for detecting an error indication from the execution programming logic, the error indication being that the storage state is required for the execution of the operation and that the storage state does not exist. Attached Figure Description

[0009] The present technology will be further described by way of example only, with reference to embodiments of the present technology as shown in the accompanying drawings, wherein:

[0010] Figure 1 A data processing apparatus and execution circuitry according to some embodiments are shown;

[0011] Figure 2 An execution circuit according to some embodiments is schematically shown;

[0012] Figure 3 An execution circuit in the form of a cache, according to some embodiments, is schematically illustrated;

[0013] Figure 4 Depend on Figure 4 (a) and Figure 4 (b) Composition, illustrating the process of implementing address translation using stored states according to some embodiments;

[0014] Figure 5 A flowchart illustrating the process of using execution bits to store state is shown according to some embodiments;

[0015] Figure 6 The process for performing value accumulation using stored state, according to some embodiments, is illustrated.

[0016] Figure 7 The following is illustrated, according to some embodiments, a process for performing value accumulation using checkpoints using stored state;

[0017] Figure 8 The use of a management circuit for controlling the execution circuitry is illustrated schematically according to some embodiments;

[0018] Figure 9 A process flowchart illustrating the use of management circuitry during a change in the execution environment is shown according to some embodiments;

[0019] Figure 10 A flowchart illustrating a data processing method used at an execution circuit according to some embodiments is shown;

[0020] Figure 11 A flowchart illustrating a data processing method used in a pipeline according to some embodiments is shown; and

[0021] Figure 12 A flowchart illustrating a simulator implementation according to some embodiments is shown.

[0022] Before discussing embodiments with reference to the accompanying drawings, the following description of embodiments and related advantages is provided. Specific Implementation

[0023] According to an example configuration, an execution circuit is provided, comprising: a storage circuit for maintaining a stored state of the execution circuit; an operation receiving circuit for receiving from a issuing circuit an operation signal corresponding to an operation to be performed, the operation accessing the stored state of the execution circuit from the storage circuit; a function circuit for seeking to perform an operation in response to the operation signal by accessing the stored state of the execution circuit from the storage circuit; a deletion request receiving circuit for receiving a deletion signal and deleting the stored state of the execution circuit from the storage circuit in response to the deletion signal; and a state loss indication circuit for responding to the operation signal by indicating an error when the stored state of the execution circuit is absent and required for an operation.

[0024] The execution circuitry can be a release operation to be performed from the release unit along with a data value, which can be explicitly provided as part of an instruction or obtained from a register file. After the operation is performed, the data value can then be provided to a write-back unit, which can store the data back to, for example, a register file. In the above aspects, the execution unit is capable of internally storing state. However, the execution unit allows state to be deleted at any time via a delete request receiving circuit. If an operation requiring the use of a state not saved in the execution unit is received, an error signal is issued. In this way, the execution circuitry is able to respond to the loss of necessary state (e.g., by deletion). Therefore, allowing the execution circuitry to store state enables the design of execution circuitry that is more complex than it might be designed in situations where state cannot be saved. The difficulties associated with locally saving the state in the execution circuitry are overcome by the execution circuitry itself, which is designed so that the state can be deleted. This is addressed by allowing the execution circuitry to signal the loss of necessary state during the execution of an operation, thereby enabling corrective actions to restore the state or otherwise compensate for the deleted state. If it is recognized that a functional circuit attempts to perform an operation in a sense that it may fail due to a lack of necessary state information, then an error signal can be sent to notify the circuit.

[0025] In some examples, the delete signal is received from outside the execution circuitry. Therefore, the delete signal used to cause the execution circuitry to delete its stored state via the delete request receiving circuitry can originate from outside the execution circuitry. For example, in some cases, the signal can originate from other locations in the pipeline. In other embodiments, the delete signal can be received from within the execution circuitry itself, or it can be received from either inside or outside the execution circuitry.

[0026] In some examples, the operation to be performed causes data to be output; and an error is indicated by outputting the data as a predetermined value. There are multiple ways to indicate an error. In these examples, the operation performed by the execution circuit causes data to be output by the execution circuit. Such data can typically be written back to the register file, for example, via a write-back circuit. In these examples, an error can be indicated by outputting a predetermined value of the data. The predetermined value makes it understood as having the meaning that an error has occurred. In practice, any specific value can be used, but it needs to be distinguished from the actual data value. In the case of floating-point operations, appropriate candidate values ​​could be NaN, infinity, or zero. In the case of operations that produce positive results, zero or another negative value can be used. Other reserved values ​​can also be used.

[0027] In some examples, errors are indicated by setting result flags. The execution unit uses result flags to pass information between instructions. For example, a zero flag (Z) can be used to indicate that the result of a previous instruction was zero. Similarly, a carry flag (C) can be used to indicate that the result of a previous addition operation resulted in an overflow. In these examples, a dedicated flag can be provided, or an existing flag can be used to indicate that the execution circuitry signaled an error. Obviously, if an existing flag is used, its usage should not conflict with the existing meaning of that flag. For example, if the execution unit is in the form of an arithmetic logic unit (ALU), reusing the carry flag (C) might be inappropriate, as it already has a identifiable meaning when signaled by the ALU.

[0028] In some examples, the storage circuitry includes a cache; the storage state includes cached data; and the operation is a lookup operation for cached data items. One use of the execution circuitry is to implement a cache. In such an example, the storage circuitry includes a cache, and the stored data includes cached data stored in the cache. An operation can then be performed to provide a lookup of the cache. The storage state corresponds to the cached data. Therefore, cached data can be retained across multiple calls to the execution circuitry, and this cached data can be built up over time. However, as a result of issuing a deletion signal, the cached data may also be lost at any time. However, since the cache provides a copy of the data stored in other locations, it can be repopulated from its original source.

[0029] In some examples, the stored state includes a set of data inputs; the operation receiving circuitry is adapted to receive further signals from the issuing circuitry corresponding to further operations, providing some data inputs; and the functional circuitry is adapted to seek to perform an operation in response to an operation signal by loading data inputs from the stored circuitry. In these examples, data providing signals can be repeatedly issued to provide a series of data inputs through multiple operations. In other words, each data providing signal can provide only a subset of the complete set of data inputs. After all the necessary data inputs have been provided through multiple data providing signals, the operation is performed using the complete set of data inputs that have been provided. Again, the state stored in the execution circuitry (e.g., the data inputs received so far) can be lost at any time. The consequences of losing the stored state after an operation is performed are limited. In particular, the loss of such data is likely irrelevant unless the operation is intended to be performed a second time. If the state is lost before the complete set of inputs is received, the operation will fail. This situation can be corrected in software, for example, by re-providing data inputs and re-performing the operation in the event of an error.

[0030] In some examples, this operation is a cryptographic operation. One scenario involves accumulating data values ​​through multiple operations, followed by performing the operation on the complete data input set, where multiple data items are encrypted or decrypted. If the data to be encrypted or decrypted does not fit in the register, it may be necessary to load this data through multiple operations. As mentioned earlier, the loss of some data may cause errors in the operation, which in turn leads to the data set being reloaded into the execution circuitry. By providing the encryption operation within a "black box" in the form of the execution circuitry, the encryption key can be made more secure, i.e., by making it difficult to access.

[0031] In some examples, this operation is an accumulation operation. Another example of a situation where multiple data values ​​can be provided and then operated on is in an accumulation operation. For example, a multiplicative accumulation operation performs multiple multiplications, and the results are added together. Similarly, an error occurs if state that could consist of partial accumulated values ​​or values ​​received so far is removed before the complete set of values ​​is provided.

[0032] In some examples, the storage state includes a set of configuration bits; the operation has multiple operating modes, and the choice of operating mode is influenced by this set of configuration bits. Such operating modes can affect how the execution circuitry performs its operations. For example, in a media encoding scenario, the operating mode can relate to the compression level to be performed on the media. High compression may be time-consuming and produce less compressed data, but the quality is lower than low compression, which may be faster and produce more data. Which operating mode (e.g., which compression setting) is used can vary depending on the situation and can be specified by the configuration bits. If configuration bits are lost before the compression operation completes, the compression operation will fail, triggering an error, and the configuration can be reloaded and retried.

[0033] According to an example configuration, a data processing apparatus is provided, the data processing apparatus comprising: a publishing circuit for publishing an operation to an execution circuit, wherein the execution circuit is adapted to store a storage state accessed during the execution of the operation; and an error detection circuit for detecting an error indication from the execution circuit, the error indication being that the storage state is required for the execution of the operation and that the storage state does not exist.

[0034] The above aspects pertain to a data processing apparatus, which may take the form of at least a portion of a pipeline, excluding the aforementioned execution circuitry. The data processing apparatus includes a publishing circuit that publishes an operation to the execution circuitry. The execution circuitry is adapted to internally store states accessed during operation. As previously mentioned, when the execution circuitry attempts to perform the operation, the necessary states may not exist. Therefore, the execution circuitry may generate errors. An error detection circuitry, as part of the data processing apparatus, is capable of detecting errors and triggering a response. In this way, the data processing apparatus can provide instructions to execution units that are allowed to internally store states. However, the execution unit may lose this state at any time, in which case an error is indicated. The data processing apparatus is capable of detecting the occurrence of the error and taking a response action in this case.

[0035] In some examples, the data processing device includes a delete signaling circuit for issuing a signal to the execution circuit to delete the stored state. Therefore, the data processing device is able to issue a delete signal to cause the execution circuit to delete the stored state. This can occur when erasure of state is desired or necessary, for example, in which case the security of the state to be erased can be improved. As an additional or different mechanism, the execution circuit may be able to delete its own state.

[0036] In some examples, the deletion signaling circuitry is adapted to issue a signal to the execution circuitry in response to a change in the execution environment of instructions executed by the data processing device. As previously described, the data processing device may form at least a portion of a pipeline in which instructions are executed. Instructions may be executed as part of an execution environment, such as a partition of a system in which instructions are executed. When such an environment changes, a deletion signal may be appropriately issued to delete the state, thereby maintaining security. The execution environment may be considered, for example, a thread, a process, an operating system, or a virtual machine. A change in the execution environment may be a change from one environment to another, or it may be a change in parameters relating to that execution environment, such as a thread changing from privileged mode to non-privileged mode.

[0037] In some examples, the change in execution environment is any of a context switch, a change in security level, a change in security mode, or a change in privileged mode. In each of these examples, the ongoing change in execution environment may necessitate erasing state within the execution circuitry to maintain security. For instance, if state is preserved within the execution circuitry when the operating system changes its security mode or level to a higher level, the execution circuitry could execute instructions intended for non-privileged processes in privileged mode. This may be undesirable, as it could enable the execution circuitry to perform operations that are not normally permitted. Similarly, a context switch occurs when the currently executing execution environment changes. In such cases, it may be undesirable for the execution circuitry to maintain state associated with the swapped-out execution environment, as this would allow different processes to access each other's data. Such security breaches can be prevented by issuing a signal that causes state to be erased.

[0038] In some examples, the data processing device includes management circuitry for disabling the execution circuitry in response to changes in the execution environment. Another option is to disable the execution circuitry in response to changes in the execution environment. This has the advantage of not only avoiding immediate access to data within the execution circuitry but also reducing power consumption due to the disabling of the execution circuitry.

[0039] In some examples, the management circuitry is adapted to store an identifier of the previous execution environment in which the execution circuitry was used before the execution environment changed, and to re-enable the execution circuitry in response to a further change back to the previous execution environment. After disabling the execution circuitry, the management circuitry can re-enable it upon restoration of the previous execution environment. For example, in the case of a context switch, the management circuitry stores the previous identifier of the processor thread that was executing before the context switch occurred. Once a context switch occurs, the management circuitry disables the execution circuitry. This disabling continues until the previous thread or process is swapped back, at which point the execution circuitry is re-enabled.

[0040] In some examples, the deletion signaling circuitry is adapted to reactivate and signal the execution circuitry in response to an execution environment different from the previous execution environment attempting to use it. When the execution circuitry is disabled, for example, another execution environment different from the previous one could attempt to use it by issuing an operation to the execution circuitry. This could be a malicious attempt to access data stored in the execution circuitry, or it could be a harmless attempt to simply exploit the execution circuitry through a different execution environment. In either case, the management circuitry can respond to this request by reactivating the execution circuitry from its disabled state and issuing an appropriate deletion signal to delete the state stored within the execution circuitry. Thus, the stored state is lost. However, the loss of state allows the execution circuitry to be used by different execution environments without providing access to the state used by the previous execution environment, potentially leading to a security breach.

[0041] In some examples, in response to the error, the publishing circuitry is caused to publish one or more additional operations to restore at least some of the stored states to the execution circuitry. When an error occurs, this may result in the publication of one or more instructions that restore at least some of the stored states to the execution circuitry. In practice, this can occur by detecting the error, i.e., generating a trap that causes a user-defined portion of the program code to be executed in response to the error, or it may result in a branch appearing in a predefined portion of the program code that provides a recovery subroutine. These are two examples where the software causes the publishing circuitry to publish further operations. However, dedicated hardware units can also be used to detect the error state and respond by publishing appropriate operations to restore the stored state. In any case, the stored state can be restored from, for example, a backup memory that holds an original copy of the stored state. In some embodiments, the published operation may also cause the original operation to be republished, or the original operation may be directly addressed while restoring the state.

[0042] In some examples, the data processing device includes a register file comprising a set of schema registers for storing the operational state of the data processing device. In response to a context switch, the schema registers are saved to memory circuitry, and new values ​​for the schema registers are loaded from memory circuitry without saving the stored state to memory circuitry. During a context switch, the schema registers storing the operational state of the data processing device for instruction execution can be saved to memory circuitry, such as main memory. However, these schema registers do not include the stored state within the execution circuitry. Therefore, in these examples, the operational state stored to memory circuitry explicitly excludes the stored state within the execution circuitry. Thus, during a context switch, the context switch process does not need to know about the execution circuitry and the stored state within it.

[0043] Specific embodiments will now be described with reference to the accompanying drawings.

[0044] Figure 1 An execution circuit 120 and a data processing device 110 according to some embodiments are schematically shown. In this case, the data processing device takes the form of a portion of a pipeline having an interface to the execution circuit 120. Instructions are fetched into the pipeline by a fetch circuit 145, which retrieves instructions from a memory 180 located outside the pipeline. The instructions are decoded by a decoding circuit 150 and passed to a issuing circuit 155, which issues the operation corresponding to the instruction to execution units, such as an arithmetic logic unit (ALU) 160 and a load / store unit 165. The issuing unit 155 obtains the data values ​​to be operated on by the execution units 160, 165 from a register file 170. Once these execution units 160, 165 have performed the requested operation, they can output one or more data values ​​to a write-back circuit 175, which writes the provided data values ​​back to the appropriate location in the register file 170.

[0045] It is typically desirable for users of such systems to provide additional execution circuitry. This can be achieved using so-called extended instructions, which are recognized by decoding circuitry 150 and issuing circuitry 155, causing the appropriate operation to be issued to the user-provided execution circuitry 120. A problem arising with the use of such execution circuitry 120 is whether these circuits can contain their own internal state. If such circuitry 120 does not contain internal state, the capabilities of execution circuitry 120 are limited. In particular, execution circuitry 120 cannot store data across multiple calls. However, if execution circuitry 120 does contain state, it may be necessary to save that state to memory 180 in the event of context switching or other changes in the execution environment. This enhances security, preventing data belonging to one process from being accessed by another process, and also preserving data already generated by the process so that it cannot be overwritten by another process.

[0046] In this embodiment, the execution circuit 120 is allowed to store an internal state 185. However, the execution circuit 120 allows this state to be erased at any time. There are several methods to erase this state. In some examples, a delete signaling circuit 140 is provided as part of the pipeline, such that a signal external to the execution circuit 120 can cause the execution circuit to delete its state 185. Alternatively, the execution circuit 120 can delete its own state. It should be understood that the delete signaling circuit 140 does not have to be dedicated hardware. In fact, the delete signaling circuit can be a publishing circuit 155 that signals the execution circuit 120 to notify of the deletion operation as a result of software execution on the device 100.

[0047] In addition, device 100 includes error detection circuitry 130. An error occurs when execution circuitry 120 is required to perform an operation where the necessary state is not present in the execution circuitry (e.g., if the state has been deleted). This error can be detected by error detection circuitry 130, allowing appropriate corrective action to be taken. Again, it should be understood that error detection circuitry 130 does not need to be dedicated hardware specifically for detecting such errors. In practice, errors can be detected by the results of software executed on device 100. In this case, one of the other execution units (e.g., ALU 160) can act as error detection circuitry 130 by determining whether the value of a flag or register corresponds to a specific state known to correspond to an error generated by execution circuitry 120.

[0048] As a result of the above, the execution circuit 120 can obtain the advantage of having an internal state 185. For example, the execution circuit 120 is able to perform more complex operations than would otherwise be possible without any state. However, since the execution circuit 120 is designed such that its state can be erased at any time and signal the rest of the pipeline so that corrective actions can be taken, it is possible to overcome problems that might otherwise be associated with, for example, changes in the execution environment.

[0049] Figure 2An example of the execution circuit 120 is shown in more detail, schematically. Specifically, the execution circuit 120 includes an operation receiving circuit 200, which is responsible for receiving requested operations from the issuing circuit 155 in the rest of the pipeline. The received operation is transmitted to a functional circuit 230, which is responsible for executing the requested operation. The functional circuit 230 accesses the stored state 185 to execute the requested operation. The functional circuit 230 outputs two signals. The first signal is a result signal corresponding to the result of the operation attempted to be executed. This is transmitted to a multiplexer 240, which also receives an error signal as input. The second signal (loss) output by the functional circuit 230 is an indication of whether an error should have occurred. In other words, the loss signal indicates whether the desired state is both desired and absent. This is primarily used as a switching signal to the multiplexer 240, causing the multiplexer 240 to output either the error signal or the result signal as an output signal, depending on whether the operation occurred correctly. It should be understood that the loss signal can also be output directly, for example, in the form of a result flag. In this way, a signal can be sent indicating that the requested operation cannot be executed. Error signals can be predetermined values. The appropriate predetermined output value will depend on the operation of functional circuit 230. For example, if functional circuit 230 generates floating-point numbers, the floating-point specification has defined many specially reserved values ​​that can be used to indicate errors. For example, the value NaN (Not a Number) can be output as such a value. In other cases, functional circuit 230 can cause the output to be non-zero. In this case, a zero value can be output to indicate that an error has occurred.

[0050] exist Figure 2 In the example, a deletion request receiving circuit 210 is provided to receive requests for a state to be deleted. Such requests can originate from the execution unit 120 itself, for example, from the functional circuit 230. However, in some embodiments, the signal can originate from outside the execution circuit 120.

[0051] Figure 3An example of the execution circuit 120 is shown in the form of a storage buffer. In this case, the received operation is a lookup operation, although it is understood that other operations such as storage operations can also be received and processed. The lookup operation is received by the operation receiving circuit 200, which uses a functional circuit in the form of a lookup circuit 300 to perform a lookup in the storage circuit 310, which is an example of the previously described state circuit 185. If the requested value cannot be found in the storage circuit 310 (i.e., if a miss occurs), the lookup circuit 300 outputs a "1" as a loss signal to indicate that the desired state is not part of the storage circuit 310. This is used by the multiplexer 240 to output an error as an output signal. The value of the result signal is irrelevant because, in this case, the multiplexer 240 will prioritize the error signal. Alternatively or otherwise, a special result flag can be set to indicate that an error has occurred.

[0052] In this example, as a result of, for example, a context switch, a refresh signal can be issued from outside the execution circuitry, preventing cached data stored in storage circuitry 310 from being used by another process. In these examples, execution circuitry 120 can benefit from the state stored in storage circuitry 310. In other words, in most cases, cached data can be utilized. However, by flushing the data when a context switch occurs, a situation where data must be stored as part of the context switch operation is prevented. Since the cache acts as a fast repository for information stored elsewhere, data loss in the cache is not significant and can be refilled from backup storage (e.g., main memory) over time. In fact, the issuance of an error signal can be used as a signal to reload the cache from backup storage.

[0053] One example where such caching can be used is in address mapping. This type of process can occur during dynamic instruction code translation, where a series of instructions is transformed from one form to another that can be executed by a data processing device. For example, this might happen in just-in-time (JIT) compilation. Figure 4 In (a), a program flow consisting of multiple programming blocks 400, 410, 420, and 430 is shown. The control flow can be such that it allows access from block 1 400 to either block 2 410 or block 3 420 via different branch instructions B1 and B2. Each of these blocks then proceeds to block 4430. During address mapping, these blocks are expected to be translated into a set of instructions executable by a data processing device. These are... Figure 4As shown in (b), block 1'440 flows to block 2'450 or block 3'460 via branch B1' or B2'. Then, each of these blocks 450, 460 flows to block 4'470. However, in the translated version of the instructions, the location of the instructions in memory will differ from the location of the untranslated blocks. For example, the translation from block 1 400 to block 1'440 will result in block 1'440 being located in a different memory portion than block 1 400. The same applies to blocks 2'450, 3'460, and 4'470. Therefore, at block 1'440, where a branch instruction B1' is to be executed, it is desirable for control flow to jump to block 2'450, rather than to block 2'410 in the original untranslated code. This process can be achieved by providing a hash map that maps the original block locations to the translated block locations. Therefore, this can be stored as... Figure 3 This is a portion of the storage circuitry 310 shown. When a lookup is to be performed, this can be done via the provided execution circuitry 120 to enable fast conversion between the original block and the converted block. If the requested conversion is lost, for example, if a context switch occurs during the conversion, the conversion can be accessed from main memory and reloaded into the storage circuitry 310 later.

[0054] Another example of using a cached structure is in decoding scenarios, such as when decoding bytecode, network packets, trace packets, etc. In such cases, the transformation can be provided by providing an index to a jump table based on the input to be transformed. This can be achieved using a parallel mapping structure (e.g., CAM). Such hardware structures can be used to implement complex switching statements in code. In these cases, the cached storage structure can be used to store entries for the parallel mapping structure. However, errors may occur if the transformation fails due to the absence of a mapping (i.e., a state), leading to the use of software rather than hardware structures to determine the decoding. Simultaneously, the hardware structure can be updated with relevant patterns, allowing decoding of future instances of the input. For rarely encountered input patterns, data can be evicted from the storage structure. This allows more frequently used patterns to be inserted into the hardware structure, but more frequently encountered inputs can benefit from the implemented hardware acceleration.

[0055] Another use case for execution circuit 120 of this state is to provide configuration bits. Specifically, functional circuit 130 may have multiple different operating modes or operating settings that can be used to control the operation of functional circuit 230. One situation where this occurs is in the case of a media encoder performing compression. Specifically, configuration bits can be used to indicate the compression level to be applied, which may affect the amount of time required to perform compression, the size of the resulting compressed media, and the quality of the compressed media. Therefore, depending on user preference, the amount of compression to be performed can be controlled on a case-by-case basis. In these scenarios, execution circuit 120 may be loaded with a specific configuration, which can then be applied to multiple operations (e.g., compression operations). As a result, it may not be necessary to continuously load the configuration into the execution circuit. This can be particularly efficient if loading the configuration results in an initialization that may require multiple processing cycles to complete. In these cases, state loss only results in the configuration being reinserted into execution circuit 120. Meanwhile, as long as the configuration remains present, there is benefit to not having to repeatedly insert and initialize the configuration.

[0056] Figure 5 An example of how configuration bits are used is shown. This is provided in the form of flowchart 500. The process begins at step 510, where configuration bits are obtained. At step 520, it is determined whether any bits are present. If not, an error is generated at step 525. This can be responded to by having the configuration reloaded (e.g., via software). If the bits are present, at step 530, it is determined whether the bits indicate that a first operating mode will be used. If yes, at step 535, functional circuitry 230 is made to operate in the first operating mode. If no, at step 540, it is determined whether these bits indicate that a second operating mode will be used. If yes, functional circuitry 230 is made to operate in the second operating mode. If no, at step 550, it is determined whether these bits indicate that a third operating mode will be used. If yes, functional circuitry 230 is made to operate in the third mode at step 555. If at step 550 the bits do not indicate that a third mode will be used, an error is generated at step 560. This indicates a case where the configuration bits do not correspond to any known operating mode. This situation could occur because the configuration bits are corrupted, in which case the configuration bits can be reloaded. Alternatively, it could correspond to a situation where the user provides configuration bits that do not correspond to any known configuration. In this case, the error generated at step 560 can be used to signal to the user that the provided configuration is invalid. The user can then be prompted to provide a different configuration, or the software can enable the provision of a default configuration.

[0057] Another way to use execution circuit 120 is in the form of an accumulator or a cryptographic system, where inputs are provided to execution circuit 120 through multiple operations rather than all simultaneously. This may be a result of the limited number of inputs that the instruction set can allow in a single instruction. In these examples, the stored state corresponds to the set of inputs provided so far and / or the intermediate working product calculated based on the set of inputs provided so far. The error response is for the case where an intermediate working product or the set of inputs is lost before the complete set of inputs is provided. This can be responded to by re-providing the set of inputs. Figure 6 This illustrates how this can be implemented to provide an accumulator. Before describing the program, let's summarize the function of registers:

[0058] r0 is the current value of the loop counter.

[0059] r1 is the base address in memory of the value to be accumulated.

[0060] r2 is used as a temporary storage device for the next value to be accumulated.

[0061] r3 is used as a temporary storage device for the accumulated results.

[0062] In this example, a special flag 'V' is set in case of an error. The first line of the program specifies the label "Retry" to which the branch can jump. The second line stores the value LOOP_COUNT in register r0. The value LOOP_COUNT corresponds to the number of iterations the loop should perform to accumulate a set of values. Therefore, LOOP_COUNT indicates the number of values ​​to accumulate. The third line sets the accumulator to zero. This has the effect of marking that a new accumulation operation is to be performed. It also has the function of resetting the indicator that an error has occurred. The fourth line provides the label "Loop," to which a later branch can jump. The fifth line fetches the data value and stores it in register r2. The data value is fetched by fetching the base address (stored in register r1) and the offset (stored in register r0) and combining the two addresses to provide the memory location. The data value stored in that memory location is then retrieved and stored in register r2. In the sixth line, the accumulation operation is then performed using the newly fetched value r2. This instruction represents an extension instruction that is passed to execution circuitry 120 in the form of an accumulator. Therefore, execution circuit 120 stores the value of the incoming r2 as part of its state, or the result of accumulating (so far) the value of the incoming r2. In line seven, the index stored in register r0 is decremented by four. This moves the offset counter to the next position. In line eight, it is determined whether the result of the subtraction performed on line seven resulted in a value of zero. If not, the process returns to the label "loop" on line four, allowing another value to be passed to the accumulator. Otherwise, if the subtraction resulted in a value of zero, in line nine, the value of the accumulator is retrieved and stored in register r3. Therefore, the instruction on line nine represents another extended instruction provided to execution circuit 120 in the form of an accumulator. This instruction causes execution circuit 120 to output its accumulated value. In line ten, a test is performed to determine if the result flag 'V' is set. Here, the result flag 'V' is used to indicate an error. If an error is detected, the instruction on line ten causes the program to return to the retry label on line 1, where the process is reactivated. Otherwise, if the accumulation operation has already been completed, the process continues on line eleven.

[0063] As described above, in this example, a flag 'V' is set when an error occurs during the accumulation process. State loss can be detected by accumulator 120 via a single bit in execution circuitry 120, which is set when the state of execution circuitry 120 is deleted. This state can be reset by the `set_accumulator_to_zero` instruction on line 3 and output in response to the `get_accumulator` instruction on line 9 (if it has been set).

[0064] Although the process is functional, if the state is lost, the entire process must start from scratch. This can be time-consuming if a large number of values ​​accumulate and the state is eventually lost. One improvement to this process is the idea of ​​checkpointing, where intermediate products are periodically saved, allowing the process to be restarted in the event of state loss. However, there is clearly a trade-off between the number of times checkpoints are saved, as continuously saving checkpoints reduces system efficiency, thus providing more recovery points in the event of state loss.

[0065] Figure 7 An example of using checkpoints is shown. Here, registers r0, r1, r2, and r3 are used to... Figure 6 The same purpose is stated. Lines 1 to 3 of the program are... Figure 6 Same. At line four, the label "inner_loop" appears in line nine. At line five, the label "restart_inner_loop" is defined, which will be executed when the inner loop is restarted from the checkpoint. At line six, the checkpoint, which can be stored in memory, is loaded into register r3. At line seven, the value of register r3 is passed to the accumulator in the form of execution circuit 120. At line eight, the checkpoint index, which can be stored in memory, is stored in register r0. Then, line nine defines the start of the "inner_loop" label. Lines ten through twelve are the same. Figure 6 The fifth through seventh lines correspond to this, leading to the accumulation of the next value and the decrementing of the loop counter. At line thirteen, the value in r0 is tested to determine if the loop has completed or if a checkpoint is needed. In this example (with...), Figure 6 (Same as above), the loop ends when the value of r0 equals zero. The number of checkpoints depends on the trade-offs mentioned earlier. At line fourteen, it is determined whether the previous tests have been satisfied. If the loop has not completed, and if no checkpoints are needed, the zero flag (Z) is not set, so a branch appears to the label "inner_loop" at line nine, accumulating the next value at line nine. At line fifteen, the value of the accumulator is obtained and stored in register r3. Line sixteen and... Figure 6The tenth line corresponds to this, and in the event of an error, a branch labeled "restart_inner_loop" appears on the fifth line. Therefore, this test is performed each time the loop is determined to be complete or each time a checkpoint is determined to be needed. This effect re-enables the inner loop by reloading the checkpoint from memory and resetting the index of the loop counter stored in register r0. If no error occurs, at line seventeen, the loop is tested to determine if it is complete by checking the loop counter index in register r0. If it is (e.g., if the value of r0 is zero), a branch labeled "done" appears on line 23. Otherwise, at line nineteen, a checkpoint is created. This is first achieved by storing the value in register r3 at the "checkpoint" location (which can be memory as described above). At line 20, the value in r0, identifying the loop index, is stored at the location "index_at_checkpoint," which can also be stored in memory. Thus, both the latest value of the accumulator and the index indicating the extent to which the accumulation process has been reached are stored, allowing them to be recovered later in the event of an error. Line 21 is a yield command that causes other processes to occur. Line 22 causes the "inner loop" branch from line 9 to occur. Therefore, once the checkpoint is created, the cumulative operation will continue. Then, line 23 provides the label "done".

[0066] Figure 8The use of management circuitry 800 is illustrated schematically. As previously described, there may be many situations where state 185 in execution circuitry 120 needs to be erased. Such state erasure may be appropriate in response to a change in the execution environment. The execution environment can be considered as the environment or "container" in which the current stream of instructions executed by device 100 occurs. For example, this could be an operating system, a process, a virtual machine, a virtual processor, a security mode, or a security domain. The change can be a direct swap of the execution environment or a change in the mode of the execution environment. For example, one such change in the execution environment could be a change of the operating system from non-privileged mode to privileged mode, even if the same operating system is being executed. As an alternative to erasing state 185 of execution circuitry 120, management circuitry 800 can be provided to offer a more efficient option. Specifically, in this example, execution circuitry 120 is disabled in response to a change in the execution environment. This means that state 185 of execution circuitry 120 is no longer accessible. Management circuitry 800 can track the previous execution environment in storage circuitry 810. Therefore, once the previous execution environment is restored, execution circuitry 120 can be re-enabled, allowing access to state 185 again. During this process, another execution environment may request access to execution circuitry 120. In some embodiments, this can be simply denied because it does not correspond to a previous execution environment 810 stored by management circuitry 800. In particular, granting access to execution circuitry 120 for different execution environments may lead to security issues. Furthermore, state 185 used by the previous execution environment can be overwritten. In other embodiments, instead of denying access to the disabled execution circuitry 120, the request can be responded to by sending a signal to execution circuitry 120 that both enables execution circuitry 120 and refreshes the stored state. Thus, state 185 is erased from execution circuitry 120 only in the event of a potential security breach. This is equivalent to a "lazy context switch." Execution circuitry is disabled until a new execution environment needs it, thus restricting access to state 185 that has not yet been erased. If execution circuitry 120 is used by the previous execution environment 810, it can be resumed without erasing the state. Alternatively, if a different execution environment requires the execution circuit 120, the state can be erased, and this only applies to the case where the state 185 of the execution circuit 120 is erased whenever the execution environment changes.

[0067] Figure 9The process is illustrated in flowchart 900. At step 910, it is determined what type of signal was received. If the signal is a request to enable and use execution circuit 120, then at step 920, an enable and refresh signal is sent to the execution circuit to erase the state 185 of the execution circuit and make the execution circuit 120 available. The execution circuit 120 can then be used by the new execution environment. If, at step 910, the received signal is a change in the execution environment, such as a context switch, then at step 930, it is determined whether the switch in progress is to a previous process stored in the memory circuit 810 of the management circuit 800. If so, then at step 970, an enable signal is issued to the execution circuit 120, allowing execution to continue. In this case, even if the execution environment may have changed, the state 185 in the execution circuit 120 is not lost. If, at step 930, there is no switch to a previous process, then at step 940, the execution circuit 120 is disabled by a disable signal. This not only results in reduced power consumption but also means that the state 185 cannot be accessed by different execution environments. At step 950, it is determined whether the previous execution environment utilized execution circuit 120. If so, at step 960, the process ID is stored in storage circuit 810 of management circuit 800. The process then returns to step 910. If the execution circuit was not used at step 950, the process simply returns to step 910. In these cases, execution circuit 120 is disabled. However, if it was not used, the previous process is not stored.

[0068] Figure 10 A flowchart 1000 illustrating a data processing method for an execution circuit according to some embodiments is shown. At step 1010, the stored state of the execution circuit is maintained. At step 1020, a signal is received. At step 1030, it is determined what type of signal was received. If a deletion signal is received at step 1030, the stored state of the execution circuit is deleted at step 1040. If an operation signal is received at step 1030, the operation is attempted at step 1050. If, at step 1060, the attempted operation results in the desired state not existing, an error is signaled at step 1070 to indicate that the desired state does not exist. Otherwise, no such error is signaled at step 1080. Of course, the operation itself can signal other errors based on the operation being performed.

[0069] Figure 11A flowchart 1100 illustrates a portion of a pipeline that interfaces with the execution circuitry. At step 1110, an operation signal is sent to the execution circuitry. At step 1120, it is determined whether an error has been detected. If so, at step 1130, it can be determined whether any corrective action is required, and if so, such action can be taken. If not, at step 1140, the process can continue.

[0070] Figure 12 Emulator implementations that can be used are illustrated. While the embodiments described above implement the invention in terms of devices and methods for operating specific processing hardware that supports the relevant technologies, instruction execution environments according to the embodiments described herein can also be provided, implemented using computer programs. Such computer programs are generally referred to as emulators whenever they provide a software-based implementation of a hardware architecture. Various emulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, emulator implementations can run on a host processor 1230, optionally running a host operating system 1220 that supports the emulator program 1210. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or between multiple different instruction execution environments provided on the same host processor. In the past, powerful processors were required to provide emulator implementations that executed at a reasonable speed, but this approach may be reasonable in certain situations (e.g., when it is desired to run code native to another processor for compatibility or reuse reasons). For example, emulator implementations may provide instruction execution environments with additional functionality not supported by the host processor hardware, or instruction execution environments typically associated with different hardware architectures. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques” (USENIX Winter 1990 Conference, Robert Bedichek, pp. 53-63).

[0071] With respect to embodiments previously described with reference to specific hardware constructions or features, equivalent functionality may be provided by suitable software constructions or features in simulated embodiments. For example, specific circuitry may be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware such as registers or caches may be implemented as software data structures in simulated embodiments. In arrangements where one or more hardware elements referenced in the foregoing embodiments are present on host hardware (e.g., host processor 1230), some simulated embodiments may utilize the host hardware where appropriate.

[0072] The simulator program 1210 can be stored on a computer-readable storage medium (which may be a non-transitory medium) and can be sent to the target code 1200 (which may include...). Figure 1 The simulator 1210 provides a program interface (instruction execution environment) for any circuit in the acquisition, decoding, publishing, execution, and write-back circuitry. This program interface is identical to the application programming interface of the hardware architecture modeled by the simulator program 1210. Therefore, the simulator program 1210 can be used to execute program instructions of the target code 1200 from the instruction execution environment, including the operation of the execution circuitry 120 and / or the remainder of the pipeline interfaced with the aforementioned execution circuitry 120, enabling a host computer 1230, which does not actually possess the hardware features of the aforementioned device, to emulate these features.

[0073] In this application, the phrase "configured as..." is used to indicate that the elements of a device have a configuration capable of performing defined operations. In this document, "configuration" refers to the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform that function. "Configured as" does not imply that the device elements need to be changed in any way to provide the defined operations.

[0074] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, features of the dependent claims can be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. An execution circuit, comprising: A storage circuit is used to maintain the storage state of the execution circuit; An operation receiving circuit is used to receive an operation signal corresponding to an operation to be performed from a publishing circuit, wherein the operation to be performed accesses the storage state of the execution circuit from the storage circuit; A functional circuit is configured to seek to perform the operation in response to the operation signal by accessing the stored state of the execution circuit from the storage circuit; A deletion request receiving circuit is configured to receive a deletion signal and, in response to the deletion signal, delete the stored state of the execution circuit from the storage circuit; as well as A state loss indication circuit is used to respond to the operation signal by indicating an error when the stored state of the execution circuit does not exist and is required for the operation. The operation to be performed requires data to be output; and The error is indicated by outputting the data to be output as a predefined value.

2. The execution circuit according to claim 1, wherein The deletion signal is received from outside the execution circuit.

3. The execution circuit according to claim 1 or 2, wherein The error is indicated by setting a result flag.

4. The execution circuit according to claim 1 or 2, wherein The storage circuit includes a cache; The storage state includes cached data; and The operation is a lookup operation for the items in the cached data.

5. The execution circuit according to claim 1 or 2, wherein The storage state includes a set of data inputs; The operation receiving circuit is adapted to receive from the publishing circuit a further signal corresponding to a further operation, the further operation being used to provide some of the data input; and The functional circuit is adapted to seek to perform the operation in response to the operation signal by loading data input from the storage circuit.

6. The execution circuit according to claim 1 or 2, wherein The storage state includes a set of configuration bits; and The operation has multiple operation modes, and the selection of the operation mode is affected by this set of configuration bits.

7. A data processing method, comprising: Maintain the stored state of the execution circuit; The execution circuit receives an operation signal corresponding to the operation to be performed, wherein the operation to be performed accesses the storage state of the execution circuit. The operation is sought in response to the operation signal by accessing the stored state of the execution circuit; Receive a deletion signal and delete the stored state of the execution circuit in response to the deletion signal; as well as When the stored state of the execution circuit does not exist and is required for the operation, the operation signal is responded to by indicating an error, wherein... The operation to be performed requires data to be output; and The error is indicated by outputting the data to be output as a predefined value.

8. A computer-readable storage medium storing a computer program, said computer program, when executed by a host data processing device, causing the host data processing device to provide an instruction execution environment, said instruction execution environment comprising: Data structures used to maintain storage state; An operation receiving programming logic is used to receive an operation signal from the publishing programming logic corresponding to an operation to be performed, wherein the operation to be performed accesses the storage state; Functional programming logic is used to seek to perform the operation in response to the operation signal by accessing the stored state from the data structure; The deletion request receiving programming logic is used to receive a deletion signal and, in response to the deletion signal, delete the stored state from the data structure. as well as The state loss indication programming logic is used to respond to the operation signal by indicating an error when the stored state is absent and required for the operation, wherein... The operation to be performed requires data to be output; and The error is indicated by outputting the data to be output as a predefined value.

9. A data processing device, comprising: A publishing circuit for publishing an operation to an execution circuit, wherein the execution circuit is adapted to store a memory state accessed during the execution of the operation; An error detection circuit is configured to detect an error indication from the execution circuit, the error indication being that the stored state is required for the execution of the operation and that the stored state does not exist; and A deletion signaling circuit is used to send a signal to the execution circuit to delete the stored state in response to a change in the execution environment of an instruction executed by the data processing device.

10. The data processing apparatus according to claim 9, wherein The change in the execution environment is any of the following: context switching, change of security level, change of security mode, and change of privileged mode.

11. The data processing apparatus according to claim 9 or 10, comprising: Management circuitry for disabling the execution circuitry in response to changes in the execution environment.

12. The data processing apparatus according to claim 11, wherein The management circuitry is adapted to store an identifier of a previous execution environment in which the execution circuitry was used prior to the change in the execution environment, and is adapted to reactivate the execution circuitry in response to a further change in the execution environment back to the previous execution environment.

13. The data processing apparatus according to claim 12, wherein The deletion signaling circuit is adapted to reactivate the execution circuit and send the signal to the execution circuit in response to an execution environment different from the previous execution environment attempting to use the execution circuit.

14. The data processing apparatus according to claim 9 or 10, wherein In response to the error, the publishing circuit is caused to publish one or more further operations to restore at least some of the stored states to the execution circuit.

15. The data processing apparatus according to claim 9 or 10, comprising: A register file, comprising an architecture register set, for storing the operational state of the data processing device, wherein... In response to a context switch, the architecture register is saved to the storage circuit, and a new value of the architecture register is loaded from the storage circuit without saving the storage state to the storage circuit.

16. A data processing method, comprising: An operation is issued to an execution circuit, wherein the execution circuit stores a memory state that is accessed during the execution of the operation; Detect an error indication from the execution circuitry, the error indication being that the stored state is required for the execution of the operation and that the stored state does not exist; and In response to a change in the execution environment of an instruction executed by a data processing device, a signal is sent to the execution circuit to delete the stored state.

17. A computer-readable storage medium storing a computer program, said computer program, when executed by a host data processing device, causes the host data processing device to provide an instruction execution environment, said instruction execution environment comprising: Publishing programming logic for publishing operations to the execution programming logic, wherein the execution programming logic is adapted to store a storage state that is accessed during the execution of the operation; Error detection programming logic is used to detect error indications from the execution programming logic, the error indications being that the stored state is required for the execution of the operation and that the stored state does not exist; and In response to a change in the execution environment of an instruction executed by the instruction execution environment, a signal is sent to the execution programming logic to delete the stored state.

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