Memory device and memory system having the memory device

Abstract

A memory system includes: a plurality of memory cells located at intersections between a plurality of word lines and a plurality of bit lines; and a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers being configured to write data to or read data from the plurality of memory cells via the plurality of bit lines, wherein a redundant bit line sense amplifier among the plurality of bit line sense amplifiers is configured to generate a physically unclonable function (PUF) key comprising a unique random numerical value.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0168800, filed on December 17, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a memory device and a memory system including the memory device. Background Technology

[0004] In the field of hardware security, key information, such as IDs and security keys, which may be unique information about a chip, should not be lost even when there is no power supply. The most common approach to this is to store data (e.g., key information) in non-volatile memory (NVM), such as electrically erasable programmable read-only memory (EEPROM). However, when storing such data in NVM, the data must be managed separately, and there is a risk of data leakage if management is neglected. Furthermore, even after the data is stored, it can still be read through various physical security attacks. One approach to address this challenge is the physically unclonable function (PUF) technique. Summary of the Invention

[0005] One aspect of the present invention is to provide a memory device capable of generating unpredictable or difficult-to-predict chip-specific information by using the distribution of elements included in the memory device.

[0006] According to one aspect of the present invention, a memory system includes: a plurality of memory cells located at intersections between a plurality of word lines and a plurality of bit lines; and a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers being configured to write data to or read data from the plurality of memory cells via the plurality of bit lines, wherein a redundant bit line sense amplifier among the plurality of bit line sense amplifiers is configured to generate a physically unclonable function (PUF) key comprising a unique random numerical value.

[0007] According to one aspect of the present invention, a memory device includes: a memory cell array including a plurality of memory cells located at intersections between a plurality of word lines and a plurality of bit lines; a first bit line sense amplifier connected to a first bit line of the plurality of bit lines, the first bit line sense amplifier being configured to operate as a data sense amplifier, the data sense amplifier including writing data to or reading data from the plurality of memory cells via the first bit line; and a second bit line sense amplifier connected to a second bit line of the plurality of bit lines, the second bit line sense amplifier being configured to operate as a physically unclonable function (PUF) bit line sense amplifier, the physically unclonable function bit line sense amplifier including generating a PUF key as a unique random digital value.

[0008] According to one aspect of the present invention, a memory device includes: a plurality of memory cells located at intersections between a plurality of word lines and a plurality of bit lines; a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers being configured to write data to or read data from the plurality of memory cells via the plurality of bit lines, a first bit line sense amplifier of the plurality of bit line sense amplifiers being connected to a first bit line of the plurality of bit lines, a second bit line sense amplifier of the plurality of bit line sense amplifiers being connected to a second bit line of the plurality of bit lines, each of the first bit line sense amplifier and the second bit line sense amplifier including a pair of first transistors and a pair of second transistors; and processing circuitry, which is... The configuration includes: outputting a first drive signal during a pre-sensing operation, the first drive signal being configured to drive the pair of first transistors of the first bit line sense amplifier, the pair of first transistors of the first bit line sense amplifier being driven before the pair of second transistors of the first bit line sense amplifier being driven; the pre-sensing operation including pre-sensing the voltages of the plurality of bit lines and the voltages of the plurality of complementary bit lines corresponding to the plurality of bit lines; and outputting a second drive signal during the pre-sensing operation, the second drive signal being configured to drive the pair of second transistors of the second bit line sense amplifier, the pair of second transistors of the second bit line sense amplifier being driven before the pair of first transistors of the second bit line sense amplifier being driven. Attached Figure Description

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram schematically illustrating some example embodiments of a memory system according to the present invention.

[0011] Figure 2 This is a block diagram illustrating some example embodiments of a memory device according to the present invention.

[0012] Figure 3 This is a block diagram illustrating some example embodiments of a memory device according to the present invention.

[0013] Figure 4 This is a diagram illustrating the operation of a memory device according to some exemplary embodiments of the present invention.

[0014] Figure 5 This is a circuit diagram illustrating some example embodiments of a memory device according to the present invention.

[0015] Figures 6 to 9 These are timing diagrams illustrating the operation of a memory device according to some exemplary embodiments of the present invention.

[0016] Figure 10 This is a diagram illustrating the authentication operation of a memory system according to some example embodiments of the concept of the present invention.

[0017] Figure 11 This is a diagram illustrating the verification operation of a memory system according to some example embodiments of the concept of the present invention.

[0018] Figures 12A to 16B This is a diagram illustrating the operation of an encryption / decryption module according to some example embodiments of the present invention. Detailed Implementation

[0019] In the following description, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0020] Figure 1 This is a block diagram schematically illustrating some example embodiments of a memory system according to the present invention.

[0021] Reference Figure 1 The memory system 1 may include a first memory module 10, a second memory module 20, and / or a memory controller 30. The first memory module 10, the second memory module 20, and the memory controller 30 may be integrated into a single semiconductor device. For example, the first memory module 10, the second memory module 20, and the memory controller 30 may be integrated into a single semiconductor device to form a solid-state drive (SSD). Therefore, the memory controller 30 may be an SSD controller.

[0022] The first memory module 10 may include volatile memory (e.g., dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), static random access memory (SRAM), etc.) and / or non-volatile memory (e.g., ferroelectric random access memory (FRAM), resistive random access memory (ReRAM), spin-transfer torque magnetoresistive random access memory (STT-MRAM), phase random access memory (PRAM), etc.). The first memory module 10 may be used as a buffer memory for temporarily storing data received from the host and / or data received from the second memory module 20. According to some example embodiments, the first memory module 10 may be used to store a mapping table for translating logical addresses seen by the host into physical addresses in flash memory.

[0023] The second memory module 20 can be implemented using various non-volatile memory devices, such as read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, PRAM, ReRAM, FRAM, and / or STT-MRAM.

[0024] The memory controller 30 may include a DRAM controller 310, a host controller 320, a non-volatile memory (NVM) controller 330, an encryption / decryption module 340, a security module 350, a CPU 360, and / or a ROM 370.

[0025] The DRAM controller 310 can control the read and / or write operations of the first memory module 10. For example, the DRAM controller 310 can temporarily store write data destined for or read data from the first memory module 10.

[0026] The host controller 320 can process read and / or write commands from the host (e.g., an external device, an external processor, etc.). The host controller 320 provides an interface for communication between the host and the memory system 1 under the control of the CPU 360. For example, the interface may include at least one of Peripheral Component Interconnect (PCI Fast), Small Computer System Interface (SCSI), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), and Serial Attachment SCSI (SAS). According to some example embodiments, the interface may be NVM Fast (NVMe) for exchanging data in a PCI Fast manner.

[0027] The non-volatile memory controller 330 can control the read and / or write operations of the second memory module 20.

[0028] The encryption / decryption module 340 can encrypt data sent from the host, or decrypt encrypted data. The encryption / decryption module 340 can perform symmetric key cryptography.

[0029] Symmetric-key cryptography (also known as secret-key cryptography) refers to cryptography in which the key used to encrypt data is the same as or similar to the key used to decrypt data. Examples of symmetric-key cryptography include the Data Encryption Standard (DES) scheme and the Advanced Encryption Standard (AES) scheme.

[0030] CPU 360 can interpret multiple host instructions that enter the command queue and can read data from or write data to the second memory module 20 via non-volatile memory controller 330. CPU 360 can operate according to firmware provided for various control operations of memory controller 30. For example, CPU 360 can execute a flash translation layer (FTL) for managing the second memory module 20, which performs garbage collection, address mapping, and / or wear leveling. CPU 360 can execute firmware from ROM 370 supporting in-memory computing (ISC) functionality.

[0031] Security module 350 can perform public-key cryptography. Public-key cryptography (also known as asymmetric-key cryptography) refers to cryptography in which the key used to decrypt data is different from the key used to encrypt data. For example, public-key cryptography can include the Hellman scheme, the Rivest-Shamir-Adleman (RSA) scheme, the ElGamal scheme, elliptic curve cryptography, etc.

[0032] Security module 350 can perform authentication and / or verification operations on memory system 1. For example, when a program such as a bootloader and / or firmware is first generated or updated, security module 350 can perform authentication of the program. Furthermore, when memory system 1 is booted and a program is loaded or updated, security module 350 can perform verification of the program. Unlike memory system 1, security module 350 can be implemented as a separate chip.

[0033] Even when performing the same or similar operations in a semiconductor manufacturing process, process variations can occur due to the characteristics of the semiconductor manufacturing process. Due to process variations, differences can exist in many areas, from device characteristics such as transistors, capacitors, and / or resistors to circuit characteristics such as gate delay times. The greater the difference, the higher the distribution, and a high distribution can generate different numerical values ​​of 0 or 1 for each chip. Unlike devices that generate random numbers, the same or similar values ​​can be output each time a numerical value used as chip-specific information is generated. A physically unclonable function (PUF) can refer to a function or system that generates a large number of unpredictable random numerical values ​​implemented in a chip by using a high distribution. Because the unpredictable values ​​are output by hardware, replication is impossible. As used herein, the terms “random” or “unpredictable” can refer to random or substantially random values ​​(e.g., numbers, etc.) and / or unpredictable or nearly unpredictable values ​​(e.g., numbers, etc.).

[0034] According to some exemplary embodiments of the present invention, the memory system 1 can generate chip-specific information from the first memory module 10 in PUF operation mode. The memory system 1 can generate unpredictable chip-specific information in PUF operation mode by utilizing the distribution of devices included in the first memory module 10. Therefore, it is possible to generate random digital values ​​that cannot be modulated and / or copied, or digital values ​​that are difficult to modulate and / or copy.

[0035] Figure 2 This is a block diagram illustrating some exemplary embodiments of a memory device according to the present invention. (Refer to...) Figure 2 The memory device 10 of this invention may include a memory cell array 100, a row decoder 200, an address buffer 300, a column decoder 400, multiple bit line sense amplifiers (BLSAs) 500, a data buffer 600, a command decoder 700, control logic 800, a fuse circuit 910, column repair logic 920, and / or row repair logic 930. According to some example embodiments, the memory device 10 may be the same as or similar to a first memory module 10.

[0036] The memory cell array 100 may include multiple memory cells and multiple redundant memory cells. The multiple memory cells may be located at points where multiple word lines and multiple bit lines intersect. For example, each of the multiple memory cells may be connected to a single word line and a single bit line.

[0037] Each of the plurality of memory cells may include a switching element and an information storage capacitor. In some example embodiments, the switching element may include a transistor. The gate terminal of the transistor may be connected to a word line. One end of the transistor (e.g., the drain terminal) may be connected to a bit line or a complementary bit line. The other end of the transistor (e.g., the source terminal) may be connected to an information storage capacitor.

[0038] According to some example embodiments, a portion of multiple memory cells and multiple redundant memory cells can be used as a PUF operation. A memory cell used as a PUF operation can be referred to as a PUF cell. According to some example embodiments, a portion of multiple bit lines can be used as a PUF operation. A bit line used as a PUF operation can be referred to as a PUF bit line.

[0039] Address buffer 300 can temporarily store addresses (ADDs) input from a memory controller (e.g., memory controller 30). Address buffer 300 can output the row address (RA) included in the address (ADD) to row decoder 200. Address buffer 300 can output the column address (CA) included in the address (ADD) to column decoder 400.

[0040] The line decoder 200 can decode the line address (RA) to determine the single word line corresponding to the line address (RA) among multiple word lines as the selected word line. The line decoder 200 can activate (e.g., connect, select, power, etc.) the selected word line.

[0041] Column decoder 400 can decode the column address (CA) to determine the single bit line corresponding to the column address (CA) among multiple bit lines as the selected bit line. Row decoder 200 and column decoder 400 can determine the memory cell connected to the selected word line and the selected bit line as the selected memory cell.

[0042] Multiple bit line sense amplifiers 500 can be connected to multiple bit lines. The multiple bit line sense amplifiers 500 can write data to a selected memory cell via a selected bit line. The multiple bit line sense amplifiers 500 can read data stored in a selected memory cell via a selected bit line. Additionally, the multiple bit line sense amplifiers 500 can perform a refresh operation to rewrite data in the selected memory cell, allowing the charge in the information storage capacitor of the selected memory cell to discharge naturally without data loss. For example, a portion of the multiple bit line sense amplifiers 500 can operate as data sense amplifiers, and the bit line sense amplifier operating as a data sense amplifier can be a master bit line sense amplifier.

[0043] Multiple bit line sense amplifiers 500 can be driven based on control signals (e.g., ISO, OC, LANG, and LAPG) provided from control logic 800. For example, the multiple bit line sense amplifiers 500 can perform offset cancellation operations based on an isolation signal (ISO) and an offset cancellation signal (OC). Offset can refer to differences in characteristics (e.g., threshold voltage) between the semiconductor devices constituting the multiple bit line sense amplifiers 500.

[0044] According to some example embodiments, a portion of the bit line sense amplifier 500 can operate as a PUF (Power-On-Flight) amplifier, and the remainder of the bit line sense amplifier 500 can operate as a data sense amplifier. A bit line sense amplifier operating as a PUF can be referred to as a PUF bit line sense amplifier.

[0045] The data buffer 600 can temporarily store data input from the memory controller and can output data to multiple bit line sense amplifiers 500. The data buffer 600 can also temporarily store data output from multiple bit line sense amplifiers 500 and can output data externally. According to some example embodiments, the address buffer 300 and / or the data buffer 600 can be implemented using memory (e.g., RAM, ROM, etc.).

[0046] The command decoder 700 can decode write enable signals ( / WE), row address strobe signals ( / RAS), column address strobe signals ( / CAS), chip select signals ( / CS), etc., sent from the memory controller to determine the command (CMD) sent from the memory controller. For example, the command (CMD) can be an activation command, an auto-refresh command, a precharge command, a write command, a read command, etc.

[0047] Control logic 800 can control multiple bit line sense amplifiers 500 in response to commands (CMDs). Control logic 800 can generate control signals (e.g., ISO, OC, LANG, and LAPG) for controlling the multiple bit line sense amplifiers 500.

[0048] The fuse circuit 910 may include at least one of an antifuse circuit, a laser fuse circuit, and an electric fuse circuit. The fuse circuit 910 may store location information (FA) of at least one bad memory cell among a plurality of memory cells included in the memory cell array 100. A bad memory cell may represent a memory cell with a hard defect or a soft defect. The location information (FA) of the bad memory cell stored in the fuse circuit 910 may be updated. The location information (FA) of the bad memory cell may be obtained by testing whether a bad bit occurs in the memory device 10. Testing may be performed before packaging the memory device 10, for example, at the wafer level, or even after packaging the memory device 10. For example, post-packaging repair (PPR) is possible.

[0049] According to some example embodiments, the fuse circuit 910 may store PUF position information (PA). For example, the PUF position information (PA) may include the position information of the PUF cells, the position information of the PUF bit lines, and the position information of the PUF bit line sense amplifiers.

[0050] Column repair logic 920 can generate a first control signal (CTRL1) based on the column address (CA) and the PUF location information (PA). Control logic 800 can control a portion of multiple bit line sense amplifiers 500 to operate as PUF bit line sense amplifiers based on the first control signal (CTRL1). For example, a portion of the multiple bit line sense amplifiers 500 that has been replaced by redundant bit line sense amplifiers can be used to generate a PUF key that includes a unique random numeric value. As used herein, the term "unique" can mean unique or uncommon.

[0051] According to some example embodiments, control logic 800 can control a portion of multiple bit lines as PUF bit lines based on a first control signal (CTRL1).

[0052] The row repair logic 930 can generate a second control signal (CTRL2) based on the row address (RA) and the PUF location information (PA). The row decoder 200 can control multiple memory cells and a portion of multiple redundant memory cells to operate as PUF cells based on the second control signal (CTRL2).

[0053] According to some example embodiments, row repair logic 930 and column repair logic 920 can replace bad memory cells with redundant memory cells. Row repair logic 930 can generate a redundant row address (RRA) based on the row address (RA) and the location information (FA) of the bad memory cell. Row decoder 200 can replace word lines connected to bad memory cells with redundant word lines connected to multiple redundant memory cells based on the redundant row address (RRA) (e.g., associating a command containing the RA of the word line connected to the bad memory cell with the RA of the redundant word line). Column repair logic 920 can generate a replacement column address (RCA) based on the column address (CA) and the location information (FA) of the bad memory cell. Control logic 800 can replace bit lines connected to bad memory cells with redundant bit lines connected to multiple redundant memory cells based on the replacement column address (RCA) (e.g., associating a command containing the CA of the bit line connected to the bad memory cell with the CA of the redundant bit line).

[0054] According to some exemplary embodiments of the present invention, the memory device 10 can control a portion of the bit line sense amplifier 500 to operate as a data sense amplifier. According to some exemplary embodiments, the memory device 10 can control a portion of the bit line sense amplifier 500 to operate as a PUF bit line sense amplifier. According to some exemplary embodiments, the memory device 10 can control a portion of multiple bit lines to operate as PUF bit lines. According to some exemplary embodiments, the memory device 10 can control a portion of multiple memory cells and multiple redundant memory cells to operate as PUF cells. Therefore, the memory device 10 can generate unpredictable chip-specific information. Using at least one of the PUF bit line sense amplifier, PUF bit lines, and PUF cells, the memory system can perform program authentication and / or verification operations, and / or data encryption and / or decryption operations.

[0055] Figure 3 This is a block diagram illustrating some example embodiments of a memory device according to the present invention.

[0056] Reference Figure 3 The memory device 10a may include a plurality of memory cell arrays 110, 120, and 130, a plurality of redundant memory cell arrays 140 and 150, and a plurality of sense amplifiers 510 to 540 (e.g., a first plurality of bit line sense amplifiers 510, a second plurality of bit line sense amplifiers 520, a third plurality of bit line sense amplifiers 530, and a fourth plurality of bit line sense amplifiers 540). Each of the plurality of sense amplifiers 510 to 540 may include a plurality of bit line sense amplifiers (BLSAs). The plurality of bit line sense amplifiers (BLSAs) may be derived from... Figure 2The memory device 10a is implemented using a plurality of bit line sense amplifiers 500 as described herein. According to some example embodiments, the memory device 10a corresponds to the memory cell array 100 and the bit line sense amplifiers 500 of the memory device 10.

[0057] Multiple pairs of bit lines (BL and BLB) connected to multiple memory cell arrays 110, 120, and 130 can be connected to multiple bit line sense amplifiers (BLSAs). A portion of the bit lines of redundant memory cell arrays 140 and 150 can be connected to adjacent bit line sense amplifiers (BLSAs) as complementary bit lines. The remaining bit lines of redundant memory cell arrays 140 and 150 can be left unconnected to bit line sense amplifiers (BLSAs) as pseudo-bit lines.

[0058] According to some embodiments, a portion of a plurality of bit line sense amplifiers (BLSAs) can operate as a PUF (Publicly Utilized Field-Sensitive Amplifier). For example, the second bit line sense amplifier 520-2 and the fourth bit line sense amplifier 520-4 of the plurality of bit line sense amplifiers 520-1 to 520-n (e.g., the first bit line sense amplifier 520-1, the second bit line sense amplifier 520-2, the third bit line sense amplifier 520-3, the fourth bit line sense amplifier 520-4, ..., the nth bit line sense amplifier 520-n) included in sense amplifier 520 can each be a PUF bit line sense amplifier. The PUF bit line sense amplifier can be a defective bit line sense amplifier having a high threshold voltage distribution of the transistors included in the PUF bit line sense amplifier. Whenever the PUF bit line sense amplifier is powered, the PUF bit line sense amplifier can output data '0' or data '1' according to the threshold voltage distribution of the transistors included in the PUF bit line sense amplifier. For example, each time the PUF bit line sense amplifier is powered, the PUF bit line sense amplifier can randomly output unique data. For example, a PUF bit-line sense amplifier can output a unique random digital value.

[0059] For example, when the storage capacity of memory device 10a is 8 Gbit, the number of defective bit line sense amplifiers (BLSAs) may be 40,000 or more. Specifically, when the storage capacity of memory device 10a is 8 Gbit or 16 Gbit, the number of multiple bit line sense amplifiers (BLSAs) may be approximately 4,000,000. 1% of the multiple bit line sense amplifiers (BLSAs) may be defective. For example, memory device 10a may include approximately 40,000 defective bit line sense amplifiers. Therefore, memory device 10a can generate approximately 40,000,000 bits using defective bit line sense amplifiers.

[0060] In a first operating mode, for example, in normal operating mode, the plurality of bit line sense amplifiers 520-1 to 520-n included in sense amplifier 520 can write data to selected memory cells or read data stored in selected memory cells via bit lines BL connected to the first memory cell array 110 and the second memory cell array 120. In this case, some of the plurality of bit line sense amplifiers 520-1 to 520-n may be defective bit line sense amplifiers. For example, the second bit line sense amplifier 520-2 and the fourth bit line sense amplifier 520-4 may be defective bit line sense amplifiers, and the defective bit line sense amplifiers may be located between the main bit line sense amplifiers that serve as data sense amplifiers. Redundant bit line sense amplifiers can be used to replace the defective bit line sense amplifiers. The redundant bit line sense amplifiers can operate as data sense amplifiers.

[0061] In a second operating mode, for example, in a PUF operating mode, the second bit-line sense amplifier 520-2 and the fourth bit-line sense amplifier 520-4 can each be a PUF bit-line sense amplifier. The memory device 10a can generate a unique random digital value using the PUF bit-line sense amplifier. This unique random digital value can be referred to as a PUF key. Because the PUF bit-line sense amplifier generates the PUF key by using the threshold voltage distribution of the transistors included in the PUF bit-line sense amplifier, the PUF key can output a unique random digital value each time it is generated. Therefore, the PUF key can be used as chip-specific information. For example, the PUF key can be used as an ID or security key, which can be unique information for the memory device 10a.

[0062] Conventional electronic systems store key information (e.g., identification information, security keys, etc.) in non-volatile memory. Non-volatile memory is vulnerable to various security risks, including physical security attacks. Therefore, conventional electronic systems cannot provide sufficient security for key information.

[0063] However, some example embodiments provide improved apparatuses and systems configured to generate keys (also referred to herein as PUF keys) based on Physically Unclonable Functions (PUFs). A PUF key is a unique, random numerical value based on the physical properties of elements in a memory device. Therefore, a PUF key cannot be modified or copied, or is very difficult to modify or copy. Thus, the improved memory devices and systems overcome the shortcomings of conventional electronic systems to provide more secure key information.

[0064] Figure 4 This is a diagram illustrating the operation of a memory device according to some exemplary embodiments of the present invention.

[0065] Reference Figure 4The memory device 10b may include a plurality of memory cells 111 and 112 connected to a bit line (BL), a plurality of memory cells 121 and 122 connected to a complementary bit line (BLB), and / or a bit line sensing amplifier 521, a precharge circuit (EQ) 522, a first isolation transistor 31, and / or a second isolation transistor 32 connected to the bit line (BL) and the complementary bit line (BLB). According to some example embodiments, the memory device 10b corresponds to the memory cell array 100 and the bit line sensing amplifier 500 of the memory device 10.

[0066] In normal operating mode, bit line sensing amplifier 521 can sequentially perform pre-charge operation, offset cancellation operation, charge sharing operation, pre-sensing operation, and / or recovery operation.

[0067] During the precharge operation, the isolation signal (ISO) can be logic high. Because the first isolation transistor 31 and the second isolation transistor 32 are turned on, a pair of bit lines (BL and BLB) and a pair of sensing bit lines (SABL and SABLB) can be connected to each other. Under the control of the precharge circuit 522, the pair of bit lines (BL and BLB) can be precharged to the precharge voltage.

[0068] During the offset cancellation operation, the isolation signal (ISO) can be logic low, such that the voltages of the bit line (BL) and the complementary bit line (BLB) can be stored as a difference having the magnitude of the offset voltage. According to some example embodiments, the bit line sensing amplifier 521 can compensate for the offset voltage during the offset cancellation operation.

[0069] When the first memory cell 111 is the selected memory cell, during charge-sharing operation, the isolation signal (ISO) can be logic low, and the word line (WL1-1) connected to the first memory cell 111 can be activated. Charge sharing can occur (e.g., by combining charges) between the charge stored in the capacitor of the first memory cell 111 and the charge stored in the bit line (BL) (e.g., the charge of the bit line). For example, when data '1' is stored in the first memory cell 111, during charge-sharing operation, the voltage level of the bit line (BL) can be increased by a predetermined level, or alternatively, increased by a given level. When data '0' is stored in the first memory cell 111, during charge-sharing operation, the voltage level of the bit line (BL) can be decreased by a predetermined level, or alternatively, decreased by a given level.

[0070] During pre-sensing operation, the isolation signal (ISO) can be logic low, and the sensing bit line (SABL) can raise the internal supply voltage based on the voltage difference between the bit line (BL) and the complementary bit line (BLB). The complementary sensing bit line (SABLB) can lower the ground voltage.

[0071] During recovery operation, the isolation signal (ISO) can be logic high, the bit line (BL) can be charged to the voltage level of the sensing bit line (SABL), and the complementary bit line (BLB) can be discharged to the voltage level of the complementary sensing bit line (SABLB).

[0072] In PUF operation mode, memory device 10b can generate a PUF key. PUF operation mode may include a first example, a second example, and a third example.

[0073] According to the first example, bit line sense amplifier 521 can operate as a PUF bit line sense amplifier. Bit line sense amplifier 521 can generate PUF keys using the threshold voltage distribution of the transistors included in bit line sense amplifier 521. In this case, word lines (WL1-1, WL1-2, WL2-1, and WL2-2) connected to memory cells 111, 112, 121, and 122 can be inactive during charge-sharing operation.

[0074] According to the second example, a PUF key can be generated using the threshold voltage distribution of the transistors included in the bit line sensing amplifier 521 and the mismatch between the capacitance of the bit line (BL) and the capacitance of the complementary bit line (BLB). In this case, the word lines (WL1-1, WL1-2, WL2-1, and WL2-2) connected to the memory cells 111, 112, 121, and 122 may be inactive or deactivated (e.g., disconnected, deselected, not powered, etc.) during charge-sharing operation, and the isolation signal (ISO) may be logic high during pre-sensing operation. Since the isolation signal (ISO) may be logic high during pre-sensing operation, when the memory device 10b generates a PUF key, the capacitance mismatch between a pair of bit lines (BL and BLB) can be reflected.

[0075] According to the third example, a PUF key can be generated using the threshold voltage distribution of the transistors included in the bit line sense amplifier 521, the capacitance mismatch between a pair of bit lines (BL and BLB), and the mismatch between memory cells 111, 112, 121, and 122. The mismatch between memory cells can include capacitance mismatch between memory cells, the threshold voltage distribution of each transistor in the memory cell, etc.

[0076] For example, a first memory cell 111 connected to a bit line (BL) and a second memory cell 121 connected to a complementary bit line (BLB) can each operate as a PUF cell. According to some example embodiments, both the first memory cell 111 and the second memory cell 121 can be normal memory cells. According to some example embodiments, both the first memory cell 111 and the second memory cell 121 can be bad memory cells. According to some example embodiments, one of the first memory cell 111 and the second memory cell 121 can be a normal memory cell, and the other of the first memory cell 111 and the second memory cell 121 can be a bad memory cell.

[0077] Both the first memory cell 111 and the second memory cell 121 can be written with data '1' or data '0'. In this case, the bit line sense amplifier 521 can be a normal bit line sense amplifier without defects, or it can be a defective bit line sense amplifier with defects. During charge-sharing operation, the first word line (WL1-1) and the second word line (WL2-1) connected to the first memory cell 111 and the second memory cell 121 can be activated simultaneously or concurrently. The bit line sense amplifier 521 can read the data stored in the first memory cell 111 via the bit line (BL). During charge-sharing operation, since the first word line (WL1-1) and the second word line (WL2-1) can be activated simultaneously or concurrently, the mismatch between the first memory cell 111 and the second memory cell 121 can be reflected when the memory device 10b generates the PUF key.

[0078] Mismatch between the first memory cell 111 and the second memory cell 121 may include mismatch between the capacitance of the first memory cell 111 and the capacitance of the second memory cell 121, threshold voltage distribution of the transistors in the first memory cell 111 and the threshold voltage distribution of the transistors in the second memory cell 121, etc.

[0079] Based on the mismatch between the first memory cell 111 and the second memory cell 121, the bit line sensing amplifier 521 can read data '0' or data '1' through the bit line (BL). For example, the probability of the bit line sensing amplifier 521 reading data '0' through the bit line (BL) and the probability of the bit line sensing amplifier 521 reading data '1' through the bit line (BL) can both be 50%.

[0080] Figure 5 This is a circuit diagram illustrating some exemplary embodiments of a memory device according to the present invention. Figures 6 to 9 These are timing diagrams illustrating the operation of a memory device according to some exemplary embodiments of the present invention.

[0081] Reference Figure 5 The memory device 10c may include a first memory cell PC1 connected to a bit line (BL), a second memory cell PC2 connected to a complementary bit line (BLB), a first isolation transistor 41, a second isolation transistor 42, a first offset cancellation transistor 43, a second offset cancellation transistor 44, a bit line sense amplifier BLSA, a first switch 45, and / or a second switch 46. According to some example embodiments, the memory device 10c corresponds to the memory cell array 100 and the bit line sense amplifier 500 of the memory device 10.

[0082] Refer to together Figure 5 and Figure 6 In normal operating mode, the bit line sense amplifier (BLSA) can sequentially perform pre-charge operation, offset cancellation operation, charge sharing operation, pre-sensing operation, and recovery operation.

[0083] During the precharge operation (t0 to t1), the isolation signal (ISO) can be logic high. The first isolation transistor 41 and the second isolation transistor 42 can be turned on in response to the isolation signal (ISO). Therefore, the bit line (BL) and the sensing bit line (SABL) can be connected, and the complementary bit line (BLB) and the complementary sensing bit line (SABLB) can be connected. The offset cancellation signal (OC) can be logic high. The first offset cancellation transistor 43 and the second offset cancellation transistor 44 can be turned on in response to the offset cancellation signal (OC). Therefore, the bit line (BL) and the complementary sensing bit line (SABLB) can be connected, and the complementary bit line (BLB) and the sensing bit line (SABL) can be connected. Under the control of the precharge circuit, a pair of bit lines (BL and BLB) and a pair of sensing bit lines (SABL and SABLB) can be precharged to the precharge voltage (Vpre).

[0084] A bit-line sense amplifier (BLSA) may include a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and / or a second NMOS transistor NM2. Due to variations in operation, temperature, etc., a difference in threshold voltage may occur between a pair of first transistors, such as a pair of PMOS transistors PM1 and PM2, and a pair of second transistors, such as a pair of NMOS transistors NM1 and NM2. In this case, the bit-line sense amplifier (BLSA) may generate offset noise due to the threshold voltage difference between the pair of PMOS transistors PM1 and PM2 and the pair of NMOS transistors NM1 and NM2.

[0085] During the offset cancellation operation (t1 to t2), the isolation signal (ISO) may be logic low. The first control signal (LAPG) may be logic high. The first switch 45 may be turned on in response to the first control signal (LAPG). Therefore, the voltage of the first node LA may rise from the precharge voltage (Vpre) to the supply voltage (VDD). Offset cancellation operations are disclosed in patent documents US15 / 697,164, US15 / 674,022, US15 / 208,640, and US14 / 264,466. Reference can be made to the aforementioned patent documents for further understanding. Figure 6 The general operation for offset elimination.

[0086] The second control signal (LANG) can be logic high. The second switch 46 can be turned on in response to the second control signal (LANG). Therefore, the voltage of the second node LAB can be reduced from the precharge voltage Vpre to the ground voltage (VSS). The power supply voltage (VDD) can be the voltage supplied to the memory cell array. In this case, offset noise can be eliminated by storing the voltages of the bit lines (BL) and complementary bit lines (BLB) as offset voltages from each other.

[0087] During charge-sharing operation (t2 to t3), the isolation signal (ISO) and offset cancellation signal (OC) can be logic low. The first control signal (LAPG) can be logic low. The first switch 45 can be turned off in response to the first control signal (LAPG). Therefore, the voltage at the first node LA can drop from the supply voltage (VDD) to the precharge voltage (Vpre). The second control signal (LANG) can be logic low. The second switch 46 can be turned off in response to the second control signal (LANG). Therefore, the voltage at the second node LAB can rise from the ground voltage (VSS) to the precharge voltage (Vpre).

[0088] When the first memory cell PC1 is the selected memory cell, the first word line (WL1) connected to the first memory cell PC1 can be activated. Charge sharing can occur between the charge stored in the capacitor of the first memory cell PC1 and the charge stored in the bit line (BL). For example, when data '1' is stored in the first memory cell PC1, during charge sharing operation, the voltage level of the bit line (BL) can be increased by a predetermined level, or alternatively, increased by a given level. In some example embodiments, when data '0' is stored in the first memory cell PC1, during charge sharing operation, the voltage level of the bit line (BL) can be decreased by a predetermined level, or alternatively, decreased by a given level.

[0089] During the pre-sensing operation (t3 to t4), the bit line sense amplifier BLSA can pre-sense the voltage of the bit line (BL) and the voltage of the complementary bit line (BLB) corresponding to the bit line (BL).

[0090] The first control signal (LAPG) can be logic high. The first switch 45 can be turned on in response to the first control signal (LAPG). Therefore, the first voltage of the first node LA can rise from the precharge voltage (Vpre) to the supply voltage (VDD). The first control signal (LAPG) can also be a first drive signal for driving the pair of PMOS transistors PM1 and PM2 to sense data in the first memory cell PC1.

[0091] The second control signal (LANG) can be logic high. The second switch 46 can be turned on in response to the second control signal (LANG). Therefore, the second voltage of the second node LAB can be reduced from the precharge voltage (Vpre) to the ground voltage (VSS). The second control signal (LANG) can also be a second drive signal for driving the pair of NMOS transistors NM1 and NM2 to sense data in the first memory cell PC1.

[0092] In normal operating mode, the bit line sense amplifier (BLSA) operates based on the smallest threshold voltage distribution among the pair of NMOS transistors NM1 and NM2 and the pair of PMOS transistors PM1 and PM2. For example, when the pair of NMOS transistors NM1 and NM2 has a smaller threshold voltage distribution than the pair of PMOS transistors PM1 and PM2, the BLSA preferentially (e.g., first in sequence) operates the pair of NMOS transistors NM1 and NM2. Therefore, the second control signal (LANG) can be preferentially (e.g., first in sequence) enabled, and then the first control signal (LAPG) can be enabled. As a result, the voltage of the second node LAB can preferentially (e.g., first in sequence) decrease from the precharge voltage (Vpre) to the ground voltage (VSS), and then (e.g., subsequently) the voltage of the first node LA can increase from the precharge voltage (Vpre) to the supply voltage (VDD).

[0093] Based on the voltage difference between the bit line (BL) and the complementary bit line (BLB), the sensing bit line (SABL) can be raised to the internal power supply voltage, and the complementary sensing bit line (SABLB) can be lowered to the ground voltage.

[0094] In some example embodiments, during the pre-sensing operation (t3 to t4), the first voltage of the first node LA and the second voltage of the second node LAB can be increased or decreased in two steps. For example, in the first step, the first voltage of the first node LA can be increased to a level below the supply voltage (VDD), and the second voltage of the second node LAB can be decreased to a level above the ground voltage (VSS). In the second step, the first voltage of the first node LA can be increased to the supply voltage (VDD), and the second voltage of the second node LAB can be decreased to the ground voltage (VSS).

[0095] For example, during the pre-sensing operation (t3 to t4), the bit line sense amplifier BLSA can be raised to a level below the supply voltage (VDD) and then raised to the supply voltage (VDD) via a first drive signal, and the bit line sense amplifier BLSA can be lowered to a level above the ground voltage (VSS) and then lowered to the ground voltage (VSS) via a second drive signal. Therefore, the sensing margin can be improved.

[0096] During the recovery operation (t4 to t5), the isolation signal (ISO) can be logic high. The bit line (BL) can be charged to the voltage level of the sensing bit line (SABL), and the complementary bit line (BLB) can be discharged to the voltage level of the complementary sensing bit line (SABLB). Therefore, based on the difference in the magnitude of the offset voltage, the voltage of the bit line (BL) can increase and the voltage of the complementary bit line (BLB) can decrease.

[0097] Refer to together Figure 5 and Figure 7 In PUF operation mode, the bit line sense amplifier BLSA can operate as a PUF bit line sense amplifier. For example, when operating in PUF operation mode, the bit line sense amplifier BLSA can also be referred to as a PUF bit line sense amplifier in this document.

[0098] During the precharge operation (t0 to t1), the isolation signal (ISO) can be logic high. The first isolation transistor 41 and the second isolation transistor 42 can be turned on in response to the isolation signal (ISO). Therefore, the bit line (BL) and the sense bit line (SABL) can be connected, and the complementary bit line (BLB) and the complementary sense bit line (SABLB) can be connected. The offset cancellation signal (OC) can be logic high or logic low.

[0099] When the offset cancellation signal (OC) is logic high, the pair of bit lines (BL and BLB) and the pair of sensing bit lines (SABL and SABLB) can be precharged to the precharge voltage (Vpre) under the control of the precharge circuit.

[0100] Subsequently, in PUF operation mode, since the offset cancellation signal (OC) can be deactivated and the word lines (WL1 and WL2) can be deactivated, offset cancellation and charge sharing operations can be avoided.

[0101] During the pre-sensing operation (t3 to t4), the first control signal (LAPG) can be logic high. The first switch 45 can be turned on in response to the first control signal (LAPG). Therefore, the voltage at the first node LA can rise from the pre-charge voltage (Vpre) to the supply voltage (VDD). The second control signal (LANG) can be logic high. The second switch 46 can be turned on in response to the second control signal (LANG). Therefore, the voltage at the second node LAB can drop from the pre-charge voltage (Vpre) to the ground voltage (VSS).

[0102] Unlike in normal operating mode, in PUF operating mode, the bit line sense amplifier BLSA can operate based on the higher threshold voltage distribution among the pair of NMOS transistors NM1 and NM2 and the pair of PMOS transistors PM1 and PM2. For example, when the pair of PMOS transistors PM1 and PM2 has a higher threshold voltage distribution than the pair of NMOS transistors NM1 and NM2, the bit line sense amplifier BLSA can preferentially (e.g., first in sequence) operate the pair of PMOS transistors PM1 and PM2. Therefore, the first control signal (LAPG) can preferentially (e.g., first in sequence) go high, and then (e.g., subsequently) the second control signal (LANG) can go high. Thus, the voltage of the first node LA can preferentially (e.g., first in sequence) rise from the precharge voltage (Vpre) to the supply voltage (VDD), and then the voltage of the second node LAB can drop from the precharge voltage (Vpre) to ground voltage (VSS).

[0103] For example, the order in which the pair of PMOS transistors and the pair of NMOS transistors drive the bit line sense amplifier in normal operating mode may differ from the order in which they drive the bit line sense amplifier in PUF operating mode. Furthermore, in PUF operating mode, the first voltage of the first node LA may rise or fall in one continuous phase; the first voltage of the first node LA may rise to the supply voltage (VDD) in one continuous phase, and the second voltage of the second node LAB may fall to ground voltage (VSS).

[0104] For example, during the pre-sensing operation (t3 to t4), the bit line sense amplifier BLSA can be raised to the power supply voltage (VDD) once by a first drive signal, and the bit line sense amplifier BLSA can be lowered to the ground voltage (VSS) once by a second drive signal.

[0105] Based on the threshold voltage distribution of the transistors included in the PUF bit line sense amplifier, the sensing bit line (SABL) can rise to the internal power supply voltage or fall to ground. Compared to the sensing bit line (SABL), the complementary sensing bit line (SABLB) can fall to ground or rise to the internal power supply voltage. For example, the probability that the sensing bit line (SABL) rises to the internal power supply voltage and the complementary sensing bit line (SABLB) falls to ground, and the probability that the sensing bit line (SABL) falls to ground and the complementary sensing bit line (SABLB) rises to the internal power supply voltage, can each be 50%. Figure 7 An example is shown where the sensing bit line (SABL) rises to the internal power supply voltage and the complementary sensing bit line (SABLB) drops to ground voltage.

[0106] During the recovery operation (t4 to t5), the isolation signal (ISO) can be logic high. The bit line (BL) can be charged or discharged to the voltage level of the sensing bit line (SABL), and the complementary bit line (BLB) can be discharged or charged to the voltage level of the complementary sensing bit line (SABLB). Therefore, the voltage of the bit line (BL) and the voltage of the complementary bit line (BLB) can rise or fall based on the same or a similar precharge voltage.

[0107] For example, a PUF bit line sense amplifier can output data '0' or data '1' based on the threshold voltage distribution of the transistors included in the PUF bit line sense amplifier. For example, the probability of the bit line sense amplifier BLSA outputting data '0' and the probability of the bit line sense amplifier BLSA outputting data '1' can both be 50%.

[0108] Refer to together Figure 5 and Figure 8 In PUF operation mode, the threshold voltage distribution of the transistors included in the bit line sense amplifier BLSA and the capacitance mismatch of the pair of bit lines (BL and BLB) can be used to generate the PUF key.

[0109] During the precharge operation (t0 to t1), the isolation signal (ISO) and offset cancellation signal (OC) can be logic high or logic low. Depending on the control of the precharge circuit, the pair of bit lines (BL and BLB) and the pair of sensing bit lines (SABL and SABLB) can be precharged to the precharge voltage (Vpre).

[0110] Subsequently, since the offset cancellation signal (OC) is logic low and the word line (WL1) connected to the first memory cell PC1 is not activated, the offset cancellation operation and charge sharing operation can be avoided.

[0111] During the pre-sensing operation and recovery operation (t3 to t5), the isolation signal (ISO) can be logic high. Since the isolation signal (ISO) is logic high during the pre-sensing operation, the relative characteristics of the capacitors of the bit line (BL) and the complementary bit line (BLB) can be reflected in the PUF operating mode.

[0112] According to the first control signal (LAPG), the voltage of the first node LA can be increased from the precharge voltage (Vpre) to the supply voltage (VDD). According to the second control signal (LANG), the voltage of the second node LAB can be decreased from the precharge voltage (Vpre) to the ground voltage (VSS).

[0113] The sensing bit line (SABL) can be raised to the internal power supply voltage, and the complementary sensing bit line (SABLB) can be lowered to ground voltage.

[0114] Based on the threshold voltage distribution of the transistors included in the PUF bit line sense amplifier, the probability that the sense bit line (SABL) rises to the internal power supply voltage and the complementary sense bit line (SABLB) falls to the ground voltage, and the probability that the sense bit line (SABL) falls to the ground voltage and the complementary sense bit line (SABLB) rises to the internal power supply voltage, can be 50% each.

[0115] The bit line (BL) can be charged or discharged to the voltage level of the sensing bit line (SABL), and the complementary bit line (BLB) can be discharged or charged to the voltage level of the complementary sensing bit line (SABLB).

[0116] For example, based on the threshold voltage distribution of the transistors included in the PUF bit line sense amplifier and the relative characteristics of the capacitors of the bit line (BL) and complementary bit line (BLB), the PUF bit line sense amplifier can use data '0' or data '1'. For example, the probability of the bit line sense amplifier BLSA outputting data '0' and the probability of the bit line sense amplifier BLSA outputting data '1' can each be 50%.

[0117] Refer to together Figure 5 and Figure 9 The threshold voltage distribution of the transistors included in the bit line sense amplifier BLSA in the PUF operation mode, the capacitance mismatch of the pair of bit lines (BL and BLB), and the capacitance mismatch of memory cells PC1 and PC2 can be used to generate PUF keys.

[0118] The isolation signal (ISO) can be logic high during the precharge operation (t0 to t1). Since the first isolation transistor 41 and the second isolation transistor 42 can be turned on, the pair of bit lines (BL and BLB) and the pair of sensing bit lines (SABL and SABLB) can be connected to each other. The offset cancellation signal (OC) can be logic high or logic low. Under the control of the precharge circuit, the pair of bit lines (BL and BLB) and the pair of sensing bit lines (SABL and SABLB) can be precharged to the precharge voltage (Vpre).

[0119] Subsequently, since the offset cancellation signal (OC) can be logic low, the offset cancellation operation may not occur.

[0120] During charge sharing operations (t2 to t3), the isolation signal (ISO) can be logic high or logic low. According to the first control signal (LAPG), the voltage of the first node LA can be reduced from the supply voltage (VDD) to the precharge voltage (Vpre). According to the second control signal (LANG), the voltage of the second node LAB can be increased from the ground voltage (VSS) to the precharge voltage (Vpre). The first word line (WL1) connected to the first memory cell PC1 can be activated, and the second word line (WL2) connected to the second memory cell PC2 can be activated. Charge sharing can occur between the charge stored in the capacitor of the selected memory cell PC1 and the charge stored in the bit line (BL).

[0121] In PUF operation mode, both the first memory cell PC1 and the second memory cell PC2 can be written with data '1' or data '0'. The first word line (WL1) connected to the first memory cell PC1 and the second word line (WL2) connected to the second memory cell PC2 can be activated simultaneously or concurrently.

[0122] For example, when both the first memory cell PC1 and the second memory cell PC2 write the data '1', during charge-sharing operations, the voltage levels of the bit line (BL) and the complementary bit line (BLB) can be increased by a predetermined level, or alternatively, by a given level. Depending on the mismatch between the first memory cell PC1 and the second memory cell PC2, a difference may occur between the voltage levels of the bit line (BL) and the complementary bit line (BLB).

[0123] During the pre-sensing operation (t3 to t4), the isolation signal (ISO) can be either logic high or logic low. During the pre-sensing operation (t3 to t4), when the isolation signal (ISO) is logic low, the voltage of the first node LA can be increased from the pre-charge voltage (Vpre) to the supply voltage (VDD) according to the first control signal (LAPG), and the voltage of the second node LAB can be decreased from the pre-charge voltage (Vpre) to the ground voltage (VSS) according to the second control signal (LANG).

[0124] Based on the threshold voltage distribution of the transistors included in the PUF bit line sense amplifier, the probability that the sense bit line (SABL) rises to the internal power supply voltage and the complementary sense bit line (SABLB) falls to the ground voltage, and the probability that the sense bit line (SABL) falls to the ground voltage and the complementary sense bit line (SABLB) rises to the internal power supply voltage, can be 50% each.

[0125] During the recovery operation (t4 to t5), the bit line (BL) can be charged or discharged to the voltage level of the sensing bit line (SABL), and the complementary bit line (BLB) can be discharged or charged to the voltage level of the complementary sensing bit line (SABLB). For example, depending on the threshold voltage distribution of the transistors included in the PUF bit line sensing amplifier, the mismatch between the capacitance of the bit line (BL) and the capacitance of the complementary bit line (BLB), and the mismatch between the first memory cell PC1 and the second memory cell PC2, the probability that the bit line (BL) is charged to the voltage level of the sensing bit line (SABL) and the probability that the bit line (BL) is discharged to the voltage level of the sensing bit line (SABL) can each be 50%.

[0126] A PUF bit line sense amplifier can sense data '0' or data '1' through a bit line (BL). For example, the probability of a bit line sense amplifier BLSA detecting data '0' through a bit line (BL) and the probability of a bit line sense amplifier BLSA detecting data '1' through a bit line (BL) can both be 50%.

[0127] This specification shows and describes some example embodiments in which offset elimination does not occur in PUF operating mode, but offset elimination can occur in PUF operating mode.

[0128] Figure 10 These are diagrams illustrating the authentication operations of a memory system according to some exemplary embodiments of the present invention. Figure 11 This diagram illustrates the verification operations of a memory system according to some exemplary embodiments of the present invention. The memory system can check whether a program has been forged or modified through authentication and verification operations of programs such as firmware and bootloaders.

[0129] Reference Figure 10The security module 350 may include a hash value generator 351, a digital signature value generator 352, and / or a certificate generator 353. The hash value generator 351 may receive data (DATA) from the second memory module 20. The data (DATA) may be a program such as firmware, a bootloader, etc. The hash value generator 351 may generate a hash value (HASH) corresponding to the data (DATA) by using a hash function.

[0130] The first memory module 10 can be combined with Figures 5 to 9 The PUF key (PRK) is generated in a manner similar to or the same described. The digital signature value generator 352 can receive a hash value (HASH) from the hash value generator 351 and can receive the PUF key (PRK) from the first memory module 10. The PUF key (PRK) can be a private key. The digital signature value generator 352 can use the PUF key (PRK) to encrypt the hash value (HASH) and can generate a digital signature value (SIG).

[0131] Certificate generator 353 can receive data (DATA) from second memory module 20 and digital signature values ​​(SIG) from digital signature value generator 352. Certificate generator 353 can combine data (DATA) and digital signature values ​​(SIG) to generate a certificate (DSD). The certificate (DSD) can be stored in second memory module 20.

[0132] Reference Figure 11 The security module 350 may include a processor 354, a first hash value generator 355, a second hash value generator 356, and / or a determiner 357. The processor 354 may receive a certificate (DSD) from the second memory module 20. The processor 354 may extract a digital signature value (SIG) from the certificate (DSD).

[0133] The first hash generator 355 can receive a digital signature value (SIG) from the processor 354 and an encryption key (PUK) from the second memory module 20. For example, the encryption key (PUK) can be a public key. The first hash generator 355 can use the encryption key (PUK) to decrypt the digital signature value (SIG) and generate a first hash value (HASH1).

[0134] The second hash value generator 356 can receive data (DATA) from the second memory module 20. The second hash value generator 356 can use a hash function to generate a second hash value (HASH2) corresponding to the data (DATA).

[0135] Determiner 357 can receive a first hash value (HASH1) from first hash value generator 355 and a second hash value (HASH2) from second hash value generator 356. Determiner 357 can compare the first hash value (HASH1) and the second hash value (HASH2). As a result of the comparison, when the first hash value (HASH1) and the second hash value (HASH2) are the same or similar, determiner 357 can determine that the program corresponding to data (DATA) has not been forged or modified. Therefore, memory system 3 can execute data (DATA).

[0136] As a result of the comparison, when the first hash value (HASH1) and the second hash value (HASH2) are different from each other, the determiner 357 can determine that the program corresponding to the data (DATA) has been forged or modulated. Therefore, the memory system 3 may not execute the data (DATA).

[0137] Figures 12A to 16B This is a diagram illustrating the operation of an encryption / decryption module according to some example embodiments of the present invention.

[0138] Reference Figure 12A The encryption / decryption module 340 includes an Advanced Encryption Standard (AES) engine 341, a Key Derivation Function (KDF) engine 342, a first calculator 343, and / or a second calculator 344.

[0139] The AES engine 341 can perform the function of encrypting and decrypting data using an encryption key. The AES engine 341 can receive raw data (ORD) from the host controller 320. Raw data (ORD) can refer to the data received from the host before it is encrypted.

[0140] The KDF engine 342 can receive an authentication key (AUK) from the host controller 320. The authentication key (AUK) can be a combination of an ID and password (PW) received from the user, or a personal identification number (PIN) received from the user. The KDF engine 342 can use the authentication key (AUK) to generate a key encryption key (KEK) with relatively high entropy.

[0141] The first calculator 343 can output one of a plurality of first keys (KEY1-1 to KEY1-n) stored in the second memory module 20, or a combination of at least two of the plurality of first keys (KEY1-1 to KEY1-n). The second calculator 344 can combine the output of the first calculator 343 with a key encryption key (KEK) to output a media encryption key (MEK).

[0142] The AES engine 341 can receive a media encryption key (MEK) from the second computer 344. The AES engine 341 can use the media encryption key (MEK) to encrypt the raw data (ORD) received from the host controller 320. The AES engine 341 can store the encrypted data (END) in the second memory module 20.

[0143] Furthermore, the AES engine 341 can receive encrypted data (END) from the second memory module 20. The AES engine 341 can decrypt the encrypted data (END) using the media encryption key (MEK) received from the second computer 344. The AES engine 341 can then send the original data (ORD) decrypted from the encrypted data (END) to the host controller 320.

[0144] exist Figure 12B In the middle, the encryption / decryption module 340 can be used with Figure 12A The different approach does not include KDF engine 342 and second calculator 344. AES engine 341 can use the output of first calculator 343 to encrypt raw data (ORD) received from host controller 320 or decrypt encrypted data (END).

[0145] exist Figure 13A In the middle, the first calculator 343 can be compared with... Figure 12A Different methods output a combination of one of the multiple first keys (KEY1-1 to KEY1-n) stored in the second memory module 20 and a second key (KEY2) received from the first memory module 10. The second key (KEY2) can be combined with... Figures 5 to 9 The PUF key is generated in the first memory module 10 in the same or similar manner as described. The second key (KEY2) may include multiple PUF keys, and may be a combination of at least two of one or more PUF keys.

[0146] The second calculator 344 can combine the output of the first calculator 343 with the key encryption key (KEK) to output the medium encryption key (MEK).

[0147] The AES engine 341 can use the output of the second calculator 344 to encrypt raw data (ORD) received from the host controller 320 or decrypt encrypted data (END).

[0148] exist Figure 13B In the middle, the encryption / decryption module 340 can be used with Figure 13AThe different approach does not include KDF engine 342 and second calculator 344. AES engine 341 can use the output of first calculator 343 to encrypt raw data (ORD) received from host controller 320 or decrypt encrypted data (END).

[0149] exist Figure 14A In the middle, the first calculator 343 can be compared with... Figure 13A Different methods output a combination of the following three items: one of a plurality of first keys (KEY1-1 to KEY1-n) stored in the second memory module 20, a second key (KEY2) received from the first memory module 10, and a third key (KEY3) received from the ROM 370. The third key (KEY3) may include (e.g., optionally from) a plurality of keys, and may be a combination of at least two of one or more of the plurality of keys. The number of third keys (KEY3) may be less than the number of first keys (KEY1-1 to KEY1-n) and the number of second keys (KEY2).

[0150] The second calculator 344 can combine the output of the first calculator 343 with the key encryption key (KEK) to output the medium encryption key (MEK).

[0151] The AES engine 341 can use the output of the second calculator 344 to encrypt raw data (ORD) received from the host controller 320 or decrypt encrypted data (END).

[0152] exist Figure 14B In the middle, the encryption / decryption module 340 can be used with Figure 14A The different approach does not include KDF engine 342 and second calculator 344. AES engine 341 can use the output of first calculator 343 to encrypt raw data (ORD) received from host controller 320 or decrypt encrypted data (END).

[0153] exist Figure 15A In the middle, the first calculator 343 can be compared with... Figure 14A The combination of the second key (KEY2) received from the first memory module 10 and the third key (KEY3) received from the ROM 370 is output in different ways. The second calculator 344 can combine the output of the first calculator 343 with the key encryption key (KEK) to output the media encryption key (MEK).

[0154] The AES engine 341 can use the output of the second calculator 344 to encrypt raw data (ORD) received from the host controller 320 or decrypt encrypted data (END).

[0155] exist Figure 15B In the middle, the encryption / decryption module 340 can be used with Figure 15A The different approach does not include KDF engine 342 and second calculator 344. AES engine 341 can use the output of first calculator 343 to encrypt raw data (ORD) received from host controller 320 or decrypt encrypted data (END).

[0156] exist Figure 16A In the middle, the encryption / decryption module 340 can be used with Figure 13A Different methods further include a third calculator 345. The host controller 320 can receive encryption keys from the host along with the data. For example, the host controller 320 can receive one encryption key per 4KB of data from the host, and the encryption key can have a size of 128 bits to 256 bits.

[0157] The host controller 320 can send raw data (ORD) to the AES engine 341 based on data received from the host and an encryption key, and can send a fourth key (KEY4) to the third computer 345.

[0158] The first calculator 343 can output a combination of one of a plurality of first keys (KEY1-1 to KEY1-n) stored in the second memory module 20 and a second key (KEY2) received from the first memory module 10. The second calculator 344 can combine the output of the first calculator 343 with a key encryption key (KEK) to output a first media encryption key (MEK1).

[0159] The third calculator 345 may receive a fourth key (KEY4) from the host controller 320 and a first media encryption key (MEK1) from the second calculator 344. The third calculator 345 may combine the fourth key (KEY4) and the first media encryption key (MEK1) to generate a second media encryption key (MEK2).

[0160] The AES engine 341 can receive a second media encryption key (MEK2) from the third computer 345. The AES engine 341 can use the second media encryption key (MEK2) to encrypt raw data (ORD) received from the host controller 320 or decrypt encrypted data (END).

[0161] exist Figure 16B In the middle, the encryption / decryption module 340 can be used with Figure 16A The different approach does not include KDF engine 342 and second calculator 344. Third calculator 345 can combine the output of first calculator 343 and fourth key (KEY4) to generate second media encryption key (MEK2).

[0162] The AES engine 341 can use the output of the third calculator 345 to encrypt raw data (ORD) received from the host controller 320 or decrypt encrypted data (END).

[0163] According to some exemplary embodiments of the present invention, unpredictable chip-specific information can be generated by utilizing the distribution of elements included in a memory device. Therefore, random numerical values ​​that cannot be modulated or copied, or are difficult to modulate or copy, can be generated.

[0164] According to some example embodiments, the operations described herein as being performed by the following can be executed by processing circuitry: memory system 1, memory controller 30, DRAM controller 310, host controller 320, NVM controller 330, encryption / decryption module 340, security module 350, CPU 360, row decoder 200, column decoder 400, multiple bit line sense amplifiers 500, command decoder 700, control logic 800, fuse circuit 910, column repair logic 920, row repair logic 930, hash value generator 351, digital signature value generator 352, certificate generator 353, processor 354, first hash value generator 355, second hash value generator 356, determiner 357, AES engine 341, KDF engine 342, first calculator 343, second calculator 344, third calculator 345, and / or any other functional blocks, elements, and / or modules described herein. As used in this disclosure, the term "processing circuit" can refer to, for example, hardware including logic circuitry, a hardware / software combination such as a processor executing software, or a combination thereof. More specifically, processing circuitry can include, but is not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0165] Some example embodiments can be described with reference to the actions and symbolic representations of the operations (e.g., in the form of flowcharts, diagrams, data flow charts, structure diagrams, block diagrams, etc.), and the operations can be implemented in conjunction with the units and / or devices discussed in more detail below. Although discussed in a particular manner, the functions or operations specified in a particular block may be performed in a manner different from that specified in the flowcharts, diagrams, etc. For example, functions or operations shown to be performed serially in two consecutive blocks may actually be performed concurrently, simultaneously, or in some cases in the reverse order.

[0166] It should be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0167] The various operations of the above-described methods can be performed by any suitable device (e.g., processing circuitry) capable of performing the operations. For example, the operations of the above-described methods can be performed by various hardware and / or software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0168] The software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any processor-readable medium for use by or in conjunction with an instruction execution system, device, or apparatus (e.g., a single-core or multi-core processor or a system containing a processor).

[0169] The blocks or operations and functions of the methods or algorithms described in conjunction with some of the exemplary embodiments disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or a combination of both. If implemented in software, the functions may be stored as one or more instructions or code on or transmitted via a tangible non-transitory computer-readable medium. Software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0170] The various advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of describing some exemplary embodiments of the present invention.

[0171] Although some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory system, comprising: Multiple memory cells are located at the intersection of multiple word lines and multiple bit lines; as well as A plurality of bit line sense amplifiers are connected to the plurality of bit lines, the plurality of bit line sense amplifiers being configured to write data to or read data from the plurality of memory cells via the plurality of bit lines, and a defective bit line sense amplifier among the plurality of bit line sense amplifiers being configured to generate a physically unclonable function key comprising a unique random digital value based on the threshold voltage distribution of the transistors included in the defective bit line sense amplifier.

2. The memory system according to claim 1, wherein, The memory system is a solid-state drive.

3. The memory system according to claim 1, further comprising: The processing circuit is configured as follows: The authentication operation is performed using the physically unclonable function key, and Use an encryption key to perform the verification operation.

4. The memory system according to claim 1, further comprising: The processing circuit is configured as follows: The data sent from the host is encrypted using the physically unclonable function key, or The encrypted data is decrypted using the physically unclonable function key.

5. The memory system according to claim 4, wherein, The processing circuit is configured as follows: Receive the encryption key from the host along with the data; and Perform at least one of the following: The data is encrypted using the physically unclonable function key and the encryption key, or The encrypted data is decrypted using the encryption key and the physically unclonable function key.

6. The memory system according to claim 5, wherein, The encryption key has a size of 128 bits to 256 bits.

7. A memory device, comprising: A memory cell array comprising multiple memory cells located at intersections between multiple word lines and multiple bit lines; A first bit line sense amplifier is connected to the first bit line of the plurality of bit lines. The first bit line sense amplifier is configured to operate as a data sense amplifier, which includes writing data to or reading data from the plurality of memory cells via the first bit line. as well as A second bit-line sense amplifier, connected to a second bit line among the plurality of bit lines, is defective and configured to operate as a physically unclonable function bit-line sense amplifier, which generates a physically unclonable function key as a unique random digital value based on the threshold voltage distribution of the transistors included in the physically unclonable function bit-line sense amplifier.

8. The memory device according to claim 7, wherein Each of the first bit line sense amplifier and the second bit line sense amplifier includes a pair of PMOS transistors and a pair of NMOS transistors; and The memory device further includes processing circuitry, the processing circuitry being configured to: During a pre-sensing period, the pair of PMOS transistors and the pair of NMOS transistors of the first bit line sense amplifier are driven in a first sequence. The pre-sensing period is a time during which the voltages of the plurality of bit lines and the voltages of the plurality of complementary bit lines corresponding to the plurality of bit lines are pre-sensed. During the pre-sensing period, the pair of PMOS transistors and the pair of NMOS transistors of the second bit-line sense amplifier are driven in a second order, the first order being different from the second order.

9. The memory device according to claim 8, wherein, The processing circuit is configured as follows: The driving of one of the pair of PMOS transistors and the pair of NMOS transistors of the first bit line sense amplifier having a smaller threshold voltage distribution is performed before the driving of the other of the pair of PMOS transistors and the pair of NMOS transistors of the first bit line sense amplifier. as well as The driving of the one of the pair of PMOS transistors and the pair of NMOS transistors of the second bit line sense amplifier having a higher threshold voltage distribution is performed before the driving of the other of the pair of PMOS transistors and the pair of NMOS transistors of the second bit line sense amplifier.

10. The memory device of claim 7, further comprising: The processing circuit is configured to associate a command corresponding to a bit line connected to the second bit line sense amplifier with a bit line connected to a third bit line sense amplifier, the third bit line sense amplifier being configured to operate as a data sense amplifier.

11. The memory device of claim 10, wherein, The processing circuit is configured as follows: The location information of bad memory cells among the plurality of memory cells is stored; and Store the position information of the second bit line sensing amplifier.

12. The memory device of claim 7, further comprising: The processing circuit is configured to perform an offset cancellation operation using the first bit line sense amplifier instead of the second bit line sense amplifier, the offset cancellation operation including compensating for the difference between the threshold voltage of a pair of PMOS transistors of the first bit line sense amplifier and the threshold voltage of a pair of NMOS transistors of the first bit line sense amplifier.

13. The memory device of claim 7, further comprising: A plurality of second bit-line sense amplifiers, comprising a plurality of second bit-line sense amplifiers, wherein the number of the plurality of second bit-line sense amplifiers is 40,000 or more, and the memory device has a capacity of at least 16 gigabits.

14. A memory device, comprising: Multiple memory cells are located at the intersection of multiple word lines and multiple bit lines; A plurality of bit line sense amplifiers are connected to the plurality of bit lines, the plurality of bit line sense amplifiers being configured to write data to or read data from the plurality of memory cells via the plurality of bit lines, wherein a first bit line sense amplifier of the plurality of bit line sense amplifiers is connected to the first bit line of the plurality of bit lines, a second bit line sense amplifier of the plurality of bit line sense amplifiers is connected to the second bit line of the plurality of bit lines, and is defective, each of the first bit line sense amplifier and the second bit line sense amplifier includes a pair of first transistors and a pair of second transistors; as well as The processing circuit is configured as follows: During a pre-sensing operation, a first drive signal is output, configured to drive the pair of first transistors of the first bit line sense amplifier, the pair of first transistors of the first bit line sense amplifier being driven before the pair of second transistors of the first bit line sense amplifier are driven. The pre-sensing operation includes pre-sensing the voltages of the plurality of bit lines and the voltages of the plurality of complementary bit lines corresponding to the plurality of bit lines. During the pre-sensing operation, a second drive signal is output, the second drive signal being configured to drive the pair of second transistors of the second bit line sense amplifier, the pair of second transistors of the second bit line sense amplifier being driven before the pair of first transistors of the second bit line sense amplifier are driven.

15. The memory device according to claim 14, wherein, The processing circuit is configured as follows: During a charge-sharing operation, a first word line of the plurality of word lines connected to a first memory cell in the plurality of memory cells is activated, the first memory cell in the plurality of memory cells being connected to the first bit line, and during the charge-sharing operation, the charge stored in the capacitor of the first memory cell in the plurality of memory cells is combined with the charge of the first bit line; as well as During the charge-sharing operation, the second word line of the plurality of word lines connected to the second memory cell of the plurality of memory cells is deactivated, and the second memory cell of the plurality of memory cells is connected to the second bit line.

16. The memory device according to claim 15, wherein, The processing circuit is configured to output an isolation signal during the pre-sensing operation, the isolation signal being configured to connect the second bit line and the sensing bit line corresponding to the second bit line.

17. The memory device according to claim 14, wherein, The processing circuit is configured to activate, during a charge-sharing operation, one of the plurality of word lines connected to a specific memory cell among the plurality of memory cells, the specific memory cell being connected to the second bit line, wherein during the charge-sharing operation, the charge stored in the capacitor of the specific memory cell is combined with the charge of the second bit line.

18. The memory device according to claim 17, wherein, The processing circuit is configured to, during the charge-sharing operation, activate one of the plurality of word lines while simultaneously activating another word line among the plurality of word lines connected to another memory cell among the plurality of memory cells, the other memory cell being connected to a complementary bit line among the plurality of complementary bit lines corresponding to the second bit line.

19. The memory device of claim 14, wherein, The processing circuit is configured as follows: During the offset cancellation operation, a first offset cancellation signal is output, the first offset cancellation signal being configured to connect the first bit line to a complementary sensing bit line corresponding to the first bit line, the offset cancellation operation including compensating for the difference between the threshold voltage of the pair of first transistors and the threshold voltage of the pair of second transistors; as well as During the offset cancellation operation, a second offset cancellation signal is output, which disconnects the second bit line from the complementary sensing bit line corresponding to the second bit line.

20. The memory device of claim 19, wherein The first drive signal is configured to supply a first voltage to the first bit line sense amplifier, during the pre-sensing operation the first voltage rises to a level below the supply voltage and then rises to the supply voltage; The second drive signal is configured to supply a second voltage to the second bit line sense amplifier, during the pre-sensing operation the second voltage rises to the power supply voltage; as well as The processing circuit is configured as follows: A third drive signal is output, configured to supply a third voltage to the first bit-line sense amplifier, during the pre-sensing operation, the third voltage drops to a level above ground and then drops to ground. A fourth drive signal is output, which is configured to supply a fourth voltage to the second bit line sense amplifier, during the pre-sensing operation, the fourth voltage is reduced to the ground voltage.

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