Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a first gate structure on the surface of the substrate; forming source and drain openings in the substrate on both sides of the first gate structure; forming a first stress layer on the bottom surface and sidewall surface of the source and drain opening; and thinning the sidewall of the first stress layer. The semiconductor structure formed by the method can improve the performance of semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved.

[0003] In a very large scale integrated circuit, stress is usually formed on a transistor to increase the carrier mobility of the transistor and thus increase the driving current of the transistor.

[0004] However, the performance of semiconductor devices formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor devices.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first gate structure on the surface of the substrate; forming source and drain openings in the substrate on both sides of the first gate structure; forming a first stress layer on the bottom surface and side wall surface of the source and drain opening; and thinning the side wall of the first stress layer.

[0007] Optionally, the method for thinning the first stress layer includes: forming a transition layer in a side wall of the first stress layer; and removing the transition layer.

[0008] Optionally, the method for forming the transition layer includes: performing a first ion implantation process on the sidewall of the first stress layer.

[0009] Optionally, the ions implanted in the first ion implantation process include a combination of one or more of nitrogen ions, carbon ions, germanium ions and nitrogen ions.

[0010] Optionally, the parameters of the first ion implantation process include: an ion implantation energy range of 1KeV to 5KeV; an ion implantation dose range of 1e15atm / cm 2 ~1e16atm / cm 2 .

[0011] Optionally, the parameters of the first ion implantation process include: an ion implantation angle range of 7 degrees to 25 degrees, the ion implantation angle is an angle between the ion implantation direction and a reference plane, and the reference plane is a plane perpendicular to the substrate surface and parallel to the channel width direction.

[0012] Optionally, the process of removing the transition layer includes a wet etching process, wherein the wet etching process has a first etching rate for the first stress layer, and the wet etching process has a second etching rate for the transition layer, and the second etching rate is greater than the first etching rate.

[0013] Optionally, after the sidewalls of the first stress layer are thinned, the sidewalls of the first stress layer have a first thickness in a direction perpendicular to the sidewalls of the source / drain openings, and the first thickness ranges from 1 nanometer to 4 nanometers.

[0014] Optionally, the first stress layer includes a first region and a second region, the first region and the second region are arranged in a direction perpendicular to the surface of the substrate, and the sidewall of the first stress layer is located in the first region; after thinning the sidewall of the first stress layer, the first stress layer in the second region has a second thickness in a direction perpendicular to the bottom surface of the source and drain opening, and the second thickness is greater than the first thickness.

[0015] Optionally, the second thickness ranges from 5 nanometers to 10 nanometers.

[0016] Optionally, the aspect ratio of the source / drain opening is in a range of 5:6 to 10:7.

[0017] Optionally, a second stress layer is formed on the surface of the first stress layer.

[0018] Optionally, the method for forming the second stress layer includes: forming the second stress layer on the surface of the first stress layer after thinning the side wall of the first stress layer; the process for forming the first stress layer includes an epitaxial growth process; and the process for forming the second stress layer includes an epitaxial growth process.

[0019] Optionally, the method further includes: after thinning the sidewall of the first stress layer and before forming the second stress layer, performing surface treatment on the first stress layer, the surface treatment including ashing treatment and annealing treatment performed after the ashing treatment.

[0020] Optionally, the method further includes: forming a first barrier layer on the top surface of the first gate structure, forming a first sidewall spacer on the sidewall surface of the first gate structure, and forming a second sidewall spacer on the surface of the first sidewall spacer.

[0021] Optionally, the method for forming the first side wall includes: before forming the source and drain openings, forming an initial first side wall on the side wall surface of the first gate structure; after forming the second stress layer, thinning the initial first side wall to form a first side wall; the method for forming the second side wall includes: after thinning the initial first side wall, forming a second side wall on the surface of the first side wall; the material of the second side wall includes a low dielectric constant material.

[0022] Optionally, the method further includes: forming a third sidewall spacer on the surface of the second sidewall spacer; the material of the third sidewall spacer includes silicon germanium doped with boron ions.

[0023] Optionally, a fin layer is provided on the substrate, the first gate structure spans across a surface of the fin layer, and the source and drain openings are located in the fin layer on both sides of the first gate structure.

[0024] Optionally, the material of the first stress layer includes carbon silicon or silicon germanium; the material of the second stress layer includes carbon silicon or silicon germanium.

[0025] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by any of the above-mentioned formation methods.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] In the method for forming a semiconductor structure of the technical solution of the present invention, since the sidewall of the first stress layer is thinned after the first stress layer is formed, the bottom of the first stress layer is kept thicker while the thickness of the sidewall of the first stress layer is reduced. Since the sidewall of the first stress layer is thinned, the space in the source-drain opening after the first stress layer is formed is increased, that is, a larger filling space is reserved for the second stress layer formed subsequently to form a larger second stress layer, so that the larger second stress layer forms a greater stress on the first stress layer with thinned sidewall thickness, so that the driving current of the semiconductor device can be increased, the response speed of the circuit is increased, and the performance of the semiconductor device is improved. At the same time, since the bottom of the first stress layer is thicker, the ability of the bottom of the first stress layer to isolate electron tunneling is enhanced, thereby reducing the leakage current at the bottom of the first stress layer and improving the performance of the semiconductor device.

[0028] Furthermore, since the energy range of the ion implantation in the first ion implantation process is 1KeV to 5KeV, the dose range of the ion implantation is 1e15atm / cm 2 ~1e16atm / cm 2 That is, the ion implantation energy and dosage of the first ion implantation process are relatively low. Therefore, when the transition layer is formed by the first ion implantation process, the implantation and diffusion of ions can be better controlled to form a transition layer having a thickness less than that of the side wall of the first stress layer, so that after removing the transition layer, a thinner side wall of the first stress layer can be formed.

[0029] Furthermore, since the angle range of the first ion implantation process is 7 degrees to 25 degrees, the angle range can reduce the ions injected into the bottom of the first stress layer while injecting ions into the side walls of the first stress layer. Therefore, when removing the transition layer, the impact of the process of removing the transition layer on the bottom of the first stress layer is reduced, that is, the reduction in the thickness of the bottom of the first stress layer is reduced, so as to form a first stress layer with a thicker bottom thickness and a thinner sidewall thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 3 The invention is a schematic cross-sectional structure diagram of a formation process of a semiconductor structure;

[0031] Figures 4 to 11 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the performance of semiconductor devices formed by the prior art needs to be improved.

[0033] Figures 1 to 3 It is a schematic cross-sectional structure diagram of the formation process of a semiconductor structure.

[0034] Please refer to Figure 1 , providing a substrate 10; forming a gate structure 11 on the surface of the substrate 10; etching a portion of the substrate 10 on both sides of the gate structure 11 to form an opening 12 in the substrate 10, and the surface of the substrate 10 exposes the opening 12.

[0035] Please refer to Figure 2 A first stress layer 13 is formed on the sidewall surface and the bottom surface of the opening 12 .

[0036] Please refer to Figure 3 After forming the first stress layer 13 , a second stress layer 14 is formed in the opening 12 , and the first stress layer 13 and the second stress layer 14 constitute a source-drain doping layer, thereby forming a transistor device.

[0037] In the above example, the gate structure 11 is far away from the bottom of the first stress layer 13, and has poor control over the electrons at the bottom of the first stress layer 13. In order to reduce the leakage current formed at the bottom of the first stress layer 13, a thicker first stress layer 13 is formed, thereby increasing the thickness A at the bottom of the first stress layer 13 in a direction perpendicular to the bottom surface of the first stress layer 13. Due to the increase in thickness A, the ability of the bottom of the first stress layer 13 to isolate electron tunneling is enhanced, thereby reducing the leakage current at the bottom of the first stress layer 13 and improving the performance of the semiconductor device.

[0038] However, in order to increase the thickness A, the overall thickness of the formed first stress layer 13 is relatively thick, that is, in the direction perpendicular to the side wall surface of the first stress layer 13, the thickness of the side wall of the first stress layer 13 is also relatively thick. Therefore, after the first stress layer 13 is formed, the space in the opening 12 is reduced, resulting in that the second stress layer 14 formed in the opening 12 is also smaller.

[0039] Since the second stress layer 14 is relatively small, the stress generated by the second stress layer 14 on the sidewall of the first stress layer 13 is also relatively small, resulting in a smaller driving current of the transistor device, thereby deteriorating the performance of the semiconductor structure.

[0040] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a first gate structure on the surface of the substrate; forming source and drain openings in the substrate on both sides of the first gate structure; forming a first stress layer on the bottom surface and sidewall surface of the source and drain opening; and thinning the sidewall of the first stress layer. The semiconductor structure and the method for forming the same can improve the performance of semiconductor devices.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 11 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0043] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 A schematic cross-sectional structural diagram along the A-A1 direction, providing a substrate 100; forming a first gate structure 110 on the surface of the substrate 100.

[0044] The material of the substrate 100 is a semiconductor material. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0045] In this embodiment, a fin layer 101 is formed on the substrate 100 , and the first gate structure 110 spans across the surface of the fin layer 101 .

[0046] In another embodiment, the substrate 100 does not have a fin layer 101 .

[0047] In this embodiment, the first gate structure 110 includes a gate dielectric layer 111 and a first gate electrode layer 112 formed on a surface of the gate dielectric layer 111 .

[0048] In another embodiment, the first gate structure further includes a first work function layer located between the gate dielectric layer and the first gate electrode layer.

[0049] In this embodiment, the process of forming the gate dielectric layer 111 includes: a deposition process; the material of the gate dielectric layer 111 is silicon oxide.

[0050] In another embodiment, the material of the gate dielectric layer includes a material with a K value greater than 3.9, such as titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide or lanthanum oxide.

[0051] In this embodiment, the material of the first gate electrode layer 112 includes polysilicon.

[0052] In another embodiment, the material of the first gate electrode layer includes a metal material, such as a combination of one or more of tungsten, cobalt, copper, nickel, titanium and titanium nitride.

[0053] In this embodiment, the method for forming the semiconductor structure further includes: forming a first barrier layer 122 on the top surface of the first gate structure 110 , and forming an initial first spacer 121 on the sidewall surface of the first gate structure 110 .

[0054] The first blocking portion 122 is used to protect the first gate structure 110 from being affected by the process in subsequent process steps, so as to maintain a good morphology.

[0055] The initial first spacer 121 is used, on the one hand, to protect the first gate structure 110 from being affected by the process in subsequent process steps, so as to maintain a good morphology; on the other hand, it is used as the material of the first spacer formed subsequently.

[0056] In this embodiment, the material of the first blocking portion 122 is silicon nitride.

[0057] In another embodiment, the material of the first barrier portion includes a material with a K value greater than 3.9, such as titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, or lanthanum oxide.

[0058] In this embodiment, the material of the initial first spacer 121 is silicon nitride.

[0059] In another embodiment, the material of the first spacer includes a material with a K value greater than 3.9, such as titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, or lanthanum oxide.

[0060] Please refer to Figure 6 , source and drain openings 102 are formed in the substrate 100 on both sides of the first gate structure 110 .

[0061] In this embodiment, the source-drain openings 102 are located in the fin layer 101 on both sides of the first gate structure 110 .

[0062] The source / drain openings 102 provide space for subsequently forming a first stress layer and a second stress layer.

[0063] The process of forming the source / drain openings 102 includes: an anisotropic dry etching process or an anisotropic wet etching process.

[0064] In this embodiment, the aspect ratio of the source and drain openings 102 ranges from 5:6 to 10:7. Specifically, the depth in the aspect ratio refers to the distance between the bottom surface of the source and drain openings 102 and the surface of the fin layer 101 in a direction perpendicular to the surface of the substrate 100 to which it belongs; the width in the aspect ratio refers to the distance between the sidewall surfaces of the source and drain openings 102 in a direction perpendicular to the extension plane of the fin layer 101.

[0065] If the aspect ratio is too large, when a first stress layer is subsequently formed in the source / drain opening 102 and a transition layer is formed in the sidewall of the first stress layer, the reaction gas in the process of forming the transition layer may have difficulty entering the deep part of the source / drain opening 102, resulting in failure to form the transition layer in the sidewall of the first stress layer in the deep part of the source / drain opening 102; if the aspect ratio is too small, when the transition layer is subsequently formed, the reaction gas in the process of forming the transition layer may easily reach the bottom surface of the first stress layer, thereby forming the transition layer not only in the sidewall of the first stress layer but also in the bottom of the first stress layer, and the thickness of the transition layer formed at the bottom of the first stress layer is relatively large, resulting in a significant reduction in the thickness of the bottom of the first stress layer after the transition layer is removed, resulting in a reduction in the ability of the bottom of the first stress layer to isolate electron tunneling, thereby increasing the leakage current at the bottom of the first stress layer and reducing the performance of the semiconductor device. Therefore, when the aspect ratio of the source / drain opening 102 is appropriate, that is, when the aspect ratio ranges from 5:6 to 10:7, on the one hand, it can be beneficial to the subsequent formation of the transition layer on the entire side wall of the first stress layer; on the other hand, it can block part of the reaction gas in the process of forming the transition layer, so that the transition layer formed at the bottom of the first stress layer is thinner, thereby reducing the impact of the process of forming the transition layer on the bottom of the first stress layer.

[0066] Please refer to Figure 7 A first stress layer 130 is formed on the bottom surface and sidewall surface of the source / drain opening 102 .

[0067] The first stress layer 130 and the subsequently formed second stress layer constitute source and drain doping layers, thereby forming a transistor device.

[0068] In this embodiment, the process of forming the first stress layer 130 includes an epitaxial growth process.

[0069] In another embodiment, the process of forming the first stress layer includes an ion doping process.

[0070] In this embodiment, the first stress layer 130 includes a first region I and a second region II. The first region I and the second region II are arranged in a direction perpendicular to the surface of the substrate 100, and the sidewall of the first stress layer 130 is located in the first region I.

[0071] In this embodiment, the material of the first stress layer 130 is silicon germanium.

[0072] In another embodiment, the material of the first stress layer includes carbon silicon.

[0073] The method for forming a semiconductor structure further includes: after forming the first stress layer 130 , thinning a sidewall of the first stress layer 130 .

[0074] Since the sidewall of the first stress layer 130 is thinned after the first stress layer 130 is formed, the space in the source-drain opening 102 is increased after the first stress layer 130 is formed, that is, a larger filling space is reserved for the second stress layer formed subsequently to form a larger second stress layer. Therefore, the larger second stress layer forms a greater stress on the first stress layer 130 with a thinned sidewall thickness, so that the driving current of the semiconductor device can be increased, the response speed of the circuit is improved, and the performance of the semiconductor device is improved.

[0075] The method for thinning the first stress layer 130 includes: forming a transition layer in the side wall of the first stress layer 130; and removing the transition layer. Figures 8 to 9 .

[0076] Please refer to Figure 8 , a transition layer 131 is formed in the sidewall of the first stress layer 130 .

[0077] The sidewalls of the first stress layer 130 include: a sidewall located below the first gate structure 110 , and a sidewall 132 opposite to the sidewall located below the first gate structure 110 .

[0078] Specifically, in this embodiment, the transition layer 131 is located in the sidewall of the first stress layer 130 below the first gate structure 110 .

[0079] Since the material of the transition layer 131 is different from that of the first stress layer 130, the transition layer 131 and the first stress layer 130 can be etched at different rates through a subsequent etching process, so that the transition layer 131 is removed through the etching process while reducing damage to the remaining portion of the first stress layer 130 caused by the etching process.

[0080] The method for forming the transition layer 131 includes: performing a first ion implantation process on the sidewall of the first stress layer 130 of the first region I. Thus, the material of the transition layer 131 and the material of the first stress layer 130 are different, that is, the type and concentration of doped ions in the material of the transition layer 131 and the material of the first stress layer 130 are different, or both.

[0081] In this embodiment, when the first ion implantation process is performed, since the implanted ions of the first ion implantation process are completely blocked by the first gate structure 110 , no transition layer is formed in the sidewall 132 .

[0082] In another embodiment, since the implanted ions of the first ion implantation process are partially blocked by the first gate structure 110 , a thinner transition layer is formed in a portion of the sidewall opposite to the sidewall below the first gate structure 110 and close to the substrate surface.

[0083] In this embodiment, when the first ion implantation process is performed, since the implanted ions of the first ion implantation process are partially blocked by the first gate structure 110 and the sidewalls of the first stress layer 130 , a thinner transition layer 135 is formed at the bottom of the first stress layer 130 .

[0084] Therefore, after the transition layer 131 and the transition layer 135 are subsequently removed, the thickness of the sidewall of the first stress layer 130 can be reduced while the bottom of the first stress layer 130 is made thicker. Since the bottom of the first stress layer 130 is thicker, the ability of the bottom of the first stress layer 130 to isolate electron tunneling is enhanced, thereby reducing the leakage current at the bottom of the first stress layer and improving the performance of the semiconductor device.

[0085] In this embodiment, the ions implanted by the first ion implantation process include germanium ions. Therefore, the concentration of germanium ions in the first stress layer 130 is lower than that in the transition layer 131, so that the gas or liquid in the subsequent etching process can have different etching ratios for the material of the first stress layer 130 and the material of the transition layer 131, thereby reducing the damage of the etching process to the first stress layer 130 while removing the transition layer 131.

[0086] In another embodiment, the ions implanted by the first ion implantation process include one or more of nitrogen ions, carbon ions and a combination of nitrogen ions, or include a combination of germanium ions and one or more of nitrogen ions, carbon ions and nitrogen ions.

[0087] In this embodiment, the parameters of the first ion implantation process include: the energy range of the ion implantation is 1KeV to 5KeV; the dose range of the ion implantation is 1e15atm / cm 2 ~1e16atm / cm 2 .

[0088] Since the energy range of the ion implantation in the first ion implantation process is 1KeV to 5KeV, the dose range of the ion implantation is 1e15atm / cm 2 ~1e16atm / cm 2 That is, the ion implantation energy and dosage of the first ion implantation process are relatively low. Therefore, when the transition layer 131 is formed by the first ion implantation process, the implantation and diffusion of ions can be better controlled to form a transition layer 131 having a thickness less than the thickness of the side wall of the first stress layer 130, so that after removing the transition layer 131, a thinner side wall of the first stress layer 130 can be formed.

[0089] In this embodiment, the parameters of the first ion implantation process also include: the angle range of ion implantation is 7 degrees to 25 degrees, the angle of ion implantation is the angle between the direction of ion implantation and a reference plane, and the reference plane is a plane perpendicular to the substrate surface and parallel to the channel width direction.

[0090] Since the angle range of the first ion implantation process is 7 degrees to 25 degrees, the angle range can reduce the ions injected into the bottom of the first stress layer 130 while injecting ions into the sidewalls of the first stress layer 130. Therefore, when removing the transition layer 131, the influence of the process of removing the transition layer 131 on the bottom of the first stress layer 130 is further reduced, that is, the reduction in the thickness of the bottom of the first stress layer 130 is reduced, so that a first stress layer with a thicker bottom thickness and a thinner sidewall thickness is formed.

[0091] Please refer to Fig. 9 After forming the transition layer 131, the transition layer 131 is removed. Thus, the thickness of the side wall of the first stress layer 130 in the first region I is reduced.

[0092] In this embodiment, the transition layer 135 is removed at the same time as the transition layer 131 is removed.

[0093] The process of removing the transition layer 131 includes a wet etching process, wherein the wet etching process has a first etching rate for the first stress layer 130, and the wet etching process has a second etching rate for the transition layer 131, and the second etching rate is greater than the first etching rate. Thus, the transition layer 131 can be removed, and at the same time, the influence of the wet etching process on the first stress layer 130 is reduced, so as to achieve the purpose of thinning the side wall of the first stress layer 130.

[0094] In this embodiment, the parameters of the wet etching include: the etching solution is HCl solution, the temperature is 25 degrees Celsius to 300 degrees Celsius, and the volume percentage of the HCl solution is 20% to 90%.

[0095] After thinning the sidewalls of the first stress layer 130, specifically, after removing the transition layer 131, the sidewalls of the first stress layer 130 in the first region I have a first thickness C in a direction perpendicular to the sidewalls of the source / drain openings; and the first stress layer 130 in the second region II has a second thickness B in a direction perpendicular to the bottom surface of the source / drain openings 102.

[0096] Since the bottom of the first stress layer 130 is less affected by the first ion implantation process and the wet etching process, the first thickness C is less than the second thickness B.

[0097] In this embodiment, the first thickness C ranges from 1 nanometer to 4 nanometers. Therefore, the first thickness C is relatively thin, thereby reserving a larger space for the subsequent formation of the second stress layer, and being able to form a larger second stress layer, so that the larger second stress layer forms a larger stress on the sidewall of the thinner first stress layer, so that the driving current of the semiconductor device can be increased, the response speed of the circuit is increased, and the performance of the semiconductor device is improved.

[0098] In this embodiment, the second thickness B is in a range of 5 nanometers to 10 nanometers.

[0099] If the second thickness B is too large, the thickness of the first stress layer 130 is too large and occupies too much space in the source-drain opening 102, which is not conducive to the subsequent formation of a large second stress layer, so that the second stress layer generates a large stress on the first stress layer 130, thereby increasing the driving current of the semiconductor device; if the second thickness B is too small, the bottom of the first stress layer 130 has a poor ability to isolate electron tunneling, thereby increasing the leakage current at the bottom of the first stress layer 130. Therefore, when the second thickness B is in the range of 5 nanometers to 10 nanometers, it is more appropriate, so that the first stress layer 130 does not occupy too much space in the source-drain opening 102, while enhancing the ability of the bottom of the first stress layer 130 to isolate electron tunneling, thereby reducing the leakage current at the bottom of the first stress layer 130 and improving the performance of the semiconductor device.

[0100] Please refer to Fig.10 , a second stress layer 140 is formed on the surface of the first stress layer 130 .

[0101] The method for forming the second stress layer 140 includes: after thinning the sidewall of the first stress layer 130, forming the second stress layer 140 on the surface of the first stress layer 130. Specifically, after removing the transition layer 131, the second stress layer 140 is formed.

[0102] In this embodiment, the process of forming the second stress layer 140 includes an epitaxial growth process.

[0103] In another embodiment, the process of forming the second stress layer includes an ion doping process.

[0104] In this embodiment, the material of the second stress layer 140 is silicon germanium.

[0105] In another embodiment, the material of the second stress layer includes carbon silicon.

[0106] In this embodiment, after removing the transition layer 131 and before forming the second stress layer 140, the first stress layer 130 is subjected to surface treatment. Thus, on the one hand, the residue on the surface of the first stress layer 130 can be removed to increase the reliability of the semiconductor device, and on the other hand, the surface of the first stress layer 130 is made smoother, which is beneficial to the process of forming the second stress layer 140, thereby forming the second stress layer 140 with better morphology and fewer internal defects.

[0107] The surface treatment includes: an ashing treatment and an annealing treatment performed after the ashing treatment.

[0108] The process parameters of the ashing treatment include: the gas includes one or more combinations of argon, helium and hydrogen isotope gases, and the temperature ranges from 100°C to 200°C.

[0109] The process parameters of the annealing treatment include: the gas includes an inert gas, and the temperature ranges from 500°C to 800°C.

[0110] Please refer to Fig.11 After forming the second stress layer 140 , the initial first sidewall 121 is thinned to form a first sidewall 123 ; a second sidewall 150 is formed on a surface of the first sidewall 123 ; and a third sidewall 160 is formed on a surface of the second sidewall 150 .

[0111] The first spacer 123 is used to form an isolation region for isolating the first gate structure 110 , so that the first gate structure 110 can be used as a dummy gate to perform a gate-last process on the semiconductor structure.

[0112] The second spacer is used to reduce the parasitic capacitance between the first gate structure 110 or the second gate structure formed subsequently and the source-drain doped layer, so as to improve the performance of the semiconductor device.

[0113] The third sidewall 160 can, on the one hand, be used to smooth the surface of the semiconductor structure, thereby facilitating the subsequent formation of other graphic layers on the surface of the semiconductor structure; and on the other hand, can also raise the surface of the source-drain doped layer, thereby facilitating the subsequent formation of an interconnect structure electrically interconnected with the source-drain doped layer.

[0114] In this embodiment, the process of thinning the initial first sidewall spacer 121 includes a dry etching process.

[0115] In this embodiment, the process of forming the second spacer 150 includes an epitaxial growth process.

[0116] The material of the second spacer 150 includes a low dielectric constant material, and the dielectric constant of the low dielectric constant material is less than 3.9. Thus, the parasitic capacitance between the first gate structure 110 or the second gate structure formed subsequently and the source-drain doped layer can be better reduced to improve the performance of the semiconductor device.

[0117] In this embodiment, the process of forming the third spacer 160 includes an epitaxial growth process, and while the third spacer 160 is formed by epitaxial growth, the third spacer 160 is in-situ doped to introduce doping ions.

[0118] In this embodiment, the material of the third spacer 160 includes silicon germanium doped with boron ions.

[0119] In this embodiment, the method for forming the semiconductor structure also includes: after forming the third sidewall 160, planarizing the first barrier layer 122, the first sidewall 123, the second sidewall 150 and the third sidewall 160 until the top surface of the first gate structure 110 is exposed; after exposing the top surface of the first gate structure 110, removing the first gate structure 110 to form a second opening (not shown); and forming a second gate structure (not shown) across the fin layer 101 in the second opening.

[0120] The second gate structure includes a second gate dielectric layer located on the fin layer 101 , a second work function layer located on the second gate dielectric layer, and a second gate electrode layer located on the second work function layer.

[0121] In another embodiment, the second gate structure is not formed.

[0122] Correspondingly, the present invention also provides a semiconductor structure formed by the above-mentioned forming method.

[0123] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first gate structure on a surface of the substrate; forming source and drain openings in the substrate on both sides of the first gate structure; forming a first stress layer on the bottom surface and side wall surface of the source / drain opening; thinning a side wall of the first stress layer; Wherein, the sidewall of the first stress layer includes: a sidewall located below the first gate structure and a sidewall opposite to the sidewall located below the first gate structure; The method for thinning the first stress layer includes: forming a transition layer in the side wall of the first stress layer located below the first gate structure, and no transition layer is formed on the side wall opposite to the side wall located below the first gate structure; etching to remove the transition layer; the transition layer and the first stress layer have different etching rates.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the transition layer includes: performing a first ion implantation process on the sidewall of the first stress layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The ions implanted in the first ion implantation process include one or more combinations of nitrogen ions, carbon ions, germanium ions and nitrogen ions.

4. The method for forming a semiconductor structure according to claim 2, wherein: The parameters of the first ion implantation process include: the energy range of ion implantation is 1KeV to 5KeV; the dose range of ion implantation is 1e15 atm / cm 2 ~1e16 atm / cm 2 .

5. The method for forming a semiconductor structure according to claim 2, wherein: The parameters of the first ion implantation process include: the angle range of ion implantation is 7 degrees to 25 degrees, the angle of ion implantation is the angle between the direction of ion implantation and a reference plane, and the reference plane is a plane perpendicular to the substrate surface and parallel to the channel width direction.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the transition layer includes a wet etching process, wherein the wet etching process has a first etching rate for the first stress layer, and the wet etching process has a second etching rate for the transition layer, and the second etching rate is greater than the first etching rate.

7. The method for forming a semiconductor structure according to claim 1, wherein: After the sidewall of the first stress layer is thinned, the sidewall of the first stress layer has a first thickness in a direction perpendicular to the sidewall surface of the source / drain opening, and the first thickness ranges from 1 nanometer to 4 nanometers.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first stress layer includes a first region and a second region, the first region and the second region are arranged in a direction perpendicular to the surface of the substrate, and the sidewall of the first stress layer is located in the first region; after thinning the sidewall of the first stress layer, the first stress layer in the second region has a second thickness in a direction perpendicular to the bottom surface of the source and drain opening, and the second thickness is greater than the first thickness.

9. The method for forming a semiconductor structure according to claim 8, wherein: The second thickness is in a range of 5 nanometers to 10 nanometers.

10. The method for forming a semiconductor structure according to claim 1, wherein: The depth-to-width ratio of the source-drain opening is in a range of 5:6 to 10:

7.

11. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A second stress layer is formed on the surface of the first stress layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the second stress layer includes: forming the second stress layer on the surface of the first stress layer after thinning the side wall of the first stress layer; the process of forming the first stress layer includes an epitaxial growth process; the process of forming the second stress layer includes an epitaxial growth process.

13. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: After thinning the sidewall of the first stress layer and before forming the second stress layer, the first stress layer is subjected to surface treatment, wherein the surface treatment includes ashing treatment and annealing treatment after the ashing treatment.

14. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: A first barrier layer is formed on the top surface of the first gate structure, a first sidewall spacer is formed on the sidewall surface of the first gate structure, and a second sidewall spacer is formed on the surface of the first sidewall spacer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first sidewall includes: before forming the source-drain opening, forming an initial first sidewall on the sidewall surface of the first gate structure; after forming the second stress layer, thinning the initial first sidewall to form a first sidewall; the method for forming the second sidewall includes: after thinning the initial first sidewall, forming a second sidewall on the surface of the first sidewall; the material of the second sidewall includes a low dielectric constant material.

16. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: forming a third sidewall spacer on the surface of the second sidewall spacer; The material of the third spacer includes silicon germanium doped with boron ions.

17. The method for forming a semiconductor structure according to claim 1, wherein: A fin layer is provided on the substrate, the first gate structure spans across the surface of the fin layer, and the source and drain openings are located in the fin layer on both sides of the first gate structure.

18. The method for forming a semiconductor structure according to claim 11, wherein: The material of the first stress layer includes carbon silicon or silicon germanium; the material of the second stress layer includes carbon silicon or silicon germanium.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18.

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