Semiconductor device and method for forming a semiconductor structure

Abstract

Systems, devices, and methods related to semiconductor structure formation are described. An example device includes a first trench and a second trench formed in a semiconductor substrate material, wherein the first trench and the second trench are adjacent to and separated by the semiconductor substrate material. The device includes: a metal material formed in the first trench to a first height, the first height being less than a second height of the metal material formed in the second trench relative to the semiconductor substrate material; and a polysilicon material formed above the metal material in the first trench to a first depth, the first depth being greater than a second depth of the polysilicon material formed above the metal material in the second trench relative to the semiconductor substrate material. The larger first depth of the polysilicon material formed in the first trench reduces charge transfer through the metal material in the first trench.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods, and more particularly to semiconductor structure formation. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), and flash memory (e.g., NAND, NOR, etc.), among others. Some types of memory devices may be non-volatile memory (e.g., ReRAM, NAND), and may be used in a wide range of electronic applications requiring high memory density, high reliability, and low power consumption. Volatile memory cells (e.g., DRAM cells) require power to maintain their stored data state (e.g., to compensate for charge loss via a refresh process), in contrast to non-volatile memory cells (e.g., flash memory cells), which maintain their stored state without power. However, various volatile memory cells, such as DRAM cells, can be operated (eg, programmed, read, erased, etc.) faster than various nonvolatile memory cells, such as flash memory cells. Summary of the invention

[0003] One aspect of the present disclosure relates to a semiconductor device, comprising: a first trench and a second trench formed in a semiconductor substrate material, wherein the first trench and the second trench are adjacent to and separated by the semiconductor substrate material; a metal material formed in the first trench to a first height, the first height being smaller than a second height of the metal material formed in the second trench relative to the semiconductor substrate material; and a polysilicon material formed to a first depth above the metal material in the first trench, the first depth being greater than a second depth of the polysilicon material formed on the metal material in the second trench relative to the semiconductor substrate material; wherein the larger first depth of the polysilicon material formed in the first trench reduces charge transfer via the metal material in the first trench.

[0004] Another aspect of the present disclosure relates to a method for forming a semiconductor structure, which includes: forming a portion of a first trench in a semiconductor substrate material to a first depth, wherein the portion of the first trench is designed to serve as a through access line of an isolation trench; forming an adjacent portion of a second depth of a second trench in the semiconductor substrate material to a second depth, wherein the first depth is greater than the second depth, and the portion of the second trench is designed to serve as a gate of an active access line of an access device of a memory cell; forming a metal material to have a first height in the first trench and a second height in the second trench, the first height and the second height each conforming to a difference between a corresponding first depth and a corresponding second depth; forming a polysilicon material above the metal material to conform to a difference between the corresponding first depth and the second depth, such that the polysilicon material in the first trench has a third depth greater than a fourth depth of the polysilicon material in the second trench; and in response to the larger third depth of the polysilicon material in the first trench, affecting the work function of electron movement to reduce charge transfer from a storage node of the memory cell via the metal material in the first trench.

[0005] Another aspect of the present disclosure relates to a method for forming a semiconductor structure, comprising: forming a first portion of a trench in a semiconductor substrate material to a first depth; forming an adjacent second portion of the trench in the semiconductor substrate material to a second depth, wherein the first depth is greater than the second depth; forming a first metal material to have a first height in the first portion of the trench and a second height in the second portion of the trench, the first height and the second height each conforming to a difference between a corresponding first depth and a corresponding second depth; forming a polysilicon material over the first metal material to conform to the difference between the corresponding first depth and the second depth, such that the polysilicon material in the first portion of the trench has a third depth greater than a fourth depth of the polysilicon material in the second portion of the trench; forming a second metal material in a recess of the polysilicon material in the first portion and the second portion of the trench, wherein a bottom of the recess conforms to the third depth in the first portion of the trench and the fourth depth in the second portion of the trench and separates the second metal material from the first metal material; and reducing resistance along the length of the corresponding first portion and the corresponding second portion of the trench in response to the second metal material having a work function substantially equal to the work function of the polysilicon material and a resistivity lower than the resistivity of the polysilicon material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An example cross-sectional view of a portion of a semiconductor structure formed according to various embodiments of the present disclosure is shown.

[0007] Figure 2 An example top view of a memory array structure according to various embodiments of the present disclosure is shown.

[0008] Figures 3A to 3CExample cross-sectional views of memory array structures at different locations within a semiconductor substrate in a semiconductor manufacturing sequence are shown according to various embodiments.

[0009] Figures 4A to 4E Perspective views showing various cutouts of a portion of an example three-dimensional semiconductor structure at specific points in an example semiconductor fabrication sequence according to various embodiments of the present disclosure.

[0010] Figure 5 An example cross-sectional view of a portion of another semiconductor structure formed according to various embodiments of the present disclosure is shown.

[0011] Figures 6 to 7 is a flow chart of an example method for fabricating a semiconductor structure according to various embodiments of the present disclosure.

[0012] Figure 8 is a functional block diagram of a system for implementing an example semiconductor manufacturing process according to various embodiments of the present disclosure.

[0013] Fig. 9 is a functional block diagram of a computing system including at least one storage system according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The physical size of memory devices is getting smaller and smaller. Memory devices may include memory cells having transistors and memory elements. The transistors and memory elements may be implemented as one transistor one capacitor (1T1C) memory cells. The memory cells may maintain spacing from other components of the memory device, such as sensing circuits (e.g., sense amplifiers) and sub-word line drivers (SWDs). As the spacing of these other components of the memory device decreases, the spacing of the transistors of the memory device also decreases. Reducing the spacing of transistors reduces the spacing between adjacent transistors, which may increase the probability of short channel effects (SCE) and / or random doping fluctuations (RDF). Halo margins may deteriorate, and there may be a threshold voltage (Vt) mismatch between adjacent transistors. Increasing the spacing between adjacent transistors may reduce the probability of SCE, but it may also limit the minimum spacing of other components of the memory device. It is becoming increasingly difficult to turn on and off transistors during a read operation to shrink the device and accurately detect the stored charge.

[0015] In some approaches, a buried recessed access device (BRAD) may be used to accommodate shrinking dimensions. BRADs may use doping to improve channel conductivity. Scaling BRADs for the next generation has become increasingly challenging due to the coupled tradeoff between gate induced drain leakage (GIDL) and subthreshold leakage. However, due to higher junction field injection damage, the process of achieving a desired Vt through various injections has a higher GIDL tradeoff. The reduced scale for BRAD implementation also results in storage nodes being coupled to active access lines (e.g., in the active region of a word line) of an access device (e.g., a transistor), which has an electric field at the interface that may cause GIDL of charge to reach adjacent access lines (e.g., in an isolation region adjacent to a word line). Charge leakage (e.g., transfer) to adjacent isolation regions may be offset by increasing the frequency of data refresh operations performed on storage nodes (e.g., capacitor cells) that are intended to reduce such charge leakage. However, such an increase in the frequency of data refresh operations may be incompatible with specific applications or design rules. Additionally, this charge leakage may be accelerated by the access device repeatedly accessing the storage node in a short period of time (eg, by a row hammer effect), such that the intended charge of the storage node is not maintained by, for example, a predetermined data refresh operation frequency.

[0016] The present disclosure includes systems, devices, and methods related to semiconductor structure formation. Compared to some previous methods, the present disclosure describes how to reduce charge transfer in a storage device based on multiple embodiments of semiconductor structure formation. An example of the device described herein includes a first trench and a second trench formed in a semiconductor substrate material, wherein the first trench is adjacent to the second trench and is separated by the semiconductor substrate material and / or pillar material. The device includes: a metal material formed to a first height in the first trench, the first height is less than the second height of the metal material formed in the second trench relative to the corresponding height in the semiconductor substrate material; and a polysilicon material formed to a first depth above the metal material in the first trench, the first depth is greater than the second depth of the polysilicon material formed above the metal material in the second trench relative to the corresponding height in the semiconductor substrate material. The larger first depth of the polysilicon material formed in the first trench reduces charge transfer through the metal material in the first trench.

[0017] This embodiment may, for example, include forming a trench (e.g., a portion of a trench) for a through access line that is deeper than a trench (e.g., a portion of a trench) for an adjacent active access line, and forming a metal (conductive) material at the bottom of the trench for the through access line such that it is deeper than the metal material at the bottom of the trench for the active access line. The trench for the through access line may include a polysilicon material formed above (e.g., on) the metal material such that the polysilicon material is also deeper than the polysilicon material formed above the metal material for the active access line. Increasing the depth of the polysilicon material above the metal material in the through access line relative to the depth of the polysilicon material above the metal material in the active access line may cause the bottom of the polysilicon material in the trench for the through access line to be lower than the top of the metal material in the trench for the active access line. This difference may help reduce charge transfer via the metal material in the through access line.

[0018] Thus, embodiments of semiconductor structure formation described herein can provide multiple benefits for data value retention in storage nodes of storage devices. For example, such benefits can include reducing the probability of a change in a data value stored by a storage node (e.g., from 0 to 1 or 1 to 0, depending on programming parameters) based on reduced charge transfer from the storage node in response to repeated accesses to the storage node. Alternatively or additionally, such benefits can include reducing the frequency of performing data refresh operations on the storage node based on reduced charge transfer from the storage node, as well as other possible benefits based on critical dimension (CD), specific applications and / or design rules, etc.

[0019] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which is shown by way of illustration how one or more embodiments of the present disclosure may be implemented. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present invention, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0020] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits represent an element or component in the drawing. Similar elements or components between different drawings may be represented by using similar numerals. For example, 217 may refer to Figure 1 3, and similar elements may be referenced as 317 in FIG. 3. In some cases, multiple similar, but functionally and / or structurally distinguishable elements or components in the same or different drawings may be referenced sequentially by the same element number (e.g., Figures 4A to 4E 407-1 and 107-N).

[0021] Figure 1 An example cross-sectional view of a portion of a semiconductor structure 100 formed in accordance with various embodiments of the present disclosure is shown. Figure 1 Adjacent access devices 102 and 104 (eg, memory cell transistors) are shown, which may be present in, for example, Fig. 9 In the storage array of the storage device shown in FIG. Figure 1 In the example embodiment of FIG. 1 , adjacent access devices 102 and 104 are shown as BRADs. However, the embodiments are not limited to this example. Isolation trenches 107 - 1 , . . . , 107 -N (collectively or individually referred to as isolation trenches 107 ) can be used to isolate adjacent access devices from other access devices according to a specific array layout. Figure 1 A pair of isolation trenches 107 in one such architecture according to an embodiment of the present disclosure is shown. In the semiconductor structure 100, the isolation trenches 107 may be included to reduce current and / or charge leakage from and between adjacent components of the semiconductor structure 100 (e.g., from the storage node 131 coupled to the access devices 102 and 104). The isolation trenches 107 may be formed by etching a pattern of isolation trenches 107 between the pillars 103-1, ..., 103-N and / or in the semiconductor substrate material 124 and depositing a dielectric material (e.g., oxide 117) into the isolation trenches 107.

[0022] During semiconductor manufacturing, trenches may be formed, and gate dielectric 137 and semiconductor material may be deposited in trenches 101-1 and 101-N to form gates 106 and 136 (collectively or individually referred to as gate 106) for coupling to access devices (e.g., BRAD devices 102 and 104 according to a particular BRAD design process) of storage node 131. Gates 106 in isolation trenches 107-1 and 107-N may be referred to as through access lines that are not directly coupled to adjacent (e.g., neighboring) access devices or storage nodes. Embodiments are not limited to the examples shown.

[0023] In this example of adjacent BRAD devices 104 and 102, isolation trench 107 may be formed to a greater depth than the depth of gate 106 used to form active regions of access lines (e.g., at 106 and 136) in trenches 101-1, ..., 101-N of BRAD devices 102 and 104. In various embodiments, isolation trench 107 may be formed as an isolation region having a depth of 150 nanometers (nm) or greater, a width of 15 nm or less, and an aspect ratio (AR) of depth to width of ten to one (10:1) or greater. In contrast, trench 101 of access devices 102 and 104 may be formed as an active region (e.g., including a hybrid metal gate formed by 106 and 136) having a depth of less than 150 nm, a width of 15 nm or less, and an aspect ratio of less than 10:1. Thus, for BRAD devices 102 and 104, the bottoms 108-1 and 108-N of the respective isolation trenches 107-1 and 107-N may be at a greater depth relative to the bottoms 108-2 and 108-3 of the respective trenches 101-1, ..., 101-N. In various embodiments, consistent with the above-described depths, the greater depth of the isolation trench 107 may be in a range of about 20 nm to about 50 nm.

[0024] In various embodiments, a dielectric material 117 may be deposited into the isolation trenches 107-1 and 107-N. The dielectric material 117 may be deposited to a thickness of 1-5 nm on the inner walls 114-1 and 114-N of the respective isolation trenches 107-1 and 107-N to form the sidewalls 111 of the opening (e.g., as shown at 410 and in combination with the dielectric material 117). Figures 4A to 4E ). The dielectric material 117 may be an initial barrier between the pillars 103 and / or the semiconductor substrate material 124 and other adjacent semiconductor devices and / or components. In various embodiments, the dielectric material 117 may be an oxide deposited using a conformal deposition technique, such as a chemical vapor deposition (CVD) technique in a semiconductor processing apparatus (e.g., as combined with Figure 8 ). The oxide used for the dielectric material 117 may be silicon oxide (SiOx), which may not represent SiO2, but is not limited thereto.

[0025] like Figure 1 As shown in FIG. 1 , a gate 106 for accessing devices 102 and 104 is also formed. As shown, gate 106 may be a gate to BRAD. As further described (e.g., in conjunction with Figures 4A to 4Eand elsewhere herein), the gate 106 may be formed of a metal material (e.g., tungsten (W), titanium nitride (TiN), and other possible metals, metal compounds, and combinations thereof, which may be collectively referred to as metal material 106) and a polysilicon material 136 formed above (e.g., on) the metal material 106 to produce a hybrid metal gate (HMG). In various embodiments, the polysilicon material 136 may be or may include doped polysilicon. The doped polysilicon for the gate 106 in the isolation regions of the trenches 107-1 and 107-N and the active regions of the trenches 101-1, ..., 101-N may be n-doped polysilicon. The polysilicon material 136 above the metal material 106 in the isolation region of the trenches 107 through the access line may extend deeper into the semiconductor substrate material 124 than the polysilicon material 136 formed above the metal material 106 in the active region of the trench 101. The top of the metal material 106 in the isolation region of the through access line in the isolation trench 107 may also be deeper in the semiconductor substrate material 124 than the top of the metal material 106 in the active region of the trench 101. Thus, the through access line in the isolation trench 107 may be about 20 nm to about 50 nm deeper than the active access line in the trench 101 (e.g., consistent with the increased depth of the bottom 108 of the trench 107 relative to the bottom of the trench 101).

[0026] exist Figure 1 In the example of, in the active region of the trenches 101-1, ..., 101-N, the gate 106 can be separated from the channel 135, and the first source / drain regions 116-1 and 116-2 (collectively or individually referred to as the first source / drain region 116) are separated from the second source / drain regions 112-1 and 112-2 (collectively or individually referred to as the second source / drain region 112) by the gate dielectric 137. Two adjacent access devices 102 and 104 are shown as sharing the second source / drain region 112 at the junction. The sense line contact 130 can be formed of a metal material or other conductive contact. The sense line contact 130 can be formed to contact the second source / drain region 112 and the junction. A contact sense line 133 (e.g., a digit line or a bit line) can be formed to contact the sense line contact 130. Storage node contacts 132 may be coupled to each first source / drain region 116, and storage nodes 131 may be coupled to storage node contacts 132. Insulating material 140 (eg, dielectric material) may be formed on spacer material 126 and mask material 138 to separate conductive contacts 132.

[0027] In various embodiments, a portion of the sense line contact 130 may be formed in contact with the spacer material 126, the second source / drain region 112, and the junction. The insulating material 140 may be formed on the spacer material 126, the mask material 138, and in contact with a portion of the sense line contact 130 and the storage node contact 132. The gate dielectric 137 may be directed to Figure 1 Each of the adjacent BRAD devices 102 and 104 shown in the example of FIG. 1 separates a gate 106 from a channel 135 .

[0028] Figure 2 An example top view of a memory array structure 276 is shown in accordance with various embodiments of the present disclosure. Figure 2 A plurality of active regions (e.g., 290 and 291) a first source / drain region 278 and a second source / drain region 280 are shown. Region 291 contains a pair of access devices that share a second source / drain region 280-1 that can be connected to a sense line and a pair of first source / drain regions 278-1 and 278-2. The second source / drain region 280-1 and the first source / drain region 278-1 can be separated by a channel and an access line 282-1. Adjacent to the example active regions 291 and 290 on either side can be a plurality of through access lines 282-3 and 282-4 to other active regions.

[0029] exist Figure 2 In the example of FIG. 2 , region 290 includes active regions adjacent to access devices and adjacent to through access lines 282 - 2 and 282 - 5 . Figure 3A A cross-sectional view taken along the cut line AB 284 is shown in FIG. The access lines 282-2 and 282-5 in region 290 may be provided in isolation trenches (eg, Figure 1 The semiconductor structure formed according to the top view of the example memory array layout may include access devices (e.g., transistors) and storage nodes (e.g., capacitor cells), etc. A dynamic random access memory (DRAM) array is a form of an example memory array that may be formed by a semiconductor structure manufactured by a semiconductor manufacturing process performed on a substrate of a semiconductor wafer. The memory array may have an array of access devices and storage nodes that form memory cells at the intersections of rows and columns.

[0030] Area 292 shows the isolation area between the sensing lines of the access device taken along cut line CD 286. Figure 3B286. The isolation region may be formed by depositing a dielectric material between adjacent active regions (e.g., 291 and 290). The dielectric material in the isolation region may reduce the probability that semiconductor structures formed adjacent active regions 291 and 290 communicate in an undesirable manner (e.g., interfere with each other). Region 292 may also include a portion through which access line 282-2 passes.

[0031] Area 294 illustrates a portion of access line 282 - 1 along cut line EF 288 . Figure 3C A cross section along cut line EF 288 is shown. Access line 282-1 can be used as a gate adjacent to the active region. A transistor access line (e.g., a word line) can be used to activate an access device (e.g., an access transistor) to access (e.g., "turn on" or "turn off" access) a storage node of a memory cell (e.g., a capacitor cell). A sense line (e.g., a bit line) can be used to read and / or program (e.g., write, refresh, erase, etc.) to and / or from a storage node of a memory cell.

[0032] Figures 3A to 3C Example cross-sectional views of memory array structures at different locations within a semiconductor substrate in a semiconductor manufacturing sequence are shown according to various embodiments. Figures 3A to 3C The cross-sectional view corresponds to Figure 2 Cutting lines AB, CD and EF are shown.

[0033] Figure 3A FIG. 1 shows a semiconductor structure fabrication process at a specific time point in the process of cutting along the cutting line AB and by Figure 2 290 is a cross-sectional view of a memory array structure surrounded by an active area 290 as shown in FIG. Figure 3A Isolation trenches 307-1 and 307-N (collectively or individually referred to as isolation trenches 307) and gates 336 and 306 (collectively or individually referred to as gates 306) are shown, which are formed at the bottoms 308-1 and 308-N of the trenches to a depth into the working surface 309 of the semiconductor structure on the semiconductor substrate material 324. Figure 3A Also shown is a gate dielectric 337 deposited on the gate 306 in the trenches 301-1 and 301-N for the access device. The trenches 301 and gates 336 and 306 for the active area can be formed at a depth less than the depth of the bottoms 308-2 and 308-3 of the trenches 307-1 and 307-N of the isolation regions. The trenches 301 and 307 can be formed between the pillars 303-1, ..., 303-N, which in a three-dimensional representation (e.g., as combined with Figures 4A to 4E ) may be present as walls defining the boundaries of the trench.

[0034] The isolation regions of trenches 307-1 and 307-N may include dielectric material 317 on respective walls 314-1 and 314-N of the trenches, and through access line conductive materials 306 and 336 and insulator fill material 338 within the walls of openings 311 in dielectric material 317. The active regions of trenches 301-1 and 301-N may include gate dielectric material 337 on respective walls 314-2 and 314-3 of the trenches, and active access line conductive materials 306 and 336 and insulator fill material 338 within the walls of openings 311 in gate dielectric material 337. In various embodiments, dielectric material 317 for the isolation regions of trench 307 and gate dielectric material 337 for the active regions of trench 301 may both be SiOx; however, embodiments are not limited thereto.

[0035] Figure 3B FIG. 1 shows a semiconductor structure fabrication process in which a semiconductor structure is cut along a cutting line CD at a specific time point. Figure 2 A cross-sectional view of a memory array structure surrounded by an active area 392 is shown in FIG. Figure 3B An isolation trench 307 is shown. The isolation trench 307 may contain a dielectric material 317, through access line conductive materials 306 and 336, and an insulator fill material 338. Figure 3B Semiconductor substrate material 324 and additional dielectric materials 318 , 319 , 320 , and 329 may also be included.

[0036] Figure 3C FIG. 1 shows a semiconductor structure fabrication process at a specific time point in the process of cutting along the cutting line EF and by Figure 2 A cross-sectional view of a memory array structure surrounded by an active area 394 is shown in FIG. Figure 3C Semiconductor substrate material 324 , dielectric material 329 , through access line conductive materials 336 and 338 , and mask material 306 are shown.

[0037] Figures 4A to 4E Perspective views showing various cutouts of a portion of an example three-dimensional semiconductor structure at specific points in an example semiconductor fabrication sequence according to various embodiments of the present disclosure. Figures 4A to 4E The manufacturing sequence shown is shown at a specific time point corresponding to a specific processing activity performed in the manufacturing process. For ease of description, other processing activities included in a specific manufacturing process may be omitted.

[0038] Figure 4A A perspective view of an example structural feature 437 of a portion of an example semiconductor structure at a particular point in time in an example manufacturing sequence is shown. The semiconductor structures described herein may include the semiconductor structures shown at 100 and 968 and may be combined with Figure 1 and 9Example storage devices are described, but embodiments are not intended to be limited to these types of storage devices.

[0039] Figure 4A The illustrated structural features 437 are shown at points in time corresponding to processing activities that have been performed in a manufacturing sequence. Figure 4A The portion of structural feature 437 shown illustrates a structural configuration at a comparative baseline for structure formation as described herein. Figures 4A to 4E The structural features shown are shown at a point in time after various other processing activities have been performed in the manufacturing sequence. Figures 4A to 4E Other structural features and processing activities may be omitted.

[0040] The structural features and processing activities shown can correspond to the formation and removal of structural features. For example, in multiple embodiments, structural features can be formed using a deposition process, such as diffusion, spin-on deposition, atomic layer deposition, physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, pulsed laser deposition, sputtering deposition, and bottom-up deposition of seam suppression (as further described elsewhere herein), and other suitable deposition processes. Alternatively or additionally, atomic layer epitaxy can be used to form structural features. A subtractive etching process (e.g., any suitable wet etching or dry etching process) can be used to remove specific portions of various materials so that the remaining materials contribute to the formation of the intended components. Alternatively or additionally, an additive (e.g., inlaid gold and silver) deposition process can be used to form structural features. For example, multiple embodiments can use chemical mechanical polishing (CMP) instead of a subtractive etching process.

[0041] Combination Figure 8 An example system 880 that can be used for this processing activity is shown and described. In various embodiments, Figure 8 A single system 880 is shown to perform various processing activities, or multiple such systems may be used to perform various processing activities, each of which is capable of performing a specific activity in a manufacturing sequence. For example, a portion of a manufacturing sequence using a wet etching process may be performed in one portion of a processing system, while another portion of a manufacturing sequence using a dry etching process performed in a vacuum may be performed in another portion of the processing system.

[0042] Figure 4AAn orientation indicator 420 having an x-axis, a y-axis, and a z-axis is included. The direction indicated by the x-axis is intended to orient a description of a component associated with a trench that is "adjacent" or "adjacent" to another component in another trench (e.g., separated by a pillar). The direction indicated by the x-axis may also be applied to a description of an opening or trench oriented "between" two pillars (although each opening or trench may extend in the direction indicated by the y-axis). The direction indicated by the y-axis is intended to orient a description of a component in a trench that is "adjacent" or "adjacent" to another component in the same trench (e.g., not separated by a pillar). For example, such components may be isolation regions and active regions in two adjacent trenches in the direction indicated by the x-axis or in the same trench in the direction indicated by the y-axis. The direction indicated by the y-axis may also be applied to a description of a resistor, such as "along the length of a first portion and a second portion of a trench." The direction indicated by the z-axis is intended to orient a description of the top or bottom of a component and / or a description of a component or material (e.g., a layer) formed on top of or below another component or material.

[0043] Figure 4A The formation of the structural feature 437 shown may, for example, include forming pillars 403-1, ..., 403-N (which may correspond to the bonding Figure 1 The pillars 103-1, ..., 103-N) shown and described are formed (e.g., deposited or etched) on or in a semiconductor substrate 424. In various embodiments, at least one of silicon (Si), polycrystalline Si, amorphous Si, and doped Si may be used as a pillar material 426 for forming pillars 403, and at least one of Si, polycrystalline Si, and amorphous Si may be used to form semiconductor substrate material 424.

[0044] Oxide material 417 may be formed (e.g., deposited) on pillar material 426 from above the top of pillar material 426 (e.g., on the top) and above the inner walls of isolation trenches 407-1 and 407-N (e.g., on the inner walls) to form sidewalls of openings 410-1 and 410-N. Oxide material 417 may also be formed on pillar material 426 from above the top of pillar material 426 (e.g., on the top) and above the inner walls of trenches 401-1 and 401-N for access devices (e.g., on the inner walls) to form sidewalls of openings 410-2 and 410-3. In various embodiments, oxide material 417 for trenches 401-1 and 401-N may correspond to the combination of Figure 1 The gate oxide material 137 shown and described. In various embodiments, the gate oxide material 137 and / or the oxide material 417 may be or may include a SiOx dielectric (e.g., SiO2) formed to a thickness in the range of 1-5 nm. Figure 1The inner walls of trenches 401 and 407 and the side walls of opening 410 are depicted.

[0045] As described herein, a first trench (e.g., as shown at 407-1 and 407-N and collectively or individually referred to as trench 407) and a second trench (e.g., as shown at 401-1 and 401-N and collectively or individually referred to as trench 401) can be formed in a semiconductor substrate material 424. The first trench 407 is adjacent to the second trench 401 and is separated by the semiconductor substrate material 424 and / or the pillar material 426. The first trench 407 can have a first bottom (e.g., a portion of the first trench 407 shown at 408-1, 408-4, and 408-N) at a greater depth 425 relative to a second bottom of the second trench 401 (e.g., a portion of the second trench 401 shown at 408-2, 408-3, 408-5, and 408-6). In various embodiments, the greater depth 425 of the bottom of the first trench 407 relative to the bottom of the second trench 401 can be in a range of about 20 nm to about 50 nm.

[0046] Figure 4B The following diagram shows the steps of manufacturing the components of the present invention in an example manufacturing sequence according to various embodiments of the present invention. Figure 4A A perspective view of example structural feature 438 after a particular point in time is shown. Figure 4B It is shown that the metal material 406 in various embodiments can be formed in the first trench 407 above (e.g., on) the oxide material 417 to a first height 422 that is less than 428 a second height 423 of the metal material 406 formed in the second trench 401 relative to a corresponding height in the semiconductor substrate material 424. For ease of illustration, and because each trench described herein can have an isolation region corresponding to a first depth shown at 408-1, 408-4, and 408-N and an active region corresponding to a smaller depth shown at 408-2, 408-3, 408-5, and 408-6, a difference 428 of the first height 422 of the metal material 406 relative to the second height 423 of the metal material 406 is also shown in the trench 407-1.

[0047] In various embodiments, the metal material 406 may be or may include W and / or TiN. For example, the metal material 406 may be formed of either W and TiN, or the metal material 406 may be formed of a mixture of W and TiN, of alternating layers of W and TiN, or of one or both of W and TiN in addition to one or more other metal materials.

[0048] As further described elsewhere herein, the metal material 406 can be deposited using a deposition technique that reduces the probability of (e.g., inhibits) the formation of seams in the metal material 406 during deposition in trenches having a narrow width relative to depth, resulting in a high AR (e.g., an AR of at least 5:1). Among other features of the deposition technique, the technique is designed to reduce the deposition rate of the metal material 406 on the top of the pillars 403 and on the upper portions of the sidewalls of the openings 410-1 and 401-2 of the respective first trenches 407-1 and second trenches 401-1 relative to the deposition rate of the metal material 406 on the lower portions of the sidewalls and bottoms of the first and second trenches, so as to enable controlled bottom-up deposition that inhibits the formation of seams and / or voids in the metal material 406 during deposition.

[0049] The metal material 406 may be formed such that the metal material 406 has substantially equal heights above the bottom 408 of each of the first trench 401-1 and the second trench 401-1. In various embodiments, the metal material 406 may be deposited in the first trench and the second trench substantially simultaneously to reach substantially equal heights. Thus, the first height 422 of the metal material in the first trench 407 may be less than the second height 423 of the metal material 406 formed in the second trench 401. In various embodiments, the difference 428 between the first height 422 and the second height 423 may conform to the difference 425 in the depth of the bottom of the first trench 407 relative to the bottom of the second trench 401. In various embodiments, the difference 428 between the first height 422 and the second height 423 conforming to the difference 425 in the depth of the bottom of the trench may be produced by depositing the metal material 406 at different depths in different portions of the trench using the bottom-up deposition technique described herein and / or by using a timed etching technique in different portions of the trench. Thus, the difference 428 may be in the range of about 20 nm to about 50 nm.

[0050] In various embodiments, a spacer material 421 may be formed over (e.g., on) the oxide material 417 before the metal material 406 is formed over (e.g., on) the isolation material 421. The spacer material 421 may be formed of TiN, but embodiments are not limited thereto. The spacer material 421 may be formed on the oxide material 417 as a layer having a thickness in a range of about 1 nm to about 3 nm.

[0051] Figure 4C The following diagram shows the steps of manufacturing the components of the present invention in an example manufacturing sequence according to various embodiments of the present invention. Figure 4B A perspective view of example structural feature 439 after a particular point in time is shown. Figure 4CA polysilicon material 436 is shown that has been formed (e.g., deposited) over the semiconductor structure 400. The polysilicon material 436 may be deposited to fill the openings 410-1 and 410-N of the respective trenches 407-1 and 407-N and to fill the openings 410-2 and 410-3 of the respective trenches 401-1 and 401-N to cover the metal material of each of the trenches. The deposition of the polysilicon material 436 may also result in the formation (e.g., a layer) of polysilicon material 436 over the trenches 407 and 401 and over the pillars 403 and / or the metal material 406 deposited on top of the pillars. In various embodiments, the polysilicon material 436 may be or may include n-doped polysilicon.

[0052] Figure 4D The following diagram shows the steps of manufacturing the components of the present invention in an example manufacturing sequence according to various embodiments of the present invention. Figure 4C A perspective view of example structural feature 440 after a particular point in time is shown. Figure 4D It is shown that polysilicon material 436 formed over trenches 407 and 401 and polysilicon material 436 and metal material 406 formed on top of oxide material 417 on pillar 403 may be removed to expose working surface 409 of semiconductor structure 400. In various embodiments, polysilicon material 436 and metal material 406 may be removed by performing CMP and / or various suitable etching techniques.

[0053] Figure 4E The following diagram shows the steps of manufacturing the components of the present invention in an example manufacturing sequence according to various embodiments of the present invention. Figure 4D A perspective view of example structural feature 441 after a particular point in time is shown. Figure 4E It is shown that a portion of the remaining polysilicon material 436 in the trenches 407 and 401 has been removed to a substantially equal depth 418. In various embodiments, the polysilicon material 436 may be etched substantially simultaneously (e.g., using a dry etching technique) in the trenches 407 and 401 to achieve the substantially equal depth 418. Thus, the first height 418 of the polysilicon material 436 in the first trench 407-1 may be substantially equal to the second height 418 of the polysilicon material 436 in the second trench 401-1 relative to the corresponding height in the semiconductor substrate material 424.

[0054] Thus, the polysilicon material 436 may have a third height 415 (e.g., a first thickness) above the metal material 406 in the first trench 407-1, and may have a fourth height 427 (e.g., a second thickness that is reduced relative to the first thickness) above the metal material 406 in the second trench 401-1. The first thickness 415 and the second thickness 427 may correspond to the isolation region and the active region of each trench (e.g., as shown in trench 407-1) and / or adjacent trenches (e.g., as shown in trench 407-1 adjacent to trench 401-1), respectively. Thus, the first thickness 415 of the polysilicon material 436 formed above (e.g., on) the metal material 406 in the first trench 407-1 may be greater than 419 the second thickness 427 of the polysilicon material 436 formed above (e.g., on) the metal material 406 in the second trench 401-1. The greater thickness 419 of the polysilicon material 436 in the first trench 407-1 relative to the polysilicon material 436 in the second trench 401-1 may be in the range of about 20 nm to about 50 nm, similar to the case where the polysilicon material 436 in the first trench 407-1 and the second trench 401-1 are combined. Figure 4A and 4B The bottom of the trench and the metal material 406 are shown as differences 425 and 428. The trenches 407 and 401 may be filled with a filling material (not shown) formed above the polysilicon material 436 to the working surface 409. In various embodiments, the filling material may correspond to the combined Figure 1 Masking material 138 is shown and described.

[0055] In other words, the polysilicon material 436 can be formed over the metal material 406 in the first trench 407-1 to a first depth that is greater than 419 relative to a corresponding height in the semiconductor substrate material 424, a second depth of the polysilicon material 436 formed over the metal material 406 in the second trench 401-1. As described with respect to the greater thickness 419 of the polysilicon material 436 in the first trench 407-1 relative to the second trench 401-1, the greater first depth 419 of the polysilicon material 436 in the first trench 407-1 relative to the second depth of the polysilicon material 436 in the second trench 401-1 can be in the range of about 20 nm to about 50 nm.

[0056] The larger first depth of the polysilicon material 436 formed in the first trench 407-1 can reduce the charge transfer through the metal material 406 in the first trench 407-1. For example, the larger first depth of the polysilicon material in the first trench 407-1 can reduce the charge transfer from the storage node (e.g., as shown at 131 and in combination with Figure 1Without a greater depth of intervening polysilicon material 436, charge can be transferred from storage node 131 to metal material 406 in first trench 407-1, which is selectively coupled to access device 102 in second trench 401-1 via an active access line.

[0057] Figures 4A to 4E An embodiment of the semiconductor structure shown at 400 in FIG. 4 may include a first portion of a metal material 406 and a polysilicon material 436 in a first trench 407-1 configured as an isolation region for a through access line. For example, the first portion in the first trench 407-1 may substantially correspond to having a width above the bottom of the portion of the first trench 407-1 shown at 408-1 and 408-4. The isolation region may have a depth of 150 nm or more below the working surface 409, a width of 15 nm or less, and an AR of 10:1 or more. The metal material 406 and the adjacent second portion of the polysilicon material 436 in the second trench 401-1 may be or may include a hybrid metal gate of an active access line in an active region, the active access line being used to couple to an access device of a sense line (e.g., as combined with Figure 1 For example, the second portion of the first trench 407-1 may substantially correspond to having a width above the bottom portion of the portion of the first trench 407-1 shown at 408-2 and 408-3, which would correspond to the width above the bottom of the trenches 401-1 and 401-N shown at 408-5 and 408-6. The active area may have a depth below the working surface 409 of less than 150 nm, a width of 15 nm or less, and an AR of less than 10:1.

[0058] Thus, as best seen in trench 407-1, each of first trench 407 and second trench 401 may include at least one first portion of metal material 406 and polysilicon material 436, the first portion being configured to serve as a through access line. Additionally, each of first trench 407 and second trench 401 may include at least one second portion of metal material 406 and polysilicon material 436, the second portion being configured to serve as an active access line for coupling to an access device of a sense line and a storage node.

[0059] Figure 5 An example cross-sectional view of a portion of another semiconductor structure 542 formed according to various embodiments of the present disclosure is shown. Figures 4A to 4E compared to, Figure 5 A two-dimensional cross-sectional view of a portion of an example semiconductor structure 542 is shown, which may correspond to Figures 4A to 4E The x-axis and z-axis of orientation indicator 420 are shown.

[0060] As in Figures 4A to 4E As shown elsewhere herein, semiconductor structure 542 shows two trenches 507-1 and 507-N having a first portion that is designed to serve as an isolation region by being formed (e.g., etched) deeper into semiconductor substrate material 524 than the two trenches 501-1 and 501-N, and the two trenches 501-1 and 501-N having a second portion adjacent to the first portion in trench 507 that is designed to serve as an active region. The shallower active regions of the two trenches 501-1 and 501-N are located at Figures 4A to 4E 5 and elsewhere herein are shown as being positioned adjacent to each other so that the positioning of the portions in the intersecting plane is isolation region-active region-active region-isolation region. However, the embodiments of the present disclosure are not limited thereto. For example, the positioning of the portions may alternate in various other positionings such as isolation region-active region-isolation region-active region, or between pillars 503-1, ..., 503-N.

[0061] Each of the portions of trenches 507 and 501 may have a first metal material 506 formed (e.g., deposited) to a first height in a deeper portion of trench 507, which is designed to serve as an isolation region, the first height being less than a second height of the first metal material 506 in a shallower portion of trench 501, which is designed to serve as an active region, relative to a corresponding height in semiconductor substrate material 524. In various embodiments, first metal material 506 may be or may include W and / or TiN, as well as other suitable conductive metal materials.

[0062] A polysilicon material 536 may be formed (e.g., deposited) above (e.g., on) the first metal material 506 in the trenches 507 and 501. Consistent with the first height of the first metal material 506 in the trench 507 being less than the second height 528 of the first metal material 506 in the trench 501, the polysilicon material 536 may have a first depth in the trench 507 that is deeper than the second depth in the trench 501. As described herein, the difference 528 between the first height and the second height of the first metal material 506 and / or the first depth and the second depth of the polysilicon material 536 may be in a range of about 20 nm to about 50 nm. In various embodiments, the polysilicon material 536 may be or may include n-doped polysilicon. In various embodiments, the first metal material 506 and the polysilicon material 536 may be deposited above (e.g., on) the isolation region of the trench 507 of the dielectric material 517 and the active region of the trench 501 of the gate dielectric material 537 (e.g., as in combination Figure 1 and 3A described).

[0063] Polysilicon material 536 in each of trenches 507 and 501 may be formed to include recess 546. In various embodiments, recess 546 may be formed by depositing polysilicon material 536 using a conformal deposition technique and / or by using an etching technique on previously deposited polysilicon material 536.

[0064] The second metal material 543 may be formed (e.g., deposited) to at least partially fill the recess 546 in the polysilicon material 536 in the trenches 507 and 501. The bottom 545 of the recess 546 in the trenches 507 and 501 may be formed to have a configuration (e.g., shape, depth, thickness, etc.) that separates the first metal material 506 from the second metal material 543. Since the polysilicon material 536 in the trench 501 is not as deep as the polysilicon material 536 in the trench 507, the first depth of the second metal material 543 in the trench 501 may be less than the second depth of the polysilicon material 536 in the trench 507 relative to the working surface 509. In various embodiments, the second metal material 543 may be or may include ruthenium (Ru) and / or platinum (Pt), as well as other suitable conductive metal materials.

[0065] In various embodiments, the second metal material 543 may be formed in the recess 546 above (e.g., on) the polysilicon material 536 to a height that does not fill the recess 546 and / or the trenches 501, 507 (e.g., to the level of the working surface 509). In this case, the filling material 544 may be used to fill the remaining portion of the recess 546 and / or the trenches 501, 507. In various embodiments, the filling material may correspond to the combined Figure 1 The mask material 138 shown and described and / or in combination Figure 4E Description of the filling material.

[0066] The second metal material 543 in the first and second portions of the trenches 501, 507 may have a work function substantially equal to that of the polysilicon material 536 and a resistivity lower than that of the polysilicon material 536. As used herein, "work function" means the amount (e.g., minimum amount) of thermodynamic work (e.g., energy) used to move an electron from a solid surface to a point in a vacuum outside the solid surface at an atomic scale. "Resistivity" means a measure of a particular material's resistance to the flow of electric current. Thus, the second metal material 543 may be used to reduce the length of the respective first and second portions of the trenches (e.g., corresponding to the length of the respective first and second portions of the trenches). Figures 4A to 4EFor example, the second metal material 543 in the recess 546 of the polysilicon material 536 can reduce the increased resistance along the length that is associated with (e.g., generated by or caused by) the current direction transition near different depths of the first metal material 506 and / or near different depths of the polysilicon material 536 in the trenches 501, 507.

[0067] Figure 6 650 is a flow chart of an example method for manufacturing a semiconductor structure according to various embodiments of the present disclosure. Unless explicitly stated, the elements of the methods described herein are not limited to a specific order or sequence. In addition, multiple method embodiments or elements thereof described herein can be performed at the same or substantially the same time point.

[0068] At block 651, method 650 may include forming a portion of a first trench in a semiconductor substrate material to a first depth, wherein the portion of the first trench is designed to serve as a through access line of an isolation trench (e.g., as described with respect to bonding Figure 1 and 4A -4E). At block 652, method 650 may include forming an adjacent portion of a second trench in the semiconductor substrate material to a second depth, wherein the first depth is greater than the second depth, and the portion of the second trench is designed to serve as a gate of an active access line of an access device of the memory cell (e.g., as described with respect to the combination Figure 1 and 4A -4E) At block 653, method 650 may include forming the metal material to have a first height in the first trench and a second height in the second trench, the first height and the second height each corresponding to a difference in a corresponding first depth and a second depth (e.g., as described with respect to the bonding Figure 4A and 4B At block 654, the method 650 may include forming a polysilicon material over the metal material to conform to a difference between the respective first depth and the second depth such that the polysilicon material in the first trench has a third depth greater than a fourth depth of the polysilicon material in the second trench (e.g., as described with respect to the bonding Figures 4C to 4E At block 656, method 650 may include influencing (e.g., increasing) a work function of electron movement in response to the larger third depth of the polysilicon material in the first trench to reduce charge transfer from a storage node of the memory cell via the metal material in the first trench.

[0069] Thus, in various embodiments, method 650 further includes reducing the probability that a data value stored by a storage node changes based on reduced charge transfer from the storage node in response to repeated accesses to the storage node (e.g., during row hammering or other processes). Alternatively or additionally, method 650 may further include reducing the frequency of performing data refresh operations for the storage node based on the reduced charge transfer from the storage node.

[0070] The method 650 may further include forming a polysilicon material over the metal material in the first trench and the second trench to conform to a difference between the respective first depth and the second depth, such that a first height of the polysilicon material in the first trench is greater than a second height of the polysilicon material in the second trench relative to the metal material (e.g., as described with respect to the bonding Figure 4E Thus, method 650 may further include forming a polysilicon material over the metal material such that a first upper surface of the polysilicon material in the first trench has a first height substantially equal to a second upper surface of the polysilicon material in the second trench relative to the semiconductor substrate material (e.g., as described with respect to bonding Figure 4E structural features and manufacturing sequence as described).

[0071] The method 650 may further include forming a through access line in a first opening of a first trench between the first pillar and the second pillar and forming an active access line in a second opening of a second trench between the second pillar and the third pillar (eg, as described with respect to the combination Figure 1 and 4A 4E to 4E). For example, Figure 4A The through access line formed of the metal material 406 and the polysilicon material 436 in the opening above the bottom portion 408-4 of the trench 407-1 as shown can be used as an isolation region, and as shown in FIG. Figure 4E The active access line formed of metal material 406 and polysilicon material 436 in the opening of the adjacent portion of the trench 401-1 can be used as an active area. The isolation region and the adjacent portion of the active area are shown to be separated by the pillar 403-1 and are in contact with the oxide material 417 and / or spacer material 421 formed on the pillar 403-1.

[0072] Method 650 may further include forming (e.g., depositing) a nucleation film on the bottom of the opening and from the bottom portion to the top portion of the sidewalls of the first and second trenches. The nucleation film deposited in this way can achieve a deposition rate of the metal material on the upper portion of the nucleation film formed on the sidewalls of the first and second trenches relative to the deposition rate of the metal material on the lower portion of the nucleation film. By depositing the metal material above the nucleation film, the metal material can be formed to a first height in the first trench, and the metal material can be formed to a second height in the second trench. Therefore, during the deposition of the metal material in the first trench and the second trench, the probability of forming seams and / or gaps in the metal material can be reduced. The reduced probability can be based on the reduction in the deposition rate of the metal material on the upper portion of the nucleation film, so that controlled deposition can be performed from the bottom portion to the top portion of the first trench and the second trench.

[0073] Can be purchased from Applied Limited Company iSprint TM This bottom-up deposition is systematically performed to suppress seam formation in the metal (i.e., W). Further information is provided in "Improved Tungsten Gap-Fill for Advanced Contact Metallization" published in the Proceedings of the 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC / AMC) (July 11, 2016) (electronic ISSN 2380-6338).

[0074] The method 650 may further include using an atomic layer deposition (ALD) technique to form a nucleation film by depositing metal material atoms to a thickness of less than 1 nm, and using a chemical vapor deposition technique to fill the first trench with a metal material to a first height and the second trench with a metal material to a second height, wherein the probability of forming seams and / or voids is reduced. In various embodiments, the method 650 may further include substantially simultaneously filling the first trench with a metal material to a first height and filling the second trench with a metal material to a second height. The method 650 may further include using at least one of W and TiN for the nucleation film and the metal material.

[0075] Figure 7 760 is a flow chart of an example method 760 for manufacturing a semiconductor structure according to various embodiments of the present disclosure. Unless explicitly stated, the elements of the methods described herein are not limited to a particular order or sequence. In addition, various method embodiments described herein or elements thereof may be performed at the same or substantially the same time point. Figures 4A to 4EThe structural features and manufacturing sequence of 5 describe the method elements shown in blocks 761, ..., 768 and related method elements.

[0076] At block 761, method 760 may include forming a first portion of a trench in a semiconductor substrate material to a first depth. At block 762, method 760 may include forming an adjacent second portion of the trench in the semiconductor substrate material to a second depth, wherein the first depth is greater than the second depth. At block 763, method 760 may include forming a first metallic material to have a first height in the first portion of the trench and a second height in the second portion of the trench, the first height and the second height each conforming to a difference between a corresponding first depth and a second depth. At block 764, method 760 may include forming a polysilicon material over the first metallic material to conform to a difference between the corresponding first depth and the second depth, such that the polysilicon material in the first portion of the trench has a third depth greater than a fourth depth of the polysilicon material in the second portion of the trench. At block 765, the method 760 may include forming a second metallic material in a recess in the polysilicon material in the first and second portions of the trench, wherein a bottom of the recess conforms to a third depth in the first portion of the trench and a fourth depth in the second portion of the trench and separates the second metallic material from the first metallic material. At block 765, the method 760 may include reducing a resistance along a length of the respective first and second portions of the trench in response to the second metallic material having a work function substantially equal to the polysilicon material and a resistivity lower than the polysilicon material.

[0077] The method 760 may further include reducing the increased resistance along a length associated with a transition in the direction of the current flow near the difference between the respective first and second depths of the first metallic material and near the difference between the third and fourth depths of the polysilicon material. The method 760 may further include adjusting the thickness of the walls and bottom of the recess in the polysilicon material in the first and second portions of the trench so that the work function of the polysilicon material is substantially equal to the work function of the selected second metallic material. In various embodiments, the thickness of the walls and bottom of the recess in the polysilicon material may be adjusted in a range of about 1 nm to about 10 nm. The method 760 may further include using at least one of W and TiN for the first metallic material, using n-doped polysilicon for the polysilicon material, and using at least one of Ru and Pt for the second metallic material.

[0078] The method 760 may further include forming a first portion of the trench to serve as a through access line of the isolation trench. The method 760 may further include forming a second portion of the trench to serve as a gate of an active access line of an access device of the memory cell.

[0079] Figure 8is a functional block diagram of a system 880 for implementing an example semiconductor manufacturing process according to various embodiments of the present disclosure. Figure 8 An example processing device 881 that can be used in a semiconductor manufacturing process is shown. The processing device 881 can include a chamber 882 for enclosing components configured to perform deposition and / or etching operations on multiple semiconductor devices. The chamber 882 can further enclose a carrier 883 to accommodate a batch of semiconductor wafers 884. The processing device 881 can include and / or be associated with a tool including, for example, a pump 885 unit and a purge 886 unit, which is configured to introduce and remove appropriate etching chemicals at each point in the semiconductor manufacturing sequence, as described herein. The processing device 881 can further include a temperature control 887 unit, which is configured to maintain the chamber 882 at an appropriate temperature at each point in the manufacturing sequence. The system 880 can include multiple chambers 882, each chamber 882 being configured to perform a specific process (e.g., a wet etching process, a dry etching process, and / or a deposition process, etc.) during the manufacturing sequence.

[0080] The system 880 may further include a controller 888. The controller 888 may include circuitry and / or programming, or be associated with circuitry and / or programming, for implementing, for example, a dielectric material formed in a trench to pass through an access line. The dielectric material has a bias opposite to the conductivity of a channel region of an adjacent access device. Adjustment of the deposition, removal, and etching operations by the controller 888 may control the critical dimension (CD) of the semiconductor device created in the processing equipment 881.

[0081] The host computer may be configured to generate instructions related to semiconductor structure formation (eg, deposition and etching). An example of a host computer is shown in FIG. Fig. 9 958, but the embodiment is not limited to coupling to Fig. 9 The instructions may be sent to a controller 888 of the processing device 881 via the host interface 960. The instructions may be based at least in part on scaling preferences (e.g., numerically and / or structurally defined gradients) stored by the host 958, provided via input from another storage system (not shown), and / or provided via input from a user (e.g., an operator), etc. The controller 888 may be configured to enable input of instructions and scaling preferences to define a CD for fabrication of a semiconductor structure to be implemented by the processing device 881.

[0082] The scaling preferences may determine the final structure (e.g., CD) of the pillars, the sidewalls of the pillars, the width of the pillars, the width of the isolation trenches, and / or the depth of the isolation trenches, along with the positioning and / or amount of dielectric material described herein, and other components and operations. A specific CD may be achieved by a specific scaling preference input via the instructions. The controller 888 receiving and implementing the scaling preferences may result in the processing device 881 making corresponding adjustments to the deposition time of the dielectric material, the coverage area, height, and / or volume of the dielectric material, and / or the trimming direction and / or trimming time performed on the dielectric material, as well as other possible implementations of scaling preferences.

[0083] In various embodiments, the controller 888 may be configured to use hardware as a control circuit. For example, this control circuit may be an application specific integrated circuit (ASIC) having logic for controlling the manufacturing steps for the formation of the pillar adjacent to the isolation trench, and the formation and removal of dielectric material on the pillar and the isolation trench via associated deposition and etching processes. The controller 888 may be configured to receive instructions and direct the execution of operations to perform the combined Figures 1 to 7 A semiconductor structure and / or an isolation trench manufacturing method is described.

[0084] Fig. 9 is a functional block diagram of a computing system 990 including at least one storage system 962 according to one or more embodiments of the present disclosure. Fig. 9 The numbering convention used does not follow the one applied to Figures 1 to 8 The storage system 962 may be, for example, a solid state drive (SSD).

[0085] exist Fig. 9 In the illustrated embodiment, the storage system 962 includes a storage interface 964, a plurality of storage devices 968-1, ..., 968-N, and a controller 966 that is selectively coupled to the storage interface 964 and the storage devices 968-1, ..., 968-N. The storage interface 964 can be used to transfer information between the storage system 962 and another device such as a host 958. The host 958 can include a processor (not shown). As used herein, a "processor" can be a plurality of processors, such as a parallel processing system, a plurality of co-processors, and the like. An example host can include or be implemented in a laptop computer, a personal computer, a digital camera, a digital recording device and playback device, a mobile phone, a personal digital assistant (PDA), a memory card reader, an interface hub, and the like. This host 958 can be used in conjunction with and using, for example, a processor as shown at 881. Figure 8 The processing apparatus described is associated with manufacturing operations performed on semiconductor devices and / or SSDs.

[0086] In various embodiments, host 958 may be associated with (e.g., include or be coupled to) host interface 960. Host interface 960 may allow for input of scaling preferences (e.g., in numerical and / or structurally defined gradients) to define, for example, the scaling to be applied by the combined Figure 8 The critical dimensions (CD) of a final or intermediate structure of a memory device (e.g., as shown at 968) implemented by the processing device 881 shown and described and / or a memory cell array (e.g., as shown at 970) formed thereon. The array includes trenches having isolation regions and active regions formed according to embodiments described herein. The scaling preferences may be provided to the host interface 960 via inputting a plurality of preferences stored by the host 958, inputting preferences from another storage system (not shown), and / or inputting preferences of a user (e.g., an operator).

[0087] The storage interface 964 may be in the form of a standardized physical interface. For example, when the storage system 962 is used for information (e.g., data) storage in the computing system 990, the storage interface 964 may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, as well as other physical connectors and / or interfaces. However, in general, the storage interface 964 may provide an interface for passing control, addresses, information, scaling preferences, and / or other signals between a controller 966 of the storage system 962 and a host 958 (e.g., via a host interface 960).

[0088] Controller 966 may include, for example, firmware and / or control circuitry (e.g., hardware). Controller 966 may be operably coupled to and / or included on the same physical device (e.g., die) as one or more of storage devices 968-1, ..., 968-N. For example, controller 966 may be or may include an ASIC that is operably coupled as hardware to a circuit (e.g., printed circuit board) that includes storage interface 964 and storage devices 968-1, ..., 968-N. Alternatively, controller 966 may be included on a separate physical device that is communicatively coupled to a physical device (e.g., die) that includes one or more of storage devices 968-1, ..., 968-N.

[0089] Controller 966 may communicate with storage devices 968-1, ..., 968-N to direct operations of sensing (e.g., reading), programming (e.g., writing), and / or erasing information, as well as other functions and / or operations for managing storage units. Controller 966 may have circuits that may include multiple integrated circuits and / or discrete components. In various embodiments, the circuits in controller 966 may include control circuits for controlling access through storage devices 968-1, ..., 968-N and / or circuits for providing a translation layer between host 958 and storage system 962.

[0090] The memory devices 968-1, ..., 968-N may include, for example, a plurality of memory arrays 970 (e.g., volatile and / or non-volatile memory cell arrays). For example, the memory devices 968-1, ..., 968-N may include a memory cell array, such as a portion of an example memory device structured to include sense line contacts. At least one array includes transistors having a gate structure formed according to the embodiments disclosed herein. It should be understood that the memory cells in the memory array 970 of the memory devices 968-1, ..., 968-N may adopt a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash memory architecture (e.g., NAND, NOR, etc.), a three-dimensional (3D) RAM and / or flash memory cell architecture, or some other memory array architecture including pillars and adjacent trenches.

[0091] The storage device 968 may be formed on the same die. The storage device (e.g., storage device 968-1) may include one or more of the memory cell arrays 970 formed on the die. The storage device may include sensing circuits 972 and control circuits 974 associated with one or more arrays 970 formed on the die or portions thereof. The sensing circuit 972 may be used to determine (sense) a specific data value (e.g., 0 or 1) stored at a specific memory cell in a row of the array 970. In response to a command from the host 958 and / or the host interface 960, in addition to directing the storage, erasure, etc. of the data value, the control circuit 974 may also be used to direct the sensing circuit 972 to sense a specific data value. The command may be sent directly to the control circuit 974 via the storage interface 964, or sent to the control circuit 974 via the controller 966.

[0092] Fig. 9The embodiments shown in the drawings may include additional circuits that are not shown to avoid obscuring the embodiments of the present disclosure. For example, the storage device 968 may include address circuits to latch address signals provided over the input / output (I / O) connectors via input / output (I / O) circuits. The address signals may be received and decoded by the row decoder and column decoder to access the storage array 970. It should be understood that the number of address input connectors may depend on the density and / or architecture of the storage device 968 and / or storage array 970.

[0093] In the above detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which is shown by way of illustration how one or more embodiments of the present disclosure may be implemented. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present invention, and it is understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0094] It should be understood that the terms used herein are used only to describe specific embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a / an" and "the" include singular and plural referents, as do "multiple", "at least one" and "one or more" (for example, multiple storage arrays may refer to one or more storage arrays), while "multiple" is intended to refer to more than one such thing. In addition, throughout the application, the words "may" and "can" are used in a permissive sense (i.e., there is the potential, ability to) rather than a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to". The terms "coupled" and "coupled" refer to direct or indirect physical connections, and unless otherwise specified, may include wireless connections for accessing and / or for moving (transmitting) instructions (e.g., control signals, address signals, etc.) and data, as appropriate to the context.

[0095] Although example embodiments including various combinations and configurations of semiconductor materials, substrate materials, structural materials, metal materials, polysilicon materials, oxide materials, spacer materials, dielectric materials, etching techniques, deposition techniques, access devices, active access lines, through access lines, storage devices, storage cells, storage nodes, trenches and openings, and other materials and / or components associated with semiconductor structure formation have been shown and described herein, embodiments of the present disclosure are not limited to those combinations explicitly listed herein. Other combinations and configurations of semiconductor materials, substrate materials, structural materials, metal materials, polysilicon materials, oxide materials, spacer materials, dielectric materials, etching techniques, deposition techniques, access devices, active access lines, through access lines, storage devices, storage cells, storage nodes, trenches and / or openings associated with semiconductor structure formation are explicitly included within the scope of the present disclosure.

[0096] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adjustments or variations of one or more embodiments of the present disclosure. It should be understood that the above description is made in an illustrative manner, not a restrictive one. For example, Figures 1 to 5 The proportions of the elements shown in the drawings are shown for clarity and may not be to scale. By reading the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents given by such claims.

[0097] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the present disclosure. The disclosed method should not be interpreted as reflecting the intention that the disclosed embodiments of the present disclosure must use more features than the features explicitly recited in each claim. On the contrary, as reflected in the following claims, the subject matter of the present invention lies in less than all the features of a single disclosed embodiment. Therefore, the attached claims are hereby incorporated into the detailed description, wherein each claim independently serves as a separate embodiment.

Claims

1. A semiconductor device comprising: forming a first trench (407) having a first depth and a second trench (401) having a second depth less than the first depth in a semiconductor substrate material (424), wherein the first trench and the second trench are adjacent and separated by the semiconductor substrate material; forming a first metal material (406) in the first trench to a first height (422), the first height being smaller than a second height (423) of the first metal material formed in the second trench relative to the semiconductor substrate material; forming a polysilicon material (436) above the first metal material in the first trench to correspond to a difference between the first depth and the second depth, such that the polysilicon material in the first trench has a third depth (419) relative to the semiconductor substrate material that is greater than a fourth depth (427) of the polysilicon material formed above the first metal material in the second trench; and a second metal material formed in recesses of the polysilicon material in the first trench and the second trench, wherein a bottom of the recess conforms to the third depth in the first trench and the fourth depth in the second trench and separates the second metal material from the first metal material; The larger third depth of the polysilicon material formed in the first trench reduces charge transfer through the first metal material in the first trench.

2. The semiconductor device according to claim 1, wherein: The access device (102) in the second groove is selectively coupled to a storage node (131); and The larger third depth of the polysilicon material in the first trench reduces charge transfer from the storage node.

3. The semiconductor apparatus according to claim 2, wherein the access device is a buried recessed access device BRAD as part of a dynamic random access memory DRAM array.

4. The semiconductor device according to claim 1, wherein: The first metal material and the first portion of the polysilicon material in the first trench include a through access line (282) of an isolation region (292), wherein the isolation region has a depth of 150 nanometers (nm) or greater, a width of 15 nm or less, and an aspect ratio of ten to one (10:1) or greater; and The first metal material and an adjacent second portion of the polysilicon material in the second trench include a hybrid metal gate of an active access line in an active region (290, 291, 392, 394) of an access device for coupling to a sense line, wherein the active region has a depth less than 150 nm, a width of 15 nm or less, and an aspect ratio less than 10:

1.

5. The semiconductor device of claim 1 , wherein each of the respective first trench and the respective second trench comprises: the first metal material and a first portion of the polysilicon material configured to function as a through access line; as well as The first metal material and the second portion of the polysilicon material are configured to function as an active access line for an access device coupled to a sense line (133) and a storage node. 6 . The semiconductor device according to claim 1 , wherein the first metal material comprises tungsten. 7 . The semiconductor device according to claim 1 , wherein the first metal material comprises titanium nitride.

8. The semiconductor device of any one of claims 1 to 5, wherein the polysilicon material comprises n-doped polysilicon.

9. The semiconductor device according to claim 1, wherein: The first trench has a first bottom at a greater depth relative to a second bottom of the second trench, and the greater depth is in a range of 20 nanometers nm to 50 nm; The first metallic material has a substantially equal height above the bottom (408) of each of the first trench and the second trench, such that a top surface of the first metallic material in the first trench has a height that is less than a height of the top surface of the first metallic material formed in the second trench; as well as The third greater depth of the polysilicon material in the first trench is in a range of 20 nm to 50 nm relative to the second depth of the polysilicon material in the second trench.

10. The semiconductor device according to claim 1, wherein: A first thickness of the polysilicon material above the first metal material in the first trench is greater than a second thickness of the polysilicon material above the first metal material in the second trench, and the greater thickness is in a range of 20 nm to 50 nm; a first height of a top surface of the polysilicon material in the first trench substantially equal to a height of a top surface of the polysilicon material in the second trench relative to the semiconductor substrate material; as well as The first trench and the second trench each include a fill material (338, 544) formed over the polysilicon material.

11. A method (650) for forming a semiconductor structure, comprising: forming a portion of a first trench (407) in a semiconductor substrate material (424) to a first depth, wherein the portion of the first trench is designed to serve as a through access line (282) of an isolation trench (107, 307, 407); An adjacent portion of a second trench (401) is formed in the semiconductor substrate material to a second depth, wherein: The first depth is greater than the second depth; and The portion of the second trench is designed to serve as a gate (106) of an active access line of an access device (102) to a memory cell; forming a first metal material (406) to have a first height (422) in the first trench and a second height (423) in the second trench, the first height and the second height each corresponding to a difference between a corresponding first depth and a corresponding second depth; forming a polysilicon material (436) over the first metal material to conform to the difference between the corresponding first depth and the corresponding second depth such that the polysilicon material in the first trench has a third depth (419) greater than a fourth depth of the polysilicon material in the second trench; forming a second metal material in the recesses of the polysilicon material in the first trench and the second trench, wherein the bottoms of the recesses conform to the third depth in the first trench and the fourth depth in the second trench and separate the second metal material from the first metal material; and In response to the greater third depth of the polysilicon material in the first trench, a work function of electron movement is affected to reduce charge transfer from a storage node (131) of the memory cell via the first metal material in the first trench.

12. The method according to claim 11 further includes forming the polysilicon material above the first metal material in the first trench and the second trench to not conform to the difference between the corresponding first depth and the corresponding second depth, so that a first height of the polysilicon material in the first trench is greater than a second height of the polysilicon material in the second trench relative to the first metal material.

13. The method according to claim 11 further includes forming the polysilicon material above the first metal material so that a first height of a first upper surface of the polysilicon material in the first trench is substantially equal to a second height of a second upper surface of the polysilicon material in the second trench relative to the semiconductor substrate material.

14. The method of any one of claims 11 to 13, further comprising reducing a probability of a change in a data value stored by the storage node based on reduced charge transfer from the storage node in response to repeated accesses to the storage node.

15. The method of any one of claims 11 to 13, further comprising reducing the frequency of performing data refresh operations on the storage node based on the reduced charge transfer from the storage node.

16. The method according to any one of claims 11 to 13, further comprising: forming the through access line in a first opening of the first trench between a first pillar (103, 303) and a second pillar; as well as The active access line is formed in a second opening of the second trench between the second pillar and a third pillar.

17. The method according to claim 16, further comprising: using at least one of silicon Si, polycrystalline Si, amorphous Si, and doped Si for the pillar; as well as At least one of Si, polycrystalline Si, and amorphous Si is used for the semiconductor substrate material.

18. The method according to any one of claims 11 to 13, further comprising: forming a nucleation film on the bottom of the opening (410) and from the bottom portion to the top portion of the sidewalls (111) of the first trench and the second trench; reducing a deposition rate of the first metal material on an upper portion of the nucleation film formed on the sidewalls of the first and second trenches relative to a deposition rate of the first metal material on a lower portion of the nucleation film; Depositing the first metal material over the nucleation film to form the first metal material in the first trench to the first height and to form the first metal material in the second trench to the second height; as well as Based on the reduction in the deposition rate of the first metal material on the upper portion of the nucleation film, the probability of seam formation in the first metal material is reduced during the deposition of the first metal material in the first groove and the second groove, so that controlled deposition can be performed from the bottom portion to the top portion of the first groove and the second groove.

19. The method of claim 18, further comprising using at least one of tungsten and titanium nitride for the nucleation film and the first metal material.

20. The method of claim 19, further comprising: forming the nucleation film by depositing the first metal material atoms to a thickness of less than 1 nanometer nm using an atomic layer deposition (ALD) technique; as well as Using a chemical vapor deposition (CVD) technique, the first trench is filled with the first metal material to the first height, and the second trench is filled with the first metal material to the second height.

21. A method (650) for forming a semiconductor structure, comprising: forming a first portion of a trench (507) in a semiconductor substrate material (524) to a first depth; forming an adjacent second portion of the trench to a second depth in the semiconductor substrate material, wherein the first depth is greater than the second depth; forming a first metal material (506) to have a first height in the first portion of the trench and a second height in the second portion of the trench, the first height and the second height each corresponding to a difference between a corresponding first depth and a corresponding second depth; forming a polysilicon material (536) over the first metal material to conform to the difference between the corresponding first depth and the corresponding second depth such that the polysilicon material in the first portion of the trench has a third depth greater than a fourth depth of the polysilicon material in the second portion of the trench; forming a second metallic material (543) in a recess (546) in the polysilicon material in the first and second portions of the trench, wherein a bottom of the recess conforms to the third depth in the first portion of the trench and the fourth depth in the second portion of the trench and separates the second metallic material from the first metallic material; as well as In response to the second metallic material having a work function substantially equal to the polysilicon material and a resistivity lower than the polysilicon material, the resistance along the length of the respective first portion and the respective second portion of the trench is reduced.

22. The method of claim 21 , further comprising reducing an increased resistance along the length associated with a shift in current direction near the difference between the corresponding first depth and the corresponding second depth of the first metal material and near the difference between the third depth and the fourth depth of the polysilicon material.

23. The method of claim 21, further comprising: forming the first portion of the trench to serve as a through access line (282) of the isolation trench (107, 307, 407, 507); as well as The second portion of the trench is formed to serve as a gate (106) of an active access line of an access device to the memory cell.

24. The method according to any one of claims 21 to 23, further comprising: using at least one of tungsten and titanium nitride for the first metal material; Using n-doped polysilicon for the polysilicon material; as well as At least one of ruthenium and platinum is used for the second metal material.

25. The method according to any one of claims 21 to 23, further comprising adjusting the thickness of the walls and bottom of the recess in the polysilicon material in the first portion and the second portion of the trench so that the work function of the polysilicon material is substantially equal to the work function of the selected second metal material.

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