Solid-state imaging device and electronic equipment

Abstract

The present technology relates to a solid-state imaging device and an electronic device capable of improving saturation characteristics. A photodiode is formed on a substrate, and a floating diffusion accumulates signal charges read from the photodiode. A plurality of vertical gate electrodes are formed in a region between the photodiode and the floating diffusion, along a depth direction from the surface of the substrate. An overflow path is formed in a region sandwiched between the plurality of vertical gate electrodes. The present technology can be applied to a CMOS image sensor.

Description

[0001] This application is a divisional application of patent application No. 201680004605.5, whose application date is January 22, 2016 and whose invention name is “Solid-state imaging device and electronic device”. Technical Field

[0002] The present technology relates to a solid-state imaging device and an electronic device, and more particularly, to a solid-state imaging device and an electronic device capable of improving saturation characteristics. Background Art

[0003] Conventionally, there has been known a solid-state image sensor provided with a transfer gate electrode obtained by integrally forming a planar gate electrode and a vertical gate electrode.

[0004] As one of such solid-state image sensors, a solid-state image sensor in which vertical gate electrodes are unevenly arranged in the gate width direction has been proposed (for example, see Patent Document 1). According to this configuration, the potential of the overflow path can be controlled and the blooming characteristic can be improved.

[0005] Citation list

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-26264 Summary of the invention

[0008] Technical Problems to be Solved by the Invention

[0009] However, the above configuration cannot solve the phenomenon that the amount of saturation signal decreases over time when the mechanical shutter operates, and therefore, sufficient saturation characteristics cannot be obtained.

[0010] The present technology has been achieved in view of such a situation, and an object of the present invention is to improve the saturation characteristics.

[0011] Technical solutions to technical problems

[0012] According to one aspect of the present technology, a solid-state imaging device is provided with: a photodiode, which is formed on a substrate; a floating diffusion portion, which accumulates signal charges read from the photodiode; a plurality of vertical gate electrodes, each of which is formed in a region between the photodiode and the floating diffusion portion and along a depth direction from the surface of the substrate; and an overflow path, which is formed in a region sandwiched between the plurality of vertical gate electrodes.

[0013] A planar gate electrode may be further provided on the substrate, the planar gate electrode being formed to straddle the photodiode and the floating diffusion, and the vertical gate electrode may be formed integrally with the planar gate electrode.

[0014] The overflow path may be formed in a region shallower than a depth reached by the plurality of vertical gate electrodes.

[0015] A driving circuit may also be provided, which applies a predetermined voltage to the plurality of vertical gate electrodes, and at the moment when the mechanical shutter closes from an open state, the driving circuit may apply a negative voltage greater than the previously applied negative voltage to the plurality of vertical gate electrodes.

[0016] An electronic device according to one aspect of the present technology is provided with a solid-state imaging device, which includes: a photodiode formed on a substrate; a floating diffusion portion that accumulates signal charges read from the photodiode; a plurality of vertical gate electrodes, each of which is formed in a region between the photodiode and the floating diffusion portion and along a depth direction from the surface of the substrate; and an overflow path formed in a region sandwiched between the plurality of vertical gate electrodes.

[0017] According to one aspect of the present technology, a plurality of vertical gate electrodes are formed in a region between a photodiode and a floating diffusion in a depth direction from a surface of a substrate, and an overflow path is formed in a region sandwiched between the plurality of vertical gate electrodes.

[0018] Beneficial effects of the present invention

[0019] According to one aspect of the present technology, saturation characteristics can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a diagram illustrating the relationship between the operation of the mechanical shutter and the amount of saturation signal.

[0021] Figure 2 is a block diagram illustrating a configuration example of a CMOS image sensor of the present technology.

[0022] Figure 3 is a plan view illustrating a configuration example of a pixel.

[0023] Figure 4 is a cross-sectional view illustrating a configuration example of a pixel.

[0024] Figure 5 is another cross-sectional view illustrating a configuration example of a pixel.

[0025] Figure 6 It's a picture. Figure 4Diagram of the potential of the cross section.

[0026] Figure 7 It's a picture. Figure 5 Diagram of the potential of the cross section.

[0027] Figure 8 is a timing chart illustrating various signals when the mechanical shutter operates.

[0028] Fig. 9 is a diagram illustrating a modulation state of an overflow path.

[0029] Fig.10 is a plan view illustrating another configuration example of a pixel.

[0030] Fig.11 is a cross-sectional view illustrating another configuration example of a pixel.

[0031] Fig.12 is a plan view illustrating still another configuration example of a pixel.

[0032] Fig.13 is a cross-sectional view illustrating still another configuration example of a pixel.

[0033] Fig.14 is a plan view illustrating still another configuration example of a pixel.

[0034] Fig.15 is a cross-sectional view illustrating still another configuration example of a pixel.

[0035] Fig.16 is a plan view illustrating another configuration example of a pixel.

[0036] Fig.17 is a block diagram illustrating a configuration example of an electronic device of the present technology.

[0037] Fig.18 is a diagram illustrating a usage example using an image sensor. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present technology will be described with reference to the drawings.

[0039] Relationship between mechanical shutter operation and saturation signal amount

[0040] Generally, in a camera equipped with both a mechanical shutter and an electronic shutter, Figure 1 As shown in FIG. 1 , when the mechanical shutter is operating, the saturation signal amount Qs of each pixel of the image sensor decreases over time. Figure 1 In the example of FIG. 1 , at 100 ms after the mechanical shutter is closed, the saturation signal amount is reduced by a predetermined signal amount Qd.

[0041] When the mechanical shutter is closed, light does not enter the photodiode. Therefore, the equilibrium state between the electrons generated in the photodiode and the diffusion current component leaking out of the photodiode (specifically, leaking out to the floating diffusion side) will be broken. With this arrangement, the above phenomenon will occur. As a result, sufficient saturation characteristics cannot be obtained, and the dynamic range will deteriorate.

[0042] Therefore, hereinafter, a configuration for alleviating a decrease in the amount of saturation signals after the mechanical shutter is closed will be described.

[0043] Example of the structure of a CMOS image sensor

[0044] Figure 2 FIG. 1 is a diagram illustrating a main configuration example of a complementary metal oxide semiconductor (CMOS) image sensor. Figure 2 The CMOS image sensor 10 shown is an example of a solid-state imaging device to which the present technology is applied. The CMOS image sensor 10 is configured as a back-illuminated image sensor. Meanwhile, it goes without saying that the present technology can also be applied to image sensors having other configurations.

[0045] The CMOS image sensor 10 is formed of a pixel array 12 and a peripheral circuit unit. In the pixel array 12, pixels 11 are regularly arranged in a two-dimensional manner. The pixel 11 includes a photoelectric conversion element (photodiode) and a plurality of pixel transistors. The above structure is formed on a semiconductor substrate (chip) not shown.

[0046] For example, the plurality of pixel transistors include three transistors, namely, a transfer transistor, a reset transistor and an amplification transistor. In addition, the plurality of pixel transistors may also include four transistors, namely, the above three transistors plus a selection transistor.

[0047] The peripheral circuit section is formed of a control circuit 13 , a vertical drive circuit 14 , a column signal processing circuit 15 , a horizontal drive circuit 16 , and an output circuit 17 .

[0048] The control circuit 13 generates a clock signal and a control signal serving as an operation reference of the vertical drive circuit 14, the column signal processing circuit 15, and the horizontal drive circuit 16 based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock. The control circuit 13 supplies these signals to the vertical drive circuit 14, the column signal processing circuit 15, and the horizontal drive circuit 16.

[0049] The vertical drive circuit 14 is formed of, for example, a shift register. The vertical drive circuit 14 selectively scans the pixels 11 in the pixel array 12 in a row in a vertical direction in sequence. Then, the vertical drive circuit 14 supplies the pixel signal of each pixel 11 based on the signal charge generated corresponding to the amount of light received in the photodiode to the column signal processing circuit 15 through the vertical signal line VSL.

[0050] The column signal processing circuit 15 is arranged corresponding to each column of the pixel 11. The column signal processing circuit 15 performs signal processing such as noise elimination on the pixel signal output from the pixel 11 of one row by using the signal from the black reference pixel (the pixel formed around the effective pixel area) of each pixel column. Specifically, the column signal processing circuit 15 performs signal processing such as correlated double sampling (CDS: correlated double sampling) and signal amplification for removing the fixed pattern noise inherent to the pixel 11. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 15, and the horizontal selection switch is connected to the horizontal signal line 18.

[0051] The horizontal drive circuit 16 is formed of, for example, a shift register and sequentially selects each of the column signal processing circuits 15 by sequentially outputting horizontal scanning pulses. Then, the horizontal drive circuit 16 outputs pixel signals from each column signal processing circuit 15 to a horizontal signal line 18.

[0052] The output circuit 17 performs signal processing on the signals sequentially supplied from the column signal processing circuit 15 through the horizontal signal line 18 , and then outputs the signals.

[0053] Example of pixel structure

[0054] Next, refer to Figures 3 to 5 A configuration example of the pixel 11 is described. Figure 3 is a plan view illustrating a configuration example of the pixel 11 . Figure 4 It is along Figure 3 A cross-sectional view of the pixel 11 shown taken along line AA', and Figure 5 It is along Figure 3 The pixel 11 is shown in a cross-sectional view taken along line BB′.

[0055] In the pixel 11 , a photodiode (PD: photo diode) 32 is formed on a semiconductor substrate 31 .

[0056] The pixel 11 is also provided with a vertical transistor (Tr) that reads signal charges generated in the PD 32. The vertical transistor Tr is formed of a transfer gate electrode 33 and a floating diffusion (FD: floating diffusion) 34.

[0057] The transfer gate electrode 33 is obtained by integrally forming a planar gate electrode 33A and vertical gate electrodes 33B-1 and 33B-2. The planar gate electrode 33A is formed on the semiconductor substrate 31 to cross the PD 32 and the FD 34. The vertical gate electrodes 33B-1 and 33B-2 are formed to have a columnar shape in a region between the PD 32 and the FD 34 below the planar gate electrode 33A from the surface of the semiconductor substrate 31 in a depth direction.

[0058] The FD 34 is formed in a position opposing the PD 32 via the transfer gate electrode 33 on the surface of the semiconductor substrate 31. The FD 34 accumulates signal charges read from the PD 32 through the transfer gate electrode 33.

[0059] Furthermore, an overflow path 35 is formed in the region sandwiched between the vertical gate electrode 33B-1 and the vertical gate electrode 33B-2. The overflow path 35 is formed in a region shallower than the depth reached by the vertical gate electrodes 33B-1 and 33B-2. The overflow path 35 is formed by impurities injected into the region sandwiched between the vertical gate electrode 33B-1 and the vertical gate electrode 33B-2.

[0060] In the vertical transistor Tr, at the time of reading, a positive voltage is applied to the transfer gate electrode 33, whereby the potential changes just below the transfer gate electrode 33. Then, the signal charge accumulated in the PD 32 passes through the area around the vertical gate electrodes 33B-1 and 33B-2 of the transfer gate electrode 33 to be transferred to the FD 34. In other words, lateral reading is performed.

[0061] Furthermore, the overflow path 35 serves as a path for transferring signal charges (excess charges) exceeding the saturation signal amount of the PD 32 to the FD 34 when signal charges are accumulated in the PD 32 .

[0062] Figure 6 The diagram shows Figure 3 Potential profile along line A-A' in the figure.

[0063] like Figure 6As shown, when a negative voltage is applied to the transfer gate electrode 33, due to the influence of the potential applied to the vertical gate electrodes 33B-1 and 33B-2 (TG), the potential of the region sandwiched between the vertical gate electrode 33B-1 and the vertical gate electrode 33B-2 becomes lower than the potential around the above region in the line A-A' direction. In other words, the overflow path 35 can be modulated, and the PD 32 and the FD 34 are electrically connected to each other.

[0064] In this way, since the overflow path 35 is formed in the region sandwiched between the vertical gate electrode 33B- 1 and the vertical gate electrode 33B- 2 , the overflow path 35 can be modulated in two directions.

[0065] Figure 7 The diagram shows Figure 3 Potential profile along line BB' in the figure.

[0066] like Figure 7 As shown, the potential of the region of the charge transfer path below the transfer gate electrode 33 (TG), that is, the overflow path 35, is higher than the potentials of the PD 32 and the FD 34. When a negative voltage is applied to the transfer gate electrode 33, the potential of the overflow path 35 becomes higher than the potential around the overflow path in the line BB' direction due to the influence of the potential applied to the vertical gate electrodes 33B-1 and 33B-2. This potential that becomes higher serves as an overflow barrier.

[0067] Modulation of the spillover path when the mechanical shutter is operating

[0068] Here, refer to Figure 8 and Fig. 9 The modulation of the overflow path 35 when the mechanical shutter is in operation is described below. Meanwhile, it is assumed here that the CMOS image sensor 10 is mounted on a camera provided with a mechanical shutter.

[0069] Figure 8 Illustrated is a timing chart of a vertical synchronization signal (V timing), a driving signal of the mechanical shutter, a driving signal of the global shutter, and a bias voltage (TG bias) of the transfer gate electrode 33 when the mechanical shutter of the camera operates. Figure 8 Each signal in is based on the output of the control signal generated by the control circuit 13. Fig. 9 A modulation state of the overflow path according to the operation of the mechanical shutter is illustrated.

[0070] like Figure 8 As shown, in the CMOS image sensor 10, the effective pixel area is scanned within one frame period of the vertical synchronization signal.

[0071] When a trigger pulse to the global shutter is outputted while the mechanical shutter is open, exposure begins. At this time, a predetermined negative voltage is applied to the transfer gate electrode 33 (vertical gate electrodes 33B-1 and 33B-2) by the vertical drive circuit 14. In other words, Fig. 9 As shown on the left side in FIG. 3 , an overflow barrier of a predetermined potential is formed between the PD 32 and the FD 34. With this arrangement, a balanced state between electrons generated in the PD 32 and a diffusion current component leaking from the PD 32 to the FD 34 side can be maintained.

[0072] Then, at time Tc, when the mechanical shutter is closed from the open state, a negative voltage greater than the negative voltage applied before is applied to the transfer gate electrode 33 (vertical gate electrodes 33B-1 and 33B-2) by the vertical drive circuit 14. Fig. 9 As shown on the right side of the figure, a ratio is formed between PD 32 and FD 34. Fig. 9 The potential of the state shown on the left is higher than the potential of the overflow barrier.

[0073] As described above, since the overflow path 35 formed in the region sandwiched between the vertical gate electrode 33B-1 and the vertical gate electrode 33B-2 can be modulated in two directions, the modulation degree of the overflow barrier can be made higher. In other words, the potential of the overflow barrier can be dynamically controlled. With this arrangement, it is possible to prevent the saturation signal amount from decreasing over time when the mechanical shutter is operated, and it is possible to improve the saturation characteristics.

[0074] Modifications

[0075] Although the configuration example in which the overflow path is formed in the region sandwiched by two vertical gate electrodes has been described above, the number of vertical gate electrodes is not limited to two. Therefore, hereinafter, a configuration example in which no less than three vertical gate electrodes are provided will be described.

[0076] Modification 1

[0077] Fig.10 and Fig.11 Another configuration example of the pixel 11 is illustrated. Fig.10 is a plan view illustrating this configuration example of the pixel 11 . Fig.11 yes Fig.10 The pixel 11 shown is Figure 3 The cross-sectional diagram corresponding to the cross-sectional diagram of .

[0078] At the same time, Fig.10 and Fig.11 In the present invention, the same reference numerals are used to designate Figure 3 and Figure 4The structures are similar to those in , and the description of these structures is omitted.

[0079] The transfer gate electrode 51 is obtained by integrally forming a planar gate electrode 51A and vertical gate electrodes 51B-1, 51B-2, and 51B-3. The planar gate electrode 51A is formed on the semiconductor substrate 31 to cross the PD 32 and the FD 34. The vertical gate electrodes 51B-1, 51B-2, and 51B-3 are formed to have a columnar shape in a region between the PD 32 and the FD 34 below the planar gate electrode 51A in a depth direction from the surface of the semiconductor substrate 31.

[0080] An overflow path 52-1 is formed in a region sandwiched between the vertical gate electrode 51B-1 and the vertical gate electrode 51B-2. Furthermore, an overflow path 52-2 is formed in a region sandwiched between the vertical gate electrode 51B-2 and the vertical gate electrode 51B-3. The overflow paths 52-1 and 52-2 are formed in a region shallower than the depth reached by the vertical gate electrodes 51B-1, 51B-2, and 51B-3. The overflow path 52-1 is formed by impurities injected into the region sandwiched between the vertical gate electrode 51B-1 and the vertical gate electrode 51B-2. Furthermore, the overflow path 52-2 is formed by impurities injected into the region sandwiched between the vertical gate electrode 51B-2 and the vertical gate electrode 51B-3.

[0081] With this configuration, the overflow path 52-1 formed in the region sandwiched between the vertical gate electrode 51B-1 and the vertical gate electrode 51B-2 can be modulated in two directions, and the overflow path 52-2 formed in the region sandwiched between the vertical gate electrode 51B-2 and the vertical gate electrode 51B-3 can be modulated in two directions, so that the modulation degree of the overflow barrier can be made higher. As a result, it is possible to prevent the saturation signal amount from decreasing over time when the mechanical shutter is operated, and the saturation characteristics can be improved.

[0082] Modification 2

[0083] Fig.12 and Fig.13 Still another configuration example of the pixel 11 is illustrated. Fig.12 is a plan view illustrating this configuration example of the pixel 11 . Fig.13 yes Fig.12 The pixel 11 shown is Figure 3 The cross-sectional diagram corresponding to the cross-sectional diagram of .

[0084] At the same time, Fig.12 and Fig.13 In the present invention, the same reference numerals are used to designate Figure 3 and Figure 4The structures are similar to those in , and the description of these structures is omitted.

[0085] The transfer gate electrode 61 is obtained by integrally forming a planar gate electrode 61A and vertical gate electrodes 61B-1, 61B-2, and 61B-3. The planar gate electrode 61A is formed on the semiconductor substrate 31 to cross the PD 32 and the FD 34. The vertical gate electrodes 61B-1, 61B-2, and 61B-3 are formed to have a columnar shape from the surface of the semiconductor substrate 31 in the depth direction below the planar gate electrode 61A.

[0086] An overflow path 62 is formed in a region sandwiched between the vertical gate electrode 61B-1, the vertical gate electrode 61B-2, and the vertical gate electrode 61B-3. The overflow path 62 is formed in a region shallower than the depth reached by the vertical gate electrodes 61B-1, 61B-2, and 61B-3. The overflow path 62 is formed by impurities injected into the region sandwiched between the vertical gate electrode 61B-1, the vertical gate electrode 61B-2, and the vertical gate electrode 61B-3.

[0087] With this configuration, since the overflow path 62 formed in the region sandwiched between the vertical gate electrode 61B-1, the vertical gate electrode 61B-2, and the vertical gate electrode 61B-3 can be modulated in three directions, the modulation degree of the overflow barrier can be made much higher. As a result, it is possible to prevent the saturation signal amount from decreasing over time when the mechanical shutter is operated, and it is possible to improve the saturation characteristics.

[0088] Modification 3

[0089] Fig.14 and Fig.15 Still another configuration example of the pixel 11 is illustrated. Fig.14 is a plan view illustrating this configuration example of the pixel 11 . Fig.15 yes Fig.14 The pixel 11 shown is Figure 3 The cross-sectional diagram corresponding to the cross-sectional diagram of .

[0090] At the same time, Fig.14 and Fig.15 In the present invention, the same reference numerals are used to designate Figure 3 and Figure 4 The structures are similar to those in , and the description of these structures is omitted.

[0091] The transfer gate electrode 71 is obtained by integrally forming a planar gate electrode 71A and vertical gate electrodes 71B-1, 71B-2, and 71B-3. The planar gate electrode 71A is formed on the semiconductor substrate 31 to cross the PD 32 and the FD 34. The vertical gate electrodes 71B-1, 71B-2, and 71B-3 are formed to have a columnar shape from the surface of the semiconductor substrate 31 in the depth direction below the planar gate electrode 71A.

[0092] An overflow path 72 is formed in a region sandwiched between the vertical gate electrode 71B-1, the vertical gate electrode 71B-2, and the vertical gate electrode 71B-3. The overflow path 72 is formed in a region shallower than the depth reached by the vertical gate electrodes 71B-1, 71B-2, and 71B-3. The overflow path 72 is formed by impurities injected into the region sandwiched between the vertical gate electrode 71B-1, the vertical gate electrode 71B-2, and the vertical gate electrode 71B-3.

[0093] With this configuration, since the overflow path 72 formed in the region sandwiched between the vertical gate electrode 71B-1, the vertical gate electrode 71B-2, and the vertical gate electrode 71B-3 can be modulated in three directions, the modulation degree of the overflow barrier can be made much higher. As a result, it is possible to prevent the saturation signal amount from decreasing over time when the mechanical shutter is operated, and it is possible to improve the saturation characteristics.

[0094] Modification 4

[0095] Fig.16 Another configuration example of the pixel 11 is shown in the figure. Fig.16 is a plan view illustrating this configuration example of the pixel 11 .

[0096] At the same time, Fig.16 In the present invention, the same reference numerals are used to designate Figure 3 The structures are similar to those in , and the description of these structures is omitted.

[0097] The transfer gate electrode 81 is obtained by integrally forming a planar gate electrode 81A and vertical gate electrodes 81B-1, 81B-2, 81B-3, and 81B-4. The vertical gate electrodes 81B-1, 81B-2, 81B-3, and 81B-4 are obtained by combining Fig.12 and Fig.13 The vertical gate electrodes 61B-1, 61B-2 and 61B-3 in Fig.14 and Fig.15 It is obtained by the vertical gate electrode 71B-3 in.

[0098] With this configuration, since the overflow path 82 formed in the region sandwiched between the vertical gate electrode 81B-1, the vertical gate electrode 81B-2, the vertical gate electrode 81B-3, and the vertical gate electrode 81B-4 can be modulated in four directions, the modulation degree of the overflow barrier can be made much higher. As a result, it is possible to prevent the saturation signal amount from decreasing over time when the mechanical shutter is operated, and the saturation characteristics can be improved.

[0099] Example of electronic device construction

[0100] Next, a configuration example of an electronic device provided with the solid-state imaging device of the present technology will be described.

[0101] The solid-state imaging device of the present technology can be mounted on, for example, electronic devices such as camera systems such as digital cameras and video cameras, mobile phones having an imaging function, and other devices having an imaging function.

[0102] Fig.17 A configuration example of a camera capable of capturing a still image is illustrated as an example of an electronic device equipped with the solid-state imaging device of the present technology.

[0103] Fig.17 The camera 100 in FIG. 1 is provided with a solid-state imaging device 101 , an optical system 102 , a shutter device 103 , a driving circuit 104 , and a signal processing circuit 105 .

[0104] The CMOS image sensor 10 including the pixel 11 in the above-described embodiment (including the modified example) can be applied to the solid-state imaging device 101 .

[0105] The optical system (optical lens) 102 forms an image of image light (incident light) from a subject on an imaging surface of the solid-state imaging device 101. With this arrangement, signal charges can be accumulated in each pixel of the solid-state imaging device 101 for a certain period of time. Meanwhile, the optical system 102 may also be formed by an optical lens group including a plurality of optical lenses.

[0106] The shutter device 103 is provided between the solid-state imaging device 101 and the optical system 102. The shutter device 103 configured as a mechanical shutter controls a light irradiation period and a light shielding period of the solid-state imaging device 101.

[0107] The drive circuit 104 supplies a drive signal (timing signal) to the solid-state imaging device 101 and the shutter device 103. Then, the drive circuit 104 controls the signal output operation of the solid-state imaging device 101 to the signal processing circuit 105 and the shutter operation of the shutter device 103 using the supplied drive signal. In other words, in this example, signal transmission from the solid-state imaging device 101 to the signal processing circuit 105 is performed using the drive signal supplied from the drive circuit 104.

[0108] The signal processing circuit 105 performs various signal processing on the signal transmitted from the solid-state imaging device 101. The signal (image signal) subjected to various signal processing is stored in a storage medium such as a memory (not shown) and output to a monitor (not shown).

[0109] As described above, the saturation characteristic can be improved by using the CMOS image sensor 10 including the pixel 11 in the above embodiment as the solid-state imaging device 101. In other words, the dynamic range can be improved, so that the image obtained by the camera 100 can be a high gradation image.

[0110] Meanwhile, an electronic device provided with a solid-state imaging device (image sensor) to which the present technology is applied may have other configurations in addition to the above-described configurations.

[0111] Examples of image sensor usage

[0112] Finally, a usage example of an image sensor to which the present technology is applied will be described.

[0113] Fig.18 : is a diagram illustrating an example of use of the above-mentioned image sensor.

[0114] The above-described image sensor may be used, for example, in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

[0115] Devices that capture images for viewing: such as digital cameras and portable devices with camera functions.

[0116] Devices for transportation purposes: On-vehicle sensors that capture images of the front, rear, surroundings, and interior of a car for safe driving such as automatic parking and driver identification; surveillance cameras that monitor moving vehicles and roads; and distance sensors that measure the distance between vehicles.

[0117] Devices for home appliances such as televisions, refrigerators, and air conditioners: These devices capture the user's gesture and perform device operations based on the gesture.

[0118] Devices for medical and health care purposes: such as endoscopes and devices that perform angiography by receiving infrared light.

[0119] Devices used for security purposes: such as cameras for security monitoring and cameras for identity authentication.

[0120] Devices for beauty care purposes: such as skin condition measurement devices that take photos of the skin and microscopes that take photos of the scalp.

[0121] Devices for sports use: such as action cameras and wearable cameras for sports use.

[0122] Devices for agricultural use: such as cameras for monitoring the status of fields and crops.

[0123] Meanwhile, embodiments of the present technology are not limited to those described above, and various changes may be made without departing from the scope of the present technology.

[0124] Furthermore, the present technology can have the following configurations.

[0125] (1) A solid-state imaging device, comprising:

[0126] a photodiode formed on a substrate;

[0127] a floating diffusion that accumulates signal charges read from the photodiode;

[0128] a plurality of vertical gate electrodes, each of the vertical gate electrodes being formed in a region between the photodiode and the floating diffusion in a depth direction from a surface of the substrate; and

[0129] An overflow path is formed in a region sandwiched between the plurality of vertical gate electrodes.

[0130] (2) The solid-state imaging device according to (1), further comprising:

[0131] a planar gate electrode formed on the substrate to cross the photodiode and the floating diffusion,

[0132] Wherein, the vertical gate electrode and the planar gate electrode are formed integrally.

[0133] (3) The solid-state imaging device according to (1) or (2), wherein:

[0134] The overflow path is formed in a region shallower than a depth reached by the plurality of vertical gate electrodes.

[0135] (4) The solid-state imaging device according to any one of (1) to (3), further comprising:

[0136] a driving circuit that applies a predetermined voltage to the plurality of vertical gate electrodes,

[0137] Wherein, at the moment when the mechanical shutter is closed from the open state, the driving circuit applies a negative voltage greater than the previously applied negative voltage to the plurality of vertical gate electrodes.

[0138] (5) An electronic device, comprising:

[0139] A solid-state imaging device, comprising:

[0140] a photodiode formed on a substrate;

[0141] a floating diffusion that accumulates signal charges read from the photodiode;

[0142] a plurality of vertical gate electrodes, each of the vertical gate electrodes being formed in a region between the photodiode and the floating diffusion in a depth direction from a surface of the substrate; and

[0143] An overflow path is formed in a region sandwiched between the plurality of vertical gate electrodes.

[0144] Reference numerals list

[0145] 10 CMOS Image Sensor

[0146] 11 pixels

[0147] 13. Control Circuit

[0148] 14 Vertical drive circuit

[0149] 32 Photodiode (PD)

[0150] 33 Transmission gate electrode

[0151] 33A Planar Gate Electrode

[0152] 33B-1, 33B-2 Vertical gate electrode

[0153] 34 Floating diffusion (FD)

[0154] 35 Overflow Path

[0155] 100 Camera

[0156] 101 Solid-state imaging device

Claims

1. A solid-state imaging device, comprising: a photodiode formed on a substrate; a floating diffusion that accumulates signal charges read from the photodiode; a plurality of vertical gate electrodes, each of the vertical gate electrodes being formed in a region between the photodiode and the floating diffusion in a depth direction from a surface of the substrate; as well as an overflow path formed in a region sandwiched between the plurality of vertical gate electrodes, wherein the overflow path is configured to serve as a path for transferring the signal charge exceeding a saturation signal amount of the photodiode to the floating diffusion when the signal charge is accumulated in the photodiode, The overflow path is formed in a region shallower than a depth reached by the plurality of vertical gate electrodes, and The overflow path is formed by impurities implanted into a region sandwiched between the plurality of vertical gate electrodes.

2. The solid-state imaging device according to claim 1, further comprising: a planar gate electrode formed on the substrate to cross the photodiode and the floating diffusion, Wherein, the vertical gate electrode and the planar gate electrode are formed integrally.

3. The solid-state imaging device according to claim 1, further comprising: a driving circuit that applies a predetermined voltage to the plurality of vertical gate electrodes, Wherein, at the moment when the mechanical shutter is closed from the open state, the driving circuit applies a negative voltage greater than the previously applied negative voltage to the plurality of vertical gate electrodes.

4. The solid-state imaging device according to claim 1, wherein On a line along the plurality of vertical gate electrodes, a potential between the plurality of vertical gate electrodes is lower than a potential around the plurality of vertical gate electrodes.

5. The solid-state imaging device according to claim 1, wherein On a line perpendicular to the plurality of vertical gate electrodes, a potential of the overflow path is higher than a potential around the overflow path. 6 . An electronic device comprising the solid-state imaging device according to claim 1 .

Images