Manufacturing method, pixel and sensor of back-illuminated and electron impact CMOS sensor

Abstract

The present invention provides a method for manufacturing a back-illuminated CMOS sensor and an electron impact CMOS sensor capable of suppressing the increase of the offset and deviation of the characteristics of an analog circuit formed on the surface. The method for manufacturing the back-illuminated CMOS sensor (100) comprises: a forming step of forming an N-type photosensitive region (50) inside a silicon substrate (305); an implantation step of implanting ions to form a P+ diffusion layer (270) into the back side of the silicon substrate (305); and an irradiation step of irradiating a laser from the back side to activate the implanted ions, wherein the laser is irradiated to the back-illuminated CMOS sensor (100) except for the region where the analog circuit (40) is formed on the surface.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a back-illuminated CMOS sensor, a method for manufacturing an electron bombarded CMOS sensor, a pixel for a back-illuminated CMOS sensor, and an electron bombarded CMOS sensor. Background Art

[0002] The following patent documents disclose back-illuminated CMOS sensors and methods of manufacturing back-illuminated CMOS sensors.

[0003] For example, in Patent Document 1 (Japanese Patent Publication No. 2003-031785), incident light is collected into a pixel structure of a photodiode through a wiring layer. As a solution to the problem that part of the light focused by a microlens is reflected by the wiring, the following XY address type solid-state imaging element and its manufacturing method are disclosed.

[0004] The solid-state imaging element described in Patent Document 1 is an XY address type solid-state imaging element in which unit pixels including active elements are arranged in a matrix to output signal charges photoelectrically converted by a photoelectric conversion element and output an electrical signal. The element layer has a wiring layer on one side of which wiring is formed relative to the active elements, and receives incident light from the other side of the element layer into the photoelectric conversion element.

[0005] In addition, Patent Document 2 (Japanese Patent Laid-Open No. 2019-176089) discloses a solid-state imaging device that improves the degree of freedom associated with the configuration of transistors.

[0006] In the solid-state imaging device described in Patent Document 2, there are: a photoelectric conversion unit for performing photoelectric conversion; a semiconductor substrate penetrating in the depth direction; a groove formed between the photoelectric conversion units respectively formed in adjacent pixels; and a PN junction region composed of a P-type region and an N-type region on the side wall of the groove, and a part of the side surrounding the photoelectric conversion unit includes a region where the P-type region is not formed or a thin region where the P-type region is formed. The PN junction region is formed on at least one of the four sides surrounding the photoelectric conversion unit, and the P-type region is not formed on the remaining sides.

[0007] In addition, Patent Document 3 (Japanese Patent Laying-Open No. 2015-88568) discloses a solid-state imaging device and a method for manufacturing the solid-state imaging device that can suppress the generation of dark current.

[0008] In the solid-state imaging device described in Patent Document 3, a photoelectric conversion element, a groove and a semiconductor region of the first conductivity type are provided. The photoelectric conversion element is composed of a semiconductor layer of the first conductivity type and a plurality of semiconductor regions of the second conductivity type arranged two-dimensionally in a matrix on the semiconductor layer, and photoelectrically converts incident light into electric charges and accumulates them. The groove is formed between adjacent photoelectric conversion elements and is formed from the surface of the semiconductor layer of the first conductivity type in the depth direction. The semiconductor region of the first conductivity type is arranged in a manner surrounding the outer peripheral surface of the groove, and contains activated impurities of the first conductivity type.

[0009] In addition, Patent Document 4 (Japanese Patent Laying-Open No. 2015-164194) discloses a laser annealing system for annealing a semiconductor wafer in a very short residence time.

[0010] In the laser annealing system described in Patent Document 4, the annealing laser beam is scanned at a speed with a residence time within a range of about 1 μs to about 100 μs. These very short residence times make it difficult for the device side of the device wafer to be heated and damaged during the annealing process when annealing a product wafer formed of a thin device wafer.

[0011] The following invention is disclosed regarding an electron bombarded CMOS sensor.

[0012] Patent Document 5 (Japanese Patent Publication No. 2012-511711) discloses a processing method for a sensor with single-photon sensitivity and a device using the processing method.

[0013] The photon detection device described in Patent Document 5 comprises: a vacuum chamber; a photocathode arranged in the vacuum chamber and designed to convert photons into primary electrons; a converter that converts at least a portion of the energy of the accelerated primary electrons into secondary electrons collected by a plurality of detection units; an acquisition circuit that reads out the charges collected by the detection units together with the cumulative time at which the collision density can be obtained per unit time and per unit area of ​​the unit for a single electron; a unit that determines a cluster of detection units, i.e., a so-called master unit, at least one of which has a collected charge amount larger than a threshold value; a unit that determines at least one characteristic of a cluster; a unit that stores at least one characteristic of a reference cluster caused by the conversion of a primary electron; and a unit that compares the determined characteristic of the cluster with the stored characteristic of the reference cluster in order to prove whether the cluster is caused by the conversion of a primary electron.

[0014] Patent Document 6 (Japanese Patent Publication No. 2009-503857) discloses a method for manufacturing a high vacuum container that can be used as a package for an electron impact type CMOS sensor.

[0015] The method for manufacturing a high vacuum container in which a semiconductor mold is bonded to the inner surface of a package described in Patent Document 6 comprises the following steps: a step of generating a plurality of welding areas on the first surface of the mold; a step of generating a plurality of matching welding areas on the inner surface of the package formed of a material different from that of the first surface of the mold; a step of arranging a chip bonding material having a melting point lower than about 150°C between the combination of welding areas; a step of aligning the surface with the bonding welding areas; a step of arranging the photocathode to be opposite to the second surface of the mold; a step of arranging a spacer between the photocathode and the second surface of the mold; and a step of arranging the photocathode, the spacer and the mold in a contact relationship during a brazing cycle and an ultra-high vacuum treatment cycle, thereby supporting them during the period as a closed vacuum container.

[0016] In non-patent document 1 (“Energy-and spatially-resolved detection using a backside-illuminated CMOS sensor in the soft X-ray region” Tetsuo Harada et al. Applied Physics Express 12(8), 082012-082012, 2019-07-30 IOP Publishing), energy and spatial resolution detection in the soft X-ray region using an electron impact type CMOS sensor is described.

[0017] In the electron impact type CMOS sensor described in Non-Patent Document 1, a common back-illuminated CMOS sensor is used to realize a soft X-ray sensor with high quantum efficiency, low read noise, and high frame rate.

[0018] [Prior art literature]

[0019] [Patent Document]

[0020] [Patent Document 1] Japanese Patent Publication No. 2003-031785

[0021] [Patent Document 2] Japanese Patent Application Publication No. 2019-176089

[0022] [Patent Document 3] Japanese Patent Application Publication No. 2015-88568

[0023] [Patent Document 4] Japanese Patent Application Publication No. 2015-164194

[0024] [Patent Document 5] Japanese Patent Publication No. 2012-511711

[0025] [Patent Document 6] Japanese Patent Publication No. 2009-503857

[0026] [Non-patent literature]

[0027] [Non-patent document 1] "Energy-and spatial-resolved detection using a backside-illuminated CMOS sensor in the soft X-ray region" Tetsuo Harada et.al AppliedPhysics Express 12(8), 082012-082012, 2019-07-30IOP Publishing.

[0028] In a back-illuminated CMOS sensor that is illuminated from the back, electrons from electron-hole pairs generated by defects near the back side of the silicon substrate serve as dark current. Therefore, in order to create a high concentration of holes near the interface on the back side of the silicon substrate, a negatively charged film such as hafnium oxide is formed on the back side, or boron ions are diffused near the interface on the back side to make the area near the interface P-type.

[0029] Among them, the method of forming a film having a negative charge such as hafnium oxide on the back side does not require subsequent heat treatment, so there is less damage to the surface of the silicon substrate on which the elements and wiring layers are formed. However, when a back-illuminated CMOS sensor in which a film such as hafnium oxide is formed on the back side is used as an electron impact type CMOS sensor, electrons accumulate charges through the hafnium oxide film, and there is a problem that the efficiency of electrons reaching the photodiode PD deteriorates, or dark current increases as the use time increases.

[0030] On the other hand, when a P+ diffusion layer is formed near the interface on the back side, the dark current will not increase due to the accumulation of charge. In this case, after forming pixels, analog circuits such as AD converters connected to the pixels, and wiring layers on the surface side of the silicon substrate, a P+ diffusion layer is formed on the back side. Therefore, the P+ diffusion layer is usually formed by ion implantation of boron and activation of the implanted boron ions by laser annealing. Laser annealing is to activate boron by heating the back side of the local silicon substrate to a temperature at which silicon melts, and the pixels, analog circuits, and wiring layers formed on the surface side can be converged within a temperature range that is almost undamaged.

[0031] However, in order to keep the components on the surface side within a temperature range where they are hardly damaged, the heat diffusion distance determined by the thermal annealing time must be shorter than the thickness of the silicon substrate, and the analog circuits of the components on the surface side are also affected by slight changes in the threshold voltage of the MOS transistors, so in particular, when the thickness of the silicon substrate is thinned. For example, in the case of a silicon substrate thickness of about 3 μm, which is the thickness of a general back-illuminated CMOS sensor in recent years, there is a problem that the characteristics of the analog circuit formed on the surface side are shifted and the deviation becomes large, although it also depends on the irradiation conditions of the laser annealing.

[0032] In the back-illuminated CMOS, the mechanical strength is maintained by bonding the silicon substrate on which the sensor is formed to the supporting substrate. However, in this bonding process, a large number of voids are generated around the wafer. In addition, voids are also generated in the center of the wafer with a certain probability. When laser heating is applied to the portion of the bonded wafer where the void exists, there is a problem that the void explodes, etc., causing fragments to be scattered to the surrounding chips, and the surrounding chips also become defective chips.

[0033] In addition, in recent years, electron impact type CMOS sensors using back-illuminated CMOS sensors have been developed as image sensors for photon detection in scenes with low light intensity (Patent Document 5) or image sensors for soft X-ray detection (Non-Patent Document 1). The electron impact type CMOS sensor is formed by sealing a CMOS sensor and a photocathode plate whose first surface faces the photosensitive surface of the CMOS sensor and whose second surface is exposed to the outside in a vacuum chamber, applying a negative high voltage to the photocathode plate, causing photoelectrically converted electrons to collide with the CMOS sensor at high speed, multiplying the electrons, thereby improving the sensitivity of the sensor.

[0034] On the other hand, CMOS sensors are usually used <100> This is because, when using <100> When a MOS transistor is formed on a surface, a MOS transistor with fewer interface states between the silicon substrate and the silicon oxide film and excellent characteristics can be formed.

[0035] However, in <100> In the case of electron impact type CMOS sensors, when electrons are <100> When incident light from a direction perpendicular to the surface hits a specific position of the silicon crystal, there is no interaction between the incident electrons and the silicon atoms, and the electrons pass through the silicon crystal, resulting in a problem in which the electron multiplication effect inside the silicon substrate becomes weak.

[0036] In the solid-state imaging element described in Patent Document 1, boron is implanted on the back surface to form a P-type diffusion layer. However, the thickness of the silicon substrate of the solid-state imaging element described in Patent Document 1 is about 10 μm, and it is believed that the shift and increase in the variation of the characteristics of the analog circuit will not be a problem.

[0037] Similarly, a P-type diffusion layer is provided on the back side in Patent Documents 2 and 3. Patent Documents 2 and 3 do not describe the thickness of the silicon substrate, but since there is no description of the shift in the characteristics of the analog circuit, the increase in the deviation, etc., it is considered that the thickness of the silicon substrate is about the same as that of Patent Document 1.

[0038] Furthermore, in the laser annealing system described in Patent Document 4, the device wafer 10 m is also described as having a thickness TH in the range of approximately 10 μm to 100 μm, and no research is conducted on silicon wafers having a thickness less than 10 μm.

[0039] Furthermore, in Patent Documents 1 to 4, laser annealing is performed on all bonded wafers, but there is no description on explosion of voids in the bonded wafers due to laser annealing.

[0040] In addition, in the electron impact type CMOS sensor described in Patent Documents 5 and 6 and Non-Patent Document 1, it is also considered that the <100> CMOS sensor with silicon substrate, but <100> There is no description of the problem when electrons are incident in a direction perpendicular to the surface. Summary of the invention

[0041] The main object of the present invention is to provide a manufacturing method capable of suppressing the shift and increase in deviation of the characteristics of an analog circuit formed on the surface in a manufacturing method of a back-illuminated CMOS sensor in which boron is ion-implanted into the back side of a silicon substrate and the injected boron is activated by laser annealing.

[0042] Another object of the present invention is to provide a manufacturing method for a back-illuminated CMOS sensor including a step of bonding a silicon substrate on which a sensor is formed to a supporting substrate, which method can avoid void explosion caused by laser heating for activating boron.

[0043] Another object of the present invention is to assemble a <100> In an electron impact type CMOS sensor of a back-illuminated CMOS sensor having a silicon substrate on a surface, an electron impact type CMOS sensor and a manufacturing method thereof are provided, which can suppress the electron impact type CMOS sensor due to the electron impact <100> The degradation of the electron multiplication effect inside the silicon substrate is caused by the incident electrons in the direction perpendicular to the surface. (1)

[0045] According to one aspect of the present invention, a method for manufacturing a back-illuminated CMOS sensor includes: a step of forming an N-type photosensitive area inside a silicon substrate; an injection step of injecting ions into the back side of the silicon substrate to form a P+ diffusion layer; and an irradiation step of irradiating the back side with a laser to activate the injected ions, wherein the laser is irradiated to the back side of the CMOS sensor except for an area on the surface where an analog circuit is formed.

[0046] In addition, as ions forming the P+ diffusion layer, boron ions are preferred.

[0047] Electron-hole pairs are generated near the interface on the back side of the silicon substrate due to defects. When the electrons of the electron-hole pairs reach the photosensitive area, dark current is generated.

[0048] The reason why the P+ diffusion layer is formed by implanting boron or the like into the back surface of the silicon substrate is to suppress the generation of dark current by allowing electrons of generated electron-hole pairs to recombine with holes in the P+ diffusion layer.

[0049] As a method for forming the P+ diffusion layer, for example, by injecting boron ions into the back side of a silicon substrate and then annealing it by irradiating it with a short-time pulsed laser, the implanted boron ions can be activated without being affected by thermal effects on the formation of a readout gate connected to the photosensitive area or the multi-layer wiring on the surface side. This is described in Patent Document 3.

[0050] However, laser annealing has the following problems.

[0051] For example, the maximum allowable temperature of multilayer wiring is typically about 900°C for copper interconnects and about 600°C for aluminum interconnects. However, for MOS transistors, the threshold voltage is considered to fluctuate around 500°C. In this case, the fluctuation of the threshold voltage of the read gate can be compensated to some extent by a CDS (correlated double sampling) circuit, but the high-precision analog circuits such as AD converters included in image sensor chips are weak in compensating for the threshold voltage shift.

[0052] In addition, the thickness of the silicon substrate of the back-illuminated CMOS sensor is about 10 μm, as described in Patent Document 1, and about 10 μm to 100 μm in Patent Document 4, and was also about 10 μm at first. However, as described in Non-Patent Document 1, the thickness of the silicon substrate is 3.5 μm in the back-illuminated CMOS sensor used in the electron impact CMOS sensor, the thickness of the silicon substrate has recently been reduced to about 3 μm as the pixel size has been reduced. When the thickness of the silicon substrate is reduced, the influence on the laser annealing of the analog circuit becomes greater.

[0053] In addition, the thickness of the silicon substrate is reduced as the pixel size decreases. This is because, when the thickness of the silicon substrate is thick, crosstalk between pixels is generated due to the jumping of oblique incident light into adjacent pixels, etc., and the resolution may be reduced.

[0054] According to Patent Document 4, regarding laser annealing, when a laser with a relatively long wavelength such as 1 μm is used, the optical absorption depth D of the laser annealing beam isAD This may also become a problem, so we are more concerned about the impact on analog circuits.

[0055] In a method for manufacturing a back-illuminated CMOS sensor according to one aspect of the present invention, in order to activate the implanted ions, in the irradiation step of irradiating the laser from the back side, the laser is irradiated to the back-illuminated CMOS sensor except for the area where the analog circuit is formed on the surface, thereby reducing the temperature rise of the analog circuit caused by the laser irradiation, and suppressing the increase of the deviation and variation of the characteristics of the analog circuit. As a result, a back-illuminated CMOS sensor with a high SN ratio and free from problems such as vertical stripes in the image caused by the deviation of the analog characteristics between pixel columns can be manufactured. (2)

[0057] The method for manufacturing a back-illuminated CMOS sensor according to the second aspect of the present invention may be configured such that, in the method for manufacturing a back-illuminated CMOS sensor according to one aspect, the laser beam is irradiated only on a pixel region of the back-illuminated CMOS sensor.

[0058] In this case, since the laser beam is not irradiated on the backside region of the digital circuit such as the vertical selection circuit, it is possible to suppress the increase of the deviation and variation of the characteristics of the digital circuit as well. (3)

[0060] The method for manufacturing a back-illuminated CMOS sensor according to the third aspect of the present invention may be such that, in the method for manufacturing a back-illuminated CMOS sensor according to one aspect, the laser beam is irradiated only on a photosensitive area of ​​the back-illuminated CMOS sensor.

[0061] In this case, since the laser beam is not irradiated to the backside region of the circuits such as the source follower transistor arranged around the light-sensitive region of each pixel, it is possible to suppress the increase of the deviation and variation of the characteristics of the readout circuit. (4)

[0063] The manufacturing method of the back-illuminated CMOS sensor involved in the fourth invention may also be that, in the manufacturing method of the back-illuminated CMOS sensor according to one aspect, the back-illuminated CMOS sensor may have the photosensitive area and the readout circuit of each pixel arranged alternately in a direction perpendicular to the scanning direction of the laser, an analog circuit may be arranged in the peripheral portion of the chip where the photosensitive area is extended in the direction perpendicular to the scanning direction of the laser, and a digital circuit may be arranged in the peripheral portion of the chip where the photosensitive area is extended in the scanning direction of the laser, and the laser may be irradiated to the photosensitive area of ​​the back-illuminated CMOS sensor and the area on the surface of which the digital circuit is formed.

[0064] Originally, it is preferred that the laser be irradiated only to the photosensitive area in each pixel of the back-illuminated CMOS sensor, or only to the photosensitive area in each pixel and the digital circuit parts such as the vertical selection circuit around the chip. In order to irradiate the laser only to the photosensitive area in each pixel and not to irradiate the laser to the readout circuit in each pixel, it is necessary to correctly switch the laser on and off during the laser scanning.

[0065] In contrast, in the method for manufacturing a back-illuminated CMOS sensor according to the fourth invention, by studying the configuration of the back-illuminated CMOS sensor, it is possible to irradiate only the photosensitive area in each pixel and the digital circuit parts such as the selection circuit around the chip. Specifically, by alternately arranging the photosensitive area and the readout circuit of each pixel in a direction perpendicular to the scanning direction of the laser, it is possible to irradiate only the photosensitive area of ​​each pixel with the laser during the laser scanning. In addition, by arranging an analog circuit in the chip peripheral part extending in the direction perpendicular to the scanning direction of the laser in the photosensitive area, and arranging a digital circuit in the chip peripheral part along the direction of the extended line of the laser scanning in the photosensitive area, the analog circuit is not irradiated with the laser.

[0066] This makes it possible to manufacture a back-illuminated CMOS sensor without requiring precise switching control during laser scanning. (5)

[0068] According to another aspect, a method for manufacturing a back-illuminated CMOS sensor includes: a step of forming, on the surface of a silicon substrate, a roughly rectangular pixel region having an N-type photosensitive region therein and an analog circuit region adjacent to one side or two opposite sides of the pixel region; an injection step of injecting ions into the back side of the silicon substrate to form a P+ diffusion layer; and an irradiation step of irradiating a laser from the back side in order to activate the injected ions, irradiating the laser in a direction parallel to one side or two opposite sides of the pixel region adjacent to the analog circuit region.

[0069] In a CMOS sensor, usually, the pixels in the column direction of each pixel are connected to a common vertical signal line, and analog circuits such as sampling and holding, CDS, and AD converters are connected to the vertical signal line. In a manufacturing method of a back-illuminated CMOS sensor according to another aspect, laser irradiation for laser annealing performs laser annealing on the entire wafer. In this case, although the characteristics of the analog circuit vary to some extent, the scanning direction of the laser is parallel to the long side direction of the analog circuit area. That is, the portions of the analog circuit connected to the vertical signal line in the direction of each pixel column are irradiated with laser in a common manner. Therefore, even if there is a characteristic variation between the portions of the analog circuit connected to the vertical signal lines, the tendency of the characteristic variation is similar, so the characteristic deviation between the pixel columns becomes smaller. (6)

[0071] According to another aspect, a method for manufacturing a back-illuminated CMOS sensor includes: a step of forming an N-type photosensitive area inside a silicon substrate; a bonding step of bonding the silicon substrate having the N-type photosensitive area to a supporting substrate; an injection step of injecting ions into the back side of the silicon substrate to form a P+ diffusion layer; and an irradiation step of irradiating the laser from the back side in order to activate the injected ions, irradiating the laser to the area other than the peripheral area of ​​the silicon wafer.

[0072] Generally, in a back-illuminated CMOS sensor, the silicon substrate on which the sensor is formed is bonded to a supporting substrate in order to enhance the physical strength of the sensor. However, on a bonded wafer, voids are generated at the bonding interface during bonding. In particular, particles adhere to the periphery of the wafer, and small bubbles are sealed inward along the periphery of the wafer, resulting in more voids.

[0073] When the gap between the bonded wafers is irradiated with laser light, the gas or the like enclosed in the gap expands rapidly, causing the area around the gap to explode, and silicon fragments to fly onto the surrounding chips.

[0074] In the method for manufacturing a back-illuminated CMOS sensor according to another aspect, in the irradiation step, laser light is irradiated to a region other than the peripheral region of the silicon wafer, thereby preventing explosion of voids due to laser irradiation. (7)

[0076] The manufacturing method of the back-illuminated CMOS sensor involved in the seventh invention may also be a method for manufacturing a back-illuminated CMOS sensor according to another aspect, which further includes a recording step of recording the position of the chip where the gap generated in the bonding step exists, and irradiating the laser to the peripheral area of ​​the silicon wafer except for the chip where the gap exists.

[0077] In this case, not only the explosion of the voids in the peripheral region of the silicon wafer but also the explosion of the voids in the chips present inside the silicon wafer can be prevented. (8)

[0079] The manufacturing method of the back-illuminated CMOS sensor involved in the eighth invention may also be, in the manufacturing method of the back-illuminated CMOS sensor involved in one aspect to the seventh invention, further including: an oxide film forming step of forming an oxide film on the back side of the silicon substrate; and a film thickness measuring step of measuring the film thickness of the formed oxide film, in which ions are injected through the oxide film, and the ion injection energy in the injection step is determined according to the film thickness of the oxide film.

[0080] The P+ diffusion layer formed on the back side of the back-illuminated CMOS sensor is arranged as follows: the electrons of the electron-hole pairs generated by defects on the interface between the back side of the silicon substrate and the oxide film formed on the back side recombine with the multiple holes existing in the P+ diffusion layer, and thus do not reach the photosensitive area and become dark current.

[0081] However, when the P+ diffusion layer exists on the back side of the silicon substrate, the electrons that are photoelectrically converted by incident light in the P+ diffusion layer or, in the case of an electron impact type CMOS sensor, the electrons that are multiplied by colliding with the silicon lattice in the P+ diffusion layer will not reach the photosensitive area when these two electrons recombine with the holes in the P+ diffusion layer. Therefore, it is preferable to form a shallow diffusion depth in the P+ diffusion layer.

[0082] However, it is not easy to form a P+ diffusion layer with a shallow diffusion depth and a steep distribution even by ion implantation and laser annealing. One method of forming a P+ diffusion layer with a shallow diffusion depth and a steep distribution is to form an oxide film on the surface of silicon and perform ion implantation through the oxide film. However, in this case, although a P+ diffusion layer with a steep distribution can be formed, there is a problem of a diffusion depth deviation of the P+ diffusion layer due to a film thickness deviation of the oxide film.

[0083] In the method for manufacturing a back-illuminated CMOS sensor according to the eighth invention, the thickness of the oxide film to be formed is measured, and the ion implantation energy is adjusted in accordance with the thickness of the oxide film, thereby forming a P+ diffusion layer having a small diffusion depth and a steep distribution. Furthermore, by forming a P+ diffusion layer having a small diffusion depth and a steep distribution, a back-illuminated CMOS sensor having a small dark current and high sensitivity to photons in a wide energy range and a small deviation can be manufactured. Furthermore, in an electron impact type CMOS sensor using the back-illuminated CMOS sensor manufactured by this method as a sensor, a particularly high sensitivity characteristic can be obtained.

[0084] In addition, when an electron impact type CMOS sensor is used as a sensor for soft X-rays, depending on the wavelength of the X-rays, when the P+ diffusion layer on the back surface is thick, the sensitivity may be reduced. In the manufacturing method of the back-illuminated CMOS sensor involved in the eighth invention, since a shallow P+ diffusion layer can be formed with high precision, an electron impact type CMOS sensor with good sensitivity can be manufactured regardless of the wavelength of the X-rays. (9)

[0086] The manufacturing method of the back-illuminated CMOS sensor involved in the ninth invention, in the manufacturing method of the back-illuminated CMOS sensor involved in one aspect to the eighth invention, may also be that it further includes a deep trench isolation forming process of forming a deep trench isolation around the photosensitive area by trench dry etching on the back side of the silicon substrate, and in the injection process, ions forming a P+ diffusion layer are also injected into the deep trench isolation in addition to the back side of the silicon substrate.

[0087] In a back-illuminated CMOS sensor, by forming a deep trench isolation around the photosensitive area, filling it with a light-shielding material, or forming an air gap inside to perform an optical reflection function, it is possible to block stray light incident from the photosensitive area to the floating diffusion area (FD) or the photosensitive area of ​​the adjacent pixel. In addition, in an electron impact CMOS sensor using a back-illuminated CMOS sensor, it is possible to block the leakage of electrons multiplied in the silicon substrate to the photosensitive area of ​​the adjacent pixel. However, at the interface of the deep trench isolation, dark current is generated due to defects, just like the back side of the silicon substrate.

[0088] In the method for manufacturing a back-illuminated CMOS sensor according to the ninth invention, ions for forming a P+ diffusion layer are implanted into the deep trench isolation in addition to the back side of the silicon substrate, and the implanted ions are activated by laser irradiation, thereby preventing an increase in dark current. (10)

[0090] The manufacturing method of the back-illuminated CMOS sensor involved in the tenth invention may also be, in the manufacturing method of the back-illuminated CMOS sensor involved in one aspect to the eighth invention, further comprising: a deep trench isolation forming step of forming a deep trench isolation around the photosensitive area on the back side of the silicon substrate by trench dry etching; a hole inducing film forming step of forming a film inducing holes on the back side of the silicon substrate and on the surface of the deep trench isolation; and a polishing step of polishing and removing the hole inducing film formed on the back side of the silicon substrate by CMP.

[0091] When a hole-inducing film is formed on the back side of the silicon substrate facing the photosensitive region, particularly in an electron impact type CMOS sensor using a back-illuminated CMOS sensor, strong charges are generated on the film, and dark current increases with time of use.

[0092] On the other hand, it is difficult to form a shallow diffusion layer at the interface of a steeply shaped deep trench isolation by ion implantation.

[0093] In the method for manufacturing a back-illuminated CMOS sensor according to the tenth invention, after forming a P+ diffusion layer on the back side of a silicon substrate by ion implantation, a film inducing vacancy is formed on the interface between the back side of the silicon substrate and the deep trench isolation, and then the film inducing vacancy formed on the back side of the silicon substrate is polished and removed by CMP. In addition, degradation of durability due to electrification of the film can be avoided, and generation of dark current at the interface of the deep trench isolation can be suppressed.

[0094] In addition, as a film that induces holes, for example, a hafnium oxide (HfO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a zirconium oxide (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, or a titanium oxide (TiO 2 ) film can be used. (11)

[0096] According to one aspect, a pixel for a back-illuminated CMOS sensor comprises: an N-type photosensitive region that generates charge in accordance with the energy of light or electrons incident from the back side of a silicon substrate; a transfer gate formed on the surface of the silicon substrate and connected at one end to the photosensitive region; a floating diffusion region formed on the surface of the silicon substrate and connected at one end to the other end of the transfer gate; and a deep trench isolation that is formed at a predetermined depth from the back side of the silicon substrate toward the surface and surrounds the photosensitive region, and further, a P+ diffusion layer is formed on the back side of the silicon substrate and on the surface of the deep trench isolation.

[0097] In a back-illuminated CMOS sensor, by forming a deep trench isolation around the photosensitive area, filling it with a light-shielding material, or forming an air gap inside to perform an optical reflection function, it is possible to block stray light incident from the photosensitive area to the floating diffusion area (FD) or the photosensitive area of ​​the adjacent pixel. In addition, in an electron impact CMOS sensor using a back-illuminated CMOS sensor, it is possible to block the leakage of electrons multiplied in the silicon substrate to the photosensitive area of ​​the adjacent pixel. However, at the interface of the deep trench isolation, dark current is generated due to defects, just like the back side of the silicon substrate.

[0098] In a pixel for a back-illuminated CMOS sensor according to one aspect, an increase in dark current is prevented by a P+ diffusion layer formed on the back surface of a silicon substrate and the surface of a deep trench isolation by ion implantation and laser annealing.

[0099] In particular, when a back-illuminated CMOS sensor is used as an electron impact type, when electrons are multiplied near a deep trench, the electrons before acceleration form a P+ diffusion layer on the surface of the deep trench isolation, thereby being able to offset the electrons among the multiplied electrons that leak to adjacent pixels before acceleration. Therefore, crosstalk between pixels does not occur, and the sensor can be highly sensitive and have good resolution. (12)

[0101] According to another aspect, a pixel for a back-illuminated CMOS sensor comprises: an N-type photosensitive region that generates charge according to the amount of light or electrons incident from the back side of a silicon substrate; a transfer gate formed on the surface of the silicon substrate and connected to the photosensitive region at one end; a floating diffusion region formed on the surface of the silicon substrate and connected to the other end of the transfer gate at one end; and a deep trench isolation that is formed at a predetermined depth from the back side of the silicon substrate toward the surface and surrounds the photosensitive region, and further, a P+ diffusion layer is formed on the back side of the silicon substrate, and a film that induces holes is formed only on the surface of the deep trench isolation.

[0102] When a hole-inducing film is formed on the back surface of a silicon substrate facing a photosensitive region, particularly in an electron impact type CMOS sensor using a back-illuminated CMOS sensor, strong charges are generated in the film, and dark current increases over time.

[0103] On the other hand, it is difficult to form a shallow diffusion layer at the interface of a steeply shaped deep trench isolation by ion implantation.

[0104] In a pixel for a back-illuminated CMOS sensor according to another aspect, a P+ diffusion layer is formed by ion implantation instead of forming a hole-inducing film on the back side of a silicon substrate, thereby avoiding degradation of durability due to charging of the hole-inducing film. On the other hand, on the surface of a deep trench isolation, a hole-inducing film is formed instead of a P+ diffusion layer formed by ion implantation, thereby reliably making the surface of the deep trench isolation a state of high hole concentration.

[0105] In addition, as a film that induces holes, for example, a hafnium oxide (HfO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a zirconium oxide (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, or a titanium oxide (TiO 2 ) film can be used.

[0106] In particular, when a back-illuminated CMOS sensor is used as an electron impact type, since the electrons formed after photoelectric conversion directly enter the silicon substrate, when a hole-inducing film is formed on the surface of the silicon substrate, the electrons collided in the film are away from the depletion layer in the silicon substrate, and the collection efficiency of these electrons may deteriorate. Therefore, by forming a hole-inducing film only on the surface in the deep trench to suppress the generation of dark current, and forming only a P+ diffusion layer on the PD surface, it is possible to form an electron impact type sensor that improves sensitivity and can suppress crosstalk to adjacent pixels. (13)

[0108] According to one aspect, a method for manufacturing an electron impact type CMOS sensor includes: a fixing process of chip-bonding a back-illuminated CMOS sensor manufactured by the method for manufacturing a back-illuminated CMOS sensor involved in one aspect to the tenth invention to the inner side of the bottom surface of a sealed package; a configuration process of configuring a photocathode plate on the upper surface of the sealed package opposite to the photosensitive area of ​​the back-illuminated CMOS sensor; and a sealing process of sealing the space between the back-illuminated CMOS sensor and the photocathode plate under a vacuum state.

[0109] In this case, the analog circuit of the back-illuminated CMOS sensor has less deviation in characteristics due to laser annealing, or less deviation in characteristics between pixel columns. In a method for manufacturing an electron impact type CMOS sensor according to one aspect, an electron impact type CMOS sensor having high sensitivity and uniform characteristics can be manufactured. (14)

[0111] The method for manufacturing an electron impact type CMOS sensor according to the fourteenth invention may be such that the silicon substrate for the back-illuminated CMOS sensor is <100> The silicon substrate is mounted on a surface, and in the fixing process, the silicon substrate is chip-bonded in a state where it is tilted at 7° or 22° relative to the photocathode plate.

[0112] In the <100> In the case of electron impact type CMOS sensors, when electrons are <100> When incident electrons hit a specific position of silicon crystal in a direction perpendicular to the surface, the incident electrons do not interact with silicon atoms, and the electrons pass through the silicon crystal, weakening the electron multiplication effect inside the silicon substrate. In addition, electron impact type CMOS sensors sometimes become bad pixels due to sensitivity degradation or local degradation.

[0113] In the method for manufacturing an electron impact type CMOS sensor according to the fourteenth invention, in the fixing step, the silicon substrate is die-bonded in a state where it is tilted at 7° or 22° with respect to the photocathode plate.

[0114] In this case, since the electrons are incident from the vertical direction at an angle of 7° or 22° <100> Since the silicon substrate is not formed on the surface, electrons do not pass through the silicon crystal. As a result, there will be no electron impact type CMOS sensor that causes sensitivity degradation or local degradation and becomes a bad pixel. (15)

[0116] According to one aspect, the electron impact type CMOS sensor is sealed in a vacuum state. <100> In a back-illuminated CMOS sensor with a silicon substrate having a bottom surface, a photocathode plate is arranged opposite to the photosensitive area of ​​the back-illuminated CMOS sensor. In an electron impact type CMOS sensor in which a negative voltage is applied to the photocathode plate, the silicon substrate is tilted 7° or 22° relative to the photocathode plate for chip bonding.

[0117] The invention of the electron impact type CMOS sensor according to one aspect is an invention of a device corresponding to the invention of the manufacturing method of the fourteenth invention, by using <100> The chip is bonded with the silicon substrate tilted 7° or 22° relative to the photocathode plate to ensure that electrons do not pass through the silicon crystal, preventing the electron impact type CMOS sensor from becoming a bad pixel due to sensitivity degradation or local degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] Figure 1 This is a schematic plan view of the back-illuminated CMOS sensor according to the first embodiment as viewed from the front surface side.

[0119] Figure 2 This is a schematic plan view showing an example of the arrangement of a photosensitive area and a readout circuit in a pixel region of the back-illuminated CMOS sensor according to the first embodiment.

[0120] Figure 3 : is a schematic circuit diagram showing the structure of a pixel of the back-illuminated CMOS sensor according to the first embodiment.

[0121] Figure 4 1 is a schematic cross-sectional view of the periphery of the photosensitive region of the back-illuminated CMOS sensor according to the first embodiment.

[0122] Figure 5 It is a schematic diagram showing the relationship between the position of the void in the silicon wafer and the laser irradiation area in the second embodiment.

[0123] Figure 6 This is a graph showing the difference in distribution of ion-implanted boron depending on the presence or absence of an oxide film in the third embodiment.

[0124] Figure 7 1 is a schematic cross-sectional view of the periphery of a photosensitive region of a back-illuminated CMOS sensor according to a fourth embodiment.

[0125] Figure 8 1 is a schematic cross-sectional view of the periphery of a photosensitive region of a back-illuminated CMOS sensor according to a fifth embodiment.

[0126] Fig. 9 Schematic cross-sectional views for explaining a method for manufacturing a back-illuminated CMOS sensor according to the fifth embodiment.

[0127] Fig.10 It is a schematic cross-sectional view for explaining the structure and operation of the electron impact type CMOS sensor according to the sixth embodiment.

[0128] Fig.11 It is a schematic cross-sectional view for explaining the structure and operation of the electron impact type CMOS sensor according to the seventh embodiment.

[0129] [Description of symbols]

[0130] 10 pixels

[0131] 20 pixel area

[0132] 30 Digital Circuits

[0133] 40 Analog Circuits

[0134] 50 Photosensitive area

[0135] 60 Readout circuit

[0136] 70 Scan direction

[0137] 100 Back-illuminated CMOS sensor

[0138] 110 Silicon Wafer

[0139] 130 Gap

[0140] 200 P-type silicon

[0141] 210 Floating diffusion area

[0142] 220 Transmission Gate

[0143] 240 Silicon oxide film

[0144] 230 Metal Wiring

[0145] 250 P+ diffusion layer

[0146] 260 N+ diffusion layer

[0147] 270 P+ diffusion layer

[0148] 280 Silicon oxide film

[0149] 290 Deep Trench Isolation

[0150] 300 Cavitation Inducing Film

[0151] 305 Silicon substrate

[0152] 310 Support substrate

[0153] 320 Photocathode plate

[0154] 350 Sealed Package

[0155] 360 Electron Impact CMOS Sensor DETAILED DESCRIPTION

[0156] Hereinafter, the embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same components are marked with the same reference numerals. In addition, in the case of the same reference numerals, their names and functions are also the same. Therefore, the detailed description thereof will not be repeated.

[0157] [First embodiment]

[0158] Figure 1 is a schematic top view of the back-illuminated CMOS sensor 100 according to the first embodiment as viewed from the front surface side. Figure 2 1 is a schematic plan view showing an example of the arrangement of the pixel region 20, the photosensitive area 50, and the readout circuit 60 of the back-illuminated CMOS sensor 100. Figure 3 is a schematic circuit diagram showing the structure of a pixel 10 of a back-illuminated CMOS sensor 100, Figure 4 2 is a schematic cross-sectional view of the periphery of the photosensitive region 50 of the back-illuminated CMOS sensor 100 .

[0159] (Configuration of Back-Illuminated CMOS Sensor 100)

[0160] Figure 1 1 shows an example of the overall configuration of a back-illuminated CMOS sensor 100. The back-illuminated CMOS sensor 100 is composed of a pixel region 20, a digital circuit 30 (vertical selection circuit, etc.), and an analog circuit 40 (sample-hold circuit, AD converter, etc.). In the pixel region 20, the pixels 10 are arranged in the horizontal direction ( Figure 1 They are arranged in a matrix in the horizontal and vertical directions. Figure 1 In FIG. 1 , a scanning direction 70 of laser irradiation in laser annealing described later is also indicated by an arrow.

[0161] Figure 2 An example of the arrangement of the photosensitive region 50 and the readout circuit 60 of each pixel 10 within the pixel region 20 is shown. Figure 2 It also indicates the scanning direction 70 of the laser irradiation. Figure 2 It can be seen that the photosensitive area 50 and the readout circuit 60 of each pixel 10 are arranged in the horizontal direction parallel to the scanning direction 70 of the laser irradiation. Figure 2 In the embodiment, the readout circuit 60 is provided independently for each pixel 10 , but the readout circuit 60 may be provided commonly for two to four photosensitive regions 50 .

[0162] Figure 3 1 shows a schematic circuit diagram of the structure of the pixel 10 of the back-illuminated CMOS sensor 100. Figure 3 In the example, the pixel 10 is composed of a photosensitive area 50 ( Figure 3 The readout circuit 60 is composed of a transfer gate TG connected to the photosensitive area 50 at one end, a floating diffusion area FD connected to the other end of the transfer gate TG, a source follower transistor SF whose gate is connected to the FD, a selection transistor SEL for selecting the readout pixel 10, and a reset transistor RST.

[0163] exist Figure 3 In the embodiment, one readout circuit 60 is connected to one photosensitive region 50 , but by providing only the transfer gate TG for each of the four photosensitive regions 50 to perform multiple samplings, the circuits after FD can be shared by the four photosensitive regions 50 .

[0164] (Schematic cross-sectional view of the periphery of the photosensitive region 50)

[0165] Figure 4 1 is a schematic cross-sectional view showing the periphery of the photosensitive region 50 of the back-illuminated CMOS sensor 100. Figure 4 In the figure, the lower direction is the surface and the upper direction is the back. The photosensitive region 50 is formed as an N-type diffusion layer in the P-type silicon 200, and below it, a P+ diffusion layer 250 is formed between the N+ diffusion layer 260 and the silicon oxide film 240. The transmission gate 220 is formed adjacent to the photosensitive region 50 and the N+ diffusion layer 260. When the transmission gate 220 is turned on, the charge accumulated in the photosensitive region 50 is transferred to the floating diffusion region 210. Specifically, the charge is transferred via the metal wiring 230, the source follower transistor SF and the selection transistor SEL (refer to Figure 3 ) is read out and transmitted to the floating diffusion area 210.

[0166] In the back-illuminated CMOS sensor 100, light is emitted from the back side of the silicon substrate 305 ( Figure 4 The back side of the silicon substrate 305 is usually covered with a passivation film such as a silicon oxide film. However, at the interface between the silicon substrate 305 and the passivation film, the electrons in the electron-hole pairs generated by defects become dark current when they reach the photosensitive area 50. In order to prevent the electrons in the electron-hole pairs from reaching the photosensitive area 50, it is effective to increase the amount of holes in the interface and to reliably recombine the electrons in the electron-hole pairs with the holes. In addition, as a method for increasing the amount of holes in the interface, there are a method of forming a P+ diffusion layer 270 at the interface and a method of forming a film that induces holes such as hafnium oxide (hereinafter also referred to as a hole inducing film) at the interface. However, in the case where a hole inducing film is formed at the interface, when the back-illuminated CMOS sensor 100 is used as a sensor of the electron impact type CMOS sensor 360, reliability degradation caused by charge accumulation occurs, so in the present invention, a P+ diffusion layer 270 is formed at the interface. In addition, 280 is a silicon oxide film.

[0167] (Method of Forming P+ Diffusion Layer 270)

[0168] The P+ diffusion layer 270 is effective as a dark current countermeasure, but when electrons are generated by photoelectric conversion inside the P+ diffusion layer 270, or when electrons are generated by collision in an electron impact type sensor, there is a problem that the generated electrons recombine with holes and do not contribute to the output of the sensor. Therefore, it is preferred that the diffusion depth of the P+ diffusion layer 270 is shallower.

[0169] In addition, the formation of the P+ diffusion layer 270 toward the back side is to form the photosensitive area 50 and the readout circuit 60 on the surface side of the silicon substrate 305, bond the surface side of the silicon substrate 305 to the supporting substrate 310, and grind the back side by CMP or other methods. Therefore, if the temperature of the surface side is too high when the P+ diffusion layer is formed, it will have an adverse effect on the circuit or metal wiring layer on the surface side.

[0170] Therefore, the P+ diffusion layer 270 is formed on the back side by a method that can reduce the temperature rise on the surface, that is, a method of activating the boron ions by irradiating with laser light after implanting boron ions.

[0171] Patent Document 4 discloses a method for preventing the device side of a device wafer from being heated and damaged during annealing. However, Patent Document 4 aims to set the maximum temperature of a silicon substrate of 10 μm or more and about 900° C. for copper wiring and about 600° C. for aluminum wiring, and does not study the thermal effects on analog circuits such as AD converters (paragraphs

[0027] to

[0029] of the specification).

[0172] In addition, Patent Document 3 describes an annealing process that can avoid causing adverse effects due to heat on the read gate 44 or the multilayer wiring 45 (paragraph

[0059] of the specification), but does not describe the thickness of the silicon substrate, nor does it study the effects of heat on analog circuits such as AD converters.

[0173] (Effect of Laser Irradiation on Analog Circuit 40)

[0174] Sometimes, a slight change or deviation in the threshold voltage of a MOS transistor causes a change or deviation in the characteristics of the analog circuit 40. In addition, although MOS capacitors are sometimes used as important circuit elements in the analog circuit 40, when the threshold voltage of the MOS transistors used in the MOS capacitors varies between MOS capacitors, the ratio of the MOS capacitors varies, and the characteristics of the analog circuit 40 such as the AD converter often vary.

[0175] Furthermore, when the back side of the silicon substrate 305 is irradiated with laser light, the temperature rise on the surface of the silicon substrate 305 depends on the thickness of the silicon substrate 305. In the original back-illuminated CMOS sensor 100, as described in Patent Document 1, the thickness of the silicon substrate was about 10 μm, but recently, as the pixel size has been reduced, about 3 μm has become the standard. In this case, the temperature rise on the surface caused by irradiating the back side of the silicon substrate 305 with laser light is particularly large.

[0176] The reason why the silicon substrate 305 of the back-illuminated CMOS sensor 100 is thinned is that, if the silicon substrate 305 is thick, crosstalk between pixels may occur due to the oblique incident light entering adjacent pixels, etc., which may reduce the resolution. This trend is expected to continue in the future.

[0177] (Laser Irradiation Method with Less Impact on Analog Circuit 40)

[0178] In the method for manufacturing the back-illuminated CMOS sensor 100 according to the first embodiment, any one of the following methods (1) to (5) is adopted as a laser irradiation method that has little influence on the analog circuit 40 .

[0179] (1) The analog circuit 40 including the AD converter, capacitor, etc. is removed from the surface of each chip (see Figure 1 ) area and irradiate the laser.

[0180] In this case, the laser is directed along Figure 1 The horizontal direction (equivalent to Figure 1 The scanning direction 70) is not scanned in the vertical direction corresponding to the area where the analog circuit 40 is formed around the chip, thereby reducing the thermal influence on the analog circuit 40. In addition, since the laser is irradiated on the back side of the photosensitive area 50 located in the pixel 10, the boron ions ion-implanted into the back side of the photosensitive area 50 are activated.

[0181] (2) The pixel region 20 is formed only on the surface (see Figure 1 ) area is irradiated with laser.

[0182] This method can reduce the thermal effects caused by laser irradiation not only on the analog circuit 40, but also on the digital circuit 30. However, in this method, while scanning the silicon wafer 110 in the horizontal direction with the laser, it is necessary to turn off the laser in the area of ​​the digital circuit 30 in the peripheral part of each chip, so it is necessary to select a laser scanning system that can cope with such scanning.

[0183] (3) Only the back surface of the photosensitive region 50 is irradiated with laser light.

[0184] Since this method irradiates the laser only to the photosensitive area 50 where the P+ diffusion area needs to be formed on the back, it can not only reduce the thermal impact caused by laser irradiation on the analog circuit 40, but also reduce the thermal impact caused by laser irradiation on the readout circuit 60 and the surrounding digital circuit 30. However, in a general image sensor, the readout circuit 60 is arranged above, below, left and right of the photosensitive area 50. Therefore, in order to execute this method, it is necessary to select an area with a narrow scanning width and a laser scanning system that can be repeatedly turned on and off in a short time (at the beginning and end of the photosensitive area 50).

[0185] (4) The configuration of the back-illuminated CMOS sensor 100 is as follows Figure 2 As shown, the photosensitive area 50 and the readout circuit 60 of each pixel 10 are alternately arranged in a direction perpendicular to the scanning direction 70 of the laser, as shown in FIG. Figure 1 As shown, the analog circuit 40 is arranged at the chip periphery where the photosensitive region 50 is extended in a direction perpendicular to the laser scanning direction 70. Then, the digital circuit 30 is arranged at the chip periphery where the photosensitive region 50 is extended in the laser scanning direction 70, so that the laser irradiates the photosensitive region 50 of the back-illuminated CMOS sensor 100 and the region where the digital circuit 30 is formed on the surface.

[0186] In this case, since the laser is irradiated only to the photosensitive area 50 on the back side where a P+ diffusion area needs to be formed and the surrounding digital circuit 30, the thermal effects caused by laser irradiation are not only reduced on the analog circuit 40, but also on the readout circuit 60 such as the source follower transistor SF.

[0187] In addition, in the method combining the configuration of the photosensitive area 50 and the readout circuit 60 and the laser scanning method, the laser needs to scan an area with a narrow width, but while scanning the silicon wafer 110 in the horizontal direction, there is no need to turn the laser on or off, so the construction of the laser scanning system is relatively easy.

[0188] In the above methods (1) to (4), a portion of the back side of the silicon substrate 305 may be selectively irradiated with laser light, and the remaining portion may not be irradiated with laser light. Dark current is also generated in the portion not irradiated with laser light, which may adversely affect the output of the sensor. In this case, in order to suppress the influence of deterioration of the characteristics of the pixel area, low-energy laser light may be irradiated on the remaining portion; or low-energy laser light may be irradiated on the entire surface.

[0189] (5) The configuration of the back-illuminated CMOS sensor 100 is as follows Figure 1As shown in FIG. 1 , the digital circuit 30 such as the vertical selection circuit connected to each pixel row is arranged in a position adjacent to the substantially rectangular pixel region 20 and the laser scanning direction 70 so that the column of the circuit part connected to each pixel row is perpendicular to the laser scanning direction 70. In addition, the output ( Figure 3 The analog circuits 40 such as the sampling and holding circuits and the AD converter connected to the vertical signal lines of the OUT1 are arranged adjacent to the pixel region 20 and the laser scanning direction 70 in a direction perpendicular to the pixel region 20, so that the columns of the circuit parts connected to the vertical signal lines are parallel to the laser scanning direction 70. Then, the back-illuminated CMOS sensor 100 arranged as above is arranged along the entire Figure 1 The scanning direction 70 is scanned with laser in sequence.

[0190] In this case, since the area of ​​the analog circuit 40 is also scanned with a laser, there is a possibility that the characteristics of the analog circuit 40 will change due to heating, but since the portions of the analog circuit 40 connected to the vertical signal lines of each pixel column are heated in substantially the same manner, the changes in the characteristics of the portions of the analog circuit 40 connected to the vertical signal lines of each pixel column are similar, and thus the characteristic deviations between the pixel columns become smaller.

[0191] In addition, in this method, as long as the scanning direction 70 is limited to the laser scanning system, there is no need for difficult requirements such as on / off control of the laser.

[0192] [Second Embodiment]

[0193] Figure 5 1 is a schematic diagram showing the relationship between the position of the void 130 in the silicon wafer 110 and the laser irradiation region 120 in the second embodiment.

[0194] Generally, the back-illuminated CMOS sensor 100 improves physical strength by bonding the surface side of the silicon wafer 110 on which the photosensitive area 50 or the readout circuit 60 is formed to the silicon wafer as the support substrate 310. However, when the silicon wafers are bonded to each other, voids 130 (voids) are generated at the bonding interface. In particular, particles adhere to the periphery of the wafer, and small bubbles are sealed inside along the periphery of the wafer, thereby generating more voids 130.

[0195] Furthermore, when the gap 130 of the bonded wafer is irradiated with laser light, the gas or the like enclosed in the gap 130 expands rapidly, and the area around the gap 130 explodes, and silicon fragments are also scattered to the surrounding chips.

[0196] In the method for manufacturing the back-illuminated CMOS sensor 100 according to the second embodiment, the following two methods are adopted to avoid explosion when the portion of the space 130 is irradiated with laser light.

[0197] First, the laser beam is not irradiated to the periphery of the silicon wafer 110 where more gaps 130 are generated. Figure 5 As described, by limiting the laser irradiation area 120 to the periphery of the chip on which the back-illuminated CMOS sensor 100 is formed, the laser is not irradiated to the periphery of the wafer where more voids 130 are generated, thereby reducing the risk of explosion around the voids 130.

[0198] Second, the bonded silicon wafer 110 is inspected and the positions of the chips with the gaps 130 are recorded. During laser irradiation, the chips with the gaps 130 are removed from the laser irradiation in addition to the peripheral area of ​​the silicon wafer 110 .

[0199] In addition, when there are almost no voids 130 other than the peripheral region of the silicon wafer 110, only the peripheral region may be removed from the laser irradiation.

[0200] [Third Embodiment]

[0201] Figure 6 This is a graph showing the difference in distribution of ion-implanted boron depending on the presence or absence of an oxide film.

[0202] The method for manufacturing the back-illuminated CMOS sensor 100 according to the third embodiment relates to a method for implanting boron ions into the back surface of the back-illuminated CMOS sensor 100 .

[0203] like Figure 4 As shown, a P+ diffusion layer 270 is formed on the back side (light incident side) of the photosensitive region 50. This is to prevent the electrons of the electron-hole pairs generated at the interface on the back side from disappearing by recombination with the holes of the P+ diffusion layer 270 and from becoming dark current.

[0204] On the other hand, when incident photons undergo photoelectric conversion inside the P+ diffusion layer 270, the back-illuminated CMOS sensor 100 cannot detect the photons. In addition, when the back-illuminated CMOS sensor 100 is used as a sensor of the electron impact type CMOS sensor 360, the electrons that collide with the silicon crystal inside the P+ diffusion layer 270 and multiply cannot be counted as the electron impact type CMOS sensor 360.

[0205] Therefore, in the formation of the P+ diffusion layer 270 on the back side, it is necessary to use a higher concentration (for example, 10 19 / cm 3In order to form such a shallow distribution by ion implantation, even if the diffusion caused by laser annealing can be ignored, it is necessary to implant ions at a very low energy, for example, less than several KeV. However, it is sometimes difficult to perform ion implantation at low energy. In addition, there is also the problem of white spots due to metal contamination during ion implantation.

[0206] As a countermeasure to this situation, a method of forming an oxide film on the silicon surface, implanting ions through the oxide film, performing annealing, and then removing the oxide film may be considered.

[0207] Figure 6 (a) shows the distribution of boron when boron is implanted into silicon having almost no oxide film. Figure 6 (b) shows the distribution of boron when boron is injected through the oxide film. Figure 6 (a) and Figure 6 (b) shows that by injecting boron through the oxide film, the distribution depth of the implanted boron from the silicon interface becomes shallower. Figure 6 The horizontal axis is the distance from the wafer surface, and the vertical axis is the ion implantation distribution (linear scale).

[0208] However, when ions are implanted through an oxide film, a new problem occurs in that the diffusion depth varies due to variations in the thickness of the oxide film to be formed.

[0209] In the manufacturing method of the back-illuminated CMOS sensor 100 of the third embodiment, after forming an oxide film on the back side of the back-illuminated CMOS sensor 100, the film thickness of the oxide film is measured, and the ion implantation energy is adjusted according to the measured film thickness of the oxide film, so that regardless of the film thickness of the formed oxide film, a P+ diffusion layer 270 with a small deviation in diffusion depth and a steep distribution is formed. In addition, a back-illuminated CMOS sensor 100 with a small dark current and a high sensitivity to photons in a wide energy range and a small deviation can be manufactured. Furthermore, in the electron impact type CMOS sensor 360 using the back-illuminated CMOS sensor 100 manufactured by this method as a sensor, a particularly high sensitivity characteristic can be obtained.

[0210] In addition, when an electron impact type CMOS sensor is used as a sensor for soft X-rays, the P+ diffusion layer on the back surface may be thick due to the wavelength of the X-rays, resulting in reduced sensitivity. In the method for manufacturing a back-illuminated CMOS sensor of the third embodiment, a shallow P+ diffusion layer can be formed with high precision, so an electron impact type CMOS sensor with good sensitivity can be manufactured regardless of the wavelength of the X-rays.

[0211] [Fourth Embodiment]

[0212] Figure 7 1 is an example of a schematic cross-sectional view of the periphery of the photosensitive region 50 of the back-illuminated CMOS sensor 100 of the fourth embodiment. The back-illuminated CMOS sensor 100 of the fourth embodiment is different from the back-illuminated CMOS sensor 100 of the first embodiment in that a deep trench isolation 290 surrounding the periphery of the photosensitive region 50 is formed at a predetermined depth from the back surface toward the surface, and a P+ diffusion layer 270 is further formed on the deep trench isolation 290.

[0213] In the back-illuminated CMOS sensor 100 of the fourth embodiment, a structure having an optical reflection function such as a deep trench isolation 290 is formed around the photosensitive region 50, a light shielding material is buried, or an air gap is formed inside the deep trench isolation 290, thereby blocking stray light incident from the photosensitive region 50 to the floating diffusion region 210 or the photosensitive region 50 of the adjacent pixel 10. In addition, in the electron impact type CMOS sensor 360 using the back-illuminated CMOS sensor 100, it is possible to cut off the leakage of electrons multiplied in the silicon substrate 305 to the photosensitive region 50 of the adjacent pixel 10. However, at the interface of the deep trench isolation 290, dark current is generated due to defects, similar to the back surface of the silicon substrate 305. Therefore, in the back-illuminated CMOS sensor 100 of the fourth embodiment, boron ions are implanted in the deep trench isolation 290 in addition to the back surface of the silicon substrate 305 to form the P+ diffusion layer 270, and the implanted ions are activated by laser irradiation to prevent the increase of dark current.

[0214] In addition, Figure 7 In the example shown in FIG. 1 , the silicon oxide film 280 is buried inside the deep trench isolation 290, but an air gap may be buried, or aluminum or the like may be buried.

[0215] A method of forming the P+ diffusion layer 270 also in the deep trench isolation 290 in addition to the back surface of the silicon substrate 305 is as follows.

[0216] First, on the back side of the back-illuminated CMOS sensor 100 , a deep trench isolation 290 is formed around the photosensitive region 50 by trench dry etching.

[0217] Next, boron ions are implanted into the entire back surface including the deep trench isolation 290 .

[0218] Next, the entire back surface including the deep trench isolation 290 is irradiated with laser light to activate boron.

[0219] In the method for manufacturing the back-illuminated CMOS sensor 100 of the fourth embodiment, similarly to the first embodiment, a laser irradiation method (any of (1) to (5) of the first embodiment) that has little influence on the analog circuit 40 is used.

[0220] [Fifth Embodiment]

[0221] Figure 8 FIG. 1 is an example of a schematic cross-sectional view of the periphery of the photosensitive region 50 of the back-illuminated CMOS sensor 100 according to the fifth embodiment. Fig. 9 1 is a schematic cross-sectional view for explaining a method for manufacturing a back-illuminated CMOS sensor 100 according to a fifth embodiment. The back-illuminated CMOS sensor 100 according to the fifth embodiment is different from the back-illuminated CMOS sensor 100 according to the first embodiment in that a deep trench isolation 290 is formed to a predetermined depth from the back surface toward the surface to surround the photosensitive region 50, and a hole induction film 300 is formed on the deep trench isolation 290.

[0222] When the hole induction film 300 is formed on the back surface of the silicon substrate 305 facing the photosensitive region 50, particularly in the electron impact type CMOS sensor 360 using the back-illuminated CMOS sensor 100, strong charges are generated in the film, and dark current increases with the use time.

[0223] On the other hand, it is difficult to form a shallow P+ diffusion layer 270 at the interface of the steeply shaped deep trench isolation 290 by ion implantation.

[0224] In the back-illuminated CMOS sensor 100 of the fifth embodiment, the hole inducing film 300 is not formed on the back side, but a P+ diffusion layer 270 is formed by ion implantation, thereby avoiding the degradation of durability caused by the charging of the hole inducing film 300. On the other hand, on the surface of the deep trench isolation 290, the P+ diffusion layer 270 is not formed by ion implantation, but a hole inducing film 300 is formed, so that the surface of the deep trench isolation 290 can be reliably in a state of high hole concentration.

[0225] use Fig. 9 The method of forming the P+ diffusion layer 270 on the back surface and forming the hole inducing film 300 on the surface of the deep trench isolation 290 will be described.

[0226] First, boron ions are implanted into the back surface of the back-illuminated CMOS sensor 100, and the implanted boron is activated by laser annealing. In this case, the boron ions can also be implanted deeper than in the fifth embodiment.

[0227] Next, on the back side of the back-illuminated CMOS sensor 100 , a deep trench isolation 290 is formed around the photosensitive region 50 by trench dry etching.

[0228] Then, if Fig. 9 As shown in (a), a hole inducing film 300 is formed on the back surface of the back-illuminated CMOS sensor 100 and the surface of the deep trench isolation 290 .

[0229] Then, if Fig. 9As shown in (b), the hole inducing film 300 formed on the back surface is polished and removed by CMP or other methods. In the case of deeper implantation of boron ions, silicon on the back surface is also polished and removed so that the depth of the boron diffusion layer becomes appropriate.

[0230] In the method for manufacturing the back-illuminated CMOS sensor 100 of the fifth embodiment, similarly to the first embodiment, a laser irradiation method (any of (1) to (5) of the first embodiment) that has little influence on the analog circuit 40 is used.

[0231] [Sixth Embodiment]

[0232] Fig.10 It is a schematic cross-sectional view for explaining the structure and operation of an electron impact type CMOS sensor 360 according to the sixth embodiment.

[0233] exist Fig.10 In the embodiment, an N-type photosensitive region 50 is provided in the P-type silicon 200, and a photosensitive region 50 is provided on the back side ( Fig.10 The back-illuminated CMOS sensor 100 formed by bonding a silicon substrate 305 having a P+ diffusion layer 270 and a silicon oxide film 280 formed on the upper surface (the upper surface of the back-illuminated CMOS sensor 100) and a supporting substrate 310 is sealed inside the bottom surface of a sealing package 350. In addition, a photocathode plate 320 is arranged opposite to the back side (photosensitive area) of the back-illuminated CMOS sensor 100, and the back-illuminated CMOS sensor 100 and the photocathode plate 320 are sealed in a vacuum state. The photocathode plate 320 applies a high negative voltage to the back-illuminated CMOS sensor 100 through a high voltage power supply 340. When a photon (PHOTON) is incident on the photocathode plate 320, an electron (ELECTRON) is generated, and the generated electron is accelerated by the electric field applied between the back-illuminated CMOS sensor 100 and the photocathode plate 320, and is incident on the back-illuminated CMOS sensor 100. Electrons reaching the silicon substrate 305 of the back-illuminated CMOS sensor 100 generate electron-hole pairs by colliding with silicon crystals, and the electrons multiplied by the generation of electron-hole pairs reach the photosensitive region 50 and become sensor output.

[0234] The manufacturing method of the electron impact type CMOS sensor 360 of the sixth embodiment includes: a fixing process of chip-bonding the back-illuminated CMOS sensor 100 to the inner side of the bottom surface of the sealed package 350; a configuration process of configuring the photocathode plate 320 on the upper surface of the sealed package 350 opposite to the photosensitive area of ​​the back-illuminated CMOS sensor 100; and a sealing process of sealing the space between the back-illuminated CMOS sensor 100 and the photocathode plate 320 in a vacuum state.

[0235] In addition, in the electron impact CMOS sensor 360 of the sixth embodiment, in order to reduce dark current, a shallow boron ion P+ diffusion layer 270 is formed on the back side of the back-illuminated CMOS sensor 100. In the manufacturing method of the electron impact CMOS sensor 360 of the sixth embodiment, the P+ diffusion layer 270 is formed by ion implantation and laser annealing.

[0236] In this laser annealing, similarly to the first embodiment, it is preferable to use a laser irradiation method (any of (1) to (5) in the first embodiment) that has little influence on the analog circuit 40 .

[0237] In order to avoid explosion around the void 130 during laser annealing, it is preferable to limit the laser irradiation area 120 as in the second embodiment.

[0238] In order to form the P+ diffusion layer 270 of boron ions at a shallow depth with high precision, it is preferable to perform ion implantation via the silicon oxide film of the fourth embodiment.

[0239] In order to prevent the multiplied electrons from leaking to adjacent pixels 10 and to prevent an increase in dark current, it is preferable to add the deep trench isolation 290 of the fifth or sixth embodiment to the back-illuminated CMOS sensor 100 .

[0240] [Seventh Embodiment]

[0241] Fig.11 2 is a schematic cross-sectional view for explaining the structure and operation of the electron impact type CMOS sensor 360 of the seventh embodiment. The structure of the electron impact type CMOS sensor 360 of the seventh embodiment is the same as that of the electron impact type CMOS sensor 360 of the sixth embodiment except that a chip fixing table 370 made of a conductive material such as metal is inserted between the back-illuminated CMOS sensor 100 and the inner side of the bottom surface of the sealing package 350 so as to perform chip bonding with the back-illuminated CMOS sensor 100 tilted at 7° or 22° relative to the photocathode plate 320.

[0242] The back-illuminated CMOS sensor 100 used in the electron impact type CMOS sensor 360 of the seventh embodiment uses <100> In this case, when electrons are <100> When incident electrons are incident on a specific position of silicon crystal in a direction perpendicular to the surface, there is no interaction between the incident electrons and silicon atoms, and the electrons are separated from the silicon lattice, and the electron multiplication effect inside the silicon substrate 305 is weakened. In addition, the electron impact type CMOS sensor 360 sometimes becomes a bad pixel due to sensitivity degradation or local degradation.

[0243] In the electron impact type CMOS sensor 360 of the seventh embodiment, as a countermeasure to solve this problem, the back-illuminated CMOS sensor 100 is chip-bonded at an angle of 7° or 22° relative to the photocathode plate 320, so that no matter what the position of the electron incidence is, it is incident from the angle of 7° or 22° that can reliably cause interaction with silicon atoms after the tilt.

[0244] In the present invention, the silicon substrate 305 is equivalent to the "silicon substrate", the photosensitive region 50 is equivalent to the "photosensitive region", and the P+ diffusion layer 270 is equivalent to the "P+ diffusion layer". The back-illuminated CMOS sensor 100 is equivalent to the "back-illuminated CMOS sensor", the analog circuit 40 is equivalent to the "analog circuit", the pixel region 20 is equivalent to the "pixel region", the scanning direction 70 is equivalent to the "scanning direction", the pixel 10 is equivalent to the "pixel", the readout circuit 60 is equivalent to the "readout circuit", the digital circuit 30 is equivalent to the "digital circuit", the support substrate 310 is equivalent to the "support substrate", the silicon wafer 110 is equivalent to the "silicon wafer", the gap 130 is equivalent to the "gap", the deep trench isolation 290 is equivalent to the "deep trench isolation", the hole inducing film 300 is equivalent to the "hole inducing film", the transfer gate 220 is equivalent to the "transfer gate", the floating diffusion region 210 is equivalent to the "floating diffusion region", the sealing package 350 is equivalent to the "sealing package", the photocathode plate 320 is equivalent to the "photocathode plate", and the electron impact type CMOS sensor 360 is equivalent to the "electron impact type CMOS sensor".

[0245] The preferred embodiments of the present invention are as described above, but the present invention is not limited thereto. Various embodiments that do not depart from the spirit and scope of the present invention can be understood as other embodiments. Furthermore, in this embodiment, the effects and effects produced by the structure of the present invention are described, but these effects and effects are only examples and do not limit the present invention.

Claims

1. A method for manufacturing a back-illuminated CMOS sensor, characterized in that: include: A step of forming an N-type photosensitive region inside a silicon substrate; An ion implantation step of implanting ions into the back side of the silicon substrate to form a P+ diffusion layer; as well as an irradiation step of irradiating a laser beam from the back side of the silicon substrate in order to activate the implanted ions; The back-illuminated CMOS sensor is irradiated with the laser beam except for a region on the surface where an analog circuit is formed. The back-illuminated CMOS sensor has the photosensitive area and the readout circuit of each pixel arranged alternately in a direction perpendicular to the scanning direction of the laser, the analog circuit is arranged around the chip where the photosensitive area is extended along the direction perpendicular to the scanning direction of the laser, and the digital circuit is arranged around the chip where the photosensitive area is extended along the scanning direction of the laser. The laser is irradiated onto the photosensitive area of ​​the back-illuminated CMOS sensor and the area on the surface where the digital circuit is formed.

2. The method for manufacturing a back-illuminated CMOS sensor according to claim 1, characterized in that: The laser light illuminates only the pixel area of ​​the back-illuminated CMOS sensor.

3. The method for manufacturing a back-illuminated CMOS sensor according to claim 1, characterized in that: The laser irradiates only the photosensitive area of ​​the back-illuminated CMOS sensor.

4. A method for manufacturing a back-illuminated CMOS sensor, characterized in that: include: A step of forming a rectangular pixel region having an N-type photosensitive region therein and an analog circuit region adjacent to one side or two opposite sides of the pixel region on a surface of a silicon substrate; An ion implantation step of implanting ions into the back side of the silicon substrate to form a P+ diffusion layer; as well as In order to activate the implanted ions, a laser irradiation step is performed from the back surface. The laser beam is irradiated in a direction parallel to one side or two opposite sides of the pixel region adjacent to the analog circuit region.

5. A method for manufacturing a back-illuminated CMOS sensor, characterized in that: include: A step of forming an N-type photosensitive region inside a silicon substrate; A bonding step of bonding the silicon substrate having the N-type photosensitive region formed thereon to a supporting substrate; an implantation step of implanting ions into the back side of the silicon substrate to form a P+ diffusion layer; and an irradiation step of irradiating the implanted ions with laser light from the back surface, The laser beam is irradiated to the area other than the peripheral area of ​​the silicon wafer. The method further comprises a step of recording the position of the chip where the gap generated in the bonding step exists, The laser beam is irradiated to the silicon wafer except for the peripheral region and the chip where the gap exists.

6. The method for manufacturing a back-illuminated CMOS sensor according to any one of claims 1 to 5, characterized in that: Further including: an oxide film forming step of forming an oxide film on the back surface of the silicon substrate; as well as a film thickness measuring step of measuring the film thickness of the formed oxide film, In the implantation step, ions are implanted through the oxide film, and the ion implantation energy in the implantation step is determined according to the film thickness of the oxide film.

7. The method for manufacturing a back-illuminated CMOS sensor according to claim 6, characterized in that: The method further comprises forming a deep trench isolation by dry-etching a trench on the back side of the silicon substrate to form a deep trench isolation around the photosensitive area. In the implantation step, ions for forming a P+ diffusion layer are implanted into the deep trench isolation in addition to the back surface of the silicon substrate.

8. The method for manufacturing a back-illuminated CMOS sensor according to claim 6, wherein: Further including: A deep trench isolation forming step of forming deep trench isolation on the back side of the silicon substrate around the photosensitive area by trench dry etching; A hole inducing film forming step of forming a film inducing holes on the back surface of the silicon substrate and the surface of the deep trench isolation; as well as A polishing step of polishing and removing the film inducing the voids formed on the back surface of the silicon substrate by CMP.

9. A method for manufacturing an electron impact type CMOS sensor, characterized in that: include: A fixing step of bonding the back-illuminated CMOS sensor manufactured by the method for manufacturing a back-illuminated CMOS sensor according to any one of claims 1 to 8 to the inner side of the bottom surface of the sealed package by chip bonding; A process of disposing a photocathode plate on the upper surface of the sealed package, opposite to the photosensitive area of ​​the back-illuminated CMOS sensor; and A sealing step of sealing the space between the back-illuminated CMOS sensor and the photocathode plate in a vacuum state.

10. The method for manufacturing an electron impact type CMOS sensor according to claim 9, characterized in that: The silicon substrate used to manufacture the back-illuminated CMOS sensor is a (100)-plane silicon substrate. In the fixing step, the silicon substrate is die-bonded in a state where the silicon substrate is tilted at 7° or 22° with respect to the photocathode plate.

11. An electron impact type CMOS sensor manufactured according to the method for manufacturing an electron impact type CMOS sensor according to claim 9 or 10, characterized in that: A back-illuminated CMOS sensor using a (100) silicon substrate sealed in a vacuum state. A photocathode plate is arranged opposite to the photosensitive area of ​​the back-illuminated CMOS sensor. applying a negative voltage to the photocathode plate, The silicon substrate is chip-bonded at an angle of 7° or 22° relative to the photocathode plate.

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