Display device

Abstract

A display device includes a display panel defining a display area and a peripheral area adjacent to the display area, and including a plurality of wirings arranged in the peripheral area and a plurality of pads each connected to the wirings and defining an opening portion; an electronic component including a plurality of connection pads in contact with the pads; and a filling layer arranged between the display panel and the electronic component, and interposed between the connection pads, between the pads, and in the opening portion. Each of the pads overlaps at least two of the connection pads, and the opening portion is located between the connection pads when viewed in a planar direction.

Description

Technical Field

[0001] This invention relates to display devices, and more specifically to display devices with improved bonding reliability. Background Technology

[0002] We are developing various display devices for use in multimedia devices such as televisions, mobile phones, tablets, navigators, and game consoles.

[0003] The display device includes a display panel for displaying images. The display panel includes signal wiring and pixels connected to the signal wiring. The display device may include electronic components that provide electrical signals required for image display to the display panel.

[0004] On the other hand, electronic components can be electrically connected to the display panel using anisotropic conductive film, ultrasonic bonding, or laser bonding. Among these methods, ultrasonic bonding or laser bonding offers higher conductivity between the display panel and electronic components compared to anisotropic conductive film, and can simplify the manufacturing process. Summary of the Invention

[0005] The purpose of this invention is to provide a display device that improves the reliability of the bonding process.

[0006] An embodiment of the present invention relates to a display device, which may include: a display panel defining a display area and a peripheral area adjacent to the display area, and including a plurality of wirings disposed in the peripheral area and a plurality of pads respectively connected to the wirings and defined with openings; an electronic component including a plurality of connection pads in contact with the pads; and a fill layer disposed between the display panel and the electronic component, and between the connection pads, between the pads and the openings, wherein each of the pads overlaps with at least two of the connection pads, and when viewed in a plane, the openings are located between the connection pads.

[0007] Alternatively, the filling layer may be non-conductive and include a photoinitiator.

[0008] Alternatively, the electronic component may also include a base film, wherein a plurality of the connection pads extend along a first direction and are arranged along a second direction intersecting the first direction on one side of the base film.

[0009] According to one embodiment of the present invention, each of the pads may have a plurality of openings spaced apart at predetermined intervals in the first direction and the second direction.

[0010] According to one embodiment of the present invention, a plurality of the openings may be arranged side by side relative to the second direction.

[0011] According to one embodiment of the present invention, a plurality of the openings may be arranged in a zigzag pattern relative to the second direction.

[0012] According to one embodiment of the present invention, in each of the pads, a plurality of openings extend along the first direction, and a plurality of openings are provided in the second direction at predetermined intervals.

[0013] According to one embodiment of the present invention, the width of the end of the pad connected to the wiring may be substantially equal to the width of the other end of the pad opposite to the first end of the pad.

[0014] According to one embodiment of the present invention, the width of one end of the pad connected to the wiring may be greater than the width of the other end of the pad opposite to the one end of the pad.

[0015] An embodiment of the present invention relates to a display device that may include: a display panel defining a display area and a peripheral area adjacent to the display area, and including a plurality of wirings disposed in the peripheral area and a plurality of pads respectively connected to the wirings and defined with openings; an electronic component including a plurality of connection pads electrically connected to the pads; and a filler layer disposed between the display panel and the electronic component, and located in the openings, wherein each of the pads overlaps with the plurality of connection pads, and the openings do not overlap with the connection pads.

[0016] In one embodiment of the present invention, the filling layer may be non-conductive and include a photoinitiator.

[0017] In one embodiment of the present invention, the pad may be in direct contact with the connecting pad.

[0018] An embodiment of the present invention relates to a display device that may include: a display panel defining a display area and a peripheral area adjacent to the display area, and including a plurality of wirings disposed in the peripheral area and a plurality of pads respectively connected to the wirings; an electronic component located on the plurality of pads, and including a plurality of connection pads in contact with the pads, each of the pads including an overlapping area that overlaps with the connection pad and a non-overlapping area that does not overlap with the connection pad, wherein an opening is defined in the non-overlapping area of ​​the pad.

[0019] An embodiment of the present invention relates to a display device that may further include: a filling layer disposed between the display panel and the electronic component, and located between the connecting pads, between the pads, and in the opening.

[0020] Alternatively, the filling layer may be non-conductive and include a photoinitiator.

[0021] In one embodiment of the present invention, each of the pads may overlap with a plurality of the connection pads.

[0022] In one embodiment of the present invention, the electronic component may further include a substrate film, wherein the bonding pads extend along a first direction on one side of the substrate film and are arranged along a second direction intersecting the first direction.

[0023] In one embodiment of the invention, the overlapping and non-overlapping regions defined in each of the pads may be alternately arranged along the second direction.

[0024] In one embodiment of the present invention, the opening may be provided in each of the non-overlapping regions at a predetermined interval in the first direction.

[0025] In one embodiment of the present invention, each of the openings may be provided extending in the first direction in each of the non-overlapping regions.

[0026] (Invention Effects)

[0027] An embodiment of the present invention relates to a display device in which an opening is formed on the pad, thereby improving the problem of reduced bonding reliability caused by the uncured filler layer between the pads of the display panel and the connection pads of the electronic components. Attached Figure Description

[0028] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention.

[0029] Figure 2 This is an exploded perspective view of a display device according to an embodiment of the present invention.

[0030] Figure 3 It is along Figure 2 The sectional view shown is taken along line I-I'.

[0031] Figure 4 This is a plan view of a portion of a display device according to an embodiment of the present invention.

[0032] Figure 5 This is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0033] Figure 6a and Figure 6b It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically the AA region.

[0034] Figure 7 It is along Figure 6b The sectional view shown is taken from section II-II'.

[0035] Figure 8 It is along Figure 6b The sectional view shown is taken from section III-III'.

[0036] Figure 9 It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically the AA region.

[0037] Figure 10 It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically the AA region.

[0038] Figure 11 It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically the AA region.

[0039] (Symbol Explanation)

[0040] DD: Display device; DP: Display panel; CF1: First circuit board; CF2: Second circuit board; BF: Base film; IPD: Connecting pad; BP: Base board; DVL1: First power wiring; DVL2: Second power wiring; SPD: Signal pad; PD1: First power pad; PD2: Second power pad; PD3: Third power pad; PD4: Fourth power pad; PD1-OP: First opening; PD3-OP: Third opening; FL: Filler layer. Detailed Implementation

[0041] This invention can have various modifications and forms. Specific embodiments are illustrated in the figures and described in detail herein. However, this is not intended to limit the invention to the specific disclosed forms, but should be understood to include all modifications, equivalents, and substitutions encompassed within the spirit and technical scope of this invention.

[0042] In this application, terms such as "comprising" or "having" should be understood as referring to the presence of features, figures, steps, operations, constituent elements, components, or combinations thereof described in the specification, and do not preclude the existence or additional possibility of one or more other features, figures, steps, operations, constituent elements, components, or combinations thereof. Furthermore, when a layer, film, region, plate, or other portion is located on other portions, this includes not only the case where it is directly located on other portions, but also the case where other portions exist between them. Conversely, when a layer, film, region, plate, or other portion is located below other portions, this includes not only the case where it is directly located below other portions, but also the case where other portions exist between them.

[0043] In illustrating the figures, similar symbols are used for similar constituent elements. In the figures, for clarity of the invention, the dimensions of the structures are shown enlarged compared to their actual dimensions. Terms such as "first," "second," etc., can be used to describe various constituent elements, but the constituent elements should not be limited to these terms. These terms are used only for the purpose of distinguishing one constituent element from others. For example, without departing from the scope of the invention, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element. Singular expressions include plural expressions unless explicitly stated otherwise in the text.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention. Figure 2 This is an exploded perspective view of a display device according to an embodiment of the present invention.

[0046] Reference Figure 1 and Figure 2 The display device DD can be a device activated by an electrical signal. The display device DD can include various embodiments. For example, the display device DD can be a large electronic device such as a television, monitor, or external advertising board, or it can be used in small to medium-sized electronic devices such as personal computers, laptops, personal digital terminals, car navigation units, game consoles, portable electronic devices, and cameras. Furthermore, these are merely illustrative examples; the display device DD can, of course, be used in other electronic devices without departing from the concept of the invention. In this embodiment, as an example, a smartphone is shown as the display device DD.

[0047] The display device DD can display an image IM on a display surface FS that is parallel to the first direction DR1 and the second direction DR2, respectively, facing the third direction DR3. The image IM may include both moving images and still images. Figure 1The image IM is shown as an example of a clock window and an icon. The display surface FS of the image IM can correspond to the front surface of the display device DD, and can also correspond to the front surface of the window WP. In addition, depending on the structure of the display device DD, the display surface FS can also be provided on the side or the back of the display device DD.

[0048] In this embodiment, the front surface (or upper surface) and back surface (or lower surface) of each component are defined based on the direction of the displayed image IM. The front surface and back surface can be opposite each other on the third direction DR3, and the normal directions of the front surface and back surface can be parallel to the third direction DR3. On the other hand, the directions indicated by the first direction DR1 to the third direction DR3 are relative concepts and can be changed to other directions. In this specification, "when viewed on a plane" can mean the situation when viewed on the third direction DR3.

[0049] One embodiment of the present invention relates to a display device DD that can sense user input applied from the outside. User input includes various forms of external input such as a part of the user's body, light, heat, or pressure. Furthermore, the display device DD can also sense user input applied to the side or back of the display device DD, depending on its structure, and is not limited to any particular embodiment.

[0050] The display device DD may include a window WP, an anti-reflective layer RPP, a display module DM, and a housing HU. In this embodiment, the window WP and the housing HU are combined to form the appearance of the display device DD.

[0051] The window portion (WP) may include an optically transparent insulating material. For example, the window portion (WP) may include glass or plastic. The window portion (WP) may have a multi-layer structure or a single-layer structure. For example, the window portion (WP) may include multiple plastic films bonded together by an adhesive, or a glass substrate and a plastic film bonded together by an adhesive.

[0052] As described above, the front surface FS of the window portion WP defines the front surface of the display device DD. The transmissive area TA can be an optically transparent area. For example, the transmissive area TA can be an area with a visible light transmittance of approximately 90% or more.

[0053] The border region BZA can be a region with relatively low light transmittance compared to the transmittance region TA. The border region BZA defines the shape of the transmittance region TA. The border region BZA can be adjacent to the transmittance region TA and can surround the transmittance region TA.

[0054] The border area BZA can have a predetermined color. The border area BZA can cover the peripheral area NDA of the display module DM, thereby preventing the peripheral area NDA from being identified from the outside. On the other hand, this is a case illustrated by way of example. In the window WP according to an embodiment of the present invention, the border area BZA may also be omitted.

[0055] An anti-reflective layer RPP can be disposed below the window WP. The anti-reflective layer RPP reduces the reflectivity of external light incident from the upper side of the window WP. The anti-reflective layer RPP can be, for example, a polarizing film. In one embodiment of the invention, the anti-reflective layer RPP may be omitted, or it may be included in the display module DM.

[0056] The display module DM can display an image IM and can sense external input. The display module DM includes a front surface IS having a display area DA and a peripheral area NDA. The display area DA can be an area that is activated according to an electrical signal.

[0057] In this embodiment, the display area DA can be the area for displaying the image IM, and also the area for sensing external input. The area TA overlaps at least with the display area DA. For example, the area TA overlaps the entire surface or at least a portion of the display area DA. Thus, the user can identify the image IM through the area TA, or provide external input. However, this is an illustrative case; the area for displaying the image IM and the area for sensing external input within the display area DA can be separate from each other, and the embodiment is not limited to any particular embodiment.

[0058] The peripheral area NDA can be the area covered by the border area BZA. The peripheral area NDA is adjacent to the outer side of the display area DA. The peripheral area NDA can surround the display area DA. The peripheral area NDA can be configured with drive circuitry or drive wiring for driving the display area DA.

[0059] The display module DM includes a display panel DP, an input sensing layer ISL, and a driving unit DC.

[0060] The display panel (DP) can be the component that actually generates the image (IM). Users can externally identify the image (IM) generated by the display panel (DP) through the area (TA).

[0061] The input sensing layer (ISL) senses external input applied from the outside. As described above, the input sensing layer (ISL) can sense external input provided to the window (WP).

[0062] The driving unit DC can be an electronic component electrically connected to the display panel DP and the input sensing layer ISL. The driving unit DC includes a main circuit board MB, a first circuit board CF1, and a second circuit board CF2.

[0063] The first circuit board CF1 is electrically connected to the display panel DP. The first circuit board CF1 can connect the display panel DP and the main circuit board MB. In this embodiment, the first circuit board CF1 is shown as a flexible circuit film.

[0064] The first circuit board CF1 can be connected to the pads of the display panel DP disposed in the peripheral area NDA. The first circuit board CF1 provides electrical signals to the display panel DP for driving the display panel DP. The electrical signals can be generated by the first circuit board CF1 or by the main circuit board MB.

[0065] The second circuit board CF2 is electrically connected to the input sensing layer ISL. The second circuit board CF2 can also electrically connect the input sensing layer ISL to the main circuit board MB. In this embodiment, the second circuit board CF2 is shown as a flexible circuit film. However, this is an illustrative case; the second circuit board CF2 may not be connected to the main circuit board MB, or it may be omitted entirely. For example, if the second circuit board CF2 is omitted, the input sensing layer ISL can be electrically connected to the first circuit board CF1.

[0066] The second circuit board CF2 can be connected to the pads of the input sensing layer ISL disposed in the peripheral region NDA. The second circuit board CF2 provides electrical signals to the input sensing layer ISL for driving the input sensing layer ISL. The electrical signals can be generated by the second circuit board CF2 or by the main circuit board MB.

[0067] The main circuit board MB may include various driving circuits for driving the display module DM or connectors for power supply. The first circuit board CF1 and the second circuit board CF2 may be connected to the main circuit board MB respectively. According to the present invention, the display module DM can be easily controlled by a single main circuit board MB. However, this is an illustrative case; in one embodiment of the display module DM, the display panel DP and the input sensing layer ISL may also be connected to different main circuit boards, and either the first circuit board CF1 or the second circuit board CF2 may not be connected to the main circuit board MB, and the invention is not limited to any particular embodiment.

[0068] The housing HU is integrated with the window WP. The integration of the housing HU and the window WP provides a predetermined internal space. The display module DM can be housed within this internal space.

[0069] The housing HU can comprise a material with relatively high rigidity. For example, the housing HU can comprise glass, plastic, or metal, or can comprise multiple frames and / or plates composed of combinations thereof. The housing HU can stably protect the display device DD housed within its internal space from external impacts.

[0070] In one embodiment of the present invention, the display device DD may also not include the window WP. Furthermore, the display module DM may also not include the input sensing layer ISL.

[0071] Figure 3 It is along Figure 2 The sectional view shown is taken along line I-I'. Figure 3 The diagram shows the display panel DP and the first circuit board CF1, but the remaining components of the display device DD are omitted.

[0072] Reference Figure 3 The display panel DP may include a substrate BP, a circuit layer CCL, a light-emitting element layer EL, and a packaging layer TFL.

[0073] The substrate BP can be a substrate layer forming the circuit layer CCL. The substrate BP can include a single layer or multiple layers of insulating layers. The substrate BP can be at least one of a glass substrate, a plastic substrate, a film, and a laminate of multiple organic and / or inorganic films, and is not limited to any particular embodiment.

[0074] A first region AR1 and a second region AR2 can be sequentially defined along a first direction DR1 on the substrate BP. For example, the first region AR1 and the second region AR2 can be defined on the upper surface of the substrate BP.

[0075] The circuit layer CCL can be disposed on the substrate BP. The circuit layer CCL can have a stacked structure of multiple conductive layers and multiple organic and / or inorganic films. For example, the circuit layer CCL may include multiple transistors, multiple signal wirings, and multiple insulating layers.

[0076] The light-emitting element layer (EL) can be disposed on the circuit layer (CCL). The EL can be electrically connected to the driving elements and signal wiring of the circuit layer (CCL). When the display panel (DP) is an organic light-emitting display panel, the EL can include an organic light-emitting layer. When the display panel (DP) is a quantum dot light-emitting display panel, the EL can include quantum dots or quantum rods, etc.

[0077] The encapsulation layer TFL is disposed on the light-emitting element layer EL, covering the EL. The encapsulation layer TFL protects the light-emitting element layer EL. Depending on the type of display panel DP, the encapsulation layer TFL may be omitted or it may be replaced by an encapsulation substrate.

[0078] The first circuit board CF1 can be bonded to a portion of the circuit layer CCL disposed on the second region AR2 of the substrate BP. The portion of the circuit layer CCL can be, for example, a pad.

[0079] The first circuit board CF1 may include a base film BF and connection pads IPD. The base film BF may be flexible and insulating. The connection pads IPD may be electrically connected to the circuit layer CCL.

[0080] According to one embodiment of the present invention, the first circuit board CF1 can be electrically connected to the circuit layer CCL by ultrasonic bonding or laser bonding. For example, the connection pad IPD included in the first circuit board CF1 and the pad included in the display panel DP can be in direct contact with each other by ultrasonic bonding or laser bonding.

[0081] Figure 4 This is a plan view of a portion of a display device according to an embodiment of the present invention.

[0082] Reference Figure 4 An embodiment of the present invention relates to a display device DD that may include a display panel DP and a first circuit board CF1 bonded to the display panel DP. Figure 4 The image shows the state of the first circuit board CF1 before it is bonded to the display panel DP.

[0083] The display panel DP may include a substrate BP, pixels PX, driving circuit GDC, signal wiring (SL, ETCL, DL, PL, CSL), first power wiring DVL1, second power wiring DVL2, signal pad SPD, and power pads (PD1, PD2, PD3, PD4).

[0084] A first region AR1 and a second region AR2 are defined sequentially along the first direction DR1 of the substrate BP. The first region AR1 may overlap with the entirety of the display region DA and a portion of the surrounding region NDA. The second region AR2 may overlap with another portion of the surrounding region NDA.

[0085] Pixels PX can be configured on the first region AR1. Each pixel PX can display light of a predetermined color. Pixels PX may include, for example, red pixels, green pixels, and blue pixels. In other embodiments of the invention, pixels PX may also include white pixels. In other embodiments of the invention, pixels PX may further include cyan pixels, magenta pixels, and yellow pixels.

[0086] The driving circuit GDC can be configured in the peripheral area NDA. The driving circuit GDC may include a scan driving circuit and a light emission control driving circuit. The scan driving circuit generates multiple scan signals, and the light emission control driving circuit generates light emission control signals.

[0087] The driving circuit GDC may include multiple thin-film transistors formed through the same processes as the pixel driving circuit of the pixel PX, such as through LTPS (Low Temperature Polycrystaline Silicon) or LTPO (Low Temperature Polycrystalline Oxide) processes.

[0088] Signal cabling (SL, DL, CSL, PL, ETCL) can include scan cabling (SL), light control cabling (ETCL), data cabling (DL), power cabling (PL), and control signal cabling (CSL).

[0089] The scan wiring SL can extend along the second direction DR2 and be arranged along the first direction DR1. The light emission control wiring ETCL can extend along the second direction DR2 and be arranged along the first direction DR1. That is, each light emission control wiring ETCL can be arranged side by side with the corresponding scan wiring in the scan wiring SL. The scan wiring SL can receive scan signals from the driving circuit GDC, and the light emission control wiring ETCL can receive light emission control signals from the driving circuit GDC.

[0090] The data routing DL extends along the first direction DR1 and is arranged along the second direction DR2. The data routing DL can provide data signals to the corresponding pixel PX.

[0091] The power supply line PL extends along the first direction DR1 and is arranged along the second direction DR2. The power supply line PL can be electrically connected to the first power supply line DVL1. The power supply line PL can provide a first driving voltage to the corresponding pixel PX.

[0092] The control signal wiring (CSL) can be electrically connected to the drive circuit (GDC). The control signal wiring (CSL) can transmit signals used to drive the drive circuit (GDC).

[0093] The first power supply line DVL1 and the second power supply line DVL2 can respectively provide driving voltages to the pixel PX. For example, the first power supply line DVL1 can receive a first driving voltage, such as the ELVDD voltage, and can provide it to the pixel PX through the power supply line PL. The second power supply line DVL2 can receive a second driving voltage, such as the ELVSS voltage, and can provide it to the second electrode CE of the pixel PX (see reference). Figure 5The level of the second driving voltage can be lower than the level of the first driving voltage.

[0094] Signal pads (SPD) and power pads (PD1, PD2, PD3, PD4) can be configured in the second area AR2.

[0095] Signal pads (SPDs) can be arranged along the second direction DR2. Each signal pad (SPD) can be connected to a portion of a signal route (SL, ETCL, DL, PL, CSL). For example, one portion of the signal pad (SPD) can be connected to a control signal route (CSL), and another portion can be connected to a data route (DL).

[0096] The power pads (PD1, PD2, PD3, PD4) may include a first power pad PD1, a second power pad PD2, a third power pad PD3, and a fourth power pad PD4. The power pads (PD1, PD2, PD3, PD4) may be arranged along the second direction DR2.

[0097] The first power pad PD1 and the second power pad PD2 can be connected to the first power wiring DVL1, and the third power pad PD3 and the fourth power pad PD4 can be connected to the second power wiring DVL2.

[0098] The widths of the first power supply line DVL1 and the second power supply line DVL2 can each be greater than the widths of the control signal line CSL and the data line DL. Therefore, the widths of the power pads (PD1, PD2, PD3, PD4) connected to the first power supply line DVL1 and the second power supply line DVL2 respectively can be greater than the widths of the signal pads SPD connected to the control signal line CSL and the data line DL respectively.

[0099] The specific shapes of the power pads (PD1, PD2, PD3, PD4) will be specified later. Figure 6a , Figure 6b , Figure 9 , Figure 10 as well as Figure 11 Detailed explanation follows.

[0100] The first circuit board CF1 may include a base film BF and a connection pad IPD.

[0101] The bonding pad area IPDA can be defined on the substrate film BF. The bonding pad area IPDA can be defined on the lower surface of the substrate film BF. The bonding pad area IPDA can also be defined at one end of the substrate film BF adjacent to the display panel DP.

[0102] Connection pads (IPDs) can be configured within the connection pad area (IPDA). The connection pads (IPDs) can extend along a first direction (DR1) and be arranged along a second direction (DR2). The width of the connection pads (IPDs) can be smaller than the width of the power pads (PD1, PD2, PD3, PD4). This width can be the width in the direction parallel to the second direction (DR2).

[0103] Therefore, multiple connection pads IPD can be electrically connected to each of the power pads (PD1, PD2, PD3, PD4). Although not shown, multiple connection pads IPD can also be electrically connected to a signal pad that requires low resistance, within the signal pads SPD. A driver chip GC can be mounted on the upper or lower surface of the base film BF. The driver chip GC can supply data signals, etc., to the pixels PX.

[0104] Figure 5 This is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 5 It is to crop the pixel PX (refer to) Figure 4 A section of the area is shown in the cross-sectional view.

[0105] Reference Figure 5 The display panel (DP) may include a substrate (BP), a circuit layer (CCL), a light-emitting element layer (EL), and a packaging layer (TFL). Each pixel (PX) (refer to...) Figure 4 It may include multiple transistors, at least one capacitor, and an OLED light-emitting element layer. The multiple transistors and the at least one capacitor may be included in the circuit layer CCL.

[0106] A buffer layer (BFL) can be disposed on a substrate (BP). The buffer layer (BFL) improves the adhesion between the substrate (BP) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0107] Semiconductor patterns are configured on the buffer layer BFL. The semiconductor patterns may include polycrystalline silicon. However, they are not limited to this; the semiconductor patterns may also include amorphous silicon or metal oxide.

[0108] Semiconductor patterns can be arranged across pixels PX according to specific rules. The semiconductor patterns can have different electrical properties depending on whether they are doped. The semiconductor patterns can include doped and undoped regions. Doped regions can be doped using either N-type or P-type dopant. A P-type transistor includes a doped region doped using a P-type dopant.

[0109] Doped regions have higher conductivity than undoped regions and essentially function as electrodes or signal lines. Undoped regions are essentially equivalent to the active (or channel) regions of a transistor. In other words, a portion of a semiconductor pattern can be the active region of a transistor, another portion can be the source or drain of a transistor, and yet another portion can be a connecting electrode or a connecting signal line.

[0110] like Figure 5 As shown, the source S1, active region A1, and drain D1 of the first transistor T1 are formed by a semiconductor pattern, and the source S2, active region A2, and drain D2 of the second transistor T2 are formed by a semiconductor pattern. The sources S1 and S2 and the drains D1 and D2 extend in cross-section from the active regions A1 and A2 in opposite directions to each other. Figure 5 A portion of the connection signal line SCL, formed by a semiconductor pattern, is shown. Although not shown separately, the connection signal line SCL can be connected to the drain D2 of the second transistor T2 on a plane.

[0111] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 overlaps with and covers the semiconductor pattern of the pixel PX. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the circuit layer CCL, described later, may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-described substances.

[0112] Gates G1 and G2 are disposed on the first insulating layer 10. Gates G1 and G2 may be part of a metal pattern. Gates G1 and G2 overlap with active regions A1 and A2. In the process of doping the semiconductor pattern, gates G1 and G2 act as masks.

[0113] A second insulating layer 20 covering gates G1 and G2 is disposed on the first insulating layer 10. The second insulating layer 20 overlaps with the pixel PX. The second insulating layer 20 can be an inorganic layer and / or an organic layer, and can have a single-layer or multi-layer structure. In this embodiment, the second insulating layer 20 can be a single-layer silicon oxide layer.

[0114] An upper electrode UE can be configured on the second insulating layer 20. The upper electrode UE can overlap with the gate G2 of the second transistor T2. The upper electrode UE can be part of a metal pattern. A portion of the gate G2 and the upper electrode UE overlapping therewith can define a capacitor.

[0115] A third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20. The third insulating layer 30 may be a single layer of silicon oxide. A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 that passes through the first insulating layer 10 to the third insulating layer 30.

[0116] A fourth insulating layer 40, covering the first connecting electrode CNE1, is disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connecting electrode CNE2 may be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 that penetrates the fourth insulating layer 40 and the fifth insulating layer 50.

[0117] A sixth insulating layer 60, covering the second connecting electrode CNE2, is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. A first electrode AE ​​is disposed on the sixth insulating layer 60. The first electrode AE ​​is connected to the second connecting electrode CNE2 through a contact hole CNT-3 penetrating the sixth insulating layer 60. An opening OP is defined on the pixel definition film PDL. The opening OP of the pixel definition film PDL exposes at least a portion of the first electrode AE.

[0118] like Figure 5 As shown, the display area DA may include a light-emitting area PXA and a light-shielding area NPXA adjacent to the light-emitting area PXA. The light-shielding area NPXA may surround the light-emitting area PXA. In this embodiment, the light-emitting area PXA may be defined as a portion of the area corresponding to the first electrode AE ​​exposed through the opening OP.

[0119] A hole control layer (HCL) can be configured together in the light-emitting region (PXA) and the light-blocking region (NPXA). The hole control layer (HCL) includes a hole transport layer and may also include a hole injection layer. A light-emitting layer (EML) is configured on the hole control layer (HCL). The light-emitting layer (EML) can be configured in the region corresponding to the opening (OP). That is, the light-emitting layer (EML) can be formed separately in each pixel (PX).

[0120] An electronic control layer (ECL) is disposed on the light-emitting layer (EML). The ECL may include an electron transport layer and may also include an electron injection layer. A hole control layer (HCL) and the ECL may be co-formed in multiple pixels (PX) using an open mask. A second electrode (CE) is disposed on the ECL. The second electrode (CE) has a uniform shape and is co-located in the pixel (PX).

[0121] An encapsulation layer TFL is disposed on the second electrode CE. A capping layer covering the second electrode CE may also be disposed between the second electrode CE and the encapsulation layer TFL.

[0122] The encapsulation layer TFL may include a first inorganic layer, an organic layer, and a second inorganic layer stacked sequentially. However, it is not limited to this; the encapsulation layer TFL may also include multiple inorganic and organic layers.

[0123] Figure 6a and Figure 6b It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically area AA. Figure 6a The image shows the state of the first circuit board CF1 before it is bonded to the display panel DP. Figure 6b The diagram shows the state in which the circuit board CF1 is bonded to the display panel DP.

[0124] Reference Figure 4 , Figure 6a as well as Figure 6b The first power pad PD1 and the third power pad PD3 can each overlap with at least two connection pads IPD. In this case, when viewed in a plane, the first power pad PD1 and the third power pad PD3 can include an overlapping region OA that overlaps with the connection pads IPD and a non-overlapping region NOA that does not overlap with the connection pads IPD. The overlapping region OA and the non-overlapping region NOA defined by the first power pad PD1 and the third power pad PD3 can be alternately set along the second direction DR2.

[0125] The width of the end of the first power pad PD1 and the third power pad PD3 that is connected to the first power trace DVL1 and the second power trace DVL2 can be substantially equal to the width of the other end opposite to the end of the first power pad PD1 and the third power pad PD3.

[0126] A first opening PD1-OP is defined on the first power pad PD1, which is connected to the first power trace DVL1, and a third opening PD3-OP can be defined on the third power pad PD3, which is connected to the second power trace DVL2. Although not shown, a second opening can be defined on the second power pad PD2, and a fourth opening can be defined on the fourth power pad PD4.

[0127] The description of the second power pad PD2 is essentially the same as that of the first power pad PD1, and the description of the fourth power pad PD4 is essentially the same as that of the third power pad PD3, therefore it is omitted.

[0128] On the first power pad PD1, a first opening PD1-OP can be provided at a certain interval on the first direction DR1 and the second direction DR2. On the third power pad PD3, a third opening PD3-OP can be provided at a certain interval on the first direction DR1 and the second direction DR2.

[0129] Relative to the second direction DR2, the first opening PD1-OP and the third opening PD3-OP can be arranged side by side.

[0130] When viewed on a plane, the first opening PD1-OP and the third opening PD3-OP do not overlap with the connection pad IPD and are defined in the non-overlapping area NOA of the first power pad PD1 and the third power pad PD3 between the connection pads IPD.

[0131] A first opening PD1-OP and a third opening PD3-OP can be set at certain intervals along the first direction DR1 in the non-overlapping region NOA.

[0132] Figure 7 It is along Figure 6b The sectional view shown is taken at point II-II'. Figure 8 It is along Figure 6b The sectional view shown is taken from section III-III'.

[0133] Reference Figure 7 and Figure 8 An embodiment of the present invention relates to a display device DD, which further includes a filler layer FL disposed between the display panel DP and the first circuit board CF1.

[0134] The filler layer FL can be located between the connection pads IPD, between the signal pads SPD, between the first power pad PD1 and the third power pad PD3, and between the first opening PD1-OP and the third opening PD3-OP after the first circuit board CF1 is bonded to the display panel DP. Although not shown, the filler layer FL is also located between the second power pad DP2 and the fourth power pad DP4, and between the second and fourth openings. The filler layer FL can also be referred to as underfill resin.

[0135] The filler layer FL can be a non-conductive insulating resin. In this embodiment, the filler layer FL can be an adhesive resin including a photoinitiator. The curing properties of the filler layer FL can vary depending on external light. Here, the external light can be, for example, UV light.

[0136] The filler layer FL fills the space between the display panel DP and the first circuit board CF1, thereby improving the bonding reliability between the display panel DP and the first circuit board CF1.

[0137] In particular, in one embodiment of the present invention, since openings are formed in the power pads (PD1, PD2, PD3, PD4), the filler layer FL in the area overlapping with the power pads (PD1, PD2, PD3, PD4) can be easily cured. To enable photocuring of the filler layer FL, when external light is irradiated from below the display panel DP, the external light can easily reach the filler layer FL in the area overlapping with the power pads (PD1, PD2, PD3, PD4) through the openings. Therefore, even when multiple connection pads IPD are electrically connected to each power pad (PD1, PD2, PD3, PD4), the bonding reliability between the display panel DP and the first circuit board CF1 can be improved.

[0138] Figure 9 It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically area AA. Figure 9 In the description, and used in Figure 6a and Figure 6b Symbols already explained are omitted, and explanations that are repeated with them are omitted.

[0139] Reference Figure 4 and Figure 9 On the first power pad PD1, a first opening PD1-OP can be provided at a certain interval on the first direction DR1 and the second direction DR2. On the third power pad PD3, a third opening PD3-OP can be provided at a certain interval on the first direction DR1 and the second direction DR2.

[0140] The first opening PD1-OP and the third opening PD3-OP can be arranged in a sawtooth pattern relative to the second direction DR2. In this case, the filling layer FL in the first opening PD1-OP and the third opening PD3-OP is arranged in a sawtooth pattern relative to the second direction DR2 and then cured, thereby further improving the bonding reliability between the display panel DP and the first circuit board CF1.

[0141] Figure 10 It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically area AA. Figure 10 In the description, and used in Figure 6a and Figure 6b Symbols already explained are omitted, and explanations that are repeated with them are omitted.

[0142] In the first power pad PD1, a first opening PD1-OP can extend in the first direction DR1 and can be provided in the second direction DR2 at a certain interval. In the third power pad PD3, a third opening PD3-OP can extend in the first direction DR1 and can be provided in the second direction DR2 at a certain interval.

[0143] When viewed on a plane, the first opening PD1-OP is located at each of the connection pads IPD corresponding to the first power pad PD1, and the third opening PD3-OP is located at each of the connection pads IPD corresponding to the third power pad PD3.

[0144] As the first opening PD1-OP and the third opening PD3-OP extend in the first direction DR1, the area of ​​the filler layer FL in the region overlapping with the first power pad PD1 and the third power pad PD3 can be widened. This further improves the bonding reliability between the display panel DP and the first circuit board CF1.

[0145] Figure 11 It is shown in magnification Figure 4 The diagram shows a plan view of a portion of a display device according to an embodiment of the present invention, specifically area AA. Figure 11 In the description, and used in Figure 6a and Figure 6b Symbols already explained are omitted, and explanations that are repeated with them are omitted.

[0146] The width of the end of the first power pad PD1 and the third power pad PD3 that connects to the first power trace DVL1 and the second power trace DVL2 may differ from the width of the other end opposite to the end of the first power pad PD1 and the third power pad PD3. Figure 11 The diagram shows a case where the width of one end of the first power pad PD1 and the third power pad PD3 is greater than the width of the other end of the first power pad PD1 and the third power pad PD3.

[0147] Figure 11 The first power pad PD1 and the third power pad PD3 shown can be Figure 10 The shape shown is formed by removing the portion corresponding to the first opening PD1-OP and the third opening PD3-OP at the other end of the first power pad PD1 and the third power pad PD3.

[0148] In this case, as the filler layer FL is located between the first power pad PD1 and the third power pad PD3, the area at the other end is removed, which can further improve the bonding reliability between the display panel DP and the first circuit board CF1.

[0149] The above description is based on preferred embodiments of the present invention. However, those skilled in the art or those with common knowledge in related technical fields should understand that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the invention as described in the claims.

[0150] Therefore, the technical scope of this invention should not be limited to the contents described in the detailed specification, but should be determined only by the claims.

Claims

1. A display device, comprising: A display panel defines a display area and a peripheral area adjacent to the display area, and includes a plurality of wirings disposed in the peripheral area and a plurality of pads respectively connected to the wirings, wherein at least one of the plurality of pads includes one or more openings; Electronic components, including a plurality of connection pads in contact with the pads; and A filler layer is disposed between the display panel and the electronic component, and is located between the connection pads, between the pads, and within the opening. Each of the pads overlaps with at least two of the connecting pads, and when viewed in a plane, the opening is located between the connecting pads. The display panel includes a substrate, the plurality of pads are disposed on the substrate, the opening exposes the substrate, and each pad is in direct contact with at least two of the connecting pads. The filling layer is non-conductive and includes a photoinitiator.

2. The display device according to claim 1, wherein, The electronic component also includes a base film, and a plurality of the bonding pads extend along a first direction and are arranged along a second direction intersecting the first direction on one side of the base film. In each of the bonding pads, a plurality of openings are provided at predetermined intervals in the first direction and the second direction.

3. The display device according to claim 2, wherein, A plurality of the openings are arranged side by side relative to the second direction.

4. The display device according to claim 3, wherein, The plurality of openings are arranged in a zigzag pattern relative to the second direction.

5. The display device according to claim 2, wherein, In each of the pads, a plurality of openings extend along the first direction and are provided at predetermined intervals in the second direction.

6. The display device according to claim 5, wherein, The width of the end of the pad that is connected to the wiring is equal to the width of the other end of the pad that is opposite to that end.

7. The display device according to claim 5, wherein, The width of one end of the pad connected to the wiring is greater than the width of the other end of the pad opposite to that end.

8. A display device, comprising: The display panel defines a display area and a peripheral area adjacent to the display area, and includes a plurality of wirings configured in the peripheral area and a plurality of pads respectively connected to the wirings; An electronic component is located on a plurality of said pads and includes a plurality of connection pads in contact with said pads; as well as A filler layer is disposed between the display panel and the electronic components. Each of the pads includes an overlapping region that overlaps with the connecting pad and a non-overlapping region that does not overlap with the connecting pad. An opening is defined in the non-overlapping area of ​​the pads, and each pad overlaps with a plurality of the connecting pads. The filler layer is located between the connection pads, between the pads, and in the opening, and The display panel includes a substrate, the plurality of pads are disposed on the substrate, the opening exposes the substrate, and each pad is in direct contact with the plurality of connecting pads. The filling layer is non-conductive and includes a photoinitiator.

9. The display device according to claim 8, wherein, The electronic component also includes a base film, wherein a plurality of the bonding pads extend along a first direction and are arranged along a second direction intersecting the first direction on one side of the base film, and the overlapping regions and non-overlapping regions defined in each of the pads are alternately arranged along the second direction.

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