Integrated circuit crystal and method for manufacturing the same

Abstract

An integrated circuit crystal and a manufacturing method thereof, wherein the integrated circuit crystal comprises a FinFET transistor. The FinFET transistor comprises an anti-punchthrough region below a channel region. In the process of forming a source region and a drain region, unwanted dopants are removed from the anti-punchthrough region. When forming source and drain recesses, a dielectric material layer is deposited in the recesses. An annealing process is then performed. In the annealing process, unwanted dopants diffuse from the anti-punchthrough region into the dielectric material layer. Then, the dielectric material layer is removed. Then, a source region and a drain region are formed by depositing a semiconductor material in the recesses.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits. More particularly, the present disclosure relates to integrated circuits including FinFET transistors. Background Art

[0002] FinFET transistors typically include a doped anti-punch region to reduce unwanted short channel effects. However, some unwanted dopants may migrate from the anti-punch region into the channel region. These unwanted dopants in the channel region can adversely affect the performance of the transistor. Therefore, although the anti-punch region is beneficial to the operation of the FinFET transistor, the conventional anti-punch region also has some disadvantages to the FinFET performance. Summary of the invention

[0003] One aspect of the present disclosure is to provide a method for manufacturing an integrated circuit die, the method comprising the following steps. A semiconductor fin including a channel region and an anti-punch-through region is formed. A recess is formed in the semiconductor fin, the recess having a sidewall adjacent to the anti-punch-through region. A dielectric material layer is deposited on the sidewall of the recess. An annealing process is performed while the dielectric material layer is on the sidewall of the recess. The dielectric material layer is removed from the sidewall of the recess. A transistor source region is formed in the semiconductor fin by depositing a semiconductor material in the recess.

[0004] One aspect of the present disclosure is to provide a method for manufacturing an integrated circuit die, the method comprising the following steps. A semiconductor fin including a channel region and an anti-punch-through region is formed, wherein the anti-punch-through region includes fluorine and boron. A recess is formed in the semiconductor fin by etching the semiconductor fin. A dielectric material layer is deposited in the recess adjacent to the anti-punch-through region. A portion of the fluorine is removed from the anti-punch-through region and an annealing process is performed on the dielectric material layer. The dielectric material layer is removed from the recess. A transistor source region is formed in the recess by depositing a semiconductor material in the recess.

[0005] One aspect of the present disclosure is to provide an integrated circuit die, which includes a semiconductor substrate, a semiconductor fin, a channel region, a gate dielectric layer, a gate electrode, an anti-punchthrough region and a source region. The semiconductor fin protrudes from the semiconductor substrate. The channel region is located in the semiconductor fin. The gate dielectric layer is located on the semiconductor fin above the channel region. The gate electrode is located on the gate dielectric layer. The anti-punchthrough region is located in the semiconductor fin, wherein the anti-punchthrough region is doped with a first dopant type. The source region is located in the semiconductor fin. The source region is doped with a second dopant type opposite to the first dopant type, wherein the interface between the source region and the anti-punchthrough region has a peak-to-valley roughness of less than 1 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 17illustrates a cross-sectional view of an integrated circuit die at successive stages of fabrication according to one embodiment;

[0007] Fig.18 is a perspective view of an integrated circuit die according to one embodiment;

[0008] Fig.19 A method for manufacturing an integrated circuit die according to an embodiment is provided.

[0009]

Explanation of symbols

[0010] 100: Integrated circuit chips

[0011] 102:Semiconductor substrate

[0012] 104:P Well Area

[0013] 106: N Well Area

[0014] 108: Channel area

[0015] 110: Trench isolation area

[0016] 112: N Well Area

[0017] 114: Anti-penetration area

[0018] 116: Channel area

[0019] 118: Gate dielectric layer

[0020] 120: Gate electrode

[0021] 122: Gate dielectric layer

[0022] 124: Gate electrode

[0023] 126: Hard Mask

[0024] 128: Hard mask layer

[0025] 130: Spacer layer

[0026] 132: Spacer layer

[0027] 134: Spacer layer

[0028] 136: Sidewall spacer

[0029] 137: Gate Stack

[0030] 138:Mask

[0031] 140: Recess

[0032] 141: Side wall

[0033] 142: Dielectric material layer

[0034] 144: Source region

[0035] 146: Drain region

[0036] 148: Dielectric material layer

[0037] 150: Dielectric layer

[0038] 152: Dielectric layer

[0039] 153: Gate Stack

[0040] 154: Source and drain recesses

[0041] 155: Side wall

[0042] 158: Dielectric material layer

[0043] 160: Source region

[0044] 162: Drain region

[0045] 164: N-channel FinFET transistor

[0046] 166: P-channel FinFET transistor

[0047] 172:Semiconductor fins

[0048] 1900: Method for manufacturing integrated circuit die

[0049] 1902: Steps

[0050] 1904: Steps

[0051] 1906: Steps

[0052] 1908: Steps

[0053] 1910: Steps

[0054] 1912: Steps DETAILED DESCRIPTION

[0055] In the following description, many thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example for various embodiments. Those skilled in the art will recognize that in accordance with the present disclosure, in many cases, other dimensions and materials may be used without departing from the scope of the present disclosure.

[0056] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter described. Specific examples of components and arrangements are described below to simplify this description. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0057] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein likewise interpreted accordingly.

[0058] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced without such specific details. In other examples, well-known structures associated with electronic components and manufacturing techniques have been described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0059] Unless the context requires otherwise, throughout the following description and claims, the word "comprise" and variations such as, "comprises" and "comprising" are to be interpreted in an open, inclusive sense, that is, "including, but not limited to."

[0060] The use of ordinal numbers such as first, second, and third does not necessarily imply a sequential ranking meaning but may simply distinguish multiple instances of an action or structure.

[0061] Any reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0062] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used in its sense, including "and / or," unless the content clearly dictates otherwise.

[0063] Figure 1 FIG. 1 is a cross-sectional view of a portion of an integrated circuit die 100 according to one embodiment. The integrated circuit die 100 is in an intermediate manufacturing stage. When the manufacturing of the integrated circuit die 100 is completed, the integrated circuit die 100 will include an array of N-type and P-type FinFET transistors.

[0064] The integrated circuit die 100 includes a bulk semiconductor substrate 102. The bulk semiconductor substrate 102 may include single crystal silicon. The bulk semiconductor substrate 102 may include semiconductor materials other than single crystal silicon without departing from the scope of the present disclosure.

[0065] In one embodiment, the integrated circuit die 100 includes a silicon on insulator (SOI) substrate. In this case, a dielectric material layer (not shown) such as silicon dioxide is positioned below the semiconductor substrate 102. A semiconductor material layer is positioned below the dielectric material layer. This SOI configuration is utilized to reduce parasitic capacitance and short channel effects in transistors. Thus, although not explicitly shown in the figures, the integrated circuit die 100 may utilize a SOI substrate.

[0066] The integrated circuit die 100 includes a P-well region 104. The P-well region 104 is used for the formation of an N-channel transistor. Although the figures illustrate the formation of only a single N-channel transistor at the P-well region 104, those skilled in the art will recognize that the integrated circuit die 100 may include a plurality of N-channel transistors formed together with the P-well region 104 according to the present disclosure.

[0067] The P-well region 104 includes a P-type dopant. In an example where the semiconductor substrate 102 is single crystal silicon, the P-type dopant atoms may include boron atoms. The dopant concentration of the P-well region 104 is between 1E15 / cm^3 and 1E17 / cm^3. Without departing from the scope of the present disclosure, the P-well region 104 may include a dopant concentration and dopant type different from the dopant concentration and type described herein.

[0068] In one embodiment, the P-well region 104 is part of the semiconductor substrate 102. In the example where the semiconductor substrate 102 comprises single crystal silicon, the P-well region 104 also comprises single crystal silicon doped with P-type dopant atoms. The P-well region 104 comprises the same semiconductor material as the semiconductor substrate 102, with dopant atoms added thereto.

[0069] The integrated circuit die 100 includes an N-well region 112. The N-well region 112 is used for the formation of a P-channel transistor. Although the figures illustrate the formation of only a single P-channel transistor at the N-well region 106, those skilled in the art will recognize that, in practice, the integrated circuit die 100 may include a large number of P-channel transistors formed together with the N-well region 112 according to the present disclosure.

[0070] The N-well region 112 includes N-type dopant atoms. In the example where the semiconductor substrate 102 is single crystal silicon, the N-type dopant atoms may include phosphorus atoms. The dopant concentration of the N-well region 112 is between 1E15 / cm^3 and 1E17 / cm^3. Without departing from the scope of the present disclosure, the N-well region 112 may include a dopant concentration and a dopant type different from the dopant concentration and type described herein.

[0071] In one embodiment, the N-well region 112 is part of the semiconductor substrate 102. In the example where the semiconductor substrate 102 includes single crystal silicon, the N-well region 112 also includes single crystal silicon doped with N-type dopant atoms. The N-well region 112 includes the same semiconductor material as the semiconductor substrate 102, with dopant atoms added thereto.

[0072] The semiconductor substrate 102 is doped with P-type dopant atoms. For example, the semiconductor substrate 102 may be doped with P-type dopant atoms in situ during the growth of the semiconductor substrate 102. In this case, the P-well region 104 may include all of the semiconductor substrate 102 down to the dielectric layer of the SOI configuration. The N-well region 112 may be formed during a separate doping process in which N-type dopant ions are implanted at a selected depth in the semiconductor substrate 102 at a selected concentration.

[0073] The integrated circuit die 100 includes an anti-punchthrough region 106 formed above or in the P-well region 104. The anti-punchthrough region 106 helps reduce the drain-induced barrier lowering (DIBL) effect. As the channel length of the FinFET transistor decreases, the DIBL increases. The DIBL can cause a short circuit between the source and drain of the FinFET transistor. The presence of the anti-punchthrough region 106 helps reduce the DIBL and the corresponding short circuit between the source and drain of the FinFET transistor.

[0074] The anti-punch-through region 106 is a P-type anti-punch-through region for reducing punch-through in an N-channel transistor. The P-type anti-punch-through region 106 may be formed by doping a selected region with a P-type dopant including boron (B) and / or boron fluorine (BF2). The P-type dopant may be implanted during an ion implantation process at a power range from about 3 keV to about 7 keV. Alternatively, the P-type dopant may be implanted in situ during epitaxial growth of a region of the semiconductor substrate 102 corresponding to the anti-punch-through region 106. Other types of dopants and other doping processes may be utilized to form the anti-punch-through region 106 without departing from the scope of the present disclosure.

[0075] In one embodiment, a barrier layer may be formed on the anti-punch-through region 106 to inhibit the anti-punch-through region 106 from diffusing into a channel region 108. The barrier layer may include silicon carbide or other suitable layers.

[0076] The integrated circuit die 100 includes an anti-punch-through region 114 formed above or in the N-well region 112. The anti-punch-through region 114 helps reduce the drain-induced barrier lowering effect, as previously described.

[0077] The anti-punchthrough region 114 is an N-type anti-punchthrough region for reducing DIBL in a P-channel transistor. The N-type anti-punchthrough region 114 may be formed by doping a selected region with an N-type dopant including arsenic (As), phosphorus (P), or antimony (Sb). The doping process may also result in the presence of hydrogen H in the anti-punchthrough region 114. The N-type dopant may be implanted during an ion implantation process at a power range from about 3 keV to about 7 keV. Alternatively, the N-type dopant may be implanted in-situ during epitaxial growth of a region of the semiconductor substrate 102 corresponding to the anti-punchthrough region 114. Other types of dopants and other dopant processes may be utilized to form the anti-punchthrough region 114 without departing from the scope of the present disclosure.

[0078] In one embodiment, a barrier layer may be formed on the anti-punch-through region 114 to inhibit the anti-punch-through region 114 from diffusing into a channel region 116. The barrier layer may include silicon carbide or other suitable materials.

[0079] The integrated circuit die 100 includes a channel region 108. The channel region 108 includes a single crystal silicon semiconductor material. The single crystal silicon semiconductor material may include single crystal silicon. Alternatively, the channel region 108 may include a single crystal silicon semiconductor material other than silicon without departing from the scope of the present disclosure. In addition, the channel region 108 may include a single crystal silicon semiconductor material different from that of the anti-punch-through region 106. The channel region 108 will correspond to the channel region of an N-channel transistor formed together with the P-well region 104, as will be described in more detail below.

[0080] The channel region 108 may be formed via epitaxial growth after the formation of the anti-punchthrough region 106. Alternatively, the channel region may be formed in the same epitaxial growth process as the anti-punchthrough region 106, but without the dopants of the anti-punchthrough region 106.

[0081] The integrated circuit die 100 includes a channel region 116. The channel region 116 includes a single crystal silicon semiconductor material. The single crystal silicon semiconductor material may include single crystal silicon. Alternatively, the channel region 116 may include a single crystal silicon semiconductor material other than silicon without departing from the scope of the present disclosure. In addition, the channel region 116 may include a single crystal silicon semiconductor material different from that of the anti-punch-through region 114. The channel region 116 will correspond to the channel region of a P-channel transistor formed together with the N-well region 112.

[0082] The channel region 116 may be formed via epitaxial growth after the formation of the anti-punchthrough region 114. Alternatively, the channel region may be formed in the same epitaxial growth process as the anti-punchthrough region 114, but without the dopants of the anti-punchthrough region 114.

[0083] The integrated circuit die 100 includes a trench isolation region 110. The trench isolation region 110 electrically isolates the N-well region 112 from the P-well region 104. Additionally or alternatively, the trench isolation 110 may separate the N-channel transistor region from the P-channel transistor region. The trench isolation region 110 may extend to a depth below the N-well 112. In one embodiment, the trench isolation region 110 may extend all the way to an insulator layer of a silicon-on-insulator substrate. The trench isolation region 110 may include silicon dioxide. The trench isolation region 110 may include other materials, shapes, and sizes without departing from the scope of the present disclosure.

[0084] The integrated circuit die 100 includes a gate dielectric layer 118 positioned on the channel region 108. The gate dielectric layer 118 may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-K dielectric material), or a combination thereof. High-K dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, and hafnium zirconium oxide. Other suitable dielectric materials for the gate dielectric layer 118 may be utilized without departing from the scope of the present disclosure.

[0085] The integrated circuit die 100 includes a gate electrode 120. The gate electrode 120 may include polysilicon or metal. The metal used for the gate electrode 120 may include tantalum nitride, nickel silicon, cobalt silicon, molybdenum, copper, tungsten, aluminum oxide, cobalt, zirconium, platinum or other suitable materials. Other materials may be used for the gate electrode 120 without departing from the scope of the present disclosure.

[0086] The integrated circuit die 100 includes a hard mask layer 126 positioned on the gate electrode 120. The hard mask layer 126 may include silicon oxide, silicon nitride, or silicon oxynitride. Other materials may be used for the hard mask layer 126 without departing from the scope of the present disclosure. The hard mask layer 126 is used to pattern the gate electrode 120 during processing steps, resulting in Figure 1 An integrated circuit die 100 is shown in FIG.

[0087] The integrated circuit die 100 includes a gate dielectric layer 122 positioned on the channel region 116. The gate dielectric layer 122 may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-K dielectric material), or a combination thereof. High-K dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, and hafnium zirconium oxide. Other suitable dielectric materials for the gate dielectric layer 122 may be utilized without departing from the scope of the present disclosure.

[0088] The integrated circuit die 100 includes a gate electrode 124. The gate electrode 124 may include polysilicon or metal. The metal used for the gate electrode 124 may include tantalum nitride, nickel silicon, cobalt silicon, molybdenum, copper, tungsten, aluminum oxide, cobalt, zirconium, platinum or other suitable materials. Other materials may be used for the gate electrode 124 without departing from the scope of the present disclosure.

[0089] The integrated circuit die 100 includes a hard mask layer 128 positioned on the gate electrode 124. The hard mask layer 128 may include silicon oxide, silicon nitride, or silicon oxynitride. Other materials may be used for the hard mask layer 128 without departing from the scope of the present disclosure. The hard mask layer 128 is used to pattern the gate electrode 124 during processing steps, resulting in Figure 1 An integrated circuit die 100 is shown in FIG.

[0090] The integrated circuit die includes spacer layers 130, 132, and 134. The spacer layers 130, 132, and 134 are dielectric layers used to form sidewall spacers for the gate electrodes 120, 124, as described in more detail below. The spacer layers 130, 132, and 134 may include silicon oxide, silicon nitride, and silicon oxynitride. These spacer layers may include more than three or less than three layers and may include other materials without departing from the scope of the present disclosure.

[0091] Although in Figure 1 Although not obvious in the figure, the channel regions 108, 116 and the anti-punch-through regions 106, 114 may be formed in semiconductor fins protruding from the semiconductor substrate 102. Fig.18 In the perspective view, the semiconductor fin is more obvious.

[0092] Figure 2 FIG. 1 is a cross-section of an integrated circuit die 100 at an intermediate processing stage according to one embodiment. Figure 2 1 , a mask 138 is formed over the top spacer layer 134 over the portion of the integrated circuit die 100 corresponding to the P-channel FinFET transistor. The mask 138 may be formed using conventional photolithography techniques, which include depositing a photoresist layer, exposing the photoresist to light in the presence of a photolithography mask, and removing the unhardened portions of the photoresist. Other suitable processes and materials may be used to form the mask 138 without departing from the scope of the present disclosure.

[0093] A sidewall spacer 136 is formed on the sidewall of the gate electrode 120. The sidewall spacer is formed by etching the exposed portions of the spacers 130, 132, and 134. The etching process completely removes the spacers 130, 132, and 134 at the exposed locations where the spacers 130, 132, and 134 are thinnest in the vertical direction. The spacers 130, 132, and 134 are not etched immediately under the mask 138.

[0094] The sidewall spacers 136 are formed by using an anisotropic etching process. The anisotropic etching process selectively etches in a downward direction. As a result, the spacers are not significantly etched from the sidewalls of the gate electrode because the spacers 130, 132, and 134 are thicker vertically along the sidewalls of the gate electrode 120. Therefore, after the etching process, the sidewall spacers 136 remain as shown in FIG. Figure 2 as shown in .

[0095] A gate stack 137 includes a gate dielectric 118, a gate electrode 120, a hard mask 126, and a sidewall spacer 136. The gate stack 137 encloses a semiconductor fin, such as Fig.18 Shown in more detail.

[0096] Figure 3 FIG. 1 is a cross-section of an integrated circuit die 100 at an intermediate processing stage according to one embodiment. Figure 3 In the embodiment of the present invention, source and drain recesses 140 are formed in the semiconductor material in the P-well region 104, the anti-punch-through region 106, and the channel region 108. As will be described in more detail below, the source and drain recesses 140 will be used to form the source and drain regions of the N-channel FinFET transistor.

[0097] The etching process used to form the source and drain recesses 140 selectively etches the semiconductor material associated with the various semiconductor regions 104, 106, and 108 with respect to the trench isolation region 110, the sidewall spacers 136, the hard mask 126, and the mask 138. In other words, the etching process etches the semiconductor material associated with the channel region 108, the anti-punch-through region 106, and the P-well region 104 at a significantly higher rate than the material of the sidewall spacers 136, the hard mask 126, and the mask 138. The etching process may include wet etching or dry etching. Therefore, the chemistry of the etchant selectively etches the semiconductor material of the various semiconductor regions 104, 106, and 108.

[0098] In one embodiment, the etching process for forming the source and drain recesses 140 is an anisotropic etch. The anisotropic etch etches at substantially the same rate in all directions. Therefore, the bottom of the recess 140 will have a semicircular shape. Alternatively, the etching process for forming the source and drain recesses 140 may include a selective etch that etches at a significantly higher rate in the downward direction than in other directions. In this case, the recess 140 will have substantially vertical walls and a substantially flat bottom. The etching process for forming the source and drain recesses may include one or more of wet etching, dry etching, or ion beam etching. Those skilled in the art will recognize that, in accordance with the present disclosure, other etching processes may be utilized without departing from the scope of the present disclosure.

[0099] In one embodiment, the recess 140 does not extend below the anti-punch-through region 106. In this case, the anti-punch-through region 106 completely separates the recess 140 from the P-well region 104.

[0100] Figure 4 FIG. 1 is a cross-section of an integrated circuit die 100 at an intermediate processing stage according to one embodiment. Figure 4, mask 138 has been removed and a dielectric material layer 142 is deposited on the exposed surfaces of integrated circuit die 100, including the exposed walls 141 of source and drain recesses 140. As will be described in more detail below, dielectric material layer 142 will help improve the performance and characteristics of N-channel transistors associated with P-well region 104.

[0101] In one embodiment, the dielectric material layer 142 includes silicon dioxide. The dielectric material layer 142 has a thickness between 3 nm and 30 nm. The dielectric material layer 142 may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Other suitable materials, thicknesses, and deposition processes may be used for the dielectric material layer 142 without departing from the scope of the present disclosure.

[0102] Figure 5 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Figure 5 FIG. 1 is an enlarged view of a portion of the integrated circuit die 100 including a source / drain recess 140 . A dielectric material layer 142 is positioned on a sidewall 141 of the recess 140 and the anti-punch-through region 106 .

[0103] As previously mentioned Figure 1 As described above, the anti-punchthrough region 106 is formed by implanting or diffusing dopants. The doping process may include implanting boron and boron fluorine into the anti-punchthrough region 106. After or during the implantation, some of the boron and fluorine atoms are separated. As a result, free fluorine ions (F-) and boron ions (B+) exist in the anti-punchthrough region 106.

[0104] While the anti-punch-through region 106 performs a useful function in suppressing the DIBL effect and the attendant short circuit between the source and drain, the presence of free fluorine ions may also have negative effects. For example, some of the free fluorine ions may gradually diffuse into the channel region 108. The diffusion of fluorine ions into the channel region 108 may cause significant problems with the functionality of the N-channel transistor. As the concentration of fluorine ions in the channel region 108 increases, the conductivity of the channel region 108 decreases. If the concentration of fluorine ions in the channel region 108 is too high, it is possible that the N-channel transistor will not conduct enough current for proper function during channel inversion. As will be described in more detail below, the deposition of the dielectric material layer 142 may assist in reducing the concentration of fluorine atoms in the anti-punch-through region 106, thereby reducing the number of fluorine ions that may diffuse into the channel region 108.

[0105] Figure 6 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Figure 6 The diagram of the integrated circuit die 100 is shown in FIG. Figure 5The same enlarged portion is shown in Figure 2. However, Figure 6 The integrated circuit die 100 is shown after an annealing process has been performed.

[0106] During the annealing process, some of the fluorine ions migrate from the anti-punchthrough region 106 into the dielectric material layer 142. In the example where the dielectric material layer 142 includes silicon oxide, some of these fluorine ions bond with silicon atoms in the dielectric material layer 142 to form silicon fluorine (SiF). As a result, the concentration of fluorine in the anti-punchthrough region 106 is reduced. Correspondingly, the concentration of fluorine in the dielectric material layer 142 is increased.

[0107] The annealing process may include a rapid thermal annealing process. The rapid thermal annealing process may include heating the integrated circuit die 100 to a high temperature between 700° C. and 1200° C. The integrated circuit die 100 is subjected to the high temperature for a duration between 5 seconds and 20 seconds. The annealing process may include other temperatures and durations without departing from the scope of the present disclosure. For example, in some cases, the annealing process may last for several minutes. The result of the annealing process is that the fluorine ions diffuse into the dielectric material layer 142.

[0108] Figure 7 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Figure 7 The diagram of the integrated circuit die 100 is shown in FIG. Figure 6 The same enlarged portion is shown in Figure 7 , the dielectric material layer 142 has been removed.

[0109] The dielectric material layer 142 can be removed by an etching process. The etching process can include wet etching or dry etching. The etching process utilizes an etchant having a chemistry that selectively etches the dielectric material layer 142 with respect to the semiconductor material of the channel region 108, the anti-punch-through region 106, and the P-well region 104. The etching process can include an anisotropic etching process that etches the dielectric material layer 142 at a substantially similar rate in all directions. The etching process can include a timed etching. The duration of the etching is selected to be sufficient to remove the entire dielectric material layer 142. The duration of the etching is selected to be short enough so that the semiconductor material of the channel region 108, the anti-punch-through region 106, and the P-well region 104 is not etched to a significant extent. For example, the etching process can remove and Therefore, after the etching process of removing the dielectric material layer 142, the width of the recess 140 is not significantly increased.

[0110] When the dielectric material layer 142 is removed, all fluorine atoms that migrate into the dielectric material layer 142 are also removed. Therefore, as the dielectric material layer 142 is removed, a large amount of fluorine atoms are removed. In one example, the concentration of fluorine atoms in the anti-punch-through region 106 before depositing the dielectric material layer 142 is between 1E4 / cm^3 and 1E5 / cm^3. The concentration of fluorine atoms in the anti-punch-through region 106 after removing the dielectric material layer 142 is between 1E2 / cm^3 and 1E3 / cm^3. Therefore, in one embodiment, the concentration of fluorine atoms in the anti-punch-through region 106 after removing the dielectric material layer 142 is less than 1E4 / cm^3. In one embodiment, the concentration of fluorine atoms in the anti-punch-through region 106 after removing the dielectric material layer 142 is less than 1E3 / cm^3. On the other hand, the deposition of the dielectric material layer 142, the annealing process, and the removal of the dielectric material layer 142 do not adversely affect the concentration of the desired boron atoms in the anti-punch-through region 106. Therefore, the deposition of the dielectric material layer 142, the annealing process, and the removal of the dielectric material layer 142 remove the unwanted dopant without adversely affecting the concentration of the desired dopant.

[0111] Figures 5 to 7 The description of the present disclosure has mainly discussed an embodiment in which the anti-punch-through region 106 includes boron and fluorine atoms. However, the anti-punch-through region 106 may include other types of dopants, including other types of desirable dopants and undesirable dopants without departing from the scope of the present disclosure. The deposition, annealing process, and removal of the dielectric material layer 142 may remove undesirable dopants of different types than the dopants specifically described above.

[0112] Figure 8 FIG. 1 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Figure 8 In the embodiment, a source region 144 and a drain region 146 have been formed in the recess 140 .

[0113] The source region 144 and the drain region 146 include a semiconductor material. The semiconductor material of the source region 144 and the drain region 146 is heavily doped with an N-type dopant. In one example, the semiconductor material includes single crystal silicon, and the dopant includes phosphorus. Other semiconductor materials and dopants may be used for the source region 144 and the drain region 146 without departing from the scope of the present disclosure.

[0114] The source region 144 and the drain region 146 may be formed by epitaxial growth. Thus, single crystal silicon semiconductor material is epitaxially grown from the P-well region 104, the anti-punch-through region 106, and the channel region 108. N-type dopants may be implanted in situ during the epitaxial growth. Other processes for forming the source region 144 and the drain region 146 and for implanting N-type dopants in the source region 144 and the drain region 146 may be utilized without departing from the scope of the present disclosure. Those skilled in the art will recognize that many alternative or additional processes may be utilized to form various features of an N-channel FinFET transistor in accordance with the present disclosure without departing from the scope of the present disclosure.

[0115] Another benefit of the annealing and removal of the dielectric material layer 142 is that the sidewalls 141 of the recess 140 are significantly smoother after the dielectric material layer 142 is removed. This provides an additional benefit that boron atoms or other P-type dopants are not lost at the surface of the recess 140. When the source region 144 and the drain region 146 are formed in the recess 140, the interface between the anti-punchthrough region 106 and the source region 144 and the drain region 146 will therefore include an improved PN interface, which reduces leakage current between the anti-punchthrough region 106 and the source region 144 and the drain region 146. In one embodiment, the maximum peak-to-valley roughness between the interface of the source region 144 / drain region 146 and the anti-punchthrough region 106 is between 0.2 nm and 1 nm. Therefore, the maximum peak-to-valley roughness can be less than 1 nm, or less than 0.4 nm. The smoother interface results in less leakage current between the source and drain regions 144 and 146 and the P-well region 104 through the anti-punch-through region 106 .

[0116] Fig. 9 FIG. 1 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Fig. 9 In the embodiment of the present invention, a dielectric material layer 148 has been deposited on the integrated circuit die 100. The dielectric material layer 148 may include silicon nitride. Other dielectric materials may be used for the dielectric material layer 148 without departing from the scope of the present disclosure.

[0117] Fig.10 FIG. 1 is a cross-section of an integrated circuit die 100 at an intermediate processing stage according to one embodiment. Fig.10 1 , a mask 150 is formed over the dielectric material layer 148 over the portion of the integrated circuit die 100 corresponding to the P-channel FinFET transistor. The mask 150 may be formed using conventional photolithography techniques, which include depositing a photoresist layer, exposing the photoresist to light in the presence of a photolithography mask, and removing the unhardened portions of the photoresist. Other suitable processes and materials may be used to form the mask 150 without departing from the scope of the present disclosure.

[0118] A sidewall spacer 152 is formed on the sidewall of the gate electrode 124. The sidewall spacer 152 is formed by etching the exposed portions of the spacers 130, 132, and 134 and the dielectric material layer 148. The etching process completely removes the spacers 130, 132, and 134 and the dielectric material layer 148 at their exposed locations where they are thinnest in the vertical direction.

[0119] The sidewall spacers 152 are formed by using an anisotropic etching process. The anisotropic etching process selectively etches in a downward direction. As a result, the spacers are not significantly etched from the sidewalls of the gate electrode because the spacers 130, 132, and 134 are thicker vertically along the sidewalls of the gate electrode 124. Therefore, after the etching process, the sidewall spacers 152 remain as Fig.10 as shown in .

[0120] A gate stack 153 includes a gate dielectric layer 122, a gate electrode 124, a hard mask 128, and a sidewall spacer 152. The gate stack 153 encloses a semiconductor fin, such as Fig.18 Shown in more detail.

[0121] Fig.11 FIG. 1 is a cross-section of an integrated circuit die 100 at an intermediate processing stage according to one embodiment. Fig.11 In the embodiment of the present invention, source and drain recesses 154 are formed in the semiconductor material in the N-well region 112, the anti-punch-through region 114, and the channel region 116. As will be described in more detail below, the source and drain recesses 154 will be used to form the source or drain region of a P-channel FinFET transistor.

[0122] The etching process used to form the source and drain recesses 154 selectively etches the semiconductor material associated with the various semiconductor regions 112, 114, 116 with respect to the trench isolation region 110, the sidewall spacers 152, the hard mask 128, and the mask 150. In other words, the etching process etches the semiconductor material associated with the channel region 116, the anti-punch-through region 114, and the N-well region 112 at a significantly higher rate than the material of the sidewall spacers 152, the hard mask 128, and the mask 150. The etching process may include wet etching or dry etching. Therefore, the chemistry of the etchant selectively etches the semiconductor material of the various semiconductor regions 112, 114, 116.

[0123] The etching process for forming the source and drain recesses 154 is an anisotropic etch. The anisotropic etch etches at substantially the same rate in all directions. Therefore, the bottom of the recess 154 will have a semicircular shape. Alternatively, the etching process for forming the source and drain recesses 154 may include a selective etch that etches at a significantly higher rate in the downward direction than in other directions. In this case, the recess 154 will have substantially vertical walls and a substantially flat bottom. The etching process for forming the source and drain recesses may include one or more of wet etching, dry etching, or ion beam etching. Those skilled in the art will recognize that, in accordance with the present disclosure, other etching processes may be utilized without departing from the scope of the present disclosure.

[0124] Fig.12 FIG. 1 is a cross-section of an integrated circuit die 100 at an intermediate processing stage according to one embodiment. Fig.12 , mask 150 has been removed and a dielectric material layer 158 is deposited on the exposed surface of integrated circuit die 100 (including the exposed sidewalls 155 of source and drain recesses 154). As will be described in more detail below, dielectric material layer 158 will help improve the performance and characteristics of the P-channel transistor associated with N-well region 112.

[0125] In one embodiment, the dielectric material layer 158 includes silicon dioxide. The dielectric material layer 158 has a thickness between 3 nm and 30 nm. The dielectric material layer 158 may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Other suitable materials, thicknesses, and deposition processes may be used for the dielectric material layer 158 without departing from the scope of the present disclosure.

[0126] Fig.13 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Fig.13 FIG. 1 is an enlarged view of a portion of the integrated circuit die 100 including the source / drain recess 154 , the dielectric material layer 158 on a sidewall 155 of the recess 154 , and the anti-punch-through region 114 .

[0127] As previously mentioned Figure 1 As described above, the anti-punchthrough region 114 is formed by implanting or diffusing dopants. The doping process may include implanting phosphorus and phosphorus hydrogen into the anti-punchthrough region 114. After or during the implantation, some of the phosphorus and hydrogen atoms are separated. As a result, free hydrogen ions (H+) and free phosphorus ions (P-) exist in the anti-punchthrough region 114.

[0128] While the anti-punch-through region 114 performs a useful function in suppressing the DIBL effect and the accompanying short circuit between the source and drain, the presence of free hydrogen ions can also have a negative effect. For example, some of the free hydrogen ions can gradually diffuse into the channel region 116. The diffusion of hydrogen ions into the channel region 116 can cause significant problems with the functionality of the P-channel transistor. As the concentration of hydrogen ions in the channel region 116 increases, the conductivity of the channel region 116 decreases. If the concentration of hydrogen ions in the channel region 116 is too high, it is possible that the P-channel transistor will not conduct enough current for proper function during channel reversal. As will be described in more detail below, the deposition of the dielectric material layer 158 can assist in reducing the concentration of hydrogen atoms in the anti-punch-through region 114, thereby reducing the number of hydrogen ions that can diffuse into the channel region 116.

[0129] Fig.14 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Fig.14 The diagram of the integrated circuit die 100 is shown in FIG. Fig.13 The same enlarged portion is shown in Figure 2. However, Fig.14 The integrated circuit die 100 is shown after an annealing process has been performed.

[0130] During the annealing process, some of the hydrogen ions migrate from the anti-punchthrough region 114 into the dielectric material layer 158. In the example where the dielectric material layer 158 includes silicon oxide, some of these hydrogen ions bond with silicon atoms in the dielectric material layer 158 to form hydrogen oxide (HOH). As a result, the concentration of hydrogen in the anti-punchthrough region 114 is reduced. Correspondingly, the concentration of hydrogen in the dielectric material layer 158 is increased.

[0131] The annealing process may include a rapid thermal annealing process. The rapid thermal annealing process may include heating the integrated circuit die 100 to a high temperature between 700° C. and 1200° C. The integrated circuit die 100 is subjected to the high temperature for a duration between 5 seconds and 20 seconds. The annealing process may include other temperatures and durations without departing from the scope of the present disclosure. For example, in some cases, the annealing process may last up to several minutes. The result of the annealing process is that hydrogen ions diffuse into the dielectric material layer 158.

[0132] Fig.15 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Fig.15 The diagram of the integrated circuit die 100 is shown in FIG. Fig.14 The same enlarged portion is shown in Fig.15 , the dielectric material layer 158 has been removed.

[0133] The dielectric material layer 158 can be removed by an etching process. The etching process can include wet etching or dry etching. The etching process uses an etchant having a chemistry that selectively etches the dielectric material layer 158 with respect to the semiconductor material of the channel region 116, the anti-punch-through region 114, and the N-well region 112. The etching process can include an anisotropic etching process that etches the dielectric material layer 158 at a substantially similar rate in all directions. The etching process can include a timed etching. The duration of the etching is selected to be sufficient to remove the entire dielectric material layer 158. The duration of the etching is selected to be short enough so that the semiconductor material of the channel region 116, the anti-punch-through region 114, and the N-well region 112 is not etched to a significant extent. For example, the etching process can remove and Therefore, after the etching process of removing the dielectric material layer 158, the width of the recess 154 is not significantly increased.

[0134] When the dielectric material layer 158 is removed, all hydrogen atoms that migrated into the dielectric material layer 158 are also removed. Therefore, as the dielectric material layer 158 is removed, a large amount of hydrogen atoms are removed. In one example, the concentration of hydrogen atoms in the anti-punch-through region 114 before depositing the dielectric material layer 158 is between 1E4 / cm^3 and 1E5 / cm^3. The concentration of hydrogen atoms in the anti-punch-through region 114 after removing the dielectric material layer 158 is between 1E2 / cm^3 and 1E3 / cm^3. Therefore, in one embodiment, the concentration of hydrogen atoms in the anti-punch-through region 114 after removing the dielectric material layer 158 is less than 1E4 / cm^3. In one embodiment, the concentration of hydrogen atoms in the anti-punch-through region 114 after removing the dielectric material layer 158 is less than 1E3 / cm^3. On the other hand, the deposition of the dielectric material layer 158, the annealing process, and the removal of the dielectric material layer 158 do not adversely affect the concentration of desirable phosphorus atoms in the punch-through prevention region 114. Therefore, the deposition of the dielectric material layer 158, the annealing process, and the removal of the dielectric material layer 158 remove unwanted dopant atoms without adversely affecting the concentration of desired dopant atoms.

[0135] Figures 13 to 15 The description of has primarily discussed an embodiment in which the anti-punch-through region includes phosphorus and hydrogen atoms. However, the anti-punch-through region 114 may include other types of dopants, including other types of desirable dopants and undesirable dopants without departing from the scope of the present disclosure. For example, undesirable carbon atoms may be diffused into the dielectric material layer 158 and removed. The deposition, annealing process, and removal of the dielectric material layer 158 may remove undesirable dopants of different types than the dopants specifically described above.

[0136] Fig.16FIG. 1 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Fig.16 In FIG. 1 , a source region 160 and a drain region 162 have been formed in the recess 154 .

[0137] The source region 160 and the drain region 162 include a semiconductor material. The semiconductor material of the source region 160 and the drain region 162 is heavily doped with a P-type dopant. In one example, the semiconductor material includes single crystal silicon, and the dopant includes boron. In another example, the semiconductor material includes silicon germanium (SiGe), and the dopant includes boron. Other semiconductor materials and dopants may be used for the source region 160 and the drain region 162 without departing from the scope of the present disclosure.

[0138] The source region 160 and the drain region 162 may be formed by epitaxial growth. Thus, single crystal silicon semiconductor material is epitaxially grown from the N-well region 112, the anti-punch-through region 114, and the channel region 116. P-type dopants may be implanted in situ during the epitaxial growth. Other processes for forming the source region 160 and the drain region 162 and for implanting P-type dopants in the source region 160 and the drain region 162 may be utilized without departing from the scope of the present disclosure. Those skilled in the art will recognize that many alternative or additional processes may be utilized to form various features of a P-channel FinFET transistor in accordance with the present disclosure without departing from the scope of the present disclosure.

[0139] Another benefit of the annealing and removal of the dielectric material layer 158 is that the sidewalls of the recess 154 are significantly smoother after the dielectric material layer 158 is removed. This provides an additional benefit that phosphorus atoms or other N-type dopants are not lost at the surface of the recess 154. When the source region 160 and the drain region 162 are formed in the recess 154, the interface between the anti-punchthrough region 114 and the source region 160 and the drain region 162 will therefore include an improved PN interface, which reduces leakage current between the anti-punchthrough region 114 and the source region 160 and the drain region 162. In one embodiment, the maximum peak-to-valley roughness between the interface of the source region 160 / drain region 162 and the anti-punchthrough region 114 is between 0.2 nm and 1 nm. Therefore, the maximum peak-to-valley roughness can be less than 1 nm, or less than 0.4 nm. The smoother interface results in less leakage current between the source region 160 and the drain region 162 and the N-well region 112 through the anti-punch-through region 114 .

[0140] Fig.17 FIG. 1 is a cross-section of a portion of an integrated circuit die 100 during an intermediate processing stage according to one embodiment. Fig.17 , the dielectric material layer 148 has been removed. Fig.17An N-channel FinFET transistor 164 and a P-channel FinFET transistor 166 are shown. In practice, the integrated circuit die 100 may include a large number of N-channel FinFET transistors 164 and P-channel FinFET transistors 166. Fig.17 Source and drain contacts or other common integrated circuit structures are not shown. Those skilled in the art will recognize that, based on the present disclosure, the integrated circuit die 100 may include many other structures and features without departing from the scope of the present disclosure.

[0141] Fig.18 According to one embodiment Fig.17 A perspective view of a portion of an integrated circuit die. Fig.17 The perspective view of FIG. 1 shows a semiconductor fin 172 protruding from the semiconductor substrate 102. The source region 144 and the drain region 146, the channel region 108, and a portion of the anti-punch-through region 106 are positioned in the semiconductor fin 172. The gate stack 137 is made to wrap around the semiconductor fin 172. Therefore, the gate electrode 120 and the gate dielectric layer 118 wrap around the channel region 108, so that when a selected voltage is applied to the gate electrode 120, the gate electrode can more effectively cause the channel region 108 to conduct or not conduct. Although not shown in FIG. Fig.18 172, but one or more dielectric layers may be positioned on either side of the semiconductor fin 172. During the formation of the source and drain regions 144, 146, 160, 162, one or more dielectric layers may be present.

[0142] The source region 160 and the drain region 162, the channel region 116, and a portion of the anti-punch-through region 114 are positioned in the semiconductor fin 172. The gate stack 153 is made to wrap around the semiconductor fin 172. Thus, the gate electrode 124 and the gate oxide 122 wrap around the channel region 116, thereby enabling the gate electrode 124 to more effectively cause the channel region 116 to conduct or not conduct when a selected voltage is applied to the gate electrode 124.

[0143] exist Fig.18 , the anti-punch-through regions 106, 114 extend below the semiconductor fin 144 and the corresponding source and drain regions 144, 146, 160, 162. However, in some embodiments, the anti-punch-through regions may not extend below the semiconductor fin 172. In such cases, the N-well region 104 and the P-well region 112 may extend into the semiconductor fin 172. Those skilled in the art will recognize that, in accordance with the present disclosure, the integrated circuit die 100 may have various configurations and components that are not different from those shown in the figures without departing from the scope of the present disclosure.

[0144] As described herein, semiconductor fin 172 may include a single type of semiconductor material with various doped regions. Alternatively, semiconductor fin may include multiple semiconductor materials with various doped regions.

[0145] Fig.19 1 is a method 1900 for manufacturing an integrated circuit die according to an embodiment. In step 1902, the method 1900 includes forming a semiconductor fin including a channel region and an anti-punch-through region. An example of a semiconductor fin is Fig.18 A semiconductor fin 172. An example of a channel region is Figure 1 An example of an anti-breakthrough area is Figure 1 The anti-punch-through region 106. At step 1904, the method 1900 includes forming a recess in the fin, the recess having a side wall adjacent to the anti-punch-through region. An example of a recess is Figure 3 At step 1906, method 1900 includes depositing a dielectric material layer on the sidewalls of the recess. An example of a dielectric material layer is Figure 4 At step 1908, method 1900 includes performing an annealing process when the dielectric material layer is on the sidewalls of the recess. At step 1910, method 1900 includes removing the dielectric material layer from the sidewalls of the recess. At step 1912, method 1900 includes forming a transistor source region in the semiconductor fin by depositing a semiconductor material in the recess. An example of a transistor source region is Figure 8 The method 1900 may be adapted to form an integrated circuit die 100 different from that shown in the preceding figures without departing from the scope of the present disclosure.

[0146] In one embodiment, a method for manufacturing an integrated circuit die includes the following steps. A semiconductor fin including a channel region and an anti-punch-through region is formed. A recess is formed in the semiconductor fin, the recess having a sidewall adjacent to the anti-punch-through region. A dielectric material layer is deposited on the sidewall of the recess. An annealing process is performed while the dielectric material layer is on the sidewall of the recess. The dielectric material layer is removed from the sidewall of the recess. A transistor source region is formed in the semiconductor fin by depositing a semiconductor material in the recess.

[0147] In one embodiment, the above-mentioned annealing process includes: diffusing the first dopant from the anti-punchthrough region into the dielectric material layer. In one embodiment, the above-mentioned annealing process includes: reducing a concentration of the first dopant in the anti-punchthrough region. In one embodiment, the first dopant includes fluorine. In one embodiment, the first dopant includes hydrogen or carbon. In one embodiment, the concentration of the first dopant in the anti-punchthrough region after the annealing process is less than 1E4 / cm^3. In one embodiment, the concentration of the second dopant in the anti-punchthrough region after the annealing process is greater than 1E15 / cm^3. In one embodiment, the method further includes doping the transistor source region with a third dopant of a type opposite to the second dopant. In one embodiment, the step of depositing semiconductor material in the recess includes: performing epitaxial growth. In one embodiment, the step of doping the transistor source region includes: in-situ doping the transistor source region during epitaxial growth.

[0148] In one embodiment, a method of manufacturing an integrated circuit die includes forming a semiconductor fin including a channel region and an anti-punch through region, the anti-punch through region including fluorine and boron. The method may include forming a recess in the fin by etching the semiconductor fin, depositing a dielectric material layer in the recess adjacent to the anti-punch through region, and removing a portion of the fluorine from the anti-punch through region and performing an annealing process on the dielectric material layer. The method may include removing the dielectric material layer from the recess, and forming a transistor source region in the recess by depositing a semiconductor material in the recess.

[0149] In one embodiment, the method further comprises doping the transistor source region with an N-type dopant. In one embodiment, the semiconductor material is single crystal silicon and the N-type dopant is phosphorus. In one embodiment, the dielectric material layer is silicon dioxide. In one embodiment, the concentration of fluorine in the anti-punch-through region after the annealing process is less than 1E3 / cm^3. In one embodiment, the annealing process is a rapid thermal annealing process.

[0150] In one embodiment, an integrated circuit die includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and a channel region in the semiconductor fin. The integrated circuit die 100 may include a gate dielectric on the fin positioned on the channel region and a gate electrode positioned on the gate dielectric. The integrated circuit die may include an anti-punchthrough region doped with a first dopant type in the semiconductor fin, and a source region doped with a second dopant type opposite to the first dopant type in the fin. An interface between the source region and the anti-punchthrough region has a roughness of less than 1 nm peak to valley.

[0151] In one embodiment, the anti-punchthrough region includes boron and fluorine, and the concentration of fluorine in the anti-punchthrough region is less than 1E3 / cm^3. In one embodiment, the anti-punchthrough region includes hydrogen and phosphorus, and the concentration of phosphorus in the anti-punchthrough region is less than 1E3 / cm^3. In one embodiment, the integrated circuit die further includes a drain region doped with a second dopant type in the semiconductor fin, wherein an interface between the drain region and the anti-punchthrough region has a peak-to-valley roughness of less than 1 nm.

[0152] The various embodiments described above can be combined to provide additional embodiments. All U.S. patent application publications and U.S. patent applications mentioned in this specification and / or listed in the application data sheet are fully incorporated herein by reference. If necessary, the aspects of these embodiments can be modified to provide yet further embodiments using the concepts of various patents, applications and publications.

[0153] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the above claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including the full scope of all possible embodiments together with equivalents to which such claims are assigned. Therefore, these claims are not limited by the disclosure.

Claims

1. A method for manufacturing an integrated circuit die, characterized in that: The following steps are involved: forming a semiconductor fin including a channel region and an anti-punch-through region; forming a recess in the semiconductor fin, the recess having a sidewall adjacent to the anti-punch-through region; depositing a dielectric material layer on the sidewall of the recess; When the dielectric material layer is on the sidewall of the recess, an annealing process is performed, wherein the annealing process includes: diffusing a first dopant from the anti-punch-through region into the dielectric material layer; After performing the annealing process, removing the dielectric material layer from the sidewall of the recess; and A transistor source region is formed in the semiconductor fin by depositing a semiconductor material in the recess.

2. The method according to claim 1, characterized in that The dielectric material layer is silicon dioxide.

3. The method according to claim 1, characterized in that The performing of the annealing process includes: reducing a concentration of the first dopant in the anti-punchthrough region.

4. The method according to claim 3, characterized in that: The first dopant includes fluorine.

5. The method according to claim 3, characterized in that: The first dopant includes hydrogen or carbon.

6. The method according to claim 3, characterized in that Wherein a concentration of the first dopant in the anti-punchthrough region after the annealing process is less than 1E4 / cm^3.

7. The method according to claim 3, characterized in that Wherein a concentration of a second dopant in the anti-punchthrough region after performing the annealing process is greater than 1E15 / cm^3.

8. The method according to claim 7, characterized in that Further comprising: doping the transistor source region with a third dopant of an opposite type to the second dopant.

9. The method according to claim 8, characterized in that The step of depositing the semiconductor material in the recess includes performing an epitaxial growth.

10. The method according to claim 9, characterized in that The step of doping the transistor source region includes: in-situ doping the transistor source region during the epitaxial growth.

11. A method for manufacturing an integrated circuit die, characterized in that: The following steps are involved: forming a semiconductor fin including a channel region and an anti-punch-through region, wherein the anti-punch-through region includes fluorine and boron; forming a recess in the semiconductor fin by etching the semiconductor fin; depositing a dielectric material layer in the recess adjacent to the anti-punch-through region; Removing a portion of the fluorine from the anti-punch-through region and performing an annealing process on the dielectric material layer, wherein the performing the annealing process includes: diffusing the fluorine from the anti-punch-through region into the dielectric material layer; After performing the annealing process, removing the dielectric material layer from the recess; and A transistor source region is formed in the recess by depositing a semiconductor material in the recess.

12. The method according to claim 11, characterized in that The method further comprises: doping the transistor source region with an N-type dopant.

13. The method according to claim 12, characterized in that The semiconductor material is single crystal silicon and the N-type dopant is phosphorus.

14. The method according to claim 11, characterized in that The dielectric material layer is silicon dioxide.

15. The method according to claim 11, characterized in that The concentration of fluorine in the anti-punch-through region after the annealing process is less than 1E3 / cm^3.

16. The method according to claim 11, characterized in that The annealing process is a rapid thermal annealing process.

17. An integrated circuit die, characterized in that: Include: a semiconductor substrate; a semiconductor fin protruding from the semiconductor substrate; a channel region located in the semiconductor fin; a gate dielectric layer located on the semiconductor fin above the channel region; a gate electrode located on the gate dielectric layer; an anti-punch-through region located in the semiconductor fin, the anti-punch-through region being doped with a first dopant type, wherein a concentration of the first dopant in the anti-punch-through region is less than 1E3 / cm^3; and A source region is located in the semiconductor fin, the source region is doped with a second dopant type opposite to the first dopant type, wherein an interface between the source region and the anti-punchthrough region has a peak-to-valley roughness of less than 1 nm.

18. The integrated circuit die according to claim 17, characterized in that: The anti-punch-through region includes boron and fluorine, and the first dopant is fluorine.

19. The integrated circuit die according to claim 17, wherein: The anti-punch-through region includes hydrogen and phosphorus, and the first dopant is phosphorus.

20. The integrated circuit die of claim 17, wherein: Further including: A drain region doped with the second dopant type is located in the semiconductor fin, wherein an interface between the drain region and the anti-punchthrough region has a peak-to-valley roughness of less than 1 nm.

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