Methods and systems for regulating plasma cutting rates

Abstract

The rate of plasma etching in areas prone to over-etching is adjusted by providing an anti-etching structure, such as a metal saw frame, in the areas where over-etching is likely to occur. The plasma etching rate in these areas can be controlled to match the etching rate in areas where over-etching is not likely to occur by adjusting dimensions, such as the length and width of the saw frame legs and the area defined by the saw frame legs, and by adjusting the shape of the etched area using techniques such as chamfering.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuit manufacturing, and more specifically, to providing an integrated circuit die saw holder in a saw groove intersection to adjust the etching rate during die cutting to balance slower and faster plasma etching rates. Background Technology

[0002] Wafer testing is a step performed during semiconductor device manufacturing. During this step, performed before the wafer is moved to die fabrication, functional defects of individual integrated circuits are tested by applying specific test patterns to the individual integrated circuits on the wafer. Wafer testing is typically performed by a one-piece test device called a wafer prober. During wafer testing, probes are applied to contacts on each die of the wafer to communicate with the circuitry within the die. Test patterns can be provided to the circuitry by the probes, and the responses can be recorded. Wafer probes can also activate any test circuitry present on the wafer scribe lines.

[0003] Once testing is complete, individual device dies are separated from the wafer (and adjacent device dies) during the single-dic dicing process. In the past, device dies were diced from the wafer using a saw that cuts along scribe lines between dies on the wafer. As device die sizes have become increasingly smaller and the number of dies on a wafer has increased, wafer dicing technology has shifted towards stealth dicing and plasma dicing, which allow for even smaller scribe lines. These techniques do not involve sawing the dies for single-dicing, but rather provide areas where the dies can be separated along the scribe lines.

[0004] During plasma dicing of semiconductor device dies, plasma etching occurs on the material in the dicing grooves. The plasma etching rate depends on the aspect ratio of the etched region and the ease of local gas exchange. As the plasma etchs downwards, the plasma etching rate slows down as it passes through the middle region of the saw ring due to the aspect ratio of that region, compared to the plasma velocity on either side of the saw. On the other hand, in the region where the dicing grooves intersect between dies, over-etching often occurs due to the higher gas exchange in that region and therefore the increased etching rate in that region. Summary of the Invention

[0005] According to a first aspect of the present invention, a semiconductor wafer is provided, the semiconductor wafer having a plurality of semiconductor device dies arranged in a grid pattern, the semiconductor wafer comprising:

[0006] A first semiconductor device die, which is adjacent to a second semiconductor device die and is separated from the second semiconductor device die by a first dicing groove;

[0007] A third semiconductor device die, which is adjacent to the first semiconductor device die and separated from the first semiconductor device die by a second dicing groove, wherein the first dicing groove and the second dicing groove intersect at an intersection area and are substantially perpendicular;

[0008] The fourth semiconductor device die, in which

[0009] The fourth semiconductor device die is adjacent to the second semiconductor device die and is separated from the second semiconductor device die by the second dicing groove.

[0010] The fourth semiconductor device die is adjacent to the third semiconductor device die, and is separated from the third semiconductor device die through the first dicing groove;

[0011] A first conductor, the first conductor comprising:

[0012] A first portion of the first conductor extends from one side of the first semiconductor device die into the first diced groove and into the second semiconductor device die, entering the second semiconductor device die and extending into the sealing ring region of the second semiconductor device die.

[0013] The second portion of the first conductor extends from one side of the second semiconductor device die into the second diced groove and into the fourth semiconductor device die, entering the fourth semiconductor device die and extending into the sealing ring region of the fourth semiconductor device die.

[0014] The third portion of the first conductor extends from one side of the fourth semiconductor device die into the first dicing groove and into the third semiconductor device die, entering the third semiconductor device die and extending into the sealing ring region of the third semiconductor device die.

[0015] A fourth portion of the first conductor extends from one side of the third semiconductor device die into the second dicing groove and into the first semiconductor device die, entering the first semiconductor device die and extending into the sealing ring region of the first semiconductor device die, wherein...

[0016] The first conductor is formed near the corners of the first, second, third, and fourth semiconductor device dies that form the intersecting region.

[0017] In one or more embodiments, the first conductor forms a circuit between the first, second, third and fourth portions of the first conductor.

[0018] In one or more embodiments, the first conductor is formed from a first metal layer of one or more metal layers implemented on the semiconductor wafer.

[0019] In one or more embodiments, the first portion of the first conductor is formed by a first metal layer of one or more metal layers implemented on the semiconductor wafer;

[0020] One or more of the second, third, and fourth portions of the first conductor are formed by a second metal layer of the one or more metal layers; and

[0021] The second metal layer is a different metal layer from the first metal layer.

[0022] In one or more embodiments, the semiconductor wafer further includes:

[0023] A conductive pad, the conductive pad being disposed on the surface of the first semiconductor device die, wherein the conductive pad is electrically coupled to the first portion of the first conductor; and

[0024] A circuit, the circuit being in the first semiconductor device die, wherein the circuit is electrically coupled to the fourth portion of the first conductor.

[0025] In one or more embodiments, the first conductor is configured to reduce the plasma etch rate in the intersecting regions during plasma dicing of the first, second, third, and fourth semiconductor device dies.

[0026] In one or more embodiments, the semiconductor wafer further includes a second conductor, the second conductor comprising:

[0027] A first portion of the second conductor extends from one side of the second semiconductor device die into the second diced groove and into the fourth semiconductor device die, entering the fourth semiconductor device die and extending into the sealing ring region of the fourth semiconductor device die.

[0028] The second portion of the second conductor extends from one side of the fourth semiconductor device die into the first diced groove and into the third semiconductor device die, entering the third semiconductor device die and extending into the sealing ring region of the third semiconductor device die.

[0029] A third portion of the second conductor extends from one side of the third semiconductor device die into the second dicing groove and into the first semiconductor device die, entering the first semiconductor device die and extending into the sealing ring region of the first semiconductor device die.

[0030] A fourth portion of the second conductor extends from one side of the first semiconductor device die into the first dicing groove and into the second semiconductor device die, entering the second semiconductor device die and extending into the sealing ring region of the second semiconductor device die, wherein...

[0031] The second conductor is formed near the corners of the first, second, third, and fourth semiconductor device dies that form the intersecting region, and

[0032] The second conductor is formed of one or more metal layers different from the first conductor.

[0033] In one or more embodiments, the second conductor forms a circuit between the first, second, third and fourth portions of the second conductor.

[0034] In one or more embodiments, the second conductor is below the first conductor and aligned with the first conductor.

[0035] In one or more embodiments, the second conductor is below the first conductor and is not aligned with the first conductor.

[0036] According to a second aspect of the present invention, a method for adjusting the plasma etching rate in an intersecting region between two cutting grooves is provided, the method comprising:

[0037] An integrated circuit system is formed within one or more metal layers on a wafer, wherein

[0038] The integrated circuit system is arranged in a grid pattern of multiple device die regions, including a first semiconductor device die region, a second semiconductor device die region, a third semiconductor device die region, and a fourth semiconductor device die region.

[0039] The first semiconductor device die region is adjacent to the second semiconductor device die region and is separated from the second semiconductor device die region by a first dicing groove.

[0040] The third semiconductor device die region is adjacent to the first semiconductor device die region and separated from the first semiconductor device die region by a second dicing groove, wherein the first dicing groove and the second dicing groove intersect at the intersection region.

[0041] The fourth semiconductor device die region is adjacent to the second semiconductor device die region and separated from the second semiconductor device die region by the second dicing groove; and the fourth semiconductor device die region is adjacent to the third semiconductor device die region and separated from the third semiconductor device die region by the first dicing groove; and

[0042] A first set of conductors is formed near the corners of the first, second, third, and fourth semiconductor device dies that form the intersecting region, wherein the first set of conductors includes:

[0043] A first conductor extends from one side of the first semiconductor device die into the first dicing groove and into the second semiconductor device die, entering the second semiconductor device die and extending into the sealing ring region of the second semiconductor device die.

[0044] The second conductor extends from one side of the second semiconductor device die into the second diced groove and into the fourth semiconductor device die, entering the fourth semiconductor device die and extending into the sealing ring region of the fourth semiconductor device die.

[0045] A third conductor extends from one side of the fourth semiconductor device die into the first dicing groove and into the third semiconductor device die, entering the third semiconductor device die and extending into the sealing ring region of the third semiconductor device die.

[0046] A fourth conductor extends from one side of the third semiconductor device die into the second dicing groove and into the first semiconductor device die, entering the first semiconductor device die and extending into the sealing ring region of the first semiconductor device die.

[0047] In one or more embodiments, the first set of conductors forms a circuit between the first, second, third, and fourth conductors.

[0048] In one or more embodiments, the method further includes forming each of the first set of conductors as a single conductor by a metal layer of one or more metal layers implemented on the semiconductor wafer.

[0049] In one or more embodiments, the method further includes forming one or more conductors of a second, third, and fourth conductor in one or more metal layers different from the metal layer of the first conductor on the semiconductor wafer.

[0050] In one or more embodiments, the method further includes:

[0051] A circuit is formed in the first semiconductor device die; and

[0052] The circuit is electrically coupled to the conductor in the first group of conductors.

[0053] In one or more embodiments, the method further includes forming the first set of conductors such that the plasma etching rate in the intersecting regions is reduced during plasma dicing of the first, second, third, and fourth semiconductor device dies.

[0054] In one or more embodiments, the method further includes:

[0055] A second set of conductors is formed near the corners of the first, second, third, and fourth semiconductor device dies at the intersection region, wherein the second set of conductors includes:

[0056] A fifth conductor extends from one side of the second semiconductor device die into the second dicing groove and into the fourth semiconductor device die, entering the fourth semiconductor device die and extending into the sealing ring region of the fourth semiconductor device die.

[0057] A sixth conductor extends from one side of the fourth semiconductor device die into the first dicing groove and into the third semiconductor device die, entering the third semiconductor device die and extending into the sealing ring region of the third semiconductor device die.

[0058] A seventh conductor extends from one side of the third semiconductor device die into the second dicing groove and into the first semiconductor device die, entering the first semiconductor device die and extending into the sealing ring region of the first semiconductor device die.

[0059] An eighth conductor extends from one side of the first semiconductor device die into the first diced groove and into the second semiconductor device die, entering the second semiconductor device die and extending into the sealing ring region of the second semiconductor device die.

[0060] The second group of conductors is located within a metal layer that is different from the first group of conductors.

[0061] In one or more embodiments, the second set of conductors forms a circuit between the fifth, sixth, seventh and eighth conductors.

[0062] In one or more embodiments, the method further includes forming each of the second set of conductors below and aligned with the first set of conductors.

[0063] In one or more embodiments, the method further includes forming each of the second set of conductors below the first set of conductors and not aligned with the first set of conductors.

[0064] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0065] The embodiments of the present invention can be better understood by referring to the accompanying drawings.

[0066] Figure 1 It is a simplified block diagram showing a portion of a semiconductor wafer on which a single integrated circuit die is formed.

[0067] Figure 2A , 2B Figures 2C and 2C illustrate the saw frame construction and cutting process for plasma cutting using existing technology structures.

[0068] Figure 3 This is an image of the etched area along one side of the plasma-cut die, showing the different etch rates in the area where the cut grooves intersect and in the area below the saw frame structure.

[0069] Figure 4 This is a simplified block diagram showing a portion of a semiconductor wafer 400 on which a single integrated circuit die is formed, wherein a saw ring is formed in the area where the dicing grooves intersect.

[0070] Figure 5 This is a simplified block diagram showing an example close-up plan view of the intersecting area between cutting slots with saw frame rings.

[0071] Figure 6 This is a simplified block diagram of a close-up plan view showing an example of the intersecting area between cutting slots with saw frame rings.

[0072] Figure 7 This is a simplified block diagram showing an example of an etched area along one side of a plasma-cut die.

[0073] Figure 8 This is a simplified block diagram of a cross-section of an example of the intersection area between the cutting grooves, showing two saws provided in different metal layers.

[0074] Figure 9 This is a simplified block diagram of a close-up plan view of the intersecting area between cutting slots 920 and 930, illustrating an alternative for providing multiple saw frames in the intersecting area.

[0075] Unless otherwise specified, the same reference numerals are used to refer to the same objects in different figures. Figures are not necessarily drawn to scale. Detailed Implementation

[0076] Embodiments of the present invention regulate the rate of plasma etching in regions prone to accelerated plasma etching by providing an etching-resistant structure, such as a metal saw frame, in these regions. The plasma etching rate in these regions can be controlled to match the etching rate in non-accelerated regions by adjusting dimensions, such as the length and width of the saw frame legs and the area defined by the saw frame legs, and by adjusting the shape of the etching region using techniques such as chamfering.

[0077] Wafer testing may involve using test contact pads on the device die. These test pads can be configured to be deactivated after the testing process. Typically, external circuit paths are provided outside the device die to connect the internal circuitry to the test pads. These external circuit paths, known as saws, circumnavigate the scribe line area and are designed to be cut during single dicing. Other uses of the saws may include connecting internal circuitry within the device die for programming purposes during the testing and configuration phases, although still on the wafer, but deactivating this functionality after single dicing.

[0078] Traditionally, sawing is performed after wafer testing, preventing end users from accessing the die's electronic content or placing the die in a non-test mode. New die-separation technologies, such as plasma dicing, eliminate this sawing process. Plasma dicing uses deep silicon etching to individually cut dies from the wafer. This technology provides high-quality results, design flexibility, and the ability to cut the entire wafer simultaneously, regardless of die size.

[0079] Plasma dicing employs a dry etching process, in which maskless wafer areas are eroded by plasma. Process gases are used to etch the exposed dicing material and control the vertical profile of the cut within the dicing groove. Plasma dicing can be performed to partially or completely remove all exposed silicon from the dicing groove. Plasma dicing is superior to stealth dicing in that, for some techniques, the dicing width can be as small as, but not limited to, 4 μm (e.g., to avoid damage to integrated circuits within the device die), compared to 10 μm or greater for other dicing techniques such as stealth dicing.

[0080] One drawback of plasma cutting is that the etching rate is limited by the smallest area within which etching is performed. Therefore, a small area between the conductors of the saw "legs" can slow down the entire cutting process. While wider gaps in the saw rings are used to mitigate this problem, providing large gaps between the saw legs has negative consequences, including dimensional difficulties associated with smaller die sizes and costs in terms of area investment.

[0081] Another issue with plasma cutting is the existence of other regions where the plasma etching process is accelerated. This includes areas where the cutting grooves intersect at the junctions between adjacent die inserts. These intersection areas have aspect ratios that favor gas exchange and are therefore etched faster than other areas of the cutting grooves. Embodiments of the invention utilize, for example, the slower etching rate of the region between saw legs to modulate the etching rate in those regions where plasma etching is accelerated.

[0082] Figure 1 This is a simplified block diagram showing a portion of a semiconductor wafer 100 on which a single integrated circuit die is formed. In the present art, wafer diameters of 150 mm, 200 mm, and 300 mm are common. Depending on the nature of the circuitry provided by the semiconductor device die and the nature of the processing techniques used in manufacturing the semiconductor device, these sizes of semiconductor wafers can be processed to include hundreds to hundreds of thousands of possible dies per wafer (PDPW). The semiconductor wafer includes a semiconductor substrate, which can be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, single-crystal silicon, and combinations thereof.

[0083] Figure 1 A repeating group of semiconductor device dies 110 is shown. During processing, dicing grooves (120, 130) are provided between each formed semiconductor device die. After the integrated circuit in the die is completed and tested, individual dies are diced from the semiconductor wafer and each other die. The dicing process, such as those described above, is performed along saw lines 125 and 135 in the dicing grooves 120 and 130, respectively.

[0084] Die 110 includes an example of a saw extending across a dicing groove. Saw 140 electrically couples the circuitry within device die 110 to a test pad 145 located on the surface of device die 110. During device testing, probes can be brought into contact with test pad 145, for example, to provide test signals to integrated circuits within device die 110, read information from those integrated circuits, or provide instructions or data to memory within device die 110. Test pad 145 can be formed using metallization techniques known in the art, such as sputtering and photolithography. Saw 150 can be used to electrically couple integrated circuits within device die 110 for testing purposes (e.g., test mode selection). The electrical paths of both saws 140 and 150 are designed to be cut during single-dicing of device die 110 from wafer 100.

[0085] Saws 140 and 150 are extensions of a metal layer formed within device die 110, which may be formed by a combination of deposition and patterning techniques known in the art. The metal layer may comprise any conductive material, such as, but not limited to, aluminum, aluminum-tin, copper, platinum, palladium, iridium, tantalum, titanium, tungsten, or any metal alloy thereof, nitride, or silicide. The saw extends from a first device die region (e.g., 110), across a cutting groove (e.g., 120), and into a sealing ring (not shown) of an adjacent device die region (e.g., 112). The sealing ring is a stress-protective structure around the integrated circuit and protects the internal circuitry within the semiconductor chip from damage caused by sawing the semiconductor chip from the wafer. A typical sealing ring is generally formed by interconnecting metal layers, dielectric layers between the metal layers, and connecting vias that electrically couple the metal layers.

[0086] Figure 2A , 2B Figures 2C and 2C illustrate the saw frame cutting process using plasma cutting. Figure 2A This is a plan view showing the saw holder 150 extending across the cutting groove 120. (See attached image.) Figure 1 As shown, the device die 110 has a saw 150 extending from one side of the device die through a dicing groove 120 and into the device die region 112. The dicing groove 120 may include a dicing groove material 210, which includes a wafer substrate material, such as silicon, germanium, or silicon carbide. As an example, the saw 150 may have conductive legs with a width of 2 μm that extend across the dicing groove 120 to a 20 μm long annular conductor, thereby forming a 20 μm gap between the conductive legs. In this annular configuration, plasma etching for the dicing process occurs in dicing groove regions 220, 230, and 240. During the etching process, dicing groove material is removed from dicing groove regions 220, 230, and 240. As the gap between the conductive legs decreases, the etching time for region 230 will increase. This is discussed in more detail below.

[0087] Figure 2B This is a simplified block diagram illustrating the result of plasma dicing following the single-dicing of die 110 from wafer 100. As shown, a small amount of dicing material 210 remains on the surface of die 110 facing the area where the dicing groove 120 is located, and on the surface of the cut saw. The saw 150 is cut into die side pieces 250 and ring side pieces 260. As discussed above, using a plasma dicing process to single-dic die 110 requires decomposing the metal in the saw because this material is not etched. Decomposing the metal exposes metal regions 270 and 275.

[0088] Figure 2CThis is a cross-section of the saw holder region of the cutting groove after the etching process of plasma cutting. As shown, the saw holder 150 is an extension of one of the metal layers of the die 110. The saw holder extends across the cutting groove 120 and into the die region 112. The saw holder 150 extends into the sealing ring region 285 of the die region 112, thereby incorporating into the metal layer 280. In region 230, during PV etching, the etching process has partially removed the silicon oxide material above the saw holder. The remaining silicon oxide protects the metal of the saw holder during silicon plasma cutting. Additionally, as... Figure 2B As shown, the cutting groove material outside the metal layer inside the saw bow ring is etched.

[0089] Figure 3 This is an image of the etched area along one side of a plasma-cut die, showing the different etch rates in the area where the dicing trenches intersect and in the area below the saw structure. A typical etching process for dicing semiconductor devices is the deep reactive ion etching (DRIE) process. An example DRIE process involves applying pulses in two steps: in the first step, the plasma etches the wafer primarily in the vertical direction, and in the second step, a passivation layer (e.g., polytetrafluoroethylene) is chemically deposited on the silicon surface using a source gas (e.g., octafluorocyclobutane). The two steps are iterated in such a way that each surface passivation stage is followed by an etching stage, during which ions selectively, but not along the sidewalls, erode the passivation layer forming at the bottom of the trench. This iterative process allows for deep vertical etching but also affects the lateral walls, and therefore the sides are not perfectly flat but wavy.

[0090] Transverse Figure 3 The roughly horizontal lines in the image show the ripples formed during the plasma etching process. Since each “layer” in the image takes the same amount of time, a larger vertical distance between the lines indicates faster etching in that area, while a smaller vertical distance indicates slower etching in that area. Region 310 is the area where another dicing groove intersects with the dicing groove along the side of the plasma-etched die (e.g., where dicing groove 120 intersects with dicing groove 130). Due to enhanced exchange of etchant gases in this region, the etching process proceeds faster. This is shown by the larger distance between the ripple lines near this region. This also allows etching to reach the minimum level of the semiconductor material faster than the rest of the device wafer. Conversely, at saw leg 350 (e.g., corresponding to…)… Figure 1 and 2AIn the region 330 below and between the saw legs 150, the distance between the corrugated lines is significantly smaller, indicating that the etching between the narrowly separated metal saw legs is slower. Therefore, the same number of etching steps result in a less deep etching between the saw legs than in the cross region. Along the remaining portion of the side of the cut die, the corrugations have a constant spacing between the corrugations in the cross region 310 and the corrugations in the saw leg region 330.

[0091] To provide a more constant etching rate distribution for plasma cutting, embodiments of the present invention utilize a slower etching rate experienced in the saw frame region to modulate a faster etching rate experienced in the cut groove intersection region. As will be discussed more fully below, the etching rate in the intersection region can be controlled to produce a uniform etching rate along the cut groove by utilizing different geometries of the saw frame and the cut groove (e.g., the distance between the saw frame legs, the saw frame metal width, and the chamfering of the corners of the cut groove intersection region).

[0092] Figure 4 This is a simplified block diagram showing a portion of a semiconductor wafer 400 on which a single integrated circuit die is formed. (See diagram for example.) Figure 1 As shown, the semiconductor wafer includes a semiconductor substrate, which can be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, single-crystal silicon, and combinations thereof.

[0093] Figure 4 A repeating group of semiconductor device dies 410, 412, 414, and 416 is shown. During processing, dicing grooves (120, 130) are provided between each formed semiconductor device die. Plasma single-cutting, such as the plasma single-cutting described above, is performed along saw lines 425 and 435 in dicing grooves 420 and 430, respectively. Die 410 includes a saw extending across the dicing grooves into the region where dicing grooves 120 and 130 intersect. Saw 440 electrically couples the circuitry within die 410 to a test pad 445 located on the surface of die 410. The test pad 445 can be formed using the same techniques described above for test pad 145. Saw 440 can also be formed without a test pad for coupling integrated circuits within die 410 for testing purposes. Figure 1 As shown, the electrical path of the saw 440 is designed to be cut off during the single-cutting of the device die from the wafer formed above.

[0094] The saw arm 440 is an extension of the metal layer formed within the device die 410, and is formed by a combination of deposition and patterning techniques as known in the art. The saw arm extends from the first device die region 410, crosses the cutting groove 430, and enters the sealing ring (not shown) of the adjacent device die region 416. A next leg of the saw arm extends from the device die region 416, crosses the cutting groove 420, and enters the sealing ring of the adjacent device die region 414. A third leg of the saw arm extends from the device die region 414, crosses the cutting groove 430, and enters the sealing ring of the adjacent device die region 412. Finally, a fourth leg of the saw arm extends from the device die region 412, crosses the cutting groove 420, and returns to the device die region 410. By extending the saw arm between the sealing rings of four adjacent device dies, the saw arm metal is brought close to the region where the plasma cutting process intersects.

[0095] When using plasma dicing processes, the width of the dicing groove can be as small as approximately 4-10 μm, especially as the size of the device die continues to decrease. Depending on the technology used for wafer fabrication, the width of the saw metal can be 0.3 μm or less. If the distance between the saw legs extends vertically across the dicing groove, this distance can be as small as the width of the dicing groove. The distance between the saw legs can be increased by positioning the legs away from the intersection area. The distance between the saw legs can be made smaller than the width of the dicing groove by tilting the metal towards the center of the intersection area and then extending it across the dicing groove. The distance between the saw legs can be selected to adjust the etching rate in the intersection area.

[0096] Figure 5 This is a simplified block diagram showing a close-up plan view of the intersecting region between dicing grooves 420 and 430 according to an embodiment of the invention. Dicing grooves 420 and 430 are shown as including plasma etched regions 510 and 520, respectively. In typical DRIE wafer dicing, a patterning method (e.g., photolithography) is used to define the plasma etched regions. Depending on the application, the widths of the etched regions 510 and 520 can be between 4 and 10 μm, while the width of the dicing groove can be as narrow as or greater than the etched regions. As discussed above, the distances A and B between the saw legs 440, and the thicknesses C and D of the saw metal, can be adjusted to adjust the etching rate in the intersecting region.

[0097] Figure 6 This is a simplified block diagram showing a close-up plan view of the intersection area between cutting grooves 420 and 430 according to an alternative embodiment of the present invention. (As...) Figure 5 Cutting grooves 420 and 430 are shown as including plasma etched regions 610 and 620, respectively. Although Figure 6 The dimensions in the embodiments may be the same as Figure 5The dimensions are the same in the embodiments, but the corners of the intersection regions are chamfered to obtain the curved corners of device dies 410, 412, 414, and 416. The chamfering increases the area in which DRIE chemicals can interact during plasma etching, and thus increases the etching rate in this area. The chamfer radius of curvature is one of the variables that can be modified as needed for the application to increase or decrease the etching rate in the intersection regions.

[0098] Figure 7 This is a simplified block diagram illustrating an example of an etched region along one side of a plasma-cut die incorporating an embodiment of the invention. As... Figure 3 The roughly horizontal lines traversing the diagram represent the ripples formed during the plasma etching process. Region 710 is the area where another dicing groove intersects the side of the plasma-etched die (e.g., where dicing grooves 420 and 430 intersect). The presence of saw legs 440 near region 710 slows down the etching rate within region 710, resulting in a constant etching rate across the illustrated region. The etching rate within the intersecting region can be controlled by adjusting parameters such as the distance A between saw legs 440. Other parameters, such as the type of plasma etching process, the type of etchant gas, the material of the semiconductor die, and the material of the saw legs, may also affect the etching rate. Therefore, as discussed above, the distance between saw legs, the thickness of the saw, and the amount of chamfering will vary to control the etching rate.

[0099] For applications requiring more than one saw arm to pass through the circuitry or pads on the die, multiple saw arms can be provided in the intersection area. For example, multiple metal layers in the die at the intersection of the cutting grooves can be used to provide the saw arms. Figure 8 This is a simplified block diagram of the cross-section 800 of the intersection area between the cutting slots, showing two saws provided in different metal layers. Figure 8 A cross-section is provided adjacent to the kerf 820 of die 810 and die 812. Saw leg 830 extends from die 810, crosses the kerf 820, and enters the sealing ring region 840 of die 812. Saw leg 830 is an extension of the first metal layer 832. Saw leg 835 extends from die 812, crosses the kerf 820, enters the sealing ring region 850 of die 810, and is an extension of the second metal layer 837. Depending on the nature of the application, more than two saws may be stacked vertically in the kerf. The embodiment is not limited to multiple stacked saws. Furthermore, the saw legs do not necessarily need to be stacked directly above or below each other. The alignment of the stacked saw legs can be adjusted to modify how the saws change the etching rate in the intersecting areas of the kerfs.

[0100] Figure 9This is a simplified block diagram of a close-up plan view of the intersection region between cutting grooves 920 and 930 according to an embodiment of the present invention, illustrating an alternative for providing multiple saws in the intersection region. Between semiconductor device dies 910 and 912 is a saw ring 940. Similarly, between semiconductor device dies 914 and 916 is a saw ring 950. Saw rings 940 and 950 each have conductive “legs” 945 and 955 near the intersection region of cutting grooves 920 and 930, respectively. Additionally, two dummy regions 950 and 960 are formed near the intersection region of the cutting grooves. Dummy regions 950 and 960 are not saws, but are formed of a material that adjusts the etching rate in the intersection region. This material may be the same as the material used for the saw (e.g., a conductive metal) or another material that affects the etching rate, such as silicon oxide or a photoresist. In the configuration shown, saw legs 944 and 955, as well as dummy regions 960 and 970, reduce the etching rate in the cut grooves that pass through the intersecting regions in the same manner as discussed above.

[0101] The embodiment provides additional metal in the intersecting region between plasma cutting grooves to regulate the plasma etching rate. As an alternative to the saw ring, a dummy region formed of metal or other plasma etching barrier material can be created in the intersecting region to regulate the etching rate at the groove intersection. By regulating the etching rate in the intersecting region in the described manner, more predictable plasma cutting timing can be achieved, resulting in more reliable die inserts and more consistent cutting times.

[0102] It should now be understood that a semiconductor wafer having a plurality of semiconductor device dies arranged in a grid pattern has been provided. The semiconductor wafer includes: a first semiconductor device die, adjacent to a second semiconductor device die and separated from the second semiconductor device die by a first dicing groove; a third semiconductor device die, adjacent to the first semiconductor device die and separated from the first semiconductor device die by a second dicing groove. The first and second dicing grooves intersect at an intersection region and are substantially perpendicular. A fourth semiconductor device die, adjacent to the second semiconductor device die and separated from the second semiconductor device die by the second dicing groove, and adjacent to the third semiconductor device die and separated from the third semiconductor device die by the first dicing groove. The semiconductor wafer further includes a first conductor. The first conductor includes: a first portion extending from one side of a first semiconductor device die into a first dicing groove and into a second semiconductor device die, extending into the second semiconductor device die and into a sealing ring region of the second semiconductor device die; a second portion extending from one side of the second semiconductor device die into a second dicing groove and into a fourth semiconductor device die, extending into the fourth semiconductor device die and into a sealing ring region of the fourth semiconductor device die; a third portion extending from one side of the fourth semiconductor device die into a first dicing groove and into a third semiconductor device die, extending into the third semiconductor device die and into a sealing ring region of the third semiconductor device die; and a fourth portion extending from one side of the third semiconductor device die into a second dicing groove and into the first semiconductor device die, extending into the first semiconductor device die and into a sealing ring region of the first semiconductor device die, wherein the first conductor is formed near two corners of the first, second, third, and fourth semiconductor devices that form the intersecting region.

[0103] In one aspect of the above embodiments, a circuit is formed between the first conductor and the first, second, third, and fourth portions of the first conductor. In another aspect, the first conductor is formed of a first metal layer among one or more metal layers implemented on a semiconductor wafer. In yet another aspect, a first portion of the first conductor is formed of a first metal layer among one or more metal layers implemented on a semiconductor wafer, and one or more of the second, third, and fourth portions of the first conductor are formed of a second metal layer among one or more metal layers, wherein the second metal layer is a different metal layer from the first metal layer. Yet another aspect includes: a conductive pad on the surface of a first semiconductor device die, wherein the conductive pad is electrically coupled to a first portion of the first conductor; and a circuit in the first semiconductor device die, wherein the circuit is electrically coupled to a fourth portion of the first conductor.

[0104] In another aspect, the first conductor is configured to reduce the plasma etching rate in the intersecting region during plasma cutting of the first, second, third, and fourth semiconductor device dies.

[0105] In another embodiment, the semiconductor wafer further includes a second conductor. The second conductor includes: a first portion extending from one side of a second semiconductor device die into a second dicing groove and toward a fourth semiconductor device die, entering the fourth semiconductor device die and extending into a sealing ring region of the fourth semiconductor device die; a second portion extending from one side of the fourth semiconductor device die into a first dicing groove and toward a third semiconductor device die, entering the third semiconductor device die and extending into a sealing ring region of the third semiconductor device die; a third portion extending from one side of the third semiconductor device die into a second dicing groove and toward a first semiconductor device die, entering the first semiconductor device die and extending into a sealing ring region of the first semiconductor device die; and a fourth portion extending from one side of the first semiconductor device die into a first dicing groove and toward the second semiconductor device die, entering the second semiconductor device die and extending into a sealing ring region of the second semiconductor device die. The second conductor is formed near the corner of the first, second, third, and fourth semiconductor device dies that form the intersecting region, and the second conductor is formed of one or more metal layers different from the first conductor.

[0106] In another aspect, the second conductor forms a circuit between the first, second, third, and fourth portions of the second conductor. In yet another aspect, the second conductor is below and aligned with the first conductor. In still another aspect, the second conductor is below the first conductor and not aligned with it.

[0107] Another embodiment provides a method for adjusting the plasma etching rate in an intersection region between two diced slots. The method includes forming an integrated circuit system within one or more metal layers on a wafer. The integrated circuit system is arranged in a grid pattern of multiple device die regions, including a first semiconductor device die region, a second semiconductor device die region, a third semiconductor device die region, and a fourth semiconductor device die region. The first semiconductor device die region is adjacent to the second semiconductor device die region and separated from it by a first diced slot. The third semiconductor device die region is adjacent to the first semiconductor device die region and separated from it by a second diced slot, wherein the first and second diced slots intersect at an intersection region. The fourth semiconductor device die region is adjacent to the second semiconductor device die region and separated from it by a second diced slot, and is also adjacent to the third semiconductor device region and separated from it by a first diced slot. The method further includes forming a first set of conductors near the corners of the first, second, third, and fourth semiconductor devices dies forming the intersection region. The first set of conductors includes: a first conductor extending from one side of a first semiconductor device die into a first dicing groove and into a second semiconductor device die, entering the second semiconductor device die and extending into a sealing ring region of the second semiconductor device die; a second conductor extending from one side of the second semiconductor device die into a second dicing groove and into a fourth semiconductor device die, entering the fourth semiconductor device die and extending into a sealing ring region of the fourth semiconductor device die; a third conductor extending from one side of the fourth semiconductor device die into a first dicing groove and into a third semiconductor device die, entering the third semiconductor device die and extending into a sealing ring region of a third similar device die; and a fourth conductor extending from one side of the third semiconductor device die into a second dicing groove and into the first semiconductor device die, entering the first semiconductor device die and extending into a sealing ring region of the first semiconductor device die.

[0108] In one aspect of the above embodiments, a first conductor forms a circuit between the first, second, third, and fourth conductors. In another aspect, the method further includes forming each of the first group of conductors as a single conductor by a metal layer in one or more metal layers implemented on a semiconductor wafer. In another aspect, the method further includes forming one or more of the second, third, and fourth conductors in a metal layer different from the metal layer of the first conductor in one or more metal layers implemented on a semiconductor wafer. In yet another aspect, the method further includes forming a circuit in a first semiconductor device die and electrically coupling the circuit to the conductors in the first group of conductors.

[0109] In another aspect, the method further includes forming a first set of conductors such that the plasma etching rate in the intersecting regions is reduced during plasma dicing of the first, second, third, and fourth semiconductor device dies.

[0110] In another aspect, the method further includes forming a second set of conductors near the corners of the first, second, third, and fourth semiconductor device dies at the intersection region. The second set of conductors includes: a fifth conductor extending from one side of the second semiconductor device die into a second dicing groove and toward the fourth semiconductor device die, entering the fourth semiconductor device die and extending into a sealing ring region of the fourth semiconductor device die; a sixth conductor extending from one side of the fourth semiconductor device die into a first dicing groove and toward the third semiconductor device die, entering the third semiconductor device die and extending into a sealing ring region of the third semiconductor device die; a seventh conductor extending from one side of the third semiconductor device die into a second dicing groove and toward the first semiconductor device die, entering the first semiconductor device die and extending into a sealing ring region of the first semiconductor device die; and an eighth conductor extending from one side of the first semiconductor device die into a first dicing groove and toward the second semiconductor device die, entering the second semiconductor device die and extending into a sealing ring region of the second semiconductor device die. The second set of conductors is within a metal layer different from the first set of conductors.

[0111] In another aspect, the second set of conductors forms a circuit between the fifth, sixth, seventh, and eighth conductors. In yet another aspect, the method further includes forming each conductor in the second set of conductors below and aligned with the first set of conductors. In yet another aspect, the method further includes forming each conductor in the second set of conductors below and not aligned with the first set of conductors.

[0112] Because the devices implementing this invention consist mostly of electronic components and circuits known to those skilled in the art, the circuit details will not be described to any greater extent than those deemed necessary above in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or departing from its teachings.

[0113] Furthermore, the terms “front,” “back,” “top,” “bottom,” “above,” “below,” etc., as used in the specification and claims (if applicable), are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that such terms are interchangeable where appropriate, such that embodiments of the invention described herein can operate, for example, in orientations other than those shown or otherwise described herein.

[0114] Additionally, it should be noted that the term “neighboring” as used herein means “adjacent to” (e.g., right next to each other without any intermediate objects), and the term “laterally” as used herein means “in the lateral direction” (e.g., in the horizontal direction parallel to the plane of the substrate).

[0115] As used herein, the terms “approximately” and “about” mean a value that is close to or within an acceptable range of the indicated value, quantity, or number, including values ​​that are correctly indicated by themselves.

[0116] As used herein, the terms “substantially” and “substantially” mean sufficient to achieve the stated purpose or value in a practically practicable manner, taking into account any minor defects or deviations (if present) caused by common and expected process anomalies that may occur during wafer manufacturing, which are not significant to the stated purpose or value.

[0117] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention. Any benefits, advantages, or solutions to problems described herein with reference to specific embodiments are not intended to be construed as key, necessary, or essential features or elements of any or all claims.

[0118] As used in this article, the term “coupling” is not intended to be limited to direct coupling or mechanical coupling.

[0119] Furthermore, as used herein, the term "a" is defined as one or more. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that any particular claim containing a claim element introduced by the indefinite article "a" or "one" limits it to an invention containing only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and indefinite articles such as "a" or "one". The same applies to the use of definite articles.

[0120] Unless otherwise stated, terms such as “first” and “second” are used to distinguish, arbitrarily, the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements.

Claims

1. A semiconductor wafer having a plurality of semiconductor device dies arranged in a grid pattern, characterized in that, The semiconductor wafer includes: A first semiconductor device die, which is adjacent to a second semiconductor device die and is separated from the second semiconductor device die by a first dicing groove; A third semiconductor device die, which is adjacent to the first semiconductor device die and separated from the first semiconductor device die by a second dicing groove, wherein the first dicing groove and the second dicing groove intersect at an intersection area and are substantially perpendicular; The fourth semiconductor device die, in which The fourth semiconductor device die is adjacent to the second semiconductor device die and is separated from the second semiconductor device die by the second dicing groove. The fourth semiconductor device die is adjacent to the third semiconductor device die and is separated from the third semiconductor device die by the first dicing groove; and A first conductor, having a continuous shape and coupled to a circuit system of the first semiconductor device die, the first conductor comprising: A first portion of the first conductor extends from the circuitry of the first semiconductor device die to the first dicing groove on a first side of the first semiconductor device die and into the second semiconductor device die, entering the second semiconductor device die on the first side of the second semiconductor device die and extending into the sealing ring region of the second semiconductor device die. The second portion of the first conductor extends from the sealing ring region of the second semiconductor device die into the second dicing groove on a second side of the second semiconductor device die, different from the first side of the second semiconductor device die, and extends toward the fourth semiconductor device die, entering the fourth semiconductor device die on the first side of the fourth semiconductor device die, and extending into the sealing ring region of the fourth semiconductor device die. The third portion of the first conductor extends from the sealing ring region of the fourth semiconductor device die into the first diced groove and into the third semiconductor device die on a second side of the fourth semiconductor device die, different from the first side of the fourth semiconductor device die, entering the third semiconductor device die on the first side of the third semiconductor device die and extending into the sealing ring region of the third semiconductor device die. The fourth portion of the first conductor extends from the sealing ring region of the third semiconductor device die into the second dicing groove on a second side of the third semiconductor device die, different from the first side of the third semiconductor device die, and extends into the first semiconductor device die, entering the first semiconductor device die and extending into the sealing ring region of the first semiconductor device die, wherein... The first, second, third, and fourth portions of the first conductor together form the continuous shape of the first conductor. The semiconductor wafer further includes a second conductor, the second conductor having a continuous shape and comprising: A first portion of the second conductor extends from a second side of the second semiconductor device die into the second diced groove and toward the fourth semiconductor device die, entering the fourth semiconductor device die on a first side of the fourth semiconductor device die and extending into the sealing ring region of the fourth semiconductor device die. A second portion of the second conductor extends from the second side of the fourth semiconductor device die into the first diced groove and into the third semiconductor device die, entering the third semiconductor device die from the first side of the third semiconductor device die and extending into the sealing ring region of the third semiconductor device die. The third portion of the second conductor extends from the second side of the third semiconductor device die into the second dicing groove and into the first semiconductor device die, entering the first semiconductor device die on the second side of the first semiconductor device die, different from the first side of the first semiconductor device die, and extending into the sealing ring region of the first semiconductor device die. The fourth portion of the second conductor extends from the first side of the first semiconductor device die into the first dicing groove and into the second semiconductor device die, enters the second semiconductor device die on the first side of the second semiconductor device die, and extends into the sealing ring region of the second semiconductor device die, wherein... The second conductor is formed near the corners of the first, second, third, and fourth semiconductor device dies that form the intersection region. The second conductor is configured to reduce the plasma etching rate in the intersection region during plasma dicing of the first, second, third, and fourth semiconductor device dies. The plasma etching rate in the intersection region is consistent with the plasma etching rates of the first and second dicing trenches outside the intersection region. The second conductor is formed of one or more metal layers that are different from the first conductor.

2. The semiconductor wafer according to claim 1, characterized in that, The first conductor forms a circuit path between the first, second, third and fourth portions of the first conductor.

3. The semiconductor wafer according to claim 2, characterized in that, The first conductor is formed from a first metal layer of one or more metal layers implemented on the semiconductor wafer.

4. The semiconductor wafer according to claim 2, characterized in that, The first portion of the first conductor is formed by a first metal layer of one or more metal layers implemented on the semiconductor wafer; One or more of the second, third, and fourth portions of the first conductor are formed by a second metal layer of the one or more metal layers; and The second metal layer is a different metal layer from the first metal layer.

5. The semiconductor wafer according to claim 2, characterized in that, In addition, including: A conductive pad is located on the surface of the first semiconductor device die, wherein the conductive pad is electrically coupled to the first portion of the first conductor; as well as A circuit, the circuit being in the first semiconductor device die, wherein the circuit is electrically coupled to the first portion of the first conductor.

6. The semiconductor wafer according to claim 1, characterized in that, The second conductor forms a circuit between the first, second, third and fourth portions of the second conductor.

7. The semiconductor wafer according to claim 1, characterized in that, The second conductor is below the first conductor and aligned with the first conductor.

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