Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and manufacturing methods. A semiconductor device and manufacturing method are provided. In some embodiments, a treatment process is used to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent process steps (e.g., applying a subsequent photoresist material), thereby allowing the work function layer to be thinner than otherwise.

Description

Technical Field

[0001] The present application relates to semiconductor devices and manufacturing methods. Background Art

[0002] Semiconductor devices are used, for example, in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature sizes, which allows more components to be integrated into a given area. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a fin from a semiconductor substrate; forming a gate dielectric on the fin; forming a work function layer on the gate dielectric; and modifying a surface of the work function layer, wherein modifying the surface is performed at least in part by chemical immersion of implanting active elements.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a gate dielectric over a channel region of a semiconductor material, the channel region being adjacent to multiple sides of the semiconductor material; depositing a work function layer over the gate dielectric using an atomic layer deposition process; immersing the work function layer in a precursor material, wherein immersing the work function layer forms a dopant layer within the work function layer; and depositing a filling material over the work function layer.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor fin; a dielectric material, the dielectric material being adjacent to the semiconductor fin; a work function layer, the work function layer being located above the dielectric material, the work function layer comprising a dopant layer; and a filling material, the filling material being located above the work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1An example of a FinFET according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17 , Fig.18 , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Fig.22A , Fig. 22B , Fig.23A and Fig. 23B A diagram showing the composition of the various layers in which active element dopants are present.

[0011] Fig.24 A graph of the flat band voltage for different active element dopants is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] The embodiments will now be described with respect to a specific embodiment of forming a fin field effect transistor (finFET). However, the embodiments described herein may be applied in a variety of devices and methods, such as nanostructures, and all such embodiments are fully intended to be included within the scope of the embodiments.

[0015] Reference now Figure 1 , Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is provided in the substrate 50, and the fin 52 protrudes above and between adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material with the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52A refers to the portion extending between adjacent isolation regions 56.

[0016] Gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52, and gate electrode 94 is over gate dielectric layer 92. Source / drain regions 82 are disposed on the opposite side of fin 52 relative to gate dielectric layer 92 and gate electrode 94. Figure 1Reference cross sections used in subsequent figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in a direction, for example, of current flow between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects for planar devices (e.g., planar FETs), nanostructure (e.g., nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs), and the like.

[0018] Figures 2 to 21B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA is shown in , except for multiple fins / FinFETs. Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A It is along Figure 1 The reference section AA is shown, and Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 14C , Fig.15A , Fig.16A , Fig.17 and Fig.18 It is along Figure 1 Similar to cross section BB is shown, except with multiple fins / FinFETs. Fig. 10C and Fig. 10D It is along Figure 1 Reference cross section CC is shown, in addition to multiple fins / FinFETs.

[0019] exist Figure 2In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon or substrate glass substrate). Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination of the foregoing.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separation mark 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0021] exist Figure 3 In the embodiment, fin 52 is formed in substrate 50. Fin 52 is a semiconductor strip. In some embodiments, fin 52A can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination of the foregoing. Etching can be anisotropic.

[0022] The fins may be patterned by any suitable method. For example, the fins 52 may be patterned using one or more lithography processes including a double patterning process or a multi-patterning process. Typically, the double patterning process or the multi-patterning process combines a lithography process with a self-alignment process, thereby allowing the generation of a pattern having a smaller pitch than that obtainable using a single direct lithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins 52.

[0023] exist Figure 4In the embodiment, the insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination of the foregoing, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material, such as an oxide), etc., or a combination of the foregoing. Other insulating materials formed by any acceptable process may be used. In the embodiment shown, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as those discussed above may be formed over the liner.

[0024] exist Figure 5 In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 located above the fin 52. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch back process, a combination of the foregoing, etc. The planarization process exposes the fin 52 so that the top surfaces of the fin 52 and the insulating material 54 are flush after the planarization process is completed. In embodiments in which the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that the top surface of the mask or the fin 52, respectively, is flush with the top surface of the insulating material 54 after the planarization process is completed.

[0025] exist Figure 6 In the embodiment of the present invention, the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed so that the upper portion of the fin 52 in the n-type region 50N and the p-type region 50P protrudes from between the adjacent STI regions 56. In addition, the top surface of the STI region 56 can have a flat surface, a raised surface, a recessed surface (e.g., a concave) as shown, or a combination of the foregoing. The top surface of the STI region 56 can be formed to be flat, raised, and / or recessed by appropriate etching. The STI region 56 can be recessed using, for example, an acceptable etching process that is selective to the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than the material of the fin 52). For example, oxide removal using, for example, dilute hydrofluoric (dHF) acid can be used.

[0026] refer to Figures 2 to 6The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 may be recessed, and a material different from the fin 52 may be epitaxially grown over the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxially grown material disposed over the recessed material. In yet another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments in which a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and subsequent implantations, but in-situ doping and implantation doping may be used together.

[0027] In addition, it may be advantageous to epitaxially grow a different material in the n-type region 50N (eg, NMOS region) than in the p-type region 50P (eg, PMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0028] In addition, Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N, and an N-well may be formed in the p-type region 50P. In some embodiments, a P-well or an N-well is formed in both the n-type region 50N and the p-type region 50P.

[0029] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be implemented using photoresists and / or other masks (not shown). For example, a photoresist may be formed over the fins 52 and STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0030] After the p-type region 50P is implanted, a photoresist is formed over the fin 52 and the STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc., implanted into the region, and its concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0031] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0032] exist Figure 7In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination of the foregoing, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60, and then planarized by, for example, CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from a group including: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 62 may be made of other materials with high etch selectivity relative to the etching of the isolation regions (e.g., STI regions 56 and / or dummy dielectric layer 60). The mask layer 64 may include one or more layers of, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 60 is shown covering only the fin 52 for illustration purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited so that the dummy dielectric layer 60 covers the STI region 56, extends over the STI region and extends between the dummy gate layer 62 and the STI region 56.

[0033] FIG. 8A to FIG. 16B Various additional steps in the fabrication of example devices are shown. FIG. 8A to FIG. 16B Features in either the n-type region 50N or the p-type region 50P are shown. For example, FIG. 8A to FIG. 16B The structure shown in FIG. 5 may be applied to both the n-type region 50N and the p-type region 50P. The differences in structure, if any, between the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

[0034] exist Fig. 8A and Figure 8B In the embodiment, the mask layer 64 (see Figure 7 ) can be patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each of the dummy gates 72 from the adjacent dummy gates. The longitudinal direction of the dummy gate 72 can also be substantially perpendicular to the longitudinal direction of the corresponding epitaxial fin 52.

[0035] In addition, Fig. 8A and Figure 8B In the embodiment of the present invention, the gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching may form the gate sealing spacer 80. The gate sealing spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0036] After forming the gate sealing spacer 80, implantation of lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the above, Figure 6 As discussed in the implantation described above, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) may be implanted into the exposed fins 52 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) may be implanted into the exposed fins 52 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed above, and the p-type impurity may be any of the p-type impurities discussed above. The impurity concentration of the lightly doped source / drain region may be between about 10 15 cm -3 and about 10 19 cm -3 Annealing can be used to repair implantation damage and activate the implanted impurities.

[0037] exist Fig.9A and Fig. 9B In the embodiment, the gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination of the foregoing, etc.

[0038] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the gate sealing spacer 80 may not be etched before forming the gate spacer 86, an "L-shaped" gate sealing spacer may be produced, spacers may be formed and removed, etc.). In addition, different structures and steps may be used to form n-type and p-type devices. For example, an LDD region for an n-type device may be formed before forming the gate sealing spacer 80, and an LDD region for a p-type device may be formed after forming the gate sealing spacer 80.

[0039] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fin 52. The epitaxial source / drain regions 82 are formed in the fin 52 so that each dummy gate 72 is disposed between each pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fin 52 and may also penetrate the fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 82 may be selected to apply stress in the corresponding channel regions 58 to improve performance.

[0040] The epitaxial source / drain regions 82 in the n-type region 50N may be formed by masking the p-type region 50P and etching the source / drain regions of the fin 52 in the n-type region 50N to form recesses in the fin 52. The epitaxial source / drain regions 82 in the n-type region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 may include any acceptable material, such as a material suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the n-type region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 82 in the n-type region 50N may have a surface that protrudes from a corresponding surface of the fin 52 and may have a small facet.

[0041] The epitaxial source / drain region 82 in the p-type region 50P may be formed by masking the n-type region 50N and etching the source / drain region of the fin 52 in the p-type region 50P to form a recess in the fin 52. The epitaxial source / drain region 82 in the p-type region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 82 may include any acceptable material, such as a material suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P may include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 82 in the p-type region 50P may have a surface that protrudes from a corresponding surface of the fin 52 and may have a small facet.

[0042] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions may be between about 10 19 cm -3 and about 10 21 cm -3 The n-type and / or p-type impurities of the source / drain regions may be any of the above impurities. In some embodiments, the epitaxial source / drain regions 82 may be in-situ doped during growth.

[0043] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in n-type region 50N and p-type region 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets allow adjacent source / drain regions 82 of the same FinFET to merge, such as Fig. 10C In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated, such as Fig. 10D As shown. Fig. 10C and Fig. 10D In the illustrated embodiment, gate spacers 86 are formed to cover portions of the sidewalls of fins 52 that extend over STI regions 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be adjusted to remove spacer material, thereby allowing epitaxial growth regions to extend to the surface of STI regions 56.

[0044] exist Fig.11A and Fig. 11B In the embodiment, a first interlayer dielectric (ILD) 88 is deposited on Fig. 10A and Fig. 10B88 is formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask 74, and the gate spacer 86. The CESL 87 may include a dielectric material having a lower etch rate than the material of the overlying first ILD 88, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0045] exist Fig. 12A and Fig. 12B In the process of planarizing, a planarization process such as CMP may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0046] exist Fig.13A and Fig. 13BIn the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in the etching step(s) to form the recess 90. The portion of the dummy dielectric layer 60 located in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, while the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in the first region of the die (e.g., the core logic region), and the dummy dielectric layer 60 is retained in the recess 90 in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas (s) that selectively etches the dummy gate 72 while etching little or no first ILD 88 or gate spacer 86. Each recess 90 exposes and / or overlies the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between each pair of adjacent epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. Then, after the dummy gate 72 is removed, the dummy dielectric layer 60 may be optionally removed.

[0047] exist Fig.14A , Fig. 14B and Fig. 14C In the embodiment, a gate dielectric layer 92 is formed to replace the gate, wherein Fig. 14C Shows Fig. 14B Detailed view of region 89 of . The gate dielectric layer 92 includes one or more layers deposited in the recess 90, such as on the top surface and sidewalls of the fin 52, and on the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 includes an interfacial layer of silicon oxide formed by thermal oxidation or chemical oxidation, and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where portions of the dummy gate dielectric 60 remain in the recess 90 , the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (eg, SiO 2 ).

[0048] Once the gate dielectric layer 92 is formed, a capping layer 94A may be formed over the gate dielectric layer 92. The capping layer 94A may be a metal silicide material, such as titanium silicon nitride (TSN). In an embodiment, the capping layer 94A may be formed using a deposition process such as chemical vapor deposition, but may be deposited to about 1000 Å using any suitable deposition method (e.g., deposition and subsequent silicidation). to about However, any suitable thickness may be used.

[0049] Once the cap layer 94A is formed, a first barrier layer 94B may be formed adjacent to the cap layer 94A. For example, the first barrier layer 94B may be formed of a metal-containing material (e.g., TiN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations of the foregoing, etc.). Furthermore, the first barrier layer 94B may be deposited to approximately 1000 Å using a deposition process (e.g., atomic layer deposition, chemical vapor deposition, sputtering, etc.). to about A thickness between , but any suitable deposition process or thickness may be used.

[0050] After the cap layer 94B is formed, a first work function adjustment layer 94C may be formed. In some embodiments, the first work function adjustment layer 94C may be a p-type work function metal, which may be based on nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSi x N y ), tungsten nitride (WN x ), tungsten carbonitride (WC x N y ), molybdenum nitride (MoN x ), a combination of the foregoing, etc.), or may be one or more metal layers, such as tungsten, molybdenum, gold, platinum, a combination of the foregoing, etc. In other embodiments, the first work function adjustment layer 94C may be an n-type work function material, which may be based on aluminum (for example, titanium aluminum nitride (TiAl x N y ), Tantalum Aluminum Nitride (TaAl x N y )) or silicide, such as titanium silicide (TiSi x ), tantalum silicide (TaSi), combinations of the foregoing, etc. However, any suitable material may be used.

[0051] In an embodiment, the first work function adjustment layer 94C is deposited using a deposition process (eg, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, a combination of the foregoing, etc.). In addition, the first work function adjustment layer 94C may be deposited to about to about The thickness between However, any suitable process and thickness may be used.

[0052] Figure 15A-15B The process for producing the anti-reactive layer 116 in the first work function adjustment layer 94C is shown in FIG. Figure 15A-15B 114), wherein Fig. 15B Shows Fig.15A 1. A close-up view of the dashed box labeled 118 in FIG. In an embodiment, the treatment process 114 can be used to react with portions of the first work function adjusting layer 94C and prevent subsequent oxidation of the first work function adjusting layer 94C in subsequent processes.

[0053] In an embodiment, the treatment process 114 may be a chemical soak process, which may be performed in-situ with the deposition of the first work function adjustment layer 94C, or may be performed ex-situ. Fig. 15B 122 in the figure) flows through the first work function adjusting layer 94C and is used to introduce active element dopants (in Fig. 15B The active element dopant 120 is introduced into the first work function adjustment layer 94C (indicated by an "X" labeled 120 in the figure). In some embodiments, the active element dopant 120 is selected so as to be able to prevent subsequent penetration of oxygen or other undesirable elements from invading through the anti-reactive layer 116. In embodiments where it is desired to prevent the migration of oxygen, an active element dopant 120 may be used that may be an element such as tungsten, titanium, aluminum, tantalum, silicon, nitrogen, boron, chromium, combinations of the foregoing, etc. However, any suitable dopant may be used.

[0054] In embodiments where the treatment process 114 is a chemical soak process, the active element dopant 120 may be introduced by passing a precursor 122 over the surface of the first work function adjusting layer 94C. In embodiments, the precursor 122 is a chemical that includes the desired active element dopant 120 and also allows for controlled placement of the active element dopant 120. Thus, while the precise precursor depends at least in part on the desired active element dopant 120, in some embodiments, the precursor may be a tungsten chloride (WCl) such as tungsten chloride (WCl). x ), titanium chloride (TiCl4), tetraethylaluminum (TEA), tetramethylaluminum (TMA), aluminum chloride (AlCl x ), tetrakis(dimethylamino)titanium (TDMAT), tantalum chloride (TaClx ), silane (SiH4), disilane (Si2H6), ammonia, elemental nitrogen, diborane (B2H6), combinations of the foregoing, etc. However, any suitable precursor material may be used.

[0055] To begin the treatment process 114, a precursor 122 is introduced into the process chamber above the first work function adjustment layer 94C. In an embodiment, the precursor 122 may be introduced at a flow rate between about 10 sccm and about 500 sccm (e.g., about 50 sccm). In addition, the treatment process 114 may be performed at a pressure between about 0.5 Torr and about 25 Torr (e.g., about 5 Torr) and at a temperature between about 200° C. and about 470° C. (e.g., about 400° C.). However, any suitable process parameters may be used.

[0056] During the treatment process 114, the precursor 122 will contact the top surface of the first work function adjusting layer 94C, wherein the precursor 122 will react with the material of the first work function adjusting layer 94C. The reaction will cause the active element dopant 120 to remain in the material of the first work function adjusting layer 94C, while the undesirable byproducts from the reaction remain in gaseous form and are removed from the surface of the first work function adjusting layer 94C.

[0057] Furthermore, in some embodiments, the precursor 122 or the reacted active element dopant 120 will diffuse from the surface into the first work function adjusting layer 94C. If the precursor 122 diffuses, the precursor 122 will react with the material of the first work function adjusting layer 94C, and the byproducts will diffuse back out of the first work function adjusting layer 94C. Either way, a diffusion gradient of the active element dopant 120 is formed within the first work function adjusting layer 94C.

[0058] Thus, the treatment process 114 forms the anti-reactive layer 116 from the material of the first work function adjustment layer 94C and the active element dopant 120. In an embodiment, the treatment process 114 may be continued for a sufficient time so that the concentration of the active element dopant 120 along the top surface of the anti-reactive layer 116 is between about 1% and about 40%, such as about 5%. For example, the treatment process 114 may be continued for a time between about 1 second and about 180 seconds, such as greater than about 20 seconds. However, any suitable time may be used.

[0059] In addition, due to the diffusion of the active element dopant 120, the anti-reaction layer 116 may extend into the material of the first work function adjustment layer 94C with a concentration gradient that decreases with increasing distance from the surface. In some embodiments, the anti-reaction layer 116 extends to about to about Between (e.g., about ), leaving a portion of the first work function adjusting layer 94C having a second depth D2 without the oxygen active element dopant 120, wherein the second depth D2 may be between about to about Between (e.g., about ). However, any suitable depth may be used.

[0060] For example, in an embodiment where the first work function adjusting layer 94C includes titanium nitride and the active element dopant 120 is aluminum, the first work function adjusting layer 94C will include aluminum from the treatment process 114 .

[0061] Figure 16A-16B The post-treatment process for treating the anti-reaction layer 116 in the first work function adjustment layer 94C is shown (in Figure 16A-16B denoted by a curved arrow labeled 124), wherein Fig. 16B Shows Fig.16A 1 is a close-up view of the dashed box labeled 118 in FIG. Specifically, after the treatment process 114 has been performed, at least some of the active element dopants 120 may not be fully bonded to the material of the first work function adjusting layer 94C, thereby leaving dangling bonds on one or more of the active element dopants 120. If these dangling bonds are not treated, subsequent processes may react in an undesirable manner, thereby causing undesirable defects.

[0062] Therefore, in some embodiments, the anti-reactive layer 116 may be subsequently treated by a post-treatment process 124 to reduce or eliminate the number of dangling bonds, and thereby reduce or eliminate defects caused by dangling bonds. In some embodiments, the post-treatment process 124 is used to add a second dopant (in Fig. 16B The first work function adjusting layer 94C may be a dopant (represented by a point labeled 130) that will react with the active element dopant 120 and eliminate dangling bonds. For example, in an embodiment where the first work function adjusting layer 94C is titanium nitride and the active element dopant 120 is aluminum, the post-treatment process 124 may add a second dopant 130 (e.g., nitrogen) that will bond with the active element dopant 120 and reduce the number of dangling bonds.

[0063] In an embodiment, the post-treatment process 124 may be a chemical soak process that may be performed in situ with the treatment process 114, or may be performed ex situ. Fig. 16BThe second dopant 130 is introduced into the first work function adjusting layer 94C (indicated by the arrow labeled 128 in the figure) so that the second dopant 130 will bond with the dangling bonds of the active element dopant 120. In some embodiments, the second dopant 130 may be an element such as nitrogen, silicon, boron, a halogen element, a combination of the foregoing, etc. However, any suitable material may be used.

[0064] In embodiments where the post-treatment process 124 is a chemical soak process, the second dopant 130 may be introduced by passing a post-treatment precursor 128 over the surface of the anti-reactive layer 116. In embodiments, the post-treatment precursor 128 is a chemical that includes the desired material and also allows for controlled placement of the second dopant 130. Thus, while the precise post-treatment precursor 128 depends at least in part on the desired second dopant 130, in some embodiments, the post-treatment precursor 128 may be a chemical such as ammonia (NH3), SiH4, NF3, combinations of the foregoing, etc. However, any suitable post-treatment precursor may be used.

[0065] To begin the post-treatment process 124, a post-treatment precursor 128 is introduced into the process chamber above the anti-reactive layer 116. In an embodiment, the post-treatment precursor 128 may be introduced at a flow rate between about 10 sccm and about 2000 sccm (e.g., about 500 sccm). In addition, the post-treatment process 124 may be performed at a pressure between about 0.5 Torr and about 25 Torr (e.g., about 5 Torr) and at a temperature between about 200° C. and about 470° C. (e.g., about 400° C.). However, any suitable process parameters may be used.

[0066] Thus, the post-treatment process 124 will react with dangling bonds from the active element dopant 120, making them unavailable for subsequent reactions. In an embodiment, the post-treatment process 124 can be continued for a sufficient time to provide a concentration of the second dopant 130 along the top surface of the anti-reactive layer 116 between about 0.5% and about 20%, such as about 3%. For example, the post-treatment process 124 can be continued for a time between about 0.5 seconds and about 180 seconds, such as greater than about 20 seconds. However, any suitable time can be used.

[0067] For example, in an embodiment where the first work function adjusting layer 94C includes titanium nitride, the active element dopant 120 is aluminum, and the second dopant 130 is nitrogen, the first work function adjusting layer 94C will include nitrogen from the original deposition process (where the peak nitrogen concentration may occur away from the surface) and nitrogen from the post-processing process 124 (where the peak nitrogen concentration will occur at the surface due to diffusion). Therefore, the first work function adjusting layer 94C can have multiple concentration peaks, such as two concentration peaks of nitrogen.

[0068] Fig.17 It is shown that once the post-processing process 128 is performed and the anti-reactive layer 116 is completed, a mask can be placed over the first work function adjustment layer 94C in preparation for patterning the first work function adjustment layer 94C. In an embodiment, the mask is a three-layer photoresist having a bottom layer 132, an intermediate layer 134, and a photoresist 136. In an embodiment, the bottom layer 132 can be a bottom anti-reflective coating (BARC) having different optical properties than the photoresist 136 to prevent uncontrolled and undesirable reflection of energy (e.g., light) back into the overlying photoresist 136 during exposure of the photoresist 136, thereby preventing the reflected light from causing a reaction in undesirable areas of the photoresist 136. For example, the bottom layer 132 can have a different refractive index (n), a different extinction coefficient (k), or a different thickness (T) value than the photoresist 136. In addition, the bottom layer 132 can be used to provide a flat surface to help reduce the negative effects of energy impinging at a certain angle.

[0069] In an embodiment, the bottom layer 132 includes a polymer resin, a catalyst, and a cross-linking agent, all of which are placed in a BARC solvent for dispersion. The polymer resin may include a polymer having various monomers bonded to a chromophore group. The material of the bottom layer 132 may be applied to the first work function adjustment layer 94C so that the material of the bottom layer 132 coats the upper exposed surface of the first work function adjustment layer 94C, and may be coated using a process such as a spin coating process, a dip coating method, an air knife coating method, a curtain coating method, a wire bar coating method, a gravure coating method, a lamination method, an extrusion coating method, a combination of the foregoing, and the like. In an embodiment, the material of the bottom layer 132 may be initially applied so that it has a thickness between about 10 nm and about 1000 nm, for example about 100 nm.

[0070] However, since the bottom layer 132 may also include oxygen, when the bottom layer 132 is dispensed over and in contact with the first work function adjusting layer 94C during subsequent processing, the oxygen in the bottom layer 132 may begin to diffuse into the first work function adjusting layer 94C. However, in the presence of the active element dopant 120, any oxygen diffused into the first work function adjusting layer 94C will first enter the anti-reactive layer 116, where the oxygen will react with the active element dopant 120 and be trapped before further diffusing into the first work function adjusting layer 94C.

[0071] Furthermore, by reacting with the active element dopant 120, the product of the active element dopant 120 and oxygen will additionally serve to prevent additional oxygen from diffusing from the bottom layer 132. In this way, the overall diffusion of oxygen can be reduced, thereby reducing oxidation of the underlying material of the first work function adjustment layer 94C. This reduction in the amount of oxidation allows the first work function adjustment layer 94C to be formed to a thickness that is smaller than would otherwise be possible without blocking oxidation, and allows for an increased ability to fine-tune and / or control the threshold voltage of devices manufactured using these methods as devices extend to smaller and smaller process nodes (e.g., 5 nm process nodes, 3 nm processes, or even smaller).

[0072] By using the active element dopant 120 to capture any oxygen that has diffused into the first work function adjusting layer 94C, the amount of oxygen that penetrates into the first work function adjusting layer 94C can be reduced and confined to the top surface of the first work function adjusting layer 94C. For example, in an embodiment, oxygen will diffuse no more than about to about Between (e.g., about In addition, the oxygen concentration at the surface of the first work function adjusting layer 94C may be between about 10% and about 30%, for example, about 20%.

[0073] The intermediate layer 134 may be disposed over the bottom layer 132. In an embodiment, the intermediate layer 134 may be an organic layer or an inorganic layer having an etch resistance different from that of the photoresist 136. In a particular embodiment, the intermediate layer 134 is a hard mask material, such as silicon, silicon nitride, oxide, oxynitride, silicon carbide, combinations of the foregoing, or the like. The hard mask material for the intermediate layer 134 may be formed by a process such as chemical vapor deposition (CVD), but other processes such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), spin coating, or silicon oxide formation followed by nitridation may be used instead. Any suitable method or combination of methods may be used to form or otherwise place the hard mask material, and all such methods or combinations are fully intended to be included within the scope of the embodiments. The intermediate layer 134 may be formed to be between about 100 and about 100 Å. The thickness between

[0074] Photoresist 136 is placed over intermediate layer 134 to provide a patterned mask so that intermediate layer 134 can be patterned into a desired pattern. In an embodiment, photoresist 136 is a photosensitive material that is dispersed onto intermediate layer 134 and then exposed to a patterned energy source (e.g., light) to induce a chemical reaction in those portions of the photosensitive material that are exposed. The chemical reaction induces a change in physical properties that can be used in a development process to separate the exposed portions of the photosensitive material from the unexposed portions of the photosensitive material, thereby producing a patterned photoresist.

[0075] Once the photoresist 136 has been patterned into a desired pattern, the photoresist 136 can be used as a mask to pattern the intermediate layer 134 and the bottom layer 132. In addition, in the case where the bottom layer 132 is patterned, the undesired portion ( Fig.17 The portions not shown in the figure can be removed using, for example, a suitable anisotropic etching process. However, any suitable removal method can be used.

[0076] Fig.18 It is shown that once the first work function adjustment layer 94C is formed and patterned, an adhesion layer (glue layer) 94D can be formed to facilitate adhesion of the overlying fill material 94E to the underlying first work function adjustment layer 94C and provide a nucleation layer for the formation of the fill material 94E. In an embodiment, the adhesion layer 94D can be a material such as titanium nitride and can be formed to a thickness between about 1000 Å and 1000 Å using a similar process such as ALD. to about Between (e.g., about ) of the seventh thickness. However, any suitable material and process may be used.

[0077] Once adhesion layer 94D is formed, fill material 94E is deposited to fill the remainder of the opening. In an embodiment, fill material 94E may be a material such as tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of the foregoing, etc., and may be formed using a deposition process such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of the foregoing, etc. Additionally, fill material 94E may be deposited to about to about Between (e.g., about ) in thickness. However, any suitable material may be used.

[0078] Figure 19A-19BIt is shown that after the recess 90 is filled, a planarization process such as CMP may be performed to remove excess portions of the material of the gate dielectric layer 92 and the gate electrode 94 that are located above the top surface of the ILD 88. The remaining portions of the material of the gate electrode 94 and the gate dielectric layer 92 thus form a replacement gate for the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack." The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0079] The formation of the gate dielectric layer 92 in the n-type region 50N and the p-type region 50P can occur simultaneously, so that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, so that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes, so that the gate dielectric layer 92 can be a different material, and / or the gate electrode 94 in each region can be formed by different processes, so that the gate electrode 94 can be a different material. When different processes are used, various masking steps can be used to mask and expose appropriate areas. However, the processing process 114 and any other desired process described herein can be applied to any work function layer desired to be manufactured.

[0080] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, a gate mask 96 is formed over the gate stack (including the gate dielectric layer 92 and the corresponding gate electrode 94), and the gate mask may be disposed between opposite portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack so that a groove is formed directly above the gate stack and between opposite portions of the gate spacers 86. The gate mask 96 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and a planarization process is then performed to remove excess portions of the dielectric material extending over the first ILD 88.

[0081] In addition, if Fig. 20A and Fig. 20B As shown, the second ILD 108 is deposited on the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material (e.g., PSG, BSG, BPSG, USG, etc.) and can be deposited by any suitable method (e.g., CVD and PECVD). The gate contact 110 ( Fig.16A and Fig. 16B) passes through the second ILD 108 and the gate mask 96 to contact the top surface of the recessed gate electrode 94.

[0082] exist Fig.21A and Fig. 21B In some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 88. An opening for the source / drain contact 112 is formed through the first ILD 88 and the second ILD 108, and an opening for the gate contact 110 is formed through the second ILD 108 and the gate mask 96. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown) and a conductive material such as a diffusion barrier layer, an adhesion layer, etc. are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form a source / drain contact 112 and a gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 106. The source / drain contacts 112 and the gate contact 110 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contacts 112 and the gate contact 110 may be formed in different cross sections, which may avoid shorting of the contacts.

[0083] By using the anti-reactive layer 116 to help reduce or eliminate the amount of oxygen diffused into the first work function adjustment layer 94C, fewer oxygen-related defects can occur in the lower portion of the first work function adjustment layer 94C. Therefore, by confining oxygen to a smaller area, a larger area of ​​the first work function adjustment layer 94C with a similar thickness can be obtained. Therefore, the overall thickness of the first work function adjustment layer 94C can be reduced, helping to reduce the overall structure.

[0084] Fig.22A and Fig. 22B FIG. 1 shows the test results of an embodiment of the first work function adjustment layer 94C, in which a material such as tungsten carbonitride is used for the first work function adjustment layer 94C. In this embodiment, the active element dopant 120 is aluminum. Fig.22A In the example, the line labeled 222 is shown. Fig.22A, the line labeled 220 shows the atomic percentage of oxygen, the line labeled 224 shows the atomic percentage of carbon, the line labeled 226 shows the atomic percentage of silicon, the line labeled 228 shows the atomic percentage of silicon oxide, and the line labeled 230 shows the atomic percentage of nitrogen. It can be seen that the amount of active element dopant 120 (e.g., aluminum) has a concentration gradient as the measurement extends away from the surface and toward the underlying layers. In addition, it can be seen that by using an active element dopant 120 as described herein, the atomic percentage of oxygen can be reduced from about 60% (in a process where the active element dopant 120 is not used) to between about 42% and about 50%.

[0085] Fig. 22B The active element dopant 120 (eg, aluminum) present in the first work function adjusting layer 94C is shown to be bonded as described. Fig. 22B The line labeled 232 in FIG. 9 provides an indication of the bonding of aluminum with oxygen in the first work function adjusting layer 94C. Thus, the aluminum reacts with and bonds with oxygen diffused into the first work function adjusting layer 94C.

[0086] Fig.23A and Fig. 23B FIG. 1 shows the test results of an embodiment of the first work function adjustment layer 94C, in which a material such as tungsten carbonitride is used for the first work function adjustment layer 94C. In this embodiment, the active element dopant 120 is titanium. Fig.23A In the example, the line labeled 328 is shown. Fig.23A , the line labeled 320 shows the atomic percentage of oxygen, the line labeled 324 shows the atomic percentage of nitrogen, the line labeled 326 shows the atomic percentage of silicon, the line labeled 320 shows the atomic percentage of oxygen, and the line labeled 330 shows the atomic percentage of silicon oxide. It can be seen that the amount of active element dopant 120 (e.g., titanium) has a concentration gradient as the measurement extends away from the surface and toward the underlying layer. In addition, it can be seen that by using the active element dopant 120 as described herein, although there is no Figure 22A-22B As much of a reduction as is shown, the atomic percentage of oxygen can still be reduced from about 60% (in a process not using the active element dopant 120) to less than 60% at most points within the first work function adjusting layer 94C.

[0087] Fig. 23B The active element dopant 120 (e.g., titanium) present in the first work function adjusting layer 94C is shown to be bonded as described. Fig. 22B The line labeled 332 in FIG. 9 provides an indication of the bonding of titanium with oxygen in the first work function adjusting layer 94C. Thus, the titanium reacts with and bonds with oxygen diffused into the first work function adjusting layer 94C.

[0088] Fig.24 Another benefit of introducing the active element dopant 120 into the first work function adjustment layer 94C is shown. It can be seen that when the active element dopant 120 such as titanium is introduced, the flat band voltage (Vfb) of the device formed using the active element dopant 120 is increased (e.g., from 0.165V to 0.197V) compared to the device without the active element dopant 120 located in the first work function adjustment layer 94C. In addition, if the active element dopant 120 is aluminum, the flat band voltage can be further increased (e.g., from 0.165V to 0.201V).

[0089] The disclosed FinFET embodiments may also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, ring gates, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. A dummy gate stack and source / drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stack is removed, the sacrificial layer in the channel region may be partially or completely removed. A replacement gate structure is formed in a manner similar to the above-described embodiments, the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts to the replacement gate structure and the source / drain region may be formed in a manner similar to the above-described embodiments. A nanostructured device may be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0090] In an embodiment, a method of manufacturing a semiconductor device includes: forming a fin from a semiconductor substrate; forming a gate dielectric on the fin; forming a work function layer on the gate dielectric; and modifying a surface of the work function layer, wherein modifying the surface is performed at least in part by chemical soaking to implant an active element. In an embodiment, the active element is aluminum. In an embodiment, the chemical soaking includes introducing aluminum into the work function layer. In an embodiment, forming the work function layer is performed at least in part by forming it to a thickness between about 5 and about 30 using an atomic layer deposition process. In an embodiment, the method also includes reacting the active element with oxygen.

[0091] In another embodiment, a method of manufacturing a semiconductor device includes: depositing a gate dielectric over a channel region of a semiconductor material, the channel region being adjacent to multiple sides of the semiconductor material; depositing a work function layer over the gate dielectric using an atomic layer deposition process; soaking the work function layer in a precursor material, wherein soaking the work function layer forms a dopant layer within the work function layer; and depositing a fill material over the work function layer. In an embodiment, the precursor material is titanium chloride. In an embodiment, depositing the work function layer deposits the work function layer to a thickness between about 5 and about 30. In an embodiment, soaking the work function layer is performed in situ with depositing the work function layer. In an embodiment, depositing the work function layer deposits titanium nitride. In an embodiment, the method further includes performing a post-treatment process after soaking the work function layer in the precursor material, the post-treatment process reducing the number of dangling bonds in the work function layer. In an embodiment, the post-treatment process adds nitrogen to the work function layer. In an embodiment, the post-treatment process causes ammonia to flow over the work function layer. In an embodiment, the dopant layer includes titanium.

[0092] In yet another embodiment, a semiconductor device includes: a semiconductor fin; a dielectric material adjacent to the semiconductor fin; a work function layer located on the dielectric material, the work function layer including a dopant layer; and a fill material located on the work function layer. In an embodiment, the dopant layer includes titanium. In an embodiment, the dopant layer includes boron. In an embodiment, the dopant layer includes chromium. In an embodiment, the thickness of the work function layer is no greater than 30. In an embodiment, the thickness of the dopant layer is between about 1 and about 10.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0094] Example 1. A method for manufacturing a semiconductor device, the method comprising: forming a fin from a semiconductor substrate; forming a gate dielectric on the fin; forming a work function layer on the gate dielectric; and modifying a surface of the work function layer, wherein modifying the surface is performed at least in part by chemical immersion of implanting active elements.

[0095] Example 2. The method of Example 1, wherein the active element is aluminum.

[0096] Example 3. The method of Example 2, wherein the chemical soaking includes introducing aluminum into the work function layer.

[0097] Example 4. The method of Example 1, wherein the work function layer is formed at least partially by an atomic layer deposition process to a depth between to It is executed based on the thickness between.

[0098] Example 5. The method according to Example 1, further comprising: reacting the active element with oxygen.

[0099] Example 6. A method for manufacturing a semiconductor device, the method comprising: depositing a gate dielectric over a channel region of a semiconductor material, the channel region being adjacent to multiple sides of the semiconductor material; depositing a work function layer over the gate dielectric using an atomic layer deposition process; immersing the work function layer in a precursor material, wherein immersing the work function layer forms a dopant layer within the work function layer; and depositing a filling material over the work function layer.

[0100] Example 7. The method of Example 6, wherein the precursor material is titanium chloride.

[0101] Example 8. The method of Example 6, wherein depositing the work function layer deposits the work function layer onto to The thickness between.

[0102] Example 9. The method of Example 6, wherein the soaking the work function layer is performed in-situ with depositing the work function layer.

[0103] Example 10. The method of Example 6, wherein depositing the work function layer comprises depositing titanium nitride.

[0104] Example 11. The method according to Example 6 further includes: performing a post-treatment process after immersing the work function layer in the precursor material, wherein the post-treatment process reduces the number of dangling bonds in the work function layer.

[0105] Example 12. The method of Example 11, wherein the post-treatment process adds nitrogen to the work function layer.

[0106] Example 13. The method of Example 12, wherein the post-treatment process causes ammonia to flow over the work function layer.

[0107] Example 14. The method of Example 13, wherein the dopant layer comprises titanium.

[0108] Example 15. A semiconductor device comprising: a semiconductor fin; a dielectric material, the dielectric material being adjacent to the semiconductor fin; a work function layer, the work function layer being located above the dielectric material, the work function layer comprising a dopant layer; and a filling material, the filling material being located above the work function layer.

[0109] Example 16. The semiconductor device of Example 15, wherein the dopant layer comprises titanium.

[0110] Example 17. The semiconductor device of Example 15, wherein the dopant layer comprises boron.

[0111] Example 18. The semiconductor device of Example 15, wherein the dopant layer comprises chromium.

[0112] Example 19. The semiconductor device of Example 15, wherein the thickness of the work function layer is not greater than

[0113] Example 20. The semiconductor device according to Example 15, wherein the thickness of the dopant layer is between to between.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a fin from a semiconductor substrate; forming a gate dielectric over the fin; forming a work function layer on the gate dielectric; modifying a surface of the work function layer, wherein modifying the surface is performed at least in part by chemical soaking to implant active elements; and A post-treatment process is performed after modifying the surface of the work function layer, the post-treatment process reducing the number of dangling bonds in the work function layer.

2. The method according to claim 1, wherein: The active element is aluminum.

3. The method according to claim 2, wherein: The chemical soaking includes introducing aluminum into the work function layer.

4. The method according to claim 1, wherein: The work function layer is formed at least partially by an atomic layer deposition process to a depth between to It is executed based on the thickness between.

5. The method according to claim 1, wherein: Also includes: The active element is reacted with oxygen.

6. A method for manufacturing a semiconductor device, the method comprising: depositing a gate dielectric over a channel region of a semiconductor material, the channel region being adjacent to a plurality of sides of the semiconductor material; depositing a work function layer over the gate dielectric using an atomic layer deposition process; soaking the work function layer in a precursor material, wherein soaking the work function layer forms a dopant layer within the work function layer; performing a post-treatment process after immersing the work function layer in the precursor material, the post-treatment process reducing the number of dangling bonds in the work function layer; as well as A fill material is deposited over the work function layer.

7. The method according to claim 6, wherein: The precursor material is titanium chloride.

8. The method according to claim 6, wherein: Depositing the work function layer is to deposit the work function layer onto to The thickness between.

9. The method according to claim 6, wherein: The soaking of the work function layer is performed in-situ with the deposition of the work function layer.

10. The method according to claim 6, wherein: Depositing the work function layer is depositing titanium nitride.

11. The method according to claim 6, wherein: The post-treatment process adds nitrogen to the work function layer.

12. The method according to claim 11, wherein: The post-treatment process flows ammonia on the work function layer.

13. The method according to claim 12, wherein: The dopant layer includes titanium.

14. A semiconductor device comprising: Semiconductor fins; a dielectric material adjacent to the semiconductor fin; a work function layer, the work function layer being located above the dielectric material, the work function layer comprising a dopant layer, wherein the work function layer is treated by a post-treatment process, the post-treatment process reducing the number of dangling bonds in the work function layer; as well as A filling material is located on the work function layer.

15. The semiconductor device according to claim 14, wherein: The dopant layer includes titanium.

16. The semiconductor device according to claim 14, wherein The dopant layer includes boron.

17. The semiconductor device according to claim 14, wherein: The dopant layer includes chromium.

18. The semiconductor device according to claim 14, wherein: The thickness of the work function layer is not greater than 19. The semiconductor device according to claim 14, wherein The thickness of the dopant layer is between to between.

Images